Data processing method, processor and computing equipment

Abstract

The embodiment of the invention provides a data processing method, a processor and computing equipment, relates to the technical field of AI, and can improve the efficiency of matrix multiplication. The method is applied to a heterogeneous processor at least comprising a first processing core and a second processing core, and comprises the following steps: the first processing core obtains a first input matrix and a second input matrix of an input matrix multiplier which is an operator running in the heterogeneous processor; the second processing core obtains a first expected matrix and a second expected matrix; wherein the size of the expected matrix is integral multiple of the preset size, and the matrix format of the expected matrix is a first matrix format; the calculation efficiency of the second processing core on the matrix of the first matrix format is higher than the calculation efficiency on the matrix of the second matrix format, and the second matrix format is the matrix format of the input matrix; and the second processing core performs matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result.

Description

Technical Field

[0001] The present invention relates to the field of artificial intelligence (AI), and in particular to a data processing method, a processor, and a computing device. Background Art

[0002] As we all know, the matrix multiplication (MatMul) operator is the core computing unit in AI computing. The MatMul operator is used to perform multiplication operations between matrices.

[0003] The typical MatMul operator execution process involves the processor converting the data matrix to be operated (hereinafter referred to as the matrix to be operated on) into a matrix in a preset format. This matrix format is highly efficient for matrix multiplication by the processor's matrix computing core, meaning that the preset format has a high affinity for the matrix computing core. The processor then calls the matrix computing core to perform matrix multiplication on the preset format and outputs the result.

[0004] However, when the size of the matrix to be operated is not an integer multiple of the preset size (eg, 512 bytes), it takes a long time for the processor to convert the matrix to be operated into the preset format, thereby reducing the efficiency of the matrix multiplication operation. Summary of the Invention

[0005] The present application provides a data processing method, a processor, and a computing device that can improve the efficiency of matrix multiplication operations.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a data processing method, which is applied to a heterogeneous processor, wherein the heterogeneous processor includes at least: a first processing core and a second processing core, and the method includes: the first processing core obtains a first input matrix and a second input matrix of an input matrix multiplication operator, and the matrix multiplication operator is an operator running in the heterogeneous processor; the second processing core obtains a first expected matrix and a second expected matrix; the first expected matrix is ​​a matrix after the first processing core converts the first input matrix, and the second expected matrix is ​​a matrix after the first processing core converts the second input matrix, wherein the expected matrix is ​​a matrix whose size is an integer multiple of a preset size, and the matrix format of the expected matrix is ​​a first matrix format; the computational efficiency of the second processing core on the matrix in the first matrix format is higher than the computational efficiency of the second processing core on the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; the second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result.

[0008] A data processing method provided in an embodiment of the present application is applied in a heterogeneous processor including at least a first processing core and a second processing core. The method converts the first input matrix and the second input matrix of the input matrix multiplication operator obtained by the first processing core into first expected matrices and second expected matrices whose sizes are integer multiples of a preset size and whose matrix formats are in a first matrix format; so that the second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result. Among them, the computational efficiency of the second processing core for the matrix in the first matrix format is higher than the computational efficiency for the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; since the matrix multiplication operator is an operator running in a heterogeneous processor including at least the first processing core and the second processing core, and the first input matrix and the second input matrix are matrices of the input matrix multiplication operator, the conversion of the input matrix by the first processing core and the matrix multiplication operation of the second processing core on the expected matrix after conversion are both completed in the matrix multiplication operator; that is, the above embodiment converts the input matrix into a matrix whose size is an integer multiple of the preset size based on the first processing core in the above matrix multiplication operator, so it avoids the problem of taking a long time to convert the matrix format of the input matrix into the above first matrix format when the size of the input matrix is ​​not an integer multiple of the preset size, thereby improving the efficiency of the matrix multiplication operation.

[0009] In one possible implementation, the second processing core obtains the first expected matrix, including: the first processing core padding the first input matrix to obtain a first padded matrix; the first padded matrix is ​​a matrix whose size is an integer multiple of a preset size; the first processing core converts the first padded matrix into a first expected matrix in a first matrix format; and the second processing core obtains the first expected matrix in response to an acquisition notification sent by the first processing core.

[0010] Since the above embodiment completes the conversion of the input matrix into the expected matrix by the first processing core and the matrix multiplication operation on the expected matrix by the second processing core within one operator (i.e., the matrix multiplication operator); therefore, after the first processing core converts the input matrix into the expected matrix, the above matrix multiplication operation will be directly performed within the second processing core; compared with the method of using two operators (i.e., one operator converts the input matrix into the expected matrix and outputs the expected matrix in the memory; then, the other operator moves the expected matrix from the memory to the processing core where the operator is located, and performs the matrix multiplication operation within the processing core), the efficiency of moving the expected matrix is ​​improved, thereby further improving the efficiency of the matrix multiplication operation.

[0011] In one possible implementation, the first processing core performs padding processing on the first input matrix to obtain a first padded matrix, including: when the first input matrix is ​​not a matrix whose size is an integer multiple of a preset size, the first processing core performs padding processing on the first input matrix to obtain the first padded matrix.

[0012] The above embodiment converts the input matrix into a matrix whose size is an integer multiple of the preset size based on the first processing core within the above matrix multiplication operator, thereby avoiding the problem of taking a long time to convert the matrix format of the input matrix into the above first matrix format when the size of the input matrix is ​​not an integer multiple of the preset size, thereby improving the efficiency of the matrix multiplication operation.

[0013] In one possible implementation, the first input matrix and the second input matrix are the i-th batch of input matrices in N batches of input matrices, N and i are both positive integers, i is less than or equal to N, and a batch of input matrices includes at least two matrices that need to be multiplied.

[0014] In one possible implementation, after the first processing core converts the i-th batch of input matrices into the i-th batch of expected matrices, and before the second processing core completes outputting the first operation result, the method includes: the first processing core converts the i+1-th batch of input matrices into the i+1-th batch of expected matrices.

[0015] In the above embodiment, while the second processing core performs matrix multiplication operations on the i-th batch of expected matrices after the i-th batch of input matrices are converted, the first processing core performs conversion processing on the (i+1)-th batch of input matrices, thereby avoiding waste of processing resources on the first processing core and improving the efficiency of the matrix multiplication operation.

[0016] In a possible implementation, after the second processing core outputs the first operation result, the method includes: the second processing core performs a matrix multiplication operation on the (i+1)th batch of expected matrices to obtain a second operation result.

[0017] In a possible implementation, when the N batches of input matrices are submatrices of a batch of matrices to be processed, the method further includes: the first processing core dividing the matrices to be processed into the N batches of input matrices.

[0018] In one possible implementation, after the second processing core obtains N operation results from N batches of input matrices, the method includes: the second processing core determines the sum of the N operation results as the matrix multiplication operation result of the matrix to be processed; and the second processing core outputs the above-mentioned matrix multiplication operation result.

[0019] In the above embodiment, a batch of matrices to be processed is divided into N batches of sub-matrices. Then, the first processing core in the heterogeneous processor converts the sub-matrix (e.g., the i-th sub-matrix) into the i-th expected matrix whose size is an integer multiple of a preset size and whose matrix format is the first matrix format with a higher affinity for the second processing core (referred to as: conversion processing); thereafter, the second processing core performs a matrix multiplication operation on the i-th expected matrix to obtain an operation result; finally, the second processing core determines the sum of the operation results of the N batches of sub-matrices as the operation result of the matrix to be processed. Since the first processing core and the second processing core asynchronously process their respective tasks, that is, while the second processing core performs matrix multiplication on the i-th expected matrix after the i-th submatrix is ​​converted, the first processing core performs conversion processing on the i+1-th submatrix; thereby avoiding the problem of the matrix multiplication operation of the matrix to be processed being too large, resulting in a long time consumption, and also avoiding the waste of processing resources on the first processing core. It also avoids the problem of the matrix format of the submatrix being converted into the first matrix format when the size of the submatrix is ​​not an integer multiple of the preset size. Therefore, the efficiency of the matrix multiplication operation is improved.

[0020] In a possible implementation, the matrix format includes at least: a row-major storage format or a block storage format.

[0021] In the second aspect, an embodiment of the present application provides a data processing device, which includes: a transceiver unit and a processing unit; the transceiver unit is used to obtain a first input matrix and a second input matrix of an input matrix multiplication operator, and the matrix multiplication operator is an operator running in a heterogeneous processor; the transceiver unit is also used to obtain a first expected matrix and a second expected matrix; the first expected matrix is ​​a matrix after the first processing core converts the first input matrix, and the second expected matrix is ​​a matrix after the first processing core converts the second input matrix, wherein the expected matrix is ​​a matrix whose size is an integer multiple of a preset size, and the matrix format of the expected matrix is ​​a first matrix format; the computational efficiency of the second processing core on the matrix in the first matrix format is higher than the computational efficiency of the second processing core on the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; the processing unit is used to perform matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result.

[0022] In one possible implementation, a processing unit is used to perform padding processing on a first input matrix to obtain a first padding matrix; the first padding matrix is ​​a matrix whose size is an integer multiple of a preset size; the processing unit is used to convert the first padding matrix into a first expected matrix in a first matrix format, and the transceiver unit is used to obtain the first expected matrix in response to an acquisition notification sent by the first processing core.

[0023] In a possible implementation, the processing unit is configured to, when the first input matrix is ​​not a matrix whose size is an integer multiple of a preset size, perform padding processing on the first input matrix to obtain a first padded matrix.

[0024] In one possible implementation, the first input matrix and the second input matrix are the i-th batch of input matrices in N batches of input matrices, N and i are both positive integers, i is less than or equal to N, and a batch of input matrices includes at least 2 matrices that need to be multiplied.

[0025] In a possible implementation, the processing unit is configured to convert the (i+1)th batch of input matrices into the (i+1)th batch of expected matrices.

[0026] In a possible implementation, the processing unit is configured to perform a matrix multiplication operation on the (i+1)th batch of expected matrices to obtain a second operation result.

[0027] In a possible implementation, the processing unit is configured to divide the matrix to be processed into N batches of input matrices.

[0028] In a possible implementation, the processing unit is configured to determine the sum of N operation results as the matrix multiplication operation result of the matrix to be processed; and the transceiver unit is configured to output the matrix multiplication operation result.

[0029] In a possible implementation, the matrix format includes at least a row-first storage format or a block storage format.

[0030] In a third aspect, an embodiment of the present application provides a processor for running a program, wherein the program is executed when running to implement the method described in the first aspect or any possible implementation thereof.

[0031] In a fourth aspect, an embodiment of the present application provides a computing device comprising a memory and at least one processor connected to the memory, the memory being used to store computer program code, the computer program code comprising computer instructions, which, when executed by at least one processor, enable the computing device to execute the method described in the first aspect and any one of its possible implementations.

[0032] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium storing computer instructions. When the computer instructions are run on a computer, the method of the first aspect and any one of its possible implementations is executed.

[0033] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes computer instructions. When the computer instructions are run on a computer, the method described in the first aspect and any one of its possible implementation methods is executed.

[0034] In the seventh aspect, an embodiment of the present application provides a chip, including a memory and a processor, the memory being used to store computer instructions, and the processor being used to call and run the computer instructions from the memory to execute the method described in the first aspect and any one of its possible implementation methods.

[0035] It should be understood that the beneficial effects achieved by the technical solutions of the second to seventh aspects of this application and the corresponding possible implementation methods can be referred to the technical effects of the first aspect and its corresponding possible implementation methods mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A hardware schematic diagram of a computing device provided in an embodiment of the present application;

[0037] Figure 2 This is one of the flow charts of a data processing method provided in an embodiment of the present application;

[0038] Figure 3 This is one of the flow charts of a data processing method provided in an embodiment of the present application;

[0039] Figure 4 A schematic diagram of an input matrix provided in an embodiment of the present application;

[0040] Figure 5 A schematic diagram of a padding matrix provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram of a matrix format provided in an embodiment of the present application;

[0042] Figure 7 This is one of the flow charts of a data processing method provided in an embodiment of the present application;

[0043] Figure 8 A schematic diagram of a processing core executing a task provided in an embodiment of the present application;

[0044] Figure 9 This is one of the flow charts of a data processing method provided in an embodiment of the present application;

[0045] Figure 10 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0047] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, "first processing core" and "second processing core" are used to distinguish different processing cores, rather than to describe a specific order of processing cores.

[0048] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0049] In the description of the embodiments of the present application, unless otherwise specified, "a plurality" means two or more than two. For example, a plurality of processors means two or more than two processors.

[0050] First, some concepts involved in a data processing method, processor, and computing device provided in the embodiments of the present application are explained as follows:

[0051] Heterogeneous processor: A processor that includes at least two cores with different architectures (i.e., heterogeneous cores); for example, a heterogeneous processor includes the processing core of a graphics processing unit (GPU) and the processing core of a field-programmable gate array (FPGA).

[0052] Matrix multiplication operator: also called MatMul operator, is a processing unit used to perform matrix multiplication operations or a mapping of functions in the function space.

[0053] In response to the problems existing in the background technology, the data processing method provided in an embodiment of the present application is applied in a heterogeneous processor including at least a first processing core and a second processing core. The method converts the first input matrix and the second input matrix of the input matrix multiplication operator obtained by the first processing core into a first expected matrix and a second expected matrix whose size is an integer multiple of a preset size and whose matrix format is a first matrix format; so that the second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result. Among them, the computational efficiency of the second processing core for the matrix in the first matrix format is higher than the computational efficiency for the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; since the matrix multiplication operator is an operator running in a heterogeneous processor including at least the first processing core and the second processing core, and the first input matrix and the second input matrix are matrices of the input matrix multiplication operator, the conversion of the input matrix by the first processing core and the matrix multiplication operation of the second processing core on the expected matrix after conversion are both completed in the matrix multiplication operator; that is, the above embodiment converts the input matrix into a matrix whose size is an integer multiple of the preset size based on the first processing core in the above matrix multiplication operator, so it avoids the problem of taking a long time to convert the matrix format of the input matrix into the above first matrix format when the size of the input matrix is ​​not an integer multiple of the preset size, thereby improving the efficiency of the matrix multiplication operation.

[0054] The data processing method provided in the embodiment of the present application is applied to a computing system in which data matrix multiplication operations exist. The computing system includes at least an image processing system, a large model prediction system, and a speech recognition system; wherein the computing system can be a computing system of different scales, such as a very large system with more than 10 million cores. Exemplarily, the computing system in the embodiment of the present application can be any of the following: a processor including multiple cores, a server including multiple processors (the multiple processors are heterogeneous processors, and the processors are heterogeneous multi-core processors), a cabinet including multiple servers, or a cluster including multiple cabinets, etc.

[0055] Figure 1 A hardware structure diagram of a computing device provided in an embodiment of the present application is provided. The computing device can be a server, such as a central server, an edge server, or a local server in a local data center. In some embodiments, the computing device can also be a terminal device such as a desktop computer, a laptop computer, or a smartphone. Figure 1 The various components shown in the drawings may be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0056] like Figure 1As shown, the computing device may include: a heterogeneous processor 101, a memory 102, and a communication interface 103. The heterogeneous processor 101, the memory 102, and the communication interface 103 may be connected to each other via a bus 104, or in other ways.

[0057] The heterogeneous processor 101 is a processor that includes at least two processing cores with different architectures, that is, the heterogeneous processor 101 is a processor that includes heterogeneous cores; the heterogeneous processor 101 may, for example, include a graphics processing unit (GPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.

[0058] Among them, GPU, also known as visual processor or display chip, is a microprocessor specifically designed to perform image and graphics-related operations on personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). GPUs contain thousands of cores and can process thousands of threads simultaneously, allowing them to run a large number of calculations in parallel. FPGAs are programmable logic processors that can be repeatedly programmed according to users' needs. FPGAs excel at processing short, intensive data accesses. FPGAs allow users to program circuit paths through tiny logic blocks and can process any type of digital function. ASICs are specially designed integrated circuits with special specifications for a specific purpose. They are designed and manufactured according to specific user requirements and the needs of specific electronic systems. For example, tensor processing units (TPUs) and neural network processing units (NPUs) are both ASICs. TPUs and NPUs are chips designed for machine learning, suitable for computing massive amounts of data and possessing powerful computing power.

[0059] The memory 102 includes, but is not limited to, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical storage, magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer. In the embodiment of the present application, the memory 102 can store information such as computer instructions.

[0060] In one possible implementation, the memory 102 may exist independently of the heterogeneous processor 101. The memory 102 may be connected to the heterogeneous processor 101 via a bus 104 and used to store data, instructions, or program code. When the heterogeneous processor 101 calls and executes the instructions or program code stored in the memory 102, the relevant steps of the data processing method provided in the embodiments of the present application can be implemented.

[0061] In another possible implementation, the memory 102 may also be integrated with the heterogeneous processor 101 .

[0062] The communication interface 103 may be a transceiver module for communicating with other devices or communication networks, such as Ethernet, RAN, wireless local area networks (WLAN), etc. The communication interface 103 may receive instructions, messages, or data. The transceiver module may be a device such as a transceiver or a transceiver. Alternatively, the communication interface 103 may be a transceiver circuit located within the heterogeneous processor 101, for implementing signal input and signal output of the heterogeneous processor. The communication interface 103 may be a wired interface (port), such as a fiber distributed data interface (FDDI) or a gigabit Ethernet (GE) interface, or the communication interface 103 may be a wireless interface.

[0063] The bus 104 may be an ISA bus, a PCI bus, or an EISA bus. The bus may be classified as an address bus, a data bus, or a control bus. The bus may also be classified as a serial bus or a parallel bus. Figure 1 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.

[0064] It should be noted that Figure 1 The computing device in the example is only one example of a computing device that can have more Figure 1 More or fewer components shown in the figure may be combined with two or more components, or may have different component configurations. For example, the computing device may further include a smart network card, such as a data processing unit (DPU).

[0065] The data processing method provided in the embodiment of the present application is applied to a heterogeneous processor 101 including at least a first processing core and a second processing core, such as Figure 2 As shown, the method includes: S110-S140.

[0066] S110 : The first processing core obtains a first input matrix and a second input matrix of an input matrix multiplication operator.

[0067] The above-mentioned matrix multiplication operator is an operator running in the above-mentioned heterogeneous processor for performing matrix multiplication operations. The matrix multiplication operator performs matrix multiplication operations based on the first processing core and the second processing core in the heterogeneous processor; wherein the first processing core and the second processing core are heterogeneous cores with specific different architectures. Specifically, the first processing core can be a vector core and the second processing core is a matrix core.

[0068] The above-mentioned first input matrix and second input matrix are matrices that need to be multiplied, and the first input matrix and the second input matrix are the i-th batch of input matrices in N batches of input matrices; wherein a batch of input matrices includes at least two matrices that need to be multiplied, and N and i are both positive integers.

[0069] It should be understood that the N batches of input matrices mentioned above can be submatrices of a batch of input matrices (abbreviated as a batch of matrices to be processed); that is, the N batches of input matrices are N batches of submatrices obtained by dividing the batch of matrices to be processed; that is, the sum of the N multiplication results of the N batches of input matrices is the multiplication result of the matrix to be processed; it can be seen that there is a correlation between any two batches of input matrices in the N batches of input matrices. The N batches of input matrices mentioned above can also be N batches of independent input matrices, that is, the N batches of input matrices are not submatrices of a batch of matrices to be processed, but are independent matrices; that is, there is no correlation between any two batches of input matrices in the N batches of input matrices.

[0070] It should be noted that the above-mentioned matrix multiplication operator performs multiplication operations on the above-mentioned first input matrix and second input matrix within the processing core (i.e., core), so the specific implementation of the above-mentioned S110 includes: the first processing core obtains the first input matrix and the second input matrix from the memory of the computing device where the above-mentioned heterogeneous processor is located; wherein, the first input matrix and the second input matrix can be data matrices based on the output of other operations, or can be data matrices directly input by the user on the computing device, and the specific embodiments of the present application do not specifically limit them.

[0071] S120: The first processing core converts the first input matrix and the second input matrix into a first expected matrix and a second expected matrix.

[0072] The first expected matrix is ​​a matrix obtained by converting the first input matrix, and the second expected matrix is ​​a matrix obtained by converting the second input matrix. The expected matrix (i.e., the first expected matrix and the second expected matrix) is a matrix whose size is an integer multiple of a preset size, and the matrix format of the expected matrix is ​​a first matrix format; wherein the second processing core (i.e., the processing core for performing matrix multiplication operations) in the heterogeneous processor has a higher computational efficiency for matrices in the first matrix format than for matrices in the second matrix format (i.e., the matrix format of the input matrix); that is, the computational efficiency of the second processing core for the expected matrix is ​​higher than the computational efficiency of the second processor for the input matrices (i.e., the first input matrix and the second input matrix); that is, the affinity of the second processing core for the expected matrix is ​​higher than its affinity for the input matrix.

[0073] The specific implementation of the above S120 is as follows: Figure 3 As shown, including: S121-S124.

[0074] S121 . The first processing core performs padding processing on the first input matrix to obtain a first padded matrix.

[0075] The first padding matrix is ​​a matrix whose size is an integer multiple of a preset size.

[0076] For example, assuming that the above-mentioned preset size is 512 bytes, then the size of the first padding matrix is ​​an integer multiple of 512 bytes. When the size of the first padding matrix is ​​1 times the preset size, the size of the first padding matrix is ​​512 bytes; when the size of the first padding matrix is ​​2 times the preset size, the size of the first padding matrix is ​​1024 bytes.

[0077] It should be noted that, when the size of matrix A is an integer multiple of the preset size and the size of matrix B is an integer multiple of the non-preset size, the efficiency of the above-mentioned first processing core in converting the matrix A from the above-mentioned second matrix format to the first matrix format is higher than the efficiency of the first processing core in converting the matrix B from the above-mentioned second matrix format to the first matrix format; that is, the efficiency of converting a matrix whose size is an integer multiple of the preset size from the second matrix format to the first matrix format is higher than the efficiency of converting a matrix whose size is an integer multiple of the non-preset size from the second matrix format to the first matrix format.

[0078] The implementation method of the above-mentioned S121 includes: inserting N zero elements (i.e., elements with a value of 0) into the above-mentioned first input matrix so that the size of the first input matrix after the insertion of the zero elements is an integer multiple of the above-mentioned preset size (i.e., a first padded matrix); wherein the value of N is the difference between the preset size M and the remainder of the size X of the above-mentioned first input matrix and the preset size M: i.e., N=M-(X%M), wherein "%" is used to represent the remainder symbol.

[0079] For example, assuming that the first input matrix is Figure 4 The data matrix shown is 3 rows and 4 columns. The first input matrix specifically includes [{20, 1, 8, 16}, {3, 9, 32, 6}, {21, 30, 64, 7}]; wherein, {20, 1, 8, 16} represents the first row of data in the first input matrix, {3, 9, 32, 6} represents the second row of data in the first input matrix, and {21, 30, 64, 7} represents the third row of data in the first input matrix. Since the size of each element in the first input matrix is ​​1 byte, the size of the first input matrix is ​​12 bytes. Assume that the preset size is 16 bytes; then, N = 16-(12% 16), that is, the value of N is 4; at this time, the first processing core inserts 4 zero elements into the first input matrix, so that the size of the first input matrix (i.e., the first padding matrix) after inserting 4 zero elements is 16 bytes, as shown in FIG. Figure 5 The first padding matrix shown is a data matrix with 4 rows and 4 columns. Specifically, the first padding matrix includes [{20, 1, 8, 16}, {3, 9, 32, 6}, {21, 30, 64, 7}, {0, 0, 0, 0}].

[0080] It should be noted that the above S121 is executed when the size of the above-mentioned first input matrix is ​​not an integer multiple of the preset size. When the size of the first input matrix is ​​an integer multiple of the preset size, the first processing core directly executes the following S122 without executing the above-mentioned S121.

[0081] S122: The first processing core converts the first padded matrix into a first expected matrix in a first matrix format.

[0082] The matrix format of the first padded matrix is ​​the second matrix format; wherein, the multiplication operation efficiency of the second processing core on the matrix in the first matrix format is higher than the multiplication operation efficiency on the matrix in the second matrix format; that is, the affinity of the second processing core to the first matrix format is higher than the affinity to the second matrix format.

[0083] It should be noted that the matrix formats of the above matrix include at least: row-first data storage format and block storage format; among which, Figure 6 As shown, the row-first data storage format is used to represent a row-first data storage format; the arrangement of elements in the matrix of the row-first data storage format is: after the data of one row is arranged, the data of the next row is arranged, and the arrangement is repeated until the entire data matrix is ​​arranged. Figure 6 As shown, the block storage format is used to represent the storage format of block data; the arrangement of elements in the matrix of the block storage format is: the data matrix is ​​divided into multiple blocks (such as Figure 6The data in the block storage format is arranged based on the row-first data storage format (the dotted box in the diagram). After the data in a block is arranged, the data is arranged in the next block in the same column (such as the first column) of the block. After the data in all blocks in the column (i.e., the first column) are arranged, the data is arranged in the first block in the next column (such as the second column), and this process is repeated until the entire data matrix is ​​arranged.

[0084] It should be understood that when the above-mentioned first matrix format is a row-first data storage format and the second matrix format is a block storage format, the implementation method of the above-mentioned S122 is to convert the matrix format of the above-mentioned first padding matrix from a block storage format to a row-first data storage format. When the above-mentioned first matrix format is a block storage format and the second matrix format is a row-first data storage format, the implementation method of the above-mentioned S122 is to convert the matrix format of the above-mentioned first padding matrix from a row-first data storage format to a block storage format. Among them, the implementation method of converting the matrix format of the first padding matrix includes: updating the data arrangement method in the first padding matrix so that the data arrangement method in the updated first padding matrix (i.e., the first expected matrix) is the data arrangement method of the first matrix format; its specific implementation method refers to the prior art and will not be repeated here.

[0085] Exemplarily, when the second processing core in the heterogeneous processor has a high affinity for the block storage format, the block storage format is the first matrix format and the row-major data storage format is the second matrix format; in this case, the first processing core converts the matrix format of the first padded matrix from the row-major data storage format to the block storage format, thereby obtaining the first expected matrix. When the second processing core has a high affinity for the row-major data storage format, the row-major data storage format is the first matrix format and the block storage format is the second matrix format; in this case, the first processing core converts the matrix format of the first padded matrix from the block storage format to the row-major data storage format, thereby obtaining the first expected matrix.

[0086] Optionally, in one implementation, the execution subject of the above S122 can be other heterogeneous cores in the heterogeneous processor except the first processing core and the second processing core, or it can be a homogeneous processor (such as a CPU) in the computing device where the heterogeneous processor is located, or it can be other hardware in the computing device. The specific embodiments of this application do not specifically limit it.

[0087] S123 : The first processing core performs padding processing on the second input matrix to obtain a second padded matrix.

[0088] S124 : The first processing core converts the second padded matrix into a second expected matrix in the first matrix format.

[0089] It should be noted that the implementation method of the above S123-S124 is similar to the implementation method of S121-S122. For the specific description of S123-S124, please refer to the above description of S121-S122, which will not be repeated here.

[0090] S130: The second processing core obtains a first expected matrix and a second expected matrix.

[0091] The above-mentioned S130 can be implemented by the first processing core sending an acquisition notification to the second processing core; then, the second processing core obtains the above-mentioned first expected matrix and second expected matrix from the first processing core in response to the acquisition notification; or, after executing the above-mentioned S120, the first processing core sends the first expected matrix and second expected matrix to the second processing core, so that the second processing core receives the expected matrices (i.e., the first expected matrix and the second expected matrix).

[0092] S140 , the second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result.

[0093] For example, assuming that the first expected matrix includes [{2, 3, 8}, {9, 5, 0}], and the second expected matrix includes [{7, 4, 1}, {9, 0, 0}]; then, the first operation result M = 2×7+3×4+8×1+9×9+5×0+0×0, that is, the first operation result is 115.

[0094] It should be noted that, when the first input matrix and the second input matrix are one batch of N independent input matrices, the second processing core outputs the first operation result from the matrix multiplication operator after executing S140. When the first input matrix and the second input matrix are one batch of N sub-matrices of a batch of matrices to be processed, the second processing core further needs to calculate the sum of the operation results of the N batches of sub-matrices after S140 and output this sum as the operation result of the batch of matrices to be processed. Details are described in S310-S390 below and are not further described here.

[0095] A data processing method provided in an embodiment of the present application is applied in a heterogeneous processor including at least a first processing core and a second processing core. The method converts the first input matrix and the second input matrix of the input matrix multiplication operator obtained by the first processing core into first expected matrices and second expected matrices whose sizes are integer multiples of a preset size and whose matrix formats are in a first matrix format; so that the second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result. Among them, the computational efficiency of the second processing core for the matrix in the first matrix format is higher than the computational efficiency for the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; since the matrix multiplication operator is an operator running in a heterogeneous processor including at least the first processing core and the second processing core, and the first input matrix and the second input matrix are matrices of the input matrix multiplication operator, the conversion of the input matrix by the first processing core and the matrix multiplication operation of the second processing core on the expected matrix after conversion are both completed in the matrix multiplication operator; that is, the above embodiment converts the input matrix into a matrix whose size is an integer multiple of the preset size based on the first processing core in the above matrix multiplication operator, so it avoids the problem of taking a long time to convert the matrix format of the input matrix into the above first matrix format when the size of the input matrix is ​​not an integer multiple of the preset size, thereby improving the efficiency of the matrix multiplication operation.

[0096] In addition, since the above embodiment completes the conversion of the input matrix into the expected matrix by the first processing core and the matrix multiplication operation on the expected matrix by the second processing core within one operator (i.e., the matrix multiplication operator); therefore, after the first processing core converts the input matrix into the expected matrix, the above matrix multiplication operation will be directly performed within the second processing core; compared to the method of using two operators (i.e., one operator converts the input matrix into the expected matrix and outputs the expected matrix in the memory; then, the other operator moves the expected matrix from the memory to the processing core where the operator is located, and performs the matrix multiplication operation within the processing core), the efficiency of moving the expected matrix is ​​improved, thereby further improving the efficiency of the matrix multiplication operation.

[0097] Based on Figure 3 The data processing method shown in the embodiment of the present application provides a specific implementation method, which is applied in the scenario where the first input matrix and the second input matrix are a batch of input matrices in N batches of independent input matrices, such as Figure 7 As shown, the method includes: S210-S280.

[0098] S210 : The first processing core obtains an i-th input matrix from N batches of input matrices.

[0099] The N batches of input matrices are N batches of independent input matrices; wherein, a batch of input matrices includes at least two matrices that need to be multiplied.

[0100] The above-mentioned i-th input matrix is ​​the i-th input matrix among the above-mentioned N batches of input matrices; wherein the above-mentioned N and i are both positive integers, and i is less than or equal to N; the i-th input matrix includes: a third input matrix and a fourth input matrix.

[0101] S220 , the first processing core converts the i th input matrix into the i th expected matrix.

[0102] S230 : The second processing core obtains the i th expected matrix from the first processing core.

[0103] S240 , the second processing core performs a multiplication operation on the i th expected matrix to obtain an i th operation result.

[0104] It should be understood that, after executing S240 , the second processing core outputs the i-th operation result from the matrix multiplication operator.

[0105] It should be noted that the implementation method of the above S210-S240 is consistent with the implementation method of S110-S140. For the specific description of S210-S240, please refer to the above related description of S110-S140, which will not be repeated here.

[0106] S250 : The first processing core obtains the (i+1)th input matrix from the N batches of input matrices.

[0107] The above-mentioned i+1th input matrix is ​​the i+1th batch of input matrices among the above-mentioned N batches of input matrices; wherein i+1 is less than or equal to N.

[0108] S260 , the first processing core converts the (i+1)th input matrix into the (i+1)th expected matrix.

[0109] It should be noted that S250-S260 are executed simultaneously with the above-mentioned S240, and their specific implementation method is: after the first processing core outputs the above-mentioned i-th expected matrix, while the second processing core performs multiplication operation on the i-th expected matrix, the first processing core obtains the next batch of input matrices (i.e., the i+1-th input matrix) from the above-mentioned N batches of input matrices, and converts the i+1-th input matrix (i.e., converts the i+1-th input matrix into the i+1-th expected matrix); that is, before the current process (e.g., the process of processing the multiplication operation of the i-th input matrix) of the above-mentioned first processing core is completed, when the first processing core is in an idle state, the first processing core executes the tasks in the next process (e.g., the process of processing the multiplication operation of the i+1-th input matrix), that is, the first processing core and the second processing core process tasks asynchronously.

[0110] S270 : The second processing core obtains the (i+1)th expected matrix from the first processing core.

[0111] S280 , the second processing core performs a multiplication operation on the (i+1)th expected matrix to obtain an (i+1)th operation result.

[0112] It should be noted that, since the first processing core and the second processing core proposed in S260 process tasks asynchronously, while the second processing core executes S280, the first processing core performs the conversion processing on the (i+2)th batch of input matrices in the N batches of input matrices.

[0113] For example, Figure 8 As shown, the first processing core performs conversion processing on the i-th batch of input matrices in the time period from 0 to t1 (abbreviated as: 0-t1); the second processing core performs matrix multiplication operation on the i-th batch of input matrices (i.e., the i-th expected matrix) after being processed by the first processing core in the time period t1-t2, and outputs the operation results; at the same time, the first processing core performs conversion processing on the i+1-th batch of input matrices (i.e., the next batch of input matrices) in the t1-t2 time period; in the t2-t3 time period, the second processing core performs multiplication operation on the i+1-th batch of input matrices (i.e., the i+1-th expected matrix) after being processed by the first processing core in the t1-t2 time period, and outputs the operation results; at the same time, the first processing core processes the i+2-th batch of input matrices in the t2-t3 time period, and repeats in sequence until all the N batches of input matrices output the operation results.

[0114] It should be noted that the implementation method of the above S250-S280 is consistent with the implementation method of S110-S140. For the specific description of S250-S280, please refer to the above description of S110-S140, which will not be repeated here.

[0115] The above embodiment converts the input matrix into a matrix whose size is an integer multiple of the preset size based on the first processing core within the above matrix multiplication operator, thereby avoiding the problem of taking a long time to convert the matrix format of the input matrix into the above first matrix format when the size of the input matrix is ​​not an integer multiple of the preset size, thereby improving the efficiency of the matrix multiplication operation.

[0116] In addition, the above embodiment improves the efficiency of matrix multiplication operations by performing conversion processing on the (i+1)th batch of input matrices by the first processing core while the second processing core performs matrix multiplication operations on the (i)th batch of expected matrices after the conversion of the (i)th batch of input matrices, thereby avoiding waste of processing resources on the first processing core.

[0117] Based on Figure 3The data processing method shown in the embodiment of the present application provides another specific implementation method, which is applied in the scenario where the first input matrix and the second input matrix are a batch of sub-matrices in N batches of sub-matrices; wherein the N batches of sub-matrices are sub-matrices of a batch of matrices to be processed, such as Figure 9 As shown, the method includes: S310-S390.

[0118] S310 , the first processing core obtains an i th submatrix from the N batches of submatrices, and converts the i th submatrix into an i th expected matrix.

[0119] The above-mentioned i-th submatrix is ​​a batch of submatrices among the above-mentioned N batches of submatrices; wherein N and i are both positive integers, and i is less than or equal to N.

[0120] It should be noted that the above-mentioned i-th submatrix is ​​similar to the input matrix in S110. For the specific description of the i-th submatrix in S310, please refer to the above-mentioned description of the input matrix of S110 (such as the first input matrix and the second input matrix), which will not be repeated here.

[0121] It should be understood that the above-mentioned N batches of sub-matrices are sub-matrices of a batch of matrices to be processed. The N batches of sub-matrices can be sub-matrices obtained by the above-mentioned first processing core by dividing the batch of matrices to be processed into N batches (i.e., N batches of input matrices), or they can be obtained by dividing the matrix to be processed by other heterogeneous cores other than the first processing core and the second processing core in the heterogeneous processor where the first processing core is located, or they can be obtained by dividing the matrix to be processed by other hardware in the computing device where the heterogeneous processor is located. Specifically, the embodiment of the present application does not limit the execution entity of dividing the matrix to be processed into N batches of sub-matrices.

[0122] S320: The second processing core obtains the i-th expected matrix from the first processing core.

[0123] S330 : The second processing core performs a multiplication operation on the i-th expected matrix to obtain an i-th operation result.

[0124] It should be noted that the implementation method of the above S310-S330 is consistent with the implementation method of S110-S140. For the specific description of S310-S330, please refer to the above related description of S110-S140, which will not be repeated here.

[0125] S340: The second processing core determines whether i is equal to N.

[0126] When i is not equal to N, i is incremented by 1 and the following steps S350 to S380 are executed.

[0127] When the above i is equal to N, the following S390 is executed.

[0128] S350 : The first processing core obtains the i+1th submatrix from the N batches of submatrices, and converts the i+1th submatrix into the i+1th expected matrix.

[0129] It should be noted that S350 and the above-mentioned S330-S340 are executed simultaneously, and its specific implementation is similar to the implementation method of the simultaneous execution of S250-S260 and S240 proposed in the above-mentioned S260. For the specific description of the simultaneous execution of S350 and S330-S340 proposed in S350, please refer to the relevant description in the above-mentioned S260, which will not be repeated here.

[0130] S360: The second processing core obtains the (i+1)th expected matrix from the first processing core.

[0131] S370 , the second processing core performs a multiplication operation on the (i+1)th expected matrix to obtain an (i+1)th operation result.

[0132] S380: The second processing core determines whether i+1 is equal to N.

[0133] When the above i+1 is not equal to N, the above operations S310 to S340 are performed on the i+2 th sub-matrix, and the process is repeated until i+z is equal to N.

[0134] When the above i is equal to N, the following S390 is executed.

[0135] S390: The second processing core outputs the sum of the operation results of the N batches of sub-matrices.

[0136] The sum of the above operation results is the matrix multiplication operation result of the above matrix to be processed.

[0137] The specific implementation of the above S290 includes: the second processing core determines the sum of the operation results of N batches of sub-matrices (i.e., N operation results) as the matrix multiplication operation result of the above matrix to be processed, and outputs the matrix multiplication operation result of the matrix to be processed from the above matrix multiplication operator.

[0138] In the above embodiment, a batch of matrices to be processed is divided into N batches of sub-matrices. Then, the first processing core in the heterogeneous processor converts the sub-matrix (e.g., the i-th sub-matrix) into the i-th expected matrix whose size is an integer multiple of a preset size and whose matrix format is the first matrix format with a higher affinity for the second processing core (referred to as: conversion processing); thereafter, the second processing core performs a matrix multiplication operation on the i-th expected matrix to obtain an operation result; finally, the second processing core determines the sum of the operation results of the N batches of sub-matrices as the operation result of the matrix to be processed. Since the first processing core and the second processing core asynchronously process their respective tasks, that is, while the second processing core performs matrix multiplication on the i-th expected matrix after the i-th submatrix is ​​converted, the first processing core performs conversion processing on the i+1-th submatrix; thereby avoiding the problem of the matrix multiplication operation of the matrix to be processed being too large, resulting in a long time consumption, and also avoiding the waste of processing resources on the first processing core. It also avoids the problem of the matrix format of the submatrix being converted into the first matrix format when the size of the submatrix is ​​not an integer multiple of the preset size. Therefore, the efficiency of the matrix multiplication operation is improved.

[0139] The above mainly introduces the solution provided by the embodiment of the present application from the perspective of method. In order to realize the above functions, the data processing device includes a hardware structure and / or software module corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0140] In the embodiment of the present application, the data processing device can be divided into functional modules according to the above method. For example, the data processing device can include functional modules corresponding to the functional divisions, or two or more functions can be integrated into one processing module. The above-mentioned integrated modules can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical functional division. In actual implementation, there may be other division methods.

[0141] In the case of dividing each functional module into corresponding functional modules, Figure 10 A possible structural diagram of the data processing device involved in the above embodiment is shown. Figure 10 As shown, the data processing device includes: a transceiver unit 1010 and a processing unit 1020.

[0142] The transceiver unit 1010 is configured to obtain a first input matrix and a second input matrix of an input matrix multiplication operator; for example, executing step S110 in the above method embodiment.

[0143] The transceiver unit 1010 is further configured to obtain the first expected matrix and the second expected matrix; for example, by executing step S130 in the above method embodiment.

[0144] The processing unit 1020 is configured to perform a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result; for example, executing step S140 in the above method embodiment.

[0145] Optionally, the processing unit 1020 is configured to perform padding processing on the first input matrix to obtain a first padded matrix; for example, executing step S121 in the above method embodiment.

[0146] The processing unit 1020 is configured to convert the first padding matrix into a first expected matrix in a first matrix format; for example, by executing step S122 in the above method embodiment.

[0147] The transceiver unit 1010 is configured to obtain the first expected matrix in response to the acquisition notification sent by the first processing core; for example, executing step S130 in the above method embodiment.

[0148] Optionally, the processing unit 1020 is configured to perform padding processing on the first input matrix to obtain a first padded matrix when the first input matrix is ​​not a matrix whose size is an integer multiple of a preset size.

[0149] Optionally, the processing unit 1020 is configured to convert the (i+1)th batch of input matrices into the (i+1)th batch of expected matrices; for example, by executing step S260 in the above method embodiment.

[0150] Optionally, the processing unit 1020 is configured to perform a matrix multiplication operation on the (i+1)th batch of expected matrices to obtain a second operation result; for example, executing step S280 in the above method embodiment.

[0151] Optionally, the processing unit 1020 is configured to divide the matrix to be processed into N batches of input matrices.

[0152] Optionally, the processing unit 1020 is configured to determine the sum of the N operation results as the matrix multiplication operation result of the matrix to be processed.

[0153] The transceiver unit 1010 is used to output the matrix multiplication result; for example, to execute step S390 in the above method embodiment.

[0154] An embodiment of the present application provides a processor for running a program, wherein the program is executed when running to implement the method described in the above embodiment.

[0155] An embodiment of the present application provides a computing device including a memory and at least one processor connected to the memory, wherein the memory is used to store computer program code, and the computer program code includes computer instructions. When the computer instructions are executed by the at least one processor, the computing device executes the method described in the above embodiment.

[0156] An embodiment of the present application provides a computer-readable storage medium storing computer instructions. When the computer instructions are executed on a computer, the method described in the above embodiment is executed.

[0157] An embodiment of the present application provides a computer program product, which includes computer instructions. When the computer instructions are run on a computer, the method described in the above embodiment is executed.

[0158] An embodiment of the present application provides a chip including a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to call and run the computer instructions from the memory to execute the method described in the above embodiment.

[0159] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented using a software program, all or part of the embodiments may be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions in accordance with the embodiments of the present application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a magnetic disk, a magnetic tape), an optical medium (eg, a digital video disc (DVD)), or a semiconductor medium (eg, a solid state drive (SSD)).

[0160] Through the description of the above embodiments, those skilled in the art will clearly understand that for the sake of convenience and brevity, only the division of the above functional modules is used as an example. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0161] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0162] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0163] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0164] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as flash memory, mobile hard disk, read-only memory, random access memory, magnetic disk or optical disk.

[0165] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: The method is applied to a heterogeneous processor, the heterogeneous processor including at least a first processing core and a second processing core, and the method includes: The first processing core obtains a first input matrix and a second input matrix of an input matrix multiplication operator, the matrix multiplication operator being an operator running in the heterogeneous processor; The second processing core obtains a first expected matrix and a second expected matrix; the first expected matrix is ​​a matrix obtained by the first processing core converting the first input matrix, and the second expected matrix is ​​a matrix obtained by the first processing core converting the second input matrix, wherein the expected matrix is ​​a matrix whose size is an integer multiple of a preset size, and the matrix format of the expected matrix is ​​a first matrix format; the computation efficiency of the second processing core on the matrix in the first matrix format is higher than the computation efficiency of the second processing core on the matrix in the second matrix format, and the second matrix format is the matrix format of the input matrix; The second processing core performs a matrix multiplication operation on the first expected matrix and the second expected matrix to obtain a first operation result.

2. The method according to claim 1, characterized in that The second processing core obtains the first expected matrix, including: The first processing core performs padding processing on the first input matrix to obtain a first padded matrix; the first padded matrix is ​​a matrix whose size is an integer multiple of a preset size; The first processing core converts the first padded matrix into the first expected matrix in the first matrix format; The second processing core obtains the first expected matrix in response to the acquisition notification sent by the first processing core.

3. The method according to claim 2, characterized in that The first processing core performs padding processing on the first input matrix to obtain a first padded matrix, including: In a case where the first input matrix is ​​not a matrix whose size is an integer multiple of a preset size, the first processing core performs padding processing on the first input matrix to obtain the first padded matrix.

4. The method according to any one of claims 1 to 3, characterized in that The first input matrix and the second input matrix are the i-th batch of input matrices in N batches of input matrices, where N and i are both positive integers, and i is less than or equal to N, wherein a batch of input matrices includes at least two matrices that need to be multiplied.

5. The method according to claim 4, characterized in that After the first processing core converts the i-th batch of input matrices into the i-th batch of expected matrices and before the second processing core completes outputting the first operation result, the method includes: The first processing core converts the (i+1)th batch of input matrices into the (i+1)th batch of expected matrices.

6. The method according to claim 5, characterized in that After the second processing core outputs the first operation result, the method includes: The second processing core performs a matrix multiplication operation on the (i+1)th batch of expected matrices to obtain a second operation result.

7. The method according to any one of claims 4 to 6, characterized in that When the N batches of input matrices are submatrices of a batch of matrices to be processed, the method further includes: The first processing core divides the matrix to be processed into the N batches of input matrices.

8. The method according to claim 7, characterized in that After the second processing core obtains N operation results in N batches of input matrices, the method includes: The second processing core determines the sum of the N operation results as the matrix multiplication operation result of the matrix to be processed; The second processing core outputs the matrix multiplication result.

9. The method according to any one of claims 2 to 8, characterized in that: The matrix format includes at least: a row-major storage format or a block storage format.

10. A processor, characterized in that: The processor is configured to run a program, wherein the program executes the method according to any one of claims 1 to 9 when running.

11. A computing device, characterized in that The method comprises a memory and at least one processor connected to the memory, wherein the memory is used to store computer program code, and the computer program code comprises computer instructions. When the computer instructions are executed by the at least one processor, the computing device executes the method according to any one of claims 1 to 9.

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