Chip layout data processing method and device, computer equipment, readable storage medium and program product

Abstract

The invention relates to a chip layout data processing method. The method comprises the following steps: acquiring original data of a chip layout and preset chip information; screening the original data of the chip layout to obtain a bare crystal boundary data set, a bonding pad outer ring boundary data set and a signal network name data set; according to the bare crystal boundary data set and the bonding pad outer ring boundary data set, obtaining standard bare crystal boundary data corresponding to each chip type and standard bonding pad outer ring boundary data corresponding to each chip type; matching each piece of standard bare crystal boundary data, each piece of standard bonding pad outer circle boundary data and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type; and according to preset chip information, correcting the standard bonding pad outer ring boundary data and the signal network name in each standard chip layout data set to obtain target chip layout data. By adopting the method, accurate structured target chip layout data can be automatically obtained.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip layout data processing method, apparatus, computer equipment, computer-readable storage medium, and computer program product. Background Art

[0002] With the rapid advancement of semiconductor technology, the field of integrated circuit (IC) design is undergoing unprecedented transformation. Chip layout data, such as Graphic Data System II (GDS) files, are a key output in the chip design process, serving as a bridge between the chip design backend and the system-side packaging design and manufacturing phases. Because GDSII files contain precise geometric information about the chip layout design, such as mask patterns, layer definitions, and their spatial relationships, this information is crucial for subsequent manufacturing processes such as mask fabrication, lithography, and etching. Furthermore, GDSII files also contain key information such as solder bump names, attributes, and locations, which are crucial parameters for system-side packaging design.

[0003] In related technologies, traditional GDSII coordinate export is basically manual, that is, engineers manually check / hide layers in the layout image interface, measure the die border with a ruler, copy the pad outline, and click text coordinates one by one.

[0004] However, faced with increasingly complex design requirements and massive amounts of GDSII data, traditional processing and export methods can no longer meet the needs of actual applications, let alone achieve efficient and accurate applications. Summary of the Invention

[0005] Based on this, it is necessary to provide a chip layout data processing method, device, computer equipment, computer-readable storage medium and computer program product that can obtain structured target chip layout data in response to the above technical problems.

[0006] In a first aspect, the present application provides a chip layout data processing method, comprising:

[0007] Obtain chip layout raw data and preset chip information;

[0008] Screening the chip layout raw data to obtain a bare die boundary dataset, a pad outer circle boundary dataset, and a signal network name dataset;

[0009] Obtaining standard bare die boundary data corresponding to each chip type and standard pad outer circle boundary data corresponding to each chip type according to the bare die boundary data set and the pad outer circle boundary data set;

[0010] Matching each of the standard bare die boundary data, each of the standard pad outer circle boundary data, and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type;

[0011] According to the preset chip information, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain target chip layout data.

[0012] In one embodiment, obtaining the standard die boundary data corresponding to each chip type based on the die boundary dataset includes:

[0013] Get preset boundary conditions;

[0014] Calculating each die boundary data in the die boundary data set to obtain a layout boundary corresponding to each die boundary data;

[0015] Based on the preset boundary conditions and the layout boundary corresponding to each of the die boundary data, standard die boundary data corresponding to each chip type is obtained.

[0016] In one embodiment, obtaining the standard pad outer circle boundary data corresponding to each chip type based on the pad outer circle boundary data set includes:

[0017] Repeatability detection is performed on the pad outer circle boundary data in each of the pad outer circle boundary data sets to obtain standard pad outer circle boundary data corresponding to each chip type.

[0018] In one embodiment, the standard die boundary data, the standard pad outer circle boundary data, and the signal net name data set are matched to obtain a standard chip layout data set corresponding to each chip type, including:

[0019] Calculating the die boundary coordinates of each of the standard die boundary data, calculating the pad outer circle diameter of each of the standard pad outer circle boundary data, calculating the pad coordinates of each of the standard pad outer circle boundary data, and calculating the network name coordinates of each signal network name in the signal network name data set;

[0020] Perform correlation matching on each of the network name coordinates and each of the pad coordinates to obtain each reference data set;

[0021] According to the standard pad outer circle boundary data, each reference data set and each die boundary coordinate are combined to obtain each standard chip layout data set.

[0022] In one embodiment, the above-mentioned matching of each reference data set with each die boundary coordinate according to the standard pad outer circle boundary data to obtain each standard chip layout data set includes:

[0023] Scaling each of the network name coordinates according to a preset scaling factor to obtain each standard network name;

[0024] Based on each of the pad coordinates, obtaining the coordinates of one or more of the standard network names adjacent to each of the pad coordinates;

[0025] Calculating each distance according to the coordinates of each pad and the coordinates of each standard network name;

[0026] Each of the distances is compared with a preset likelihood threshold to obtain the network name coordinates corresponding to each of the pad coordinates, thereby obtaining each of the reference data sets.

[0027] In one embodiment, after obtaining each standard chip layout data set by combining each reference data set with each die boundary coordinate according to the standard pad outer circle boundary data, the method further includes:

[0028] Get the optical zoom factor;

[0029] The die boundary coordinates, the pad outer diameter, and the net name coordinates in each of the standard chip layout data sets are converted into a package coordinate system according to the optical zoom factor.

[0030] In one embodiment, after obtaining the original chip layout data and the preset chip information, the method further includes:

[0031] Performing mirror processing on the original data of the chip layout;

[0032] The mirror processing is to rotate the original chip layout data when the packaging type of the original chip layout data is flip-stick packaging.

[0033] In one embodiment, the preset chip information includes pad positions and target network information; according to the preset chip information table, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain the target chip layout data, including:

[0034] Use the pad position to check the correctness of the pad outer circle boundary data;

[0035] When the correctness check passes, the target network information is used to correct the signal network name in each of the standard chip layout data groups to obtain the target chip layout data.

[0036] In one embodiment, the target network information is used to correct the signal network name in each standard chip layout data set to obtain the target chip layout data, including:

[0037] Searching the target network information according to the signal network name in each of the standard chip layout data groups to obtain a target network name corresponding to the signal network name;

[0038] The target chip layout data is obtained by replacing the signal network name in each of the standard chip layout data groups using the target network name.

[0039] In a second aspect, the present application further provides a chip layout data processing device, comprising:

[0040] The acquisition module is used to obtain the original data of the chip layout and the preset chip information;

[0041] A screening module is used to screen the chip layout raw data to obtain a bare die boundary data set, a pad outer circle boundary data set, and a signal network name data set;

[0042] A classification module is used to standardize the bare die boundary data set and the pad outer circle boundary data set to obtain standard bare die boundary data corresponding to each chip type and standard pad outer circle boundary data corresponding to each chip type;

[0043] A matching module, configured to match each of the standard die boundary data, each of the standard pad outer circle boundary data, and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type;

[0044] The correction module is used to correct the standard pad outer circle boundary data and the signal network name in each standard chip layout data group according to the preset chip information to obtain target chip layout data.

[0045] In a third aspect, the present application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method in any one of the above embodiments when executing the computer program.

[0046] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the method in any one of the above embodiments when the computer program is executed by a processor.

[0047] In a fifth aspect, the present application also provides a computer program product, comprising a computer program, which implements the steps of the method in any one of the above embodiments when executed by a processor.

[0048] The above-mentioned chip layout data processing method, device, computer equipment, computer-readable storage medium and computer program product first screen the chip layout original data to obtain the bare die boundary data set, the pad outer circle boundary data set and the signal network name data set, and then perform corresponding processing based on the bare die boundary data set, the pad outer circle boundary data set and the signal network name data set to obtain the standard pad outer circle boundary data corresponding to each chip type. After that, each standard bare die boundary data, each standard pad outer circle boundary data and the signal network name data set are matched to obtain the standard chip layout data group corresponding to each chip type. Finally, according to the preset chip information, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain the target chip layout data, which can automatically obtain the structured target chip layout data corresponding to each chip type. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments of the present application or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying any creative work.

[0050] Figure 1 1 is a flow chart of a chip layout data processing method according to an embodiment;

[0051] Figure 2 A schematic diagram of the locations of pads and signal net names in one embodiment;

[0052] Figure 3 A schematic diagram of the locations of pads and signal net names in another embodiment;

[0053] Figure 4 A schematic diagram of the positions of pads and signal net names in another embodiment;

[0054] Figure 5 A schematic diagram of matching pads with network signal names in one embodiment;

[0055] Figure 6 is a flowchart of the steps of chip layout data processing in an exemplary embodiment;

[0056] Figure 7 is a flowchart of the steps of chip layout data processing in another exemplary embodiment;

[0057] Figure 8 A structural block diagram of a chip layout data processing device in one embodiment;

[0058] Figure 9 FIG. 1 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0060] In one embodiment, Figure 1 As shown, a chip layout data processing method is provided. This embodiment uses the method applied to a terminal as an example for illustration. It is understandable that the method can also be applied to a server, or to a system including a terminal and a server, and implemented through the interaction between the terminal and the server. In this embodiment, the method includes the following steps:

[0061] Step 102: Obtain chip layout original data and preset chip information.

[0062] The chip layout raw data refers to the layout file data extracted from the chip design, which can be GDSII data or layout data in other formats, such as OASIS or DXF.

[0063] GDSII data includes various types of layout elements, such as die boundaries, solder bumps, signal network names, etc. The data format is usually complex and messy, containing a large amount of redundant information and unnecessary levels. It needs to be filtered, cleaned and formatted to effectively extract useful information for subsequent processing.

[0064] The preset chip information refers to the information that summarizes all signal network names that appear in the RTL / IP / package scripts at all levels of the entire chip.

[0065] Optionally, the preset chip information can be obtained by obtaining a dataset of classic signal network names containing classic chip data, then deleting duplicate data from the dataset to obtain the initial preset chip information. Due to the characteristics of chip signal networks, signal network names are typically unique, while power-related network names are likely to have many duplicates. Therefore, deleting these duplicate network names can significantly simplify subsequent processing and reduce the probability of errors.

[0066] Afterwards, the initial preset chip information is formatted into two columns of data: the IP network name on the left and the general signal network name on the right, and finally the complete preset chip information is obtained.

[0067] The network name of the IP is on the left. This is used to compare the network names on many chip IPs. After confirming that the information is correct, the signal network name on the GDS is used as the final version. At the same time, the universal network name on the right is the value. It is the signal network name used for hardware system design in the actual chip specification and documents. This network name is generally inconsistent with the previous IP network name.

[0068] For example, the raw chip layout data can be a GDS file. A GDS file is a layout data file used for tapeout after IC design is completed. It records all details, including a mask layer, wiring, device shape, logic cells, metal interconnects, etc. Optionally, a GDS file typically corresponds to only one chip.

[0069] Step 104 , screening the original chip layout data to obtain a bare die boundary data set, a pad outer circle boundary data set, and a signal net name data set.

[0070] The purpose of step 104 is to remove non-critical information from the original data of the chip layout. Among them, non-critical information refers to data other than the boundary data of the bare crystal, the outer circle boundary data of the pad, and the signal network name data. As mentioned above, there is a large amount of redundant information in the GDS file, which is very unfavorable for the design of the chip package. Not only is it easy to cause errors, but a large amount of data will seriously slow down the processing speed. Therefore, in this embodiment, the GDS file will be greatly deleted, the unused design data will be removed, the network names of the layers and signals that will not be used, and the redundant routing information between the BUMPs will be deleted.

[0071] The die boundary dataset represents the physical outline of the die, typically represented by a BOUNDARY element. Within the GDS file, this element is typically located at a specific layer and datatype. Optionally, you can filter all BOUNDARY elements in the GDS file; these typically appear at a specific layer, such as Layer 66.

[0072] The pad outer circle dataset is used to describe bumps. Optionally, you can filter all BOUNDARY or PATH elements in the GDS, which typically appear in Layer 70 (pad outer circle).

[0073] Signal net names are typically used to identify individual signals. By filtering the coordinate and name data within the TEXT element, a signal net name dataset is obtained. Alternatively, you can filter the TEXT element within the GDS, which is typically used to represent signal net names and is located in Layer 5 (Signal Label).

[0074] Step 106 : Obtain standard bare die boundary data corresponding to each chip type and standard pad outer circle boundary data corresponding to each chip type based on the bare die boundary data set and the pad outer circle boundary data set.

[0075] Because the die boundary dataset may include not only the actual chip frame but also other auxiliary graphics, such as the borders of multiple test chips, alignment frames, and spare chips, all die boundary data is unified into a single, standard die boundary data in step 106. A chip typically has only one unique die boundary, so after standardizing the die boundary dataset, standard die boundary data corresponding to one or more chip types is obtained.

[0076] Alternatively, standard die boundary data that can represent a chip type may be selected from the die boundary data set using a geometric method.

[0077] Similarly, since the pad outer circle boundary dataset may contain multiple pads of similar shapes, such as multiple repeated pad outer circle patterns, these repeated patterns may represent the same type of pads. Therefore, standard pad outer circle boundary data corresponding to each chip type can be generated based on these repeated pad outer circle patterns.

[0078] Step 108 : Match each standard die boundary data, each standard pad outer circle boundary data, and the signal net name data set to obtain a standard chip layout data set corresponding to each chip type.

[0079] To ensure that in the subsequent packaging and testing processes, each layout element, namely the bare die boundary, pad outer circle, and signal network name, corresponds one to one, a standard chip layout data set corresponding to each chip type is obtained, thereby avoiding incorrect connections, misalignment or redundancy.

[0080] Optionally, the coordinates of each standard die boundary data, each standard pad outer circle boundary data, and each signal net name in the signal net name data set may be calculated and matched using the coordinates.

[0081] Alternatively, pairing can be performed using overlapping area matching. For example, the geometry of the pad's outer ring is checked for overlap with the text box of the signal net name, and the pad and net name with the largest overlapping area are selected as matching pairs, ensuring a good spatial match between each pad and signal name.

[0082] Alternatively, you can use a pre-set mapping table for matching. If you have a standardized mapping table that includes the standard signal names for each pad, you can directly search and match the signal net name with the pad outer ring data. This method is more efficient and avoids redundant geometry calculations.

[0083] Step 110 , correcting the signal net name in each standard chip layout data set according to the preset chip information to obtain target chip layout data.

[0084] Due to various reasons, the same solder bump may have different signal net names. Although the meanings are similar, the excessive number of signal net names inevitably leads to errors during comparison and processing. On the other hand, the packaging system design side cannot use these net names, resulting in a mismatch between the two. Therefore, signal correction is required to facilitate subsequent packaging design and even motherboard design.

[0085] Using the unified signal network names in the preset chip information, the signal network names in each standard chip layout data set are corrected to obtain the target chip layout data. The target chip layout data includes the standard die boundary data, the pad outer circle boundary data, and the corrected signal network names.

[0086] In the above chip layout data processing method, the chip layout original data is first screened to obtain the bare die boundary data set, the pad outer circle boundary data set and the signal network name data set, and then the bare die boundary data set, the pad outer circle boundary data set and the signal network name data set are processed accordingly to obtain the standard pad outer circle boundary data corresponding to each chip type. After that, each standard bare die boundary data, each standard pad outer circle boundary data and the signal network name data set are matched to obtain the standard chip layout data group corresponding to each chip type. Finally, according to the preset chip information, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain the target chip layout data, and the structured target chip layout data corresponding to each chip type can be automatically obtained.

[0087] Furthermore, in one embodiment, based on the die boundary data set, standard die boundary data corresponding to each chip type is obtained, including: obtaining preset boundary conditions; calculating each die boundary data in the die boundary data set to obtain the layout boundary corresponding to each die boundary data; based on the preset boundary conditions and the layout boundary corresponding to each die boundary data, standard die boundary data corresponding to each chip type is obtained.

[0088] The preset boundary condition refers to the standard for selecting the die boundary data. For example, it can be the largest and unique matrix, that is, selecting the largest, regular and unique rectangle as the die boundary. It can also be a minimum bounding matrix or a specific geometric shape. The minimum bounding rectangle refers to calculating the minimum bounding rectangle for each die boundary data and selecting the largest and most representative rectangle as the standard boundary. The specific geometric shape refers to the requirement that the boundary of certain special chip types conform to certain specific geometric shapes, such as polygons.

[0089] Specifically, geometric calculations are performed on each die boundary data to obtain the corresponding layout boundary. Then, based on the preset boundary conditions, the standard die boundary data corresponding to each chip type is obtained.

[0090] Exemplarily, assuming that the preset boundary condition is the largest and unique rectangle, the die boundary data set includes the following four types of die boundary data, the layout boundary corresponding to each die boundary data is calculated, and the largest and unique matrix is ​​selected from the above four layout boundaries as the corresponding standard die boundary data.

[0091] Furthermore, in one embodiment, based on the pad outer circle boundary data set, standard pad outer circle boundary data corresponding to each chip type is obtained, including: performing repeatability detection on the pad outer circle boundary data in each pad outer circle boundary data set to obtain standard pad outer circle boundary data corresponding to each chip type.

[0092] According to the characteristics and design requirements of the chip, usually each chip type will only use one type of BUMP pad. Therefore, in this embodiment, repeatability detection is performed to obtain the standard pad outer circle boundary data corresponding to each chip type.

[0093] Optionally, geometric features such as radius, side length, and angle are first extracted from the pad outer circle boundary data. If multiple pads have the same geometric features, for example, circular pads with a diameter of 50µm, they can be determined to be the same type of pad outer circle.

[0094] Optionally, a clustering algorithm, such as K-means clustering, may be used to identify repeated patterns and find the patterns that appear the most times. These patterns are the outer circles of the standard pads.

[0095] In one embodiment, each standard bare die boundary data, each standard pad outer circle boundary data and signal network name data set are matched to obtain a standard chip layout data set corresponding to each chip type, including: calculating the bare die boundary coordinates of each standard bare die boundary data, calculating the pad outer circle diameter of each standard pad outer circle boundary data, calculating the pad coordinates of each standard pad outer circle boundary data, and calculating the network name coordinates of each signal network name in the signal network name data set; performing correlation matching on each network name coordinate and each pad coordinate to obtain each reference data set; matching each reference data set with each bare die boundary coordinate according to the standard pad outer circle boundary data to obtain each standard chip layout data set.

[0096] When matching the standard die boundary data, pad outer circle boundary data, and signal net names, the bumps and net signal names are first matched based on the pad outer circle boundary data and signal net names to obtain each reference data set. The reference data set is then matched with the die boundary coordinates to obtain the standard chip layout data set.

[0097] Optionally, the corresponding die boundary coordinates are calculated based on each standard die boundary data. The die boundary coordinates may be center point coordinates or corner point coordinates of the die, ie, the four vertex positions of the die outer frame.

[0098] Optionally, the corresponding pad outer circle diameter and pad coordinates are calculated based on each standard pad outer circle boundary data, wherein the pad coordinates can be the center point coordinates or any point on the pad.

[0099] Optionally, the network name coordinates corresponding to each signal network name are calculated based on the signal network name data set, which may be the center point coordinates or the lower left corner coordinates.

[0100] Afterwards, a calculation can be performed based on the network name coordinates and the coordinates of each pad to obtain the distance between the bump and the network signal name, and the signal network name and the bump can be matched according to the distance to obtain a reference data set.

[0101] Once the net signal name is matched to the bump, the next step is to determine which die the bump is on. Optionally, each reference data set can be matched to each die boundary coordinate by determining whether the bump is within the corresponding rectangular range of the die to obtain each standard chip layout data set.

[0102] For example, the pad coordinates are checked to be between min_x and max_x and min_y and max_y, where min_x and max_x and min_y and max_y are the length and width ranges of the rectangle respectively.

[0103] Combine Figure 2 , Figure 2 Figure 1 is a schematic diagram showing the locations of pads and signal net names in one embodiment. Figure 2 In the example above, the possible signal network will be significantly offset from the center of the bump pad, which is very disadvantageous for subsequent processing and can easily lead to mismatching or mismatching. Therefore, it is necessary to process the data.

[0104] Therefore, further, in one embodiment, correlation matching is performed based on each network name coordinate and each pad coordinate to obtain each reference data group, including: scaling each network name coordinate according to a preset proportional coefficient to obtain each standard network name; based on each pad coordinate, obtaining the coordinates of one or more standard network names adjacent to each pad coordinate; calculating each distance based on each pad coordinate and the coordinates of each standard network name; comparing each distance with a preset likelihood threshold to obtain the network name coordinate corresponding to each pad coordinate, and obtaining each reference data group.

[0105] The preset scaling factor is pre-set and used to scale each network signal name to obtain a scaled network signal name, that is, a standard network name.

[0106] For example, combined Figure 3 , Figure 3 Schematic diagram of the positions of pads and signal net names in another embodiment. Figure 3 The signal network name in the diagram is a schematic diagram of the position between the pad and the signal network name after being reduced by a preset scale factor of 0.5.

[0107] Optionally, for more intuitive calculation and viewing, the signal network name is sometimes processed. In addition to scaling by setting the scale factor, the entire or part of the signal network name is offset to a certain extent so that all signal network names are located at the center of the bump, such as Figure 4 As shown, this processing will look more intuitive. In which, the network signal name is offset by presetting the offset data.

[0108] Then, based on the pad coordinates, one or more standard network names adjacent to the pad coordinates are obtained. Figure 5 , Figure 5 A schematic diagram of matching pads with network signal names in one embodiment.

[0109] like Figure 5 As shown, grab the bump center point OB_1, and then grab the center point coordinates of the surrounding signal network names, such as ON_1, ON_2, and ON_3.

[0110] Optionally, next, calculate the difference between the coordinates of the bump center point OB_1 and the coordinates of the standard network names, such as ON_1, ON_2, and ON_3. When calculating, first take the absolute difference of the X coordinates, then take the absolute difference of the Y coordinates. Then, calculate the total difference between the bump center coordinates and the coordinates of each standard network name. The specific calculation process is shown in formula (1).

[0111] Formula (1)

[0112] in, is the absolute value difference of the X coordinates, is the absolute value difference of the Y coordinates. It is the straight-line distance between the BUMP and the signal network name coordinates.

[0113] Afterwards, the distance is compared with a preset likelihood threshold to obtain the network name coordinates corresponding to each pad coordinate, thereby obtaining each reference data set.

[0114] Exemplarily, assuming that the preset likelihood threshold is 1.0, if the distance is less than or equal to the preset likelihood threshold, it is considered that the BUMP and the signal network name match.

[0115] In one embodiment, after obtaining each standard chip layout data group based on the standard pad outer circle boundary data, each reference data group and each bare die boundary coordinate are combined, the method further includes: obtaining an optical zoom coefficient; and converting the bare die boundary coordinates, pad outer circle diameter, and network name coordinates in each standard chip layout data group into a package coordinate system based on the optical zoom coefficient.

[0116] Among them, the optical zoom factor is a key parameter used to adjust the layout size in the chip manufacturing process, which is determined by the optical characteristics of the manufacturing process.

[0117] During the photolithography process, due to optical errors and processing errors, the actual chip size will differ from the designed size. To compensate for this error, an optical scaling factor is applied to the design data to scale it up proportionally.

[0118] In this embodiment, the die boundary coordinates, pad outer diameter, and net name coordinates in each standard chip layout data set are scaled according to the optical scaling factor. Alternatively, the optical scaling factor may be directly multiplied by the die boundary coordinates, pad outer diameter, and net name coordinates to perform scaling.

[0119] Through these transformations, all elements in the standard chip layout data set can be adjusted to the package coordinate system to meet the size and position requirements in the actual manufacturing process.

[0120] In one embodiment, after obtaining the original chip layout data and the preset chip information, it also includes: mirroring the original chip layout data; the mirroring process is to rotate the original chip layout data when the packaging type of the original chip layout data is flip-stick packaging.

[0121] When mirroring raw chip layout data, it's necessary to first determine the chip's packaging type. While chip packaging varies widely, there are essentially two types based on the chip's essential characteristics: wire bond and flip chip. These two types of packaging directly influence the subsequent processing flow. According to actual chip production processes, wire bond chip packaging does not require mirroring during design, while flip chip packaging does. Consequently, there's the question of whether the GDS data needs to be flipped 180 degrees.

[0122] Optionally, the package type may be determined by the GDS file identifier. GDSII includes comments on the package type, and the package type may be determined by reading the comments.

[0123] Alternatively, the package type can be determined by the pad layout. If the pad arrangement in the chip design has a specific directionality and no mirror images, it may be a wire bond package. If the pads are symmetrically distributed, it may be a flip chip package. Typically, the pad array in a flip chip package is symmetrical.

[0124] In one embodiment, according to the preset chip information table, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain the target chip layout data, including: when the correctness check passes, the preset chip information is used to correct the signal network name in each standard chip layout data group to obtain the target chip layout data.

[0125] Before correcting the signal net name in each standard chip layout data set, it is first determined whether the standard pad outer circle boundary data in each standard chip layout data set is correct.

[0126] When the correctness check passes, the preset chip information is used to correct the signal network name in each standard chip layout data group to obtain the target chip layout data.

[0127] Furthermore, in one embodiment, the target network information is used to correct the signal network name in each standard chip layout data group to obtain the target chip layout data, including: searching in the preset chip information according to the signal network name in each standard chip layout data group to obtain the target network name corresponding to the signal network name; using the target network name, replacing the signal network name in each standard chip layout data group to obtain the target chip layout data.

[0128] Because the preset chip information consists of two columns, the IP network name on the left and the general signal network name on the right, we can search the preset chip information based on the signal network name in each standard chip layout data set to obtain the target network name corresponding to the signal network name. We can then replace the target network name with the found target network name to obtain the target chip layout data.

[0129] Optionally, after obtaining the target chip layout data, the target chip layout data is rechecked using preset chip information.

[0130] In one exemplary embodiment, in combination Figure 6 as well as Figure 7 As shown, Figure 6 as well as Figure 7 The figure is a flowchart of the steps of chip layout data processing in one embodiment.

[0131] The first step is to import the original GDS file, which is the raw chip layout data. This imported GDS file may contain a large amount of internal chip connection data and is a key indicator of chip design completion. However, packaging and system design do not require such a large amount of data. They only need key information such as the chip AP layer representing the chip size, the size and location of the bumps (pads), and the corresponding net names of the bumps. Therefore, data preprocessing is essential.

[0132] The second step is GDS data preprocessing. As mentioned earlier, GDS files contain a large amount of redundant information for packaging and system design, which is very detrimental to chip packaging design. Not only is it prone to errors, but the large amount of data can seriously slow down processing. This step will significantly reduce the GDS file based on the key information mentioned above, removing unused design data, deleting net names for unused layers and signals, and deleting redundant routing information between bumps.

[0133] The third step is to determine the general package type. While chip packages vary widely and come in many varieties, they are essentially categorized into two types based on their essential characteristics: wire bond and flip chip. These two types of packages directly determine the subsequent processing flow. According to actual chip production processes, wire bond chip packages do not require mirroring during design, while flip chip packages do require mirroring. Consequently, there's the question of whether the GDS data needs to be flipped 180 degrees. Mistakes in this step can directly lead to design failure, so it's crucial to anticipate and plan ahead.

[0134] The fourth step is to determine whether the GDS data needs to be mirrored based on the chip package type. As mentioned earlier, if the chip package is a wire bond type, the chip does not need to be mirrored; if the chip type is a flip chip type, the chip does need to be mirrored.

[0135] The fifth step is to determine the data type in the GDS and process important data. The pre-processed data mainly contains information used for subsequent packaging.

[0136] The sixth step is to find the key data of GDS. It is necessary to find three types of important data of GDS: find the border data of DIE, which is the original cutting size of the core particle DIE, that is, the bare crystal boundary data set mentioned in the above embodiment; find the outer circle graphic of the bump, that is, the outer circle boundary data set of the pad in the above embodiment. This is the actual size of the bump, which is equivalent to the size of the bump pad and will serve as a key reference factor for selecting BUMP; finally, find the network name of the signal, that is, the signal network name data set mentioned in the above embodiment. A simple BUMP without a signal network name is meaningless and cannot be used in actual engineering design, so extracting the network name of the signal is important and critical.

[0137] The seventh step is to process the key data found previously. The DIE border pattern is found and the largest, unique rectangle is calculated, which serves as the DIE outline (layout boundary). A chip has only one outline. This characteristic can be used to determine the outer boundary of the DIE core. This is the original DIE size and serves as an important basis for later chip cutting and placement in chip package design. It is generally placed at the center of the core's DIE.

[0138] The outer circle of the bump is found and repeated patterns are calculated as the outer circle boundary of the bump pad. Due to the characteristics of the chip, there is generally only one type of bump, so the repeated patterns in the scanned file are extracted as the outer circle boundary of the chip bump.

[0139] The network name of the signal will be found and the center point coordinates of the network name of the signal will be calculated. Each network name of the signal corresponds to a unique center point coordinate.

[0140] Step 8: Calculate the corresponding coordinates and check the correlation between the signal network name and the coordinates. Calculate the corresponding coordinates OA for the dieoutlie found in the previous step. Use the outer circle of the bump as the size of the bump and calculate the outer circle's diameter OD, which serves as an important basis for constructing the bump pad size. Also, calculate the bump's center point OB as the center point of the bump. Furthermore, compare the correlation between OB and the center point ON of the signal network. Pairwise match ON and OB with the highest correlation.

[0141] This is a critical step because it involves adjusting the signal network name size to match the bump pad size. To illustrate this issue in detail, the actual GDS data case is as follows: Figure 2 In the example, the possible signal network will be significantly offset from the center of the bump pad, which is very disadvantageous for subsequent processing and may easily lead to mismatching or mismatching. Therefore, it is necessary to process the data. The method of this embodiment is to scale the signal network name. For example, this embodiment will set a scale factor for the signal network name, such as 0.5, and scale it to Figure 3 Of course, in order to make calculation and viewing more intuitive, the signal network name is sometimes processed. In addition to scaling by setting the proportional coefficient, the entire or part of the signal network name is offset to make all the signal network names at the center of the bump, such as Figure 4 For example, this approach will seem more intuitive.

[0142] Step 9: Set the correlation likelihood threshold for ON and OB based on the actual chip. Adjust the correlation likelihood threshold to pairwise match the net name corresponding to the center point of the signal net name with the bump corresponding to the center point of the signal bump. Note that the signal net name is often offset and cannot be used as the center point of the signal bump, so this step is essential.

[0143] As shown in the figure, the implementation method will capture the bump center point OB_1, and then capture the center point coordinates of the surrounding signal network names, such as ON_1, ON_2, ON_3... Then, the coordinates are compared, the absolute value is taken, and after comparing with 1, the absolute value is taken again. Then, the coordinate ON_1 closest to the likelihood threshold is found, the two coordinates are matched, and the correspondence is completed.

[0144] Step 10: Construct the key array Adie for the DIE chip. Assign the most relevant net name to the center point of the bump. Associate the signal net name with the bump to form the array OC. Next, combine the DIE outline coordinates OA, the array OC consisting of the signal net and center point, and the bump pad size coordinates OD to form the key array Adie for the DIE chip. This provides critical information for chip package design.

[0145] The eleventh step is to define the shrinkage (optical scaling) coefficient K according to the process requirements of chip manufacturing. Different chip manufacturing processes have completely different optical shrinkage coefficients, which will directly affect the overall coordinate parameters of the DIE core particle.

[0146] In step 12, the DIE key array Adie is scaled down using the scale factor K, which is the preset scale factor mentioned in the above embodiment.

[0147] Step 13: Extract the coordinates in the array: OA1, OC1, OD1. This is the actual coordinate array required for the final package.

[0148] Step 12: Export GDS data. According to the package encapsulation requirements, export GDS data in the format, usually in .txt format.

[0149] Afterwards, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected according to the preset chip information.

[0150] The first step is to prepare the signal network names of the chip golden (classic data). This file is a summary of the signal network names at each level of the chip design.

[0151] The second step is to delete the duplicates and create the file ARYnn. Due to the chip's signal network characteristics, signal network names are unique, while power-related network names are likely to have many duplicates. Deleting these duplicate network names greatly simplifies subsequent processing and significantly reduces the probability of errors. Furthermore, the previously unprocessed DIE core data, DIE_dataA, is read synchronously.

[0152] The third step is to process ARYnn, with the IP network name on the left and the general signal network name on the right, saving them as a dictionary array DICnn. The IP network name on the left is used to compare the network names on numerous chip IPs. After confirming the information is correct, the signal network name on the GDS is used as the final version. Furthermore, the general network name with a label is the value, which is the general signal network name used in the actual chip specifications and documents. This is generally used to facilitate hardware system design and is generally inconsistent with the IP network name. Furthermore, the correctness of the DIE_dataA bump is determined. If it is incorrect, it is processed and saved as DIE_dataB.

[0153] The fourth step is to check whether the signal network to be tested exists using the constructed dictionary DICnn. For the DIE_dataB data, read each row of data in turn and extract the signal network name data NET_N in the corresponding column. Then, check whether NET_N exists using the constructed dictionary DICnn.

[0154] Step 5: If the above check does not exist, check whether the chip design process is correct and whether the signal network exists. If there is a missing or an error is found, it needs to be updated and checked again. If the above check is judged as YES.

[0155] Step 6: Search the dictionary and update the data. Search the dictionary file and replace the signal net name with a generic signal net name. This is the file used in the actual package design. Then, repeat the dictionary search and update the data based on the search results. Define the updated die data as DIE_dataC.

[0156] Step 7: Check the target data DIE_dataC and compare it with the constructed dictionary file. If any errors are found, update it and check again.

[0157] In step 8, if no error is found and the data is confirmed to be correct, the data is used as the final file DIE_dataD and the process ends.

[0158] It should be understood that, although each step in the flowcharts involved in each embodiment described above is displayed in sequence as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the flowcharts involved in each embodiment described above may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0159] Based on the same inventive concept, embodiments of the present application also provide a chip layout data processing device for implementing the aforementioned chip layout data processing method. The solution provided by this device is similar to the solution described in the aforementioned method. Therefore, the specific limitations of one or more chip layout data processing device embodiments provided below can be found in the aforementioned limitations of the chip layout data processing method and will not be further elaborated here.

[0160] In an exemplary embodiment, Figure 8 As shown, a chip layout data processing device is provided, comprising: an acquisition module 100, a screening module 200, a classification module 300, a matching module 400 and a correction module 500, wherein:

[0161] The acquisition module is used to obtain the original data of the chip layout and the preset chip information;

[0162] The screening module is used to screen the original chip layout data to obtain the bare die boundary data set, the pad outer circle boundary data set and the signal network name data set.

[0163] The classification module is used to standardize the bare die boundary data set and the pad outer circle boundary data set to obtain the standard bare die boundary data corresponding to each chip type and the standard pad outer circle boundary data corresponding to each chip type.

[0164] The matching module is used to match each standard bare die boundary data, each standard pad outer circle boundary data and the signal network name data set to obtain the standard chip layout data set corresponding to each chip type.

[0165] The correction module is used to correct the standard pad outer circle boundary data and signal network name in each standard chip layout data group according to the preset chip information to obtain the target chip layout data.

[0166] In one embodiment, the classification module includes:

[0167] The condition acquisition unit is used to acquire preset boundary conditions.

[0168] The boundary calculation unit is used to calculate each bare die boundary data in the bare die boundary data set to obtain the layout boundary corresponding to each bare die boundary data.

[0169] The first classification unit is configured to obtain standard bare die boundary data corresponding to each chip type based on preset boundary conditions and a layout boundary corresponding to each bare die boundary data.

[0170] In one embodiment, the classification module includes:

[0171] The repeatability detection unit is used to perform repeatability detection on the pad outer circle boundary data in each pad outer circle boundary data set to obtain standard pad outer circle boundary data corresponding to each chip type.

[0172] In one embodiment, the matching module includes:

[0173] The coordinate calculation unit is used to calculate the bare die boundary coordinates of each standard bare die boundary data, calculate the pad outer circle diameter of each standard pad outer circle boundary data, calculate the pad coordinates of each standard pad outer circle boundary data, and calculate the network name coordinates of each signal network name in the signal network name data set.

[0174] The first correlation matching unit is used to perform correlation matching on each network name coordinate and each pad coordinate to obtain each reference data group.

[0175] The second correlation matching unit is used to perform correlation matching on each reference data set and each bare die boundary coordinate according to the standard pad outer circle boundary data to obtain each standard chip layout data set.

[0176] In one embodiment, the first relevance matching unit includes:

[0177] The scaling subunit is used to scale the coordinates of each network name according to a preset scale factor to obtain each standard network name.

[0178] The adjacent coordinate acquisition subunit is used to obtain the coordinates of one or more standard network names adjacent to each pad coordinate based on each pad coordinate.

[0179] The distance calculation subunit is used to calculate each distance according to the coordinates of each pad and the coordinates of each standard network name.

[0180] The comparison subunit is used to compare each distance with a preset likelihood threshold to obtain the network name coordinates corresponding to each pad coordinate and obtain each reference data group.

[0181] In one embodiment, the matching module further includes:

[0182] The coefficient acquisition unit is used to obtain the optical zoom coefficient.

[0183] The coordinate conversion unit is used to convert the bare die boundary coordinates, pad outer diameter and network name coordinates in each standard chip layout data set into the package coordinate system according to the optical zoom coefficient.

[0184] In one embodiment, the above device further includes a pre-processing module, which includes:

[0185] The mirror processing unit is used to perform mirror processing on the original data of the chip layout; the mirror processing is to rotate the original data of the chip layout when the packaging type of the original data of the chip layout is flip-stick packaging.

[0186] In one embodiment, the correction module includes:

[0187] The network name correction unit is used to correct the signal network name in each standard chip layout data group using preset chip information when the correctness check of the pad outer circle boundary data is passed to obtain the target chip layout data.

[0188] In one embodiment, the network name correction unit includes:

[0189] The network name search subunit is used to search the preset chip information according to the signal network name in each standard chip layout data group to obtain the target network name corresponding to the signal network name.

[0190] The replacement subunit is used to replace the signal network name in each standard chip layout data group with the target network name to obtain the target chip layout data.

[0191] Each module in the aforementioned chip layout data processing device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0192] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 9As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, abbreviated as I / O) and a communication interface. The processor, memory and input / output interface are connected via a system bus, and the communication interface is connected to the system bus via the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store chip layout raw data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, a chip layout data processing method is implemented.

[0193] Those skilled in the art will understand that Figure 9 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0194] In an exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor implements the steps of the method in any one of the above embodiments when executing the computer program.

[0195] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the method in any one of the above embodiments are implemented.

[0196] In one embodiment, a computer program product is provided, comprising a computer program, which implements the steps of the method in any one of the above embodiments when executed by a processor.

[0197] Those skilled in the art will understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of each of the above-mentioned method embodiments. In each embodiment provided in this application, any reference to a memory, database, or other medium can include at least one of a non-volatile memory and a volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processor involved in each embodiment provided herein may be, but are not limited to, a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a programmable logic unit (PLC), a data processing logic unit based on quantum computing, an artificial intelligence (AI) processor, and the like.

[0198] Each technical feature of the above embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of each technical feature in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0199] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A chip layout data processing method, characterized in that: The method comprises: Obtain chip layout raw data and preset chip information; Screening the chip layout raw data to obtain a bare die boundary dataset, a pad outer circle boundary dataset, and a signal network name dataset; Obtaining standard bare die boundary data corresponding to each chip type and standard pad outer circle boundary data corresponding to each chip type according to the bare die boundary data set and the pad outer circle boundary data set; Matching each of the standard bare die boundary data, each of the standard pad outer circle boundary data, and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type; According to the preset chip information, the standard pad outer circle boundary data and the signal network name in each standard chip layout data group are corrected to obtain target chip layout data.

2. The method according to claim 1, characterized in that Obtaining standard die boundary data corresponding to each chip type according to the die boundary data set includes: Get preset boundary conditions; Calculating each die boundary data in the die boundary data set to obtain a layout boundary corresponding to each die boundary data; Based on the preset boundary conditions and the layout boundary corresponding to each of the die boundary data, standard die boundary data corresponding to each chip type is obtained.

3. The method according to claim 1, characterized in that The step of obtaining standard pad outer circle boundary data corresponding to each chip type according to the pad outer circle boundary data set includes: Repeatability detection is performed on the pad outer circle boundary data in each of the pad outer circle boundary data sets to obtain standard pad outer circle boundary data corresponding to each chip type.

4. The method according to claim 1, wherein The matching of each of the standard die boundary data, each of the standard pad outer circle boundary data, and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type includes: Calculating the die boundary coordinates of each of the standard die boundary data, calculating the pad outer circle diameter of each of the standard pad outer circle boundary data, calculating the pad coordinates of each of the standard pad outer circle boundary data, and calculating the network name coordinates of each signal network name in the signal network name data set; Perform correlation matching on each of the network name coordinates and each of the pad coordinates to obtain each reference data set; According to the standard pad outer circle boundary data, each reference data group is matched with each bare die boundary coordinate to obtain each standard chip layout data group.

5. The method according to claim 4, characterized in that The step of matching each reference data set with each die boundary coordinate according to the standard pad outer circle boundary data to obtain each standard chip layout data set includes: Scaling each of the network name coordinates according to a preset scaling factor to obtain each standard network name; Based on each of the pad coordinates, obtaining the coordinates of one or more of the standard network names adjacent to each of the pad coordinates; Calculating each distance according to the coordinates of each pad and the coordinates of each standard network name; Each of the distances is compared with a preset likelihood threshold to obtain the network name coordinates corresponding to each of the pad coordinates, thereby obtaining each of the reference data sets.

6. The method according to claim 4, characterized in that After obtaining each standard chip layout data set by combining each reference data set with each die boundary coordinate according to the standard pad outer circle boundary data, the method further includes: Get the optical zoom factor; The die boundary coordinates, the pad outer diameter, and the net name coordinates in each of the standard chip layout data sets are converted into a package coordinate system according to the optical zoom factor.

7. The method according to claim 1, characterized in that After obtaining the original chip layout data and the preset chip information, the method further includes: Performing mirror processing on the original chip layout data; The mirror processing is to rotate the original chip layout data when the packaging type of the original chip layout data is flip-stick packaging.

8. The method according to claim 1, characterized in that The method of correcting the standard pad outer circle boundary data and the signal network name in each standard chip layout data group according to the preset chip information to obtain target chip layout data includes: When the correctness check of the pad outer circle boundary data is passed, the preset chip information is used to correct the signal network name in each of the standard chip layout data groups to obtain the target chip layout data.

9. The method according to claim 8, characterized in that The method of using the preset chip information to correct the signal network name in each of the standard chip layout data groups to obtain the target chip layout data includes: According to the signal network name in each of the standard chip layout data groups, a search is performed in the preset chip information to obtain a target network name corresponding to the signal network name; The target chip layout data is obtained by replacing the signal network name in each of the standard chip layout data groups using the target network name.

10. A chip layout data processing device, characterized in that: The device comprises: The acquisition module is used to obtain the original data of the chip layout and the preset chip information; A screening module is used to screen the chip layout raw data to obtain a bare die boundary data set, a pad outer circle boundary data set, and a signal network name data set; a classification module, configured to obtain standard bare die boundary data corresponding to each chip type and standard pad outer circle boundary data corresponding to each chip type based on the bare die boundary data set and the pad outer circle boundary data set; A matching module, configured to match each of the standard die boundary data, each of the standard pad outer circle boundary data, and the signal network name data set to obtain a standard chip layout data set corresponding to each chip type; The correction module is used to correct the standard pad outer circle boundary data and the signal network name in each standard chip layout data group according to the preset chip information to obtain target chip layout data.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 9 are implemented.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

13. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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