A yield analysis method, device and electronic equipment based on maximum ranking mode

Abstract

The application provides a yield analysis method and device based on a maximum ranking mode and electronic equipment. Part of collected circuit samples are selected for simulation, and a substitute model is trained by using the circuit samples carrying simulation results and taking the maximum ranking index as a guide to obtain a substitute model meeting preset requirements. The maximum ranking index is a range required for a set number of failure points determined based on simulation results of the circuit samples to be completely covered by prediction results of the substitute model. Prediction results of the remaining circuit samples are obtained by using the substitute model, and a preset number of circuit samples with the worst prediction results are screened out. Simulation is performed on the screened circuit samples to determine failure points, and then the yield of the target circuit is obtained. In the scheme, the training of the substitute model is guided by the maximum ranking index, so that the substitute model has high capability to find failure points in the case of a small number of samples, and can reduce time cost while improving the accuracy of the analysis result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, in particular to a yield analysis method and device based on maximum sorting mode and electronic equipment. BACKGROUND

[0002] With the increasingly precise chip manufacturing technology, the size of transistors and other components has been reduced to nanometer level, making the internal structure of the chip more and more complex. However, it also brings severe challenges. The existence of extremely small parameter deviation in the manufacturing process can have a great impact on the electrical characteristics of the components, and even cause device failure. Therefore, accurate analysis of the yield of integrated circuits is crucial to ensure product quality.

[0003] In the existing circuit yield analysis, the Monte Carlo (MC) sampling method is usually used to sample the circuit, and then the circuit performance simulation is carried out based on the circuit simulation tool such as Simulation Program with Integrated Circuit Emphasis (SPICE), and then the failure points are determined based on the simulation results, so as to calculate the yield of the circuit.

[0004] However, for devices with extremely high yield requirements, the yield evaluation is a very small probability problem, which leads to the fact that the traditional MC method needs millions of simulation times to capture the failure points, and each simulation needs to call a transistor-level simulator such as SPICE simulator, which will generate a large time overhead and has the problem of low efficiency. SUMMARY

[0005] The purpose of the embodiments of the present application is to provide a yield analysis method and device based on maximum sorting mode and electronic equipment, which can reduce the time cost and improve the accuracy of the analysis results.

[0006] In a first aspect, the present application provides a yield analysis method based on maximum sorting mode, which comprises:

[0007] Collecting circuit samples in a target circuit, and selecting part of the circuit samples for simulation to obtain simulation results;

[0008] Using the circuit samples carrying the simulation results and the maximum sorting index as guidance to train the substitute model, and obtaining a substitute model meeting the preset requirements, wherein the maximum sorting index is the range required for the set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the substitute model;

[0009] obtaining prediction results of the remaining circuit samples in the collected circuit samples by using the trained substitute model, and screening a preset number of circuit samples with the worst prediction results;

[0010] determining a failure point from the screened circuit samples based on the simulation mode, and obtaining the yield of the target circuit based on the determined failure point.

[0011] In an optional implementation, the maximum ranking index is calculated by the following method:

[0012] obtaining simulation results, prediction results and a set number of the circuit samples;

[0013] performing a first ranking of the circuit samples according to the simulation results of the circuit samples, and determining a set number of circuit samples with the worst performance in the first ranking;

[0014] performing a second ranking of the circuit samples according to the prediction results of the circuit samples, and determining an index when a set number of circuit samples in the second ranking completely cover the set number of circuit samples with the worst performance in the first ranking as an index value of the maximum ranking index.

[0015] In an optional implementation, the set number is determined by the following method:

[0016] obtaining accuracy requirements and confidence requirements of simulation results about the simulation mode;

[0017] determining a minimum number of failure samples based on the accuracy requirements and the confidence requirements;

[0018] determining the set number based on the minimum number of failure samples.

[0019] In an optional implementation, the step of selecting part of the circuit samples to obtain simulation results includes:

[0020] dividing the collected circuit samples into a first number of first circuit samples and a second number of second circuit samples;

[0021] performing circuit performance simulation on each of the first circuit samples by using a simulation tool to obtain simulation results of each of the first circuit samples.

[0022] In an optional implementation, the step of obtaining prediction results of the remaining circuit samples in the collected circuit samples by using the trained substitute model, and screening a preset number of circuit samples with the worst prediction results includes:

[0023] obtaining prediction results of each of the second circuit samples by using the trained substitute model;

[0024] ranking the second circuit samples based on the prediction results of the second circuit samples;

[0025] selecting a preset number of second circuit samples with the worst prediction results from the ranked second circuit samples.

[0026] In an optional implementation, the step of training the substitute model by using the circuit samples carrying the simulation results and taking the maximum ranking index as a guide comprises:

[0027] constructing a plurality of initial models, and iteratively training each of the initial models by using the circuit samples carrying the simulation results and taking the maximum ranking index as a guide;

[0028] when a preset iteration stop condition is met, obtaining an index value of the maximum ranking index of each of the initial models;

[0029] selecting an initial model with the best performance as the substitute model satisfying the preset requirement based on the index value of the maximum ranking index of each of the initial models.

[0030] In an optional implementation, the step of determining the failure point from the selected circuit samples based on the simulation manner comprises:

[0031] obtaining simulation results of each of the selected circuit samples by using a simulation tool;

[0032] comparing the simulation results of each of the circuit samples with a preset value, and determining whether the circuit sample is a failure point based on the comparison result.

[0033] In an optional implementation, the step of obtaining the yield of the target circuit based on the determined failure point comprises:

[0034] obtaining a number of the determined failure points and a total number of the collected circuit samples in the target circuit;

[0035] obtaining the yield of the target circuit by dividing the number of the failure points by the total number of the collected circuit samples.

[0036] In a second aspect, the present application provides a yield analysis device based on a maximum ranking manner, which comprises:

[0037] a collection module configured to collect circuit samples in a target circuit, and select part of the circuit samples to perform simulation to obtain simulation results;

[0038] The training module is configured to train the substitute model by using the circuit samples carrying the simulation results and by using a maximum ranking index as a guide, to obtain a substitute model satisfying preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the substitute model.

[0039] The prediction module is configured to obtain prediction results of the remaining circuit samples in the collected circuit samples by using the trained substitute model, and to screen out a preset number of circuit samples with the worst prediction results.

[0040] The determination module is configured to determine failure points from the screened circuit samples based on a simulation manner, and to obtain the yield of the target circuit based on the determined failure points.

[0041] In a third aspect, the present application provides an electronic device, comprising a processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus.

[0042] The memory is configured to store at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the method according to any one of the preceding embodiments.

[0043] The present application provides a yield analysis method and device based on a maximum ranking manner and an electronic device. After collecting circuit samples in a target circuit, a part of the circuit samples are selected for simulation. The substitute model is trained by using the circuit samples carrying the simulation results and by using a maximum ranking index as a guide, to obtain a substitute model satisfying preset requirements. The maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the substitute model. The prediction results of the remaining circuit samples are obtained by using the substitute model, and a preset number of circuit samples with the worst prediction results are screened out. The failure points are determined by performing simulation on the screened circuit samples, and then the yield of the target circuit is obtained. In the present application, the substitute model is trained by using the maximum ranking index as a guide, so that the substitute model has a high ability to find failure points in a small number of samples, thereby reducing the time cost and improving the accuracy of the analysis results. BRIEF DESCRIPTION OF DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0045] Figure 1 The flow chart of the yield analysis method based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 1.

[0046] Figure 2 The flow chart of the maximum ranking index determination method provided in the embodiment of the present application is shown in FIG. 2.

[0047] Figure 3 The flow chart of the sub-steps included in S12 in FIG. 1 is shown in FIG. 3. Figure 1 The flow chart of the sub-steps included in S13 in FIG. 1 is shown in FIG. 4. The flow chart of the sub-steps included in S14 in FIG. 1 is shown in FIG. 5.

[0048] The flow chart of the sub-steps included in S15 in FIG. 1 is shown in FIG. 6. Figure 4 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 1 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7.

[0049] The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 5 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 1 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7.

[0050] The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 6 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 1 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7.

[0051] The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 7 The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7.

[0052] The function module block diagram of the yield analysis device based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 7. Figure 8 The structure block diagram of the electronic device provided in the embodiment of the present application is shown in FIG. 8. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0054] Based on the above, in the conventional MC method, the circuit yield analysis is performed, however, for the reliability analysis of devices such as memory, since the memory is composed of millions of unit circuits, tens of thousands of MC simulations are required, and transistor-level simulation is required to evaluate the performance each time, which results in great time consumption and low analysis efficiency.

[0055] Specifically, if the definition is For independent random process variables, such as the threshold voltage of each MOS transistor, gate thickness and electron mobility, let For the joint probability density function, let be the simulation result of the circuit performance.

[0056] Let be the failure domain, and introduce the indicator function :

[0057]

[0058] The failure rate is then:

[0059] Based on the above formula, the failure rate is difficult to calculate directly, because it is not known the specific analytical form. In order to solve the calculation formula of the failure rate, the most classic method is to approximate by Monte Carlo simulation MC, that is, MC evaluates the failure rate by directly sampling from , as a result, the unbiased estimate of the failure rate is as follows:

[0060]

[0061] wherein, represents the unbiased estimate of the failure rate , N represents the total number of samples, represents the number of simulation results in the failure domain in all sampling times.

[0062] However, since the yield requirement of the memory is very high, for example, if a 1KB static random memory (SRAM) is required to have a yield of 99.73% (3 sigma), then the yield of each SRAM unit is 0.999999669964462 (4.6 sigma). Therefore, for the memory, the yield evaluation is a very small probability problem. This results in that the traditional MC method needs millions of simulation times to capture a failure point, and each simulation needs to call a transistor-level simulator (such as a SPICE simulator), which will produce a huge time overhead and is unacceptable.

[0063] In view of the defects in the traditional method, there is also a way to introduce a prediction model to perform performance prediction of the sampling points in the processing method. Compared with the traditional MC analysis method, the use of the prediction model can shorten the analysis time, has the advantages of reducing the simulation overhead, improving the efficiency of the circuit yield analysis, etc.

[0064] However, in the training process of the existing prediction model, in order to guarantee the accuracy of the prediction model near the failure domain, the relative error is used as a guide for model training. This method has high precision when applied to small-scale circuits, however, when the circuit scale increases, the number of input parameters is large, the modeling overhead increases greatly, and the precision is difficult to guarantee. Moreover, for yield analysis, the most important thing is the failure points located in the failure region, which are difficult to obtain as a test set, and because there are too many process variables affecting the circuit, a large number of training samples are needed to guarantee the accuracy of the model near the failure domain.

[0065] Therefore, in the prior art, on one hand, a large number of training samples are required, and time and resource costs are high; on the other hand, it is difficult to obtain enough failure points to add to a test set, thereby affecting the accuracy.

[0066] In view of the defects in the prior art, the yield analysis scheme based on the maximum ranking mode is provided, the maximum ranking index determined according to the range required for the prediction results of a set number of failure points determined according to the simulation results of circuit samples to be completely covered by a substitute model is used as a guide to train the substitute model, so that the substitute model has a higher ability to find failure points under the condition of a smaller number of samples, and the effect of reducing time cost while improving the accuracy of the analysis result is achieved.

[0067] The technical solutions of the present application will be described in detail below with reference to the accompanying drawings.

[0068] Figure 1 A step flowchart of a yield analysis method based on the maximum ranking mode provided in the embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, the yield analysis method based on the maximum ranking mode of the present embodiment includes the following steps:

[0069] S11, collect circuit samples in a target circuit, and select part of the circuit samples to perform simulation to obtain simulation results.

[0070] S12, use the circuit samples carrying the simulation results to train a substitute model under the guidance of a maximum ranking index, and obtain a substitute model meeting preset requirements.

[0071] The maximum ranking index is the range required for the prediction results of a set number of failure points determined according to the simulation results of the circuit samples to be completely covered by the substitute model.

[0072] S13, use the trained substitute model to obtain the prediction results of the remaining circuit samples in the collected circuit samples, and select a preset number of circuit samples with the worst prediction results.

[0073] S14, determine failure points from the selected circuit samples based on a simulation mode.

[0074] S15, obtain the yield of the target circuit based on the determined failure points.

[0075] In the embodiment, the circuit samples can be related process variables such as MOS tubes in the circuit, for example, the circuit samples can be recorded as X is These are independent random process variables, such as the threshold voltage, gate thickness, and electron mobility of each MOSFET. The McLeod sampling method can be used to sample the target circuit to collect a large number of circuit samples. The number of collected circuit samples can be denoted as... .

[0076] However, to avoid extensive simulations, only a subset of circuit samples is selected from the sampled circuit data for simulation to obtain the simulation results. For example, the number of selected circuit samples can be denoted as... Circuit performance simulation is performed using the SPICE simulation tool.

[0077] Specifically, the collected circuit samples can be divided into a first number of first circuit samples and a second number of second circuit samples. The circuit performance of each first circuit sample can be simulated using simulation tools to obtain the simulation results of each first circuit sample.

[0078] The replacement model is trained using circuit samples with simulation results. During the training process, the maximum ranking metric is used as a guide. The maximum ranking metric is defined as the range within which the prediction results of the replacement model completely cover a set number of failure points determined by the simulation results of the circuit samples. The smaller this range, the stronger the replacement model's ability to find failure points.

[0079] Please see Figure 2 In this embodiment, the maximum ranking index can be calculated during the training of the alternative model in the following way:

[0080] S21, obtain the simulation results, prediction results, and the set number of each circuit sample.

[0081] S22, the circuit samples are sorted in the first order according to the simulation results of each circuit sample, and a set number of circuit samples with the worst performance in the first order are determined.

[0082] S23, the circuit samples are sorted in a second order according to the prediction results of each circuit sample, and the index of the circuit sample that completely covers the set number of the worst-performing circuit samples in the first order is determined as the index value of the maximum sorting index.

[0083] In this embodiment, the number of circuit samples selected for training the alternative model is: ,get The simulation results of each circuit sample in the sample are analyzed, and the circuit samples are sorted according to their performance from worst to best based on the simulation results. For ease of distinction, this sorting process is called the first sort. Furthermore, the first index of each circuit sample in the first sort is marked.

[0084] In the first ranking, a certain number of circuit samples with the worst performance are determined, i.e., the circuit samples ranked in the first certain positions.

[0085] After each circuit sample is processed by the surrogate model, the surrogate model can output the predicted result corresponding to each circuit sample, i.e., the predicted circuit performance. Similarly, each circuit sample is ranked based on the predicted result from bad to good, which is referred to as the second ranking. And the second index of each circuit sample in the second ranking is determined.

[0086] In the first ranking, a certain number of circuit samples with the worst performance are determined, i.e., the circuit samples ranked in the first certain positions.

[0087] In the first ranking, a certain number of circuit samples with the worst performance are determined, i.e., the circuit samples ranked in the first certain positions.

[0088] The pseudo code of the calculation method of the maximum ranking index is as follows:

[0089] Input: real circuit performance obtained from SPICE , circuit performance predicted by the model , and the required number of failure samples ;

[0090] Output: the value of the maximum ranking index (Rating);

[0091] function

[0092] for do

[0093] if then

[0094] return

[0095] end if

[0096] end for

[0097] end function

[0098] put in order and return its index, put it in ;

[0099] put in order and return its index, put it in ;

[0100] define

[0101] for do

[0102] r = GetElementPosition ( y 2, y 1[ i ])

[0103] if then

[0104] m = r

[0105] end if

[0106] end for

[0107] return

[0108] In this embodiment, the maximum ranking index is used to determine whether the substitute model can screen out the circuit samples with the worst performance in the specified number of settings at a relatively small cost in the yield analysis scene, and the specific relative error is no longer concerned. In this way, even if the accuracy of the substitute model cannot be very high with limited training samples, the prediction result of the substitute model on the circuit performance can be relatively consistent with the ranking of the circuit simulation result, and accurate yield prediction can also be achieved.

[0109] In the above process, the value of the specified number is set, and the specified number can be determined in the following manner:

[0110] obtain accuracy requirement and confidence requirement of simulation result about simulation mode; determine failure sample minimum value based on accuracy requirement and confidence requirement; determine the specified number based on the failure sample minimum value.

[0111] In the above formula for failure rate approximation of MC, is an unbiased estimate of the true . The more N is, The closer But it can not make Therefore, the confidence and accuracy are generally used to determine N that makes the MC result converge, as shown in the following formula:

[0112]

[0113] Wherein, represents the confidence, represents the accuracy. At this time, the value of N represents that the evaluation result of MC is in (1- )100% confidence and accuracy. The quality factor of the MC method is defined as follows:

[0114]

[0115] Wherein, is the variance of . It means that the current evaluation reaches accuracy and confidence. For example, it is generally required that , that is, it means 90% accuracy and confidence. At this time, N is greater than 100 / , which means that at least 100 failure samples ( ) are required. Therefore, the set number can be determined based on the minimum failure sample (such as 100), such as the set number is greater than or equal to the minimum failure sample.

[0116] In this embodiment, considering that the scales of different circuits are different, the number of process variables affecting their performance is different, that is, the dimension is different, according to the size of the circuit scale, the dimension of may be from tens of dimensions to tens of thousands of dimensions. This leads to different models required in different scenarios. Therefore, the scheme constructs a scheme for selecting an adaptive model.

[0117] Figure 3 Specifically, please refer to In the above step of training the surrogate model by using the circuit sample carrying the simulation result and taking the maximum ranking indicator as guidance, the following methods can be used:

[0118] S121, a plurality of initial models are constructed, and each of the initial models is iteratively trained by using the circuit sample carrying the simulation result and taking the maximum ranking indicator as guidance.

[0119] S122, when the preset iteration stop condition is met, the indicator value of the maximum ranking indicator of each of the initial models is obtained.

[0120] S123, screening an initial model with the best performance based on the index value of the maximum ranking index of each initial model as the replacement model meeting the preset requirement.

[0121] In this embodiment, the plurality of initial models can include a linear model, a LASSO regression model, a neural network model, etc. Each initial model is trained using the circuit sample carrying the simulation result, and the performance of each initial model is evaluated using the maximum ranking index.

[0122] When the preset iteration stopping condition is met, for example, the number of iteration training reaches the preset maximum number, the iteration training duration reaches the preset maximum duration, or the maximum ranking index reaches convergence and no longer changes, etc., the index value of the maximum ranking index of each initial model can be obtained. The smaller the maximum ranking index, the stronger the ability of the model to find the failure point and the better the performance. Therefore, an initial model with the smallest index value is screened based on the index value of the maximum ranking index of each initial model as the replacement model meeting the preset requirement.

[0123] In this way, the best model in the current scenario can be screened based on the actual application scenario for subsequent prediction processing.

[0124] Based on the above-mentioned training of the replacement model, the prediction results of the remaining circuit samples in the collected circuit samples are obtained using the trained replacement model, and a preset number of circuit samples with the worst prediction results are screened out. Specifically, please refer to Figure 4 This step can be implemented in the following way:

[0125] S131, obtaining the prediction results of each second circuit sample using the trained replacement model.

[0126] S132, ranking the second circuit samples based on the prediction results of each second circuit sample.

[0127] S133, screening a preset number of second circuit samples with the worst prediction results based on the ranked second circuit samples.

[0128] Using the replacement model to obtain the prediction results of the circuit performance of each remaining circuit sample in the target circuit, without calling the simulation tool for simulation, can greatly improve the analysis efficiency and save time overhead. Similarly, the remaining circuit samples are ranked in the order from bad to good prediction results, and a preset number of second circuit samples with the worst prediction results are screened out after ranking.

[0129] The preset number is determined by the performance of the substitute model, and specifically, the greater the index value of the maximum ranking index, the greater the preset number of re-simulation required for screening.

[0130] After the preset number of circuit samples are screened out, the failure points are determined from the screened circuit samples based on the simulation mode. Specifically, refer to Figure 5 , this step can be implemented in the following way:

[0131] S141, using a simulation tool to obtain the simulation results of each of the screened circuit samples.

[0132] S142, comparing the simulation results of each of the circuit samples with a preset value, and determining whether the circuit sample is a failure point based on the comparison result.

[0133] In this embodiment, the simulation tool SPICE is called to perform circuit performance simulation on each of the screened circuit samples to obtain the simulation results of each of the circuit samples. The simulation results are compared with the preset value. If the simulation result exceeds the preset value, it can be determined that the corresponding circuit sample is in the failure domain, i.e., it is a failure point. If the simulation result is less than or equal to the preset value, it can be determined that the corresponding circuit sample is not in the failure domain.

[0134] In this way, on the basis of screening out a preset number of circuit samples based on the substitute model, it can be ensured that the preset number of circuit samples screened out contains a set number of circuit samples with the worst performance. On this basis, re-simulation is performed using a simulation tool to accurately obtain the simulation results of each of the circuit samples, and then accurately determine the failure points therefrom.

[0135] Finally, the yield of the target circuit is obtained based on the determined failure points. Refer to Figure 6 , this step can be implemented in the following way:

[0136] S151, obtaining the number of determined failure points and the total number of collected circuit samples in the target circuit.

[0137] S152, dividing the number of failure points by the total number of collected circuit samples to obtain the yield of the target circuit.

[0138] From the above, the total number of collected circuit samples of the target circuit is , assuming that the number of finally determined failure points is , then the yield of the target circuit is .

[0139] The yield analysis method based on the maximum sorting mode provided in the embodiment uses a maximum sorting index to measure the ability of a model to capture failure points, so that circuit yield analysis prediction under a very small probability can be realized with a small training cost. The problem of high time and resource cost caused by the need for a large number of training samples in the prior art is avoided, and the problem of affecting accuracy caused by the difficulty of obtaining enough failure points for training in the very small probability scenario is avoided. The present scheme can reduce the time cost while improving the accuracy of the analysis result.

[0140] Figure 7 A structural block diagram of the yield analysis device based on the maximum sorting mode according to the embodiment of the application is shown in FIG. 1. As shown in the figure, the yield analysis device based on the maximum sorting mode of the embodiment includes: Figure 7

[0141] A collection module for collecting circuit samples in a target circuit and selecting part of the circuit samples for simulation to obtain simulation results;

[0142] A training module for training a substitute model using the circuit samples carrying the simulation results and using a maximum sorting index as a guide to obtain a substitute model meeting preset requirements, wherein the maximum sorting index is a range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the substitute model;

[0143] A prediction module for obtaining prediction results of the remaining circuit samples in the collected circuit samples using the substitute model obtained by training, and screening a preset number of circuit samples with the worst prediction results;

[0144] A determination module for determining failure points from the screened circuit samples based on a simulation method and obtaining the yield of the target circuit based on the determined failure points.

[0145] As a possible implementation manner, the maximum sorting index is calculated by the following method:

[0146] Obtain the simulation results, prediction results, and set number of each circuit sample;

[0147] Firstly, sort the circuit samples according to the simulation results of each circuit sample, and determine the set number of circuit samples with the worst performance in the first sorting;

[0148] Secondly, sort the circuit samples according to the prediction results of each circuit sample, and determine the index when the set number of circuit samples with the worst performance in the first sorting is completely covered in the second sorting as the index value of the maximum sorting index.

[0149] ​As a possible implementation manner, the set number is determined by the following manner:

[0150] An accuracy requirement and a confidence requirement of a simulation result of the simulation manner are obtained;

[0151] A failure sample minimum value is determined based on the accuracy requirement and the confidence requirement;

[0152] The set number is determined based on the failure sample minimum value.

[0153] As a possible implementation manner, the collection module is configured to select part of the circuit samples to obtain the simulation result by the following manner:

[0154] The collected circuit samples are divided into a first number of first circuit samples and a second number of second circuit samples;

[0155] The simulation tool is used to perform circuit performance simulation on each of the first circuit samples to obtain a simulation result of each of the first circuit samples.

[0156] As a possible implementation manner, the training module is configured to train by the following manner:

[0157] A plurality of initial models are constructed, and each of the initial models is iteratively trained by using the circuit samples carrying the simulation results and guided by the maximum ranking index;

[0158] When a preset iteration stop condition is met, an index value of the maximum ranking index of each of the initial models is obtained;

[0159] Based on the index value of the maximum ranking index of each of the initial models, an initial model with the best performance is screened out as a replacement model meeting the preset requirement.

[0160] As a possible implementation manner, the prediction module is configured to predict and screen out a preset number of circuit samples with the worst prediction result by the following manner:

[0161] The replacement model obtained by training is used to obtain a prediction result of each of the second circuit samples;

[0162] Each of the second circuit samples is ranked based on the prediction result of each of the second circuit samples;

[0163] Based on the ranked second circuit samples, a preset number of second circuit samples with the worst prediction result are screened out.

[0164] As a possible implementation manner, the determination module is configured to determine the failure point from the screened circuit samples based on the simulation manner by the following manner:

[0165] Obtain a simulation result of each of the circuit samples in the screened circuit samples by using a simulation tool;

[0166] Compare the simulation result of each of the circuit samples with a preset value, and determine whether the circuit sample is a failure point based on a comparison result.

[0167] As a possible implementation, the determining module is configured to obtain the yield of the target circuit based on the determined failure points in the following manner:

[0168] Obtain the number of the determined failure points and the total number of the collected circuit samples in the target circuit;

[0169] Divide the number of the failure points by the total number of the collected circuit samples to obtain the yield of the target circuit.

[0170] The yield analysis device based on the maximum sorting manner provided in this embodiment is used to implement the yield analysis method based on the maximum sorting manner in the foregoing method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described herein again. In addition, the functions of each module in the yield analysis device based on the maximum sorting manner can be implemented by referring to the descriptions of the corresponding parts in the foregoing method embodiments, which will not be described herein again.

[0171] Referring to Figure 8 , a structural schematic diagram of an electronic device according to an example embodiment of the present application is shown. The specific implementation of the electronic device is not limited by the specific implementation of the present embodiment.

[0172] As Figure 8 shown, the electronic device can include a processor, a memory, and a communication bus, a communication interface.

[0173] The processor, the memory, and the communication interface can communicate with each other through the communication bus.

[0174] The communication interface is configured to communicate with other electronic devices or servers.

[0175] The processor is configured to execute a program, and specifically can execute the steps of the yield analysis method based on the maximum sorting manner described in any one of the foregoing embodiments.

[0176] Specifically, the program can include program code, and the program code includes computer operation instructions.

[0177] The processor can be a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors included in the smart device can be of the same type, such as one or more CPUs; or can be of different types, such as one or more CPUs and one or more ASICs.

[0178] The memory is configured to store programs. The memory can include a high-speed RAM memory, and can further include a non-volatile memory, such as at least one disk memory.

[0179] The programs can be specifically configured to enable the processor to perform steps of any of the yield analysis methods based on the maximum sorting manner described in the embodiments. The specific implementation of each step in the programs can refer to the corresponding description of the steps and units performed by any of the yield analysis methods based on the maximum sorting manner described above, and will not be repeated here.

[0180] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the devices and modules described above can refer to the corresponding process descriptions in the foregoing method embodiments.

[0181] The embodiments of the present application further provide a computer storage medium, which stores a computer program. The program is executed by a processor to implement the yield analysis method based on the maximum sorting manner described in any of the foregoing method embodiments.

[0182] The embodiments of the present application further provide a computer program product, which includes computer instructions. The computer instructions instruct a computing device to perform operations corresponding to the yield analysis method based on the maximum sorting manner described in any of the foregoing method embodiments.

[0183] In the embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, another division manner can be used. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, devices or units, and can be electrical, mechanical or other forms.

[0184] In addition, the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e. may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0185] Furthermore, the functional modules in various embodiments of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0186] It should be noted that if the function is realized in the form of a software function module and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, and various program code storage media.

[0187] In this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0188] The above is only an embodiment of the present application and is not used to limit the protection scope of the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A yield analysis method based on a maximum ordering approach, characterized by, The method comprises: collecting circuit samples in a target circuit, and selecting part of the circuit samples to perform simulation to obtain simulation results; training a substitute model by using the circuit samples carrying the simulation results and taking the maximum sorting index as a guide to obtain a substitute model meeting preset requirements, wherein the maximum sorting index is a range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by prediction results of the substitute model; obtaining prediction results of remaining circuit samples in the collected circuit samples by using the trained substitute model, and screening a preset number of circuit samples with the worst prediction results; determining failure points from the screened circuit samples based on a simulation method; obtaining a yield of the target circuit based on the determined failure points; the maximum sorting index is obtained by the following method: obtaining simulation results, prediction results and a set number of each circuit sample; performing first sorting on the circuit samples according to the simulation results of each circuit sample, and determining a set number of circuit samples with the worst performance in the first sorting; performing second sorting on the circuit samples according to the prediction results of each circuit sample, and determining an index value of the maximum sorting index when a set number of circuit samples with the worst performance in the first sorting are completely covered in the second sorting.

2. The method of claim 1, wherein, The set number is determined by the following method: obtaining accuracy requirements and confidence requirements of simulation results about a simulation method; determining a minimum value of failure samples based on the accuracy requirements and the confidence requirements; determining the set number based on the minimum value of the failure samples.

3. The method of claim 1, wherein the maximum ranking method is based on a yield analysis. The step of selecting part of the circuit samples to perform simulation to obtain simulation results comprises: dividing the collected circuit samples into a first number of first circuit samples and a second number of second circuit samples; performing circuit performance simulation on each first circuit sample by using a simulation tool to obtain simulation results of each first circuit sample.

4. The method of claim 3, wherein the maximum ranking method is based on a yield analysis of a product. The step of obtaining prediction results of remaining circuit samples in the collected circuit samples by using the trained substitute model, and screening a preset number of circuit samples with the worst prediction results comprises: obtaining prediction results of each second circuit sample by using the trained substitute model; sorting the second circuit samples based on the prediction results of each second circuit sample; screening a preset number of second circuit samples with the worst prediction results based on the sorted second circuit samples.

5. The method of claim 1, wherein the maximum ranking-based yield analysis method is based on a maximum ranking method. The step of training a substitute model by using the circuit samples carrying the simulation results and taking the maximum sorting index as a guide comprises: constructing a plurality of initial models, and iteratively training each initial model by using the circuit samples carrying the simulation results and taking the maximum sorting index as a guide; obtaining an index value of the maximum sorting index of each initial model when a preset iteration stop condition is met; screening an initial model with the best performance based on the index value of the maximum sorting index of each initial model as the substitute model meeting the preset requirements.

6. The method of claim 1, wherein the maximum ranking method is based on a yield analysis. The step of determining failure points from the screened circuit samples based on a simulation method comprises: Obtaining simulation results of each of the circuit samples screened by using a simulation tool; Comparing the simulation results of each of the circuit samples with preset values, and determining whether the circuit samples are failure points based on the comparison results.

7. The method of claim 1, wherein the maximum ranking method is based on a yield analysis. The step of obtaining the yield of the target circuit based on the determined failure points comprises: Obtaining the number of the determined failure points and the total number of the collected circuit samples in the target circuit; Dividing the number of the failure points by the total number of the collected circuit samples to obtain the yield of the target circuit.

8. A yield analysis device based on a maximum ranking method, characterized by, The device for implementing the yield analysis method based on the maximum ranking mode according to any one of claims 1-7 comprises: A collection module for collecting circuit samples in a target circuit, and selecting part of the circuit samples to obtain simulation results by simulation; A training module for training a substitute model by using the circuit samples carrying the simulation results and taking the maximum ranking index as a guide to obtain a substitute model meeting preset requirements, wherein the maximum ranking index is a range required for a set number of failure points determined based on the simulation results of the circuit samples to be completely covered by the prediction results of the substitute model; A prediction module for obtaining prediction results of each of the remaining circuit samples collected by using the trained substitute model, and screening a preset number of circuit samples with the worst prediction results; A determination module for determining failure points from the screened circuit samples based on a simulation mode, and obtaining the yield of the target circuit based on the determined failure points.

9. An electronic device, comprising: Comprise: A processor, a memory, a communication interface and a communication bus, the processor, the memory and the communication interface complete communication with each other through the communication bus; The memory is used to store at least one executable instruction, and the executable instruction makes the processor execute the corresponding operation of the method in any one of claims 1-7.

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