PCB defect detection method and device based on edge calculation, equipment and medium

Abstract

The invention relates to the technical field of PCB defect detection, and discloses a PCB defect detection method, device and equipment based on edge calculation and a medium, and the method comprises the steps: responding to a color sensor signal, and controlling a servo motor through a PID algorithm to precisely locate a PCB at the center of a field of view of an industrial camera; the edge computing micro server executes image preprocessing; extracting multi-scale features by using a lightweight YOLO model optimized by a RepVGG module; fusing the feature patterns to identify defects; outputting a defect position / category by a decoupling detection head, and generating a defect map through non-maximum suppression; and generating corresponding defect text content according to the defect map, and inputting the defect text content into a large language model to generate a semantic analysis report and a sorting instruction. According to the method, through cooperation of optical structure innovation and edge intelligent decision making, the detection efficiency is improved, the false detection rate is reduced, and the manual redetection cost is remarkably reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB defect detection, and in particular to a PCB defect detection method, device, equipment, and medium based on edge computing. Background Art

[0002] Printed circuit boards (PCBs), the core components of electronic products, face significant manufacturing defects (such as open circuits, short circuits, mousebites, burrs, residual copper, and pinholes) that directly impact the reliability of end devices. With the miniaturization and increased density of electronic products, traditional manual inspection faces three key challenges: low efficiency, with missed detection rates exceeding 15% and a surge in false positives for micron-level defects; high labor costs and difficulty adapting to harsh environments; and insufficient real-time edge processing capabilities due to the reliance on centralized cloud computing.

[0003] Current mainstream algorithms (such as the original YOLOv5) have significant limitations on edge devices: large model parameters (over 1.76 million) and high computational redundancy make it difficult to meet the millisecond-level real-time detection requirements of industrial sites. Furthermore, traditional optical solutions use forward illumination, which inadequately captures the translucent circuit characteristics of single-layer PCBs, resulting in low image contrast and difficulty identifying subtle defects.

[0004] Despite the continued expansion of the global PCB industry, with China accounting for over 50% of global production capacity, bottlenecks in inspection technology are severely hindering industry upgrades. Existing solutions struggle to balance the triad of inspection accuracy, real-time performance, and edge adaptability: centralized architectures suffer from high latency, lightweight models significantly reduce accuracy, and optical solutions are mismatched with defect characteristics. Therefore, a full-stack solution integrating edge computing, optical innovation, and model optimization is urgently needed. Summary of the Invention

[0005] The technical problem to be solved by the present invention is: the accuracy of PCB defect detection based on edge computing.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: a PCB defect detection method based on edge computing, comprising:

[0007] S10. When the PCB board enters the conveyor belt, in response to the positioning signal triggered by the color sensor, the PID algorithm is used to control the servo motor to accurately position the PCB board to the center of the field of view of the industrial camera to capture the circuit image. The conveyor belt is a high-transmittance conveyor belt with an upward irradiation light source provided below the conveyor belt;

[0008] S20, preprocessing the circuit image through the edge computing microserver;

[0009] S30, inputting the preprocessed image into a lightweight YOLO detection model, wherein the lightweight YOLO detection model extracts multi-scale features through a backbone network optimized by a RepVGG module;

[0010] S40, fusing the extracted multi-scale features into a multi-scale feature map to identify PCB defects;

[0011] S50: Use the decoupling detection head to output the PCB defect location and category, and generate a defect map after screening by the non-maximum suppression algorithm;

[0012] S60: Generate corresponding defect text content according to the defect map and input it into the large language model to generate a semantic analysis report and sorting strategy instructions.

[0013] Furthermore, the optimization of the RepVGG module in step S30 includes:

[0014] The multi-branch structure is adopted in the training phase:

[0015] Training:Y=σ(W 3*3 *X+W 1*1 *X+X)

[0016] The inference phase is reparameterized into a single-branch convolution:

[0017] Inference:Y=σ(W fused *X)

[0018] Among them, W fused is the equivalent weight after fusion, which is calculated as follows:

[0019] W fused =W 3*3 +pad(W 1*1 )+diag(1)

[0020] Among them, Y represents the feature map of the final output of the module, and X refers to the feature map of the input RepVGG module. The σ symbol represents the activation function, and the ReLU activation function is used.

[0021] Furthermore, in step S10, the upward irradiation light source is specifically:

[0022] A uniform surface light source array is set under the conveyor belt. The wavelength range of the light source is 400-700nm and the light intensity can be adjusted from 0-50000lux.

[0023] Furthermore, step S40 is specifically as follows:

[0024] The extracted multi-scale features are used to generate multi-scale feature maps ranging from 20×20 to 80×80 using the FPN+PAN bidirectional fusion network to identify PCB defects.

[0025] Furthermore, in step S40, multi-scale feature fusion specifically includes:

[0026] The 20×20×512, 40×40×256, and 80×80×128 feature maps output by the backbone network are interactively fused through top-down and bottom-up paths after dimensionality reduction by 1×1 convolution.

[0027] Furthermore, step S60 specifically includes generating corresponding defect text content according to the defect map, inputting the large language model to execute the associated historical defect data to generate process optimization suggestions, and dynamically adjusting the action parameters of the sorting mechanism.

[0028] Furthermore, in step S20, the circuit image is preprocessed by the edge computing microserver, including adaptive illumination compensation and dynamic threshold binarization.

[0029] The present invention also provides a PCB defect detection device based on edge computing, comprising:

[0030] An image acquisition module is used to control a servo motor using a PID algorithm to precisely position the PCB to the center of the industrial camera's field of view when the PCB enters the conveyor belt. The conveyor belt is a highly transparent conveyor belt with an upward irradiation light source located below it.

[0031] A preprocessing module, used to preprocess the circuit image through the edge computing microserver;

[0032] A feature extraction module is used to input the preprocessed image into a lightweight YOLO detection model, which extracts multi-scale features through the backbone network optimized by the RepVGG module;

[0033] Feature fusion module, used to fuse the extracted multi-scale features into a multi-scale feature map to identify PCB defects;

[0034] The defect recognition module uses a decoupled detection head to output the location and category of PCB defects, and generates a defect map after screening using a non-maximum suppression algorithm;

[0035] The defect processing module is used to generate the corresponding defect text content according to the defect map, input the large language model, and generate a semantic analysis report and sorting strategy instructions.

[0036] The present invention also provides a computer device, which includes a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the PCB defect detection method based on edge computing as described above is implemented.

[0037] The present invention also provides a storage medium, which stores a computer program. When the computer program is executed by a processor, it can implement the PCB defect detection method based on edge computing as described above.

[0038] The beneficial effects of the present invention are as follows: through the collaborative optical design of the transparent track and the uniformly projected light source at the bottom, single-layer PCB transmission imaging can obtain high-contrast defect features, solving the problem of missed detection of micron-level defects; combining the RepVGG-YOLOv5 lightweight model with the edge computing architecture, the detection delay is effectively compressed, breaking through the response bottleneck of traditional cloud computing; and the semantic analysis capability of the large language model is simultaneously integrated to realize an intelligent decision-making closed loop from defect location to process optimization, providing the PCB manufacturing industry with a highly real-time, low-deployment-cost automated detection solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The specific structure of the present invention is described in detail below with reference to the accompanying drawings.

[0040] Figure 1 1 is a structural diagram of a detection system according to an embodiment of the present invention;

[0041] Figure 2 This is a structural diagram under the crawler of a detection system according to an embodiment of the present invention;

[0042] Figure 3 This is a flow chart of a PCB defect detection method based on edge computing according to an embodiment of the present invention;

[0043] Figure 4 Schematic diagram of the RepVGG structure of an embodiment of the present invention;

[0044] Figure 5 A schematic diagram of a Deep_PCB dataset sample according to an embodiment of the present invention;

[0045] Figure 6 This is a diagram of the RepVGG-YOLOv5 PCB defect detection model architecture according to an embodiment of the present invention;

[0046] Figure 7 This is a rendering of a single-layer PCB under backlighting according to an embodiment of the present invention;

[0047] Figure 8 This is a block diagram of a PCB defect detection device based on edge computing according to an embodiment of the present invention;

[0048] Figure 9A schematic block diagram of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0051] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the present invention. As used in the specification and appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0052] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0053] like Figure 1-Figure 2 As shown, the detection system adopted by the edge computing-based PCB defect detection method of the present invention includes: an MCU central control unit 1; an edge computing microserver 2; a high-definition industrial camera module 3; a high-strength frame bracket 4; a precision metal support plate 5; a high-precision servo drive system 6; a reinforced angle code connector 7; a high-transmittance conveyor belt 8; a precision roller drive module 9; a uniform surface light source array 10; and a high-precision color sensor 11.

[0054] like Figure 1 、 Figure 2 As shown, the main frame of the inspection system is constructed using high-strength frame brackets 4 precisely assembled from profiles, and securely connected via reinforced angle brackets 7. The PCB board conveyor system is coordinated by a precision servo drive system 6, a transparent, highly transparent crawler track 8, and a precision roller drive module 9.

[0055] The detection and control system consists of three core components: a high-definition industrial camera module 3 responsible for high-precision image acquisition, an MCU central control unit 1 responsible for coordinating the precise operation of peripheral devices, and an edge computing microserver 2 implementing real-time image analysis and defect detection algorithms. These control and detection units are securely supported by a metal support plate 5. A uniform area light source array 10 and a high-precision color sensor 11 are located beneath the highly transparent conveyor belt 8.

[0056] A special design is that the metal support plate 5 below the high-definition industrial camera module 3 has a precision light hole slightly larger than the camera size, ensuring that the high-definition industrial camera module 3 can capture the image of the PCB below without obstacles. Figure 2 The uniform surface light source array 10 provides all-round shadow-free illumination for the PCB board, significantly improving image quality and providing ideal optical conditions for subsequent binarization processing.

[0057] like Figure 3 As shown, an embodiment of the present invention is: a PCB defect detection method based on edge computing, comprising the steps of:

[0058] S10. When the PCB board enters the conveyor belt, in response to the positioning signal triggered by the color sensor, the PID algorithm is used to control the servo motor to accurately position the PCB board to the center of the field of view of the industrial camera to capture the circuit image. The conveyor belt is a high-transmittance conveyor belt, and an upward-illuminating light source is provided below the conveyor belt.

[0059] In a specific embodiment, in step S10, the upward irradiation light source is specifically:

[0060] A uniform surface light source array is set under the conveyor belt. The wavelength range of the light source is 400-700nm and the light intensity can be adjusted from 0-50000lux.

[0061] In this embodiment, Figure 7 As shown, by fully utilizing the light-transmitting properties of a single-layer PCB, high-contrast transmissive illumination is achieved, making circuit textures and tiny defects clearly visible and completely unaffected by ambient light variations, ensuring the stability and reliability of the inspection process. Using a single surface light source instead of a traditional multi-light combination significantly reduces hardware investment and maintenance costs.

[0062] S20. Preprocess the circuit image through the edge computing microserver.

[0063] In a specific embodiment, in step S20, the circuit image is preprocessed by the edge computing microserver, including adaptive illumination compensation and dynamic threshold binarization.

[0064] In this embodiment, the pre-processing stage: the input 640×640 RGB image is first subjected to adaptive illumination compensation and binarization processing to enhance the identifiability of defects on the PCB board. This design uses an innovative pre-processing scheme of light source illumination combined with binarization processing to upgrade the traditional inspection system based on the Peking University PCB dataset to the Deep_PCB dataset that can adapt to various PCB board types, such as Figure 5 As shown, the detection system is more adaptable to the vast majority of PCB boards, significantly improving the versatility of the system.

[0065] S30, input the pre-processed image into the lightweight YOLO detection model, and the lightweight YOLO detection model extracts multi-scale features through the backbone network optimized by the RepVGG module. The structure of the RepVGG module is as follows Figure 4 shown.

[0066] In a specific embodiment, the optimization of the RepVGG module in step S30 includes:

[0067] The multi-branch structure is adopted in the training phase:

[0068] Training:Y=σ(W 3*3 *X+W 1*1 *X+X)

[0069] The inference phase is reparameterized into a single-branch convolution:

[0070] Inference:Y=σ(W fused *X)

[0071] Among them, W fused is the equivalent weight after fusion, which is calculated as follows:

[0072] W fused =W 3*3 +pad(W 1*1 )+diag(1)

[0073] Among them, Y represents the feature map of the final output of the module, and X refers to the feature map of the input RepVGG module. The σ symbol represents the activation function, and the ReLU activation function is used.

[0074] In this embodiment, during the training phase, the network includes multiple branches: W 3×3 Refers to the weight of the 3×3 convolution kernel, which performs convolution operation with the input X (indicated by the * symbol); similarly, W 1×1 is the weight of the 1×1 convolution kernel, which is also convolved with X. In addition, there is a branch that directly performs identity mapping on the input X. In the inference phase, these multi-branch structures will be fused to improve efficiency. At this time, W fusedRepresents the equivalent single convolution kernel weight obtained after fusion. This W fused It is done by adding the original 3×3 convolution kernel weight W 3×3 , the original 1×1 convolution kernel weight expanded to 3×3 size after padding operation (expressed as pad(W1×1)), and the diagonal matrix representing the contribution of the original identity mapping branch (simplified as diag(1), which is 1 at the center of the convolution kernel and 0 elsewhere). Finally, the output Y of the inference stage is obtained through this fused W fused Convolution is performed on the input X and then calculated by the activation function σ. Feature extraction stage (Backbone):

[0075] Focus layer: The input image is spatially rearranged. Using a pixel splitting strategy, the pixels in a 2×2 area are rearranged into channel dimensions (expanding from 3 channels to 12 channels). At the same time, the image resolution is reduced from 640×640 to 320×320, effectively retaining spatial information while reducing the computational complexity by 50%.

[0076] RepVGG downsampling block: replaces the Conv module in the original YOLOv5, performs initial feature extraction and downsampling, and reduces the feature map to 160×160×64.

[0077] Multi-level feature extraction: A layer-by-layer downsampling structure is formed by cascading RepVGG+C3 modules, which sequentially generate multi-scale feature maps of 80×80×128, 40×40×256, and 20×20×512 to capture the different scale features of PCB defects.

[0078] SPP module: Applies 5×5, 9×9, and 13×13 maximum pooling operations on the deepest features to enhance adaptability to defects of different sizes, such as tiny solder joints and larger residual copper areas.

[0079] Compared to the fixed convolutional architecture used in the original YOLOv5, the RepVGG module cleverly balances expressiveness and computational efficiency through differentiated structural designs during training and inference. While YOLOv5's original Conv module suffers from significant computational redundancy on edge devices, RepVGG utilizes reparameterization technology to merge complex multi-branch structures into a single, efficient 3×3 convolution during inference, significantly reducing the number of model parameters and improving model inference speed.

[0080] The Focus layer complements RepVGG's strengths: the former is responsible for channel expansion and feature reorganization, while the latter focuses on efficient feature extraction. While retaining YOLOv5's original Neck and Head design to ensure detection accuracy, the overall model is lightweight and performance is improved solely through efficient reconstruction of the backbone network.

[0081] S40: Fusing the extracted multi-scale features into a multi-scale feature map to identify PCB defects.

[0082] In a specific embodiment, step S40 is specifically as follows:

[0083] The extracted multi-scale features are used to generate multi-scale feature maps ranging from 20×20 to 80×80 using the FPN+PAN bidirectional fusion network to identify PCB defects.

[0084] In a specific embodiment, in step S40, multi-scale feature fusion specifically includes:

[0085] The 20×20×512, 40×40×256, and 80×80×128 feature maps output by the backbone network are interactively fused through top-down and bottom-up paths after dimensionality reduction by 1×1 convolution.

[0086] In this embodiment, the feature fusion stage (Neck):

[0087] A bidirectional feature fusion strategy is adopted that combines the top-down path of FPN (Feature Pyramid Network) and the bottom-up path of PAN (Path Aggregation Network).

[0088] Through 1×1 convolution dimensionality reduction and 3×3 convolution to extract semantic information, high-level semantic features are effectively integrated with low-level spatial features.

[0089] Three scale feature maps (80×80×128, 40×40×256, and 20×20×512) are generated, corresponding to the detection requirements of small, medium, and large PCB defects, respectively.

[0090] S50: Use the decoupling detection head to output the PCB defect location and category, and generate a defect map after screening by the non-maximum suppression algorithm.

[0091] In this embodiment, the detection stage (Head):

[0092] The decoupled head design separates position prediction and classification tasks, making it more suitable for the accurate identification of six major types of PCB defects (open circuits, short circuits, mouse bite marks, burrs, residual copper, and solder leaks).

[0093] The detection head is applied to the three scale feature maps respectively, and the predicted box coordinates, confidence and category probability distribution are output.

[0094] Finally, the optimal detection results are screened through the NMS (non-maximum suppression) algorithm to output the precise location and type of PCB defects.

[0095] S60: Generate corresponding defect text content according to the defect map and input it into the large language model to generate a semantic analysis report and sorting strategy instructions.

[0096] In a specific embodiment, step S60 specifically includes generating corresponding defect text content according to the defect map, inputting it into a large language model, executing correlation with historical defect data to generate process optimization suggestions, and dynamically adjusting the action parameters of the sorting mechanism.

[0097] This implementation not only achieves efficient testing but also establishes a complete data closed loop. After the entire batch is tested, all test data is seamlessly uploaded to a locally deployed industrial knowledge prediction model. Through time-series data analysis and production process correlation modeling, an intelligent analysis report containing process improvement suggestions and quality trend forecasts is automatically generated. This enables intelligent processing across the entire process chain, from testing to analysis to decision-making, providing data support for the continuous optimization of manufacturing processes.

[0098] This design constructs an efficient and high-precision PCB single-layer board defect automatic detection system through coordinated optimization of software and hardware.

[0099] First, during the image acquisition phase, an innovative transparent track combined with a uniformly projected light source from below breaks through the limitations of forward illumination in traditional PCB inspection. Taking advantage of the unique light transmittance of single-layer PCBs, a cleverly designed backward illumination system allows light to penetrate from below, perfectly capturing every detail, including the circuitry and solder joints.

[0100] Based on the images captured by this high-contrast, high-quality optical imaging system, the detection algorithm was further optimized to meet the needs of efficient, real-time PCB defect detection on edge devices. Specifically, the original YOLOv5n model was optimized and improved by introducing the RepVGG structure.

[0101] This model optimization achieved significant performance improvements. Optimization data shows that the model inference speed increased significantly from the original 202 FPS to 273.43 FPS, achieving a 35.36% speed gain. Simultaneously, the number of model parameters was reduced from 1,768,636 to 937,108, a 47.02% reduction, significantly reducing the computational burden on edge devices. While maintaining a lightweight model, detection accuracy only slightly decreased from 0.957 to 0.936, with a loss of only 2.19%. This slight sacrifice in accuracy yielded significant improvements in speed and storage efficiency, fully demonstrating the effectiveness and practical value of this algorithm optimization strategy in single-layer PCB defect detection scenarios.

[0102] In summary, the present invention provides high-quality inspection images through an innovative bottom-backlight optical solution, and combines the efficient RepVGG-YOLOv5n model optimization to achieve fast and lightweight defect recognition, constructing a set of PCB single-layer board defect automatic detection system with excellent performance, controllable cost and suitable for edge deployment.

[0103] like Figure 8 As shown, an embodiment of the present invention further provides a PCB defect detection device based on edge computing, including:

[0104] The image acquisition module 100 is used to respond to the positioning signal triggered by the color sensor when the PCB board enters the conveyor belt. It uses the PID algorithm to control the servo motor to accurately position the PCB board to the center of the industrial camera's field of view to capture the circuit image. The conveyor belt is a high-transmittance conveyor belt with an upward-illuminating light source located below the conveyor belt.

[0105] A preprocessing module 200 is used to preprocess the circuit image through an edge computing microserver;

[0106] A feature extraction module 300 is used to input the preprocessed image into a lightweight YOLO detection model, which extracts multi-scale features through a backbone network optimized by the RepVGG module;

[0107] A feature fusion module 400 is used to fuse the extracted multi-scale features into a multi-scale feature map to identify PCB defects;

[0108] Defect recognition module 500, which uses a decoupling detection head to output the location and category of PCB defects, and generates a defect map after screening using a non-maximum suppression algorithm;

[0109] The defect processing module 600 is used to generate corresponding defect text content according to the defect map, input the large language model, and generate a semantic analysis report and sorting strategy instructions.

[0110] It should be noted that technical personnel in the relevant field can clearly understand that the specific implementation process of the above-mentioned edge computing-based PCB defect detection device can refer to the corresponding description in the aforementioned method embodiment. For the convenience and conciseness of the description, it will not be repeated here.

[0111] The above-mentioned PCB defect detection device based on edge computing can be implemented in the form of a computer program. The computer program can be used in Figure 9 Runs on the computer device shown.

[0112] See also Figure 9 , Figure 9This is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 can be a terminal or a server. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, personal digital assistant, wearable device, or other electronic device with communication capabilities. The server can be a standalone server or a server cluster consisting of multiple servers.

[0113] See Figure 9 The computer device 500 includes a processor 502 , a memory, and a network interface 505 connected via a system bus 501 , wherein the memory may include a non-volatile storage medium 503 and an internal memory 504 .

[0114] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions, which, when executed, enable the processor 502 to execute a PCB defect detection method based on edge computing.

[0115] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.

[0116] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a PCB defect detection method based on edge computing.

[0117] The network interface 505 is used to communicate with other devices through the network. Figure 9 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than shown in the figure, or combine certain components, or have a different component arrangement.

[0118] The processor 502 is configured to run a computer program 5032 stored in a memory to implement the edge computing-based PCB defect detection method as described above.

[0119] It should be understood that in the embodiment of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0120] Those skilled in the art will appreciate that all or part of the steps in the method of the above-described embodiment can be implemented by instructing the relevant hardware through a computer program. The computer program includes program instructions, which can be stored in a storage medium that is computer-readable. The program instructions are executed by at least one processor in the computer system to implement the steps in the method of the above-described embodiment.

[0121] Therefore, the present invention also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the above-described edge computing-based PCB defect detection method.

[0122] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0123] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the composition and steps of each example according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0124] In the several embodiments provided herein, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the various units is merely a logical functional division, and actual implementation may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented.

[0125] The steps in the methods of the embodiments of the present invention may be adjusted in order, combined, or deleted as needed. The units in the devices of the embodiments of the present invention may be combined, divided, or deleted as needed. Furthermore, the functional units in the various embodiments of the present invention may be integrated into a single processing unit, each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0126] If this integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the existing technology, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes a number of instructions for causing a computer device (which can be a personal computer, terminal, or network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present invention.

[0127] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A PCB defect detection method based on edge computing, characterized in that: include: S10. When the PCB board enters the conveyor belt, in response to the positioning signal triggered by the color sensor, the PID algorithm is used to control the servo motor to accurately position the PCB board to the center of the field of view of the industrial camera to capture the circuit image. The conveyor belt is a high-transmittance conveyor belt with an upward irradiation light source provided below the conveyor belt; S20, preprocessing the circuit image through the edge computing microserver; S30, inputting the preprocessed image into a lightweight YOLO detection model, wherein the lightweight YOLO detection model extracts multi-scale features through a backbone network optimized by a RepVGG module; S40, fusing the extracted multi-scale features into a multi-scale feature map to identify PCB defects; S50: Use the decoupling detection head to output the PCB defect location and category, and generate a defect map after screening by the non-maximum suppression algorithm; S60: Generate corresponding defect text content according to the defect map and input it into the large language model to generate a semantic analysis report and sorting strategy instructions.

2. The PCB defect detection method based on edge computing according to claim 1 is characterized in that: The optimization of the RepVGG module in step S30 includes: The multi-branch structure is adopted in the training phase: Training:Y=σ(W 3*3 *X+W 1*1 *X+X) The inference phase is reparameterized into a single-branch convolution: Inference:Y=σ(W fused *X) Among them, W fused is the equivalent weight after fusion, which is calculated as follows: W fused =W 3*3 +pad(W 1*1 )+diag(1) Among them, Y represents the feature map of the final output of the module, and X refers to the feature map of the input RepVGG module. The σ symbol represents the activation function, and the ReLU activation function is used.

3. The PCB defect detection method based on edge computing according to claim 1 is characterized in that: In step S10, the upward irradiation light source is specifically: A uniform surface light source array is set under the conveyor belt. The wavelength range of the light source is 400-700nm and the light intensity can be adjusted from 0-50000lux.

4. The PCB defect detection method based on edge computing according to claim 1, characterized in that: Step S40 is specifically as follows: The extracted multi-scale features are used to generate multi-scale feature maps ranging from 20×20 to 80×80 using the FPN+PAN bidirectional fusion network to identify PCB defects.

5. The PCB defect detection method based on edge computing according to claim 4 is characterized in that: In step S40, multi-scale feature fusion specifically includes: The 20×20×512, 40×40×256, and 80×80×128 feature maps output by the backbone network are interactively fused through top-down and bottom-up paths after dimensionality reduction by 1×1 convolution.

6. The PCB defect detection method based on edge computing according to claim 1, characterized in that: Step S60 specifically includes generating corresponding defect text content according to the defect map, inputting it into a large language model, executing the associated historical defect data, generating process optimization suggestions, and dynamically adjusting the action parameters of the sorting mechanism.

7. The PCB defect detection method based on edge computing according to claim 1, characterized in that: In step S20, the circuit image is preprocessed by the edge computing microserver, including adaptive illumination compensation and dynamic threshold binarization.

8. A PCB defect detection device based on edge computing, characterized in that: include: An image acquisition module is used to control a servo motor using a PID algorithm to precisely position the PCB to the center of the industrial camera's field of view when the PCB enters the conveyor belt. The conveyor belt is a highly transparent conveyor belt with an upward irradiation light source located below it. A preprocessing module, used to preprocess the circuit image through the edge computing microserver; A feature extraction module is used to input the preprocessed image into a lightweight YOLO detection model, which extracts multi-scale features through the backbone network optimized by the RepVGG module; Feature fusion module, used to fuse the extracted multi-scale features into a multi-scale feature map to identify PCB defects; The defect recognition module uses a decoupled detection head to output the location and category of PCB defects, and generates a defect map after screening using a non-maximum suppression algorithm; The defect processing module is used to generate the corresponding defect text content according to the defect map, input the large language model, and generate a semantic analysis report and sorting strategy instructions.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the edge computing-based PCB defect detection method according to any one of claims 1 to 7 when executing the computer program.

10. A storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by the processor, it can implement the PCB defect detection method based on edge computing as described in any one of claims 1 to 7.

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