Gate drive circuit and display device

Abstract

The embodiment of the invention provides a gate drive circuit and a display device. The gate driving circuit comprises cascaded gate driving units. Wherein two control ends of a first anti-phase sub-module included in a first output module in the gate driving unit are connected to a third node (W). When the partition frequency division function of the display panel driven by the gate drive circuit is started, the first gate control signal output by the first output module can continuously output low level, so that the situation that the output end of the first output module is in a passive output state in the partition frequency division process is avoided.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display device. Background Art

[0002] With advancements in display technology, current gate driver circuits (GOAs) have introduced a zoned frequency modulation function, allowing display panels to display in separate zones. Each zone can have a different refresh rate to accommodate varying display needs. For example, a high refresh rate can be set for video viewing, while a low refresh rate can be set for static images such as web pages to save power. However, when the zoned frequency modulation function is activated, the GOA circuit may cause abnormal output due to internal short circuits within the display panel or other micro-short circuits. Summary of the Invention

[0003] The embodiments of the present application provide a gate driving circuit and a display device to solve the above-mentioned technical problems.

[0004] On the one hand, an embodiment of the present application provides a gate drive circuit, comprising a plurality of cascaded gate drive units, wherein the gate drive unit comprises: a shift register module, a frequency division module and an output module, wherein; the shift register module is connected to the frequency division module via a first node, and is used to transmit a frame start signal transmitted by a frame start line or a voltage of a second node of the gate drive unit of the previous stage to the first node in response to a first clock signal transmitted by a first clock line; the frequency division module comprises a first frequency division module; the first frequency division module is connected to the output module via a third node, and is used to connect or disconnect the electrical connection between the first node and the third node in response to a first frequency division control signal transmitted by a first frequency division control line; the first frequency division module disconnects the first node in response to the first frequency division control signal When the electrical connection between the point and the third node is established, the first partition frequency division function is turned on; the output module includes a first output module; the first output module includes a first inverting submodule; the first inverting submodule includes a first control end and a second control end respectively connected to the third node, a first input end connected to a first power line for transmitting a first power signal, a second input end connected to a second power line for transmitting a second power signal, and an output end for outputting a first gate control signal; the amplitude of the first power signal is greater than the amplitude of the second power signal; wherein, when the first partition frequency division function is turned on, the first inverting submodule outputs the second power signal provided by the second input end of the first inverting submodule as the first gate control signal under the voltage control of the third node.

[0005] On the other hand, an embodiment of the present application further provides a display device, comprising a plurality of pixel units arranged in an array and any one of the gate driving circuits described above, wherein each of the gate driving units is configured to drive at least one row of the pixel units.

[0006] The gate drive circuit provided in an embodiment of the present application is configured by connecting the two control terminals (first control terminal and second control terminal) of the first inverting submodule in the first output module to a third node. Furthermore, when the first partition frequency modulation function is activated, the electrical connection between the first node and the third node is disconnected, and the first inverting submodule outputs the second power supply signal provided by the second input terminal of the first inverting submodule as the first gate control signal under the voltage control of the third node. Thus, during partition frequency modulation, the output terminal of the first output module does not enter a passive output state, thereby preventing the GOA circuit from causing output abnormalities due to internal micro-short circuits in the display panel or other micro-short circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0008] Figure 1 Schematic diagram of an application scenario of the gate drive circuit provided in an embodiment of the present application.

[0009] Figure 2 This is a module diagram of the gate drive unit provided in an embodiment of the present application.

[0010] Figure 3 A circuit diagram of a gate drive unit provided in an embodiment of the present application.

[0011] Figure 4 Waveforms of some node signals in the gate drive unit provided in the embodiment of the present application Figure 1 .

[0012] Figure 5 Waveforms of some node signals in the gate drive unit provided in the embodiment of the present application Figure 2 .

[0013] Figure 6 Waveforms of some node signals in the gate drive unit provided in the embodiment of the present application Figure 3 .

[0014] Figure 7 For example, the embodiment of this application provides Figure 3 A working timing diagram of the gate drive unit shown. DETAILED DESCRIPTION

[0015] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0016] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or apparatus.

[0017] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0018] The embodiments of the present application provide a display compensation method, which includes but is not limited to the following embodiments and combinations of the following embodiments.

[0019] Reference Figure 1 As shown, it exemplarily shows a schematic diagram of the gate drive circuit provided by an embodiment of the present application applied to a display device. The display device 100 may include a plurality of pixel units P, a plurality of gate lines 10 and a gate drive circuit 20. The plurality of pixel units P may be arranged in rows and columns to form a plurality of pixel rows arranged along the row direction and a plurality of pixel columns arranged along the column direction, and each pixel row and each pixel column includes a plurality of pixel units. For ease of description, the pixel rows and pixel columns may also be referred to as "rows" and "columns" hereinafter. The gate drive circuit 20 may include a plurality of cascaded gate drive units 201. Each gate drive unit 201 is connected to at least one row of pixel units P via a gate line 10 to drive at least one row of pixel units P. The embodiment of the present application is an improvement to the gate drive unit 201. For ease of description, Figure 2 and Figure 3Only the n-th gate driver unit 201 is used as an example. Where n is a positive integer greater than or equal to 1. If n is greater than or equal to 3, then the signal P(n-2) of the second node P of the (n-2)-th gate driver unit 201 and the signal P(n-1) of the second node P of the (n-1)-th gate driver unit 201 required in the n-th gate driver unit 201 can be directly provided by the (n-2)-th gate driver unit 201 and the (n-1)-th gate driver unit 201, respectively. If n is less than 3, the above signals can be provided by a dummy gate driver unit (which does not output gate control signals to the display panel).

[0020] like Figure 2 and 3 As shown, the gate driving unit 201 may include: a shift register module 301, a frequency dividing module 302, an output module 303, and a self-stabilizing module 304. The shift register module 301 may be connected to the frequency dividing module 302 and the self-stabilizing module 304 via a first node K. The first frequency dividing module 3021 of the frequency dividing module 302 may be connected to the first output module 3031 of the output module 303 via a third node W.

[0021] Specifically, if Figure 3 As shown, the shift register module 301 can be used to respond to the valid level of the first clock signal XCK transmitted by the first clock line (exemplarily as shown in FIG. Figure 3 As shown, the effective level of the first clock signal is a low level L), and the frame start signal STV transmitted by the frame start line or the signal (or voltage) P(n-1) of the second node P of the previous gate driving unit 201 is transmitted to the first node K. Specifically, as Figure 3As shown, the shift register module 301 may include a second inverting submodule 3011 and a fifth transistor T2. The second inverting submodule 3011 includes a third transistor T13 and a fourth transistor T12, wherein a first end of the third transistor T13 is connected to a third power line for transmitting a third power signal NVGL1, a second end of the third transistor T13 and a first end of the fourth transistor T12 are connected to a fifth node O, a control end of the third transistor T13 and a control end of the fourth transistor T12 are connected to the frame start line or the second node P of the gate drive unit of the previous stage; and a second end of the fourth transistor T12 is connected to a fourth power line for transmitting a fourth power signal PVGH, wherein the third power signal NVGL1 is a DC signal and has an amplitude at a low level (or, in other words, at a low potential). The amplitude of the second power signal NVGL2 described later is greater than the amplitude of the third power signal NVGL1, or in other words, the potential of the second power signal NVGL2 described later is higher than the potential of the third power signal NVGL1. The second inverting submodule 3011 can be used to transmit the third power signal NVGL1 transmitted by the third power line to the fifth node O or transmit the fourth power signal PVGH transmitted by the fourth power line to the fifth node O in response to the frame start signal STV or the voltage of the second node P of the gate driving unit at the previous stage. Specifically, when the frame start signal STV or the voltage P(n-1) of the second node P of the gate driving unit at the previous stage is a high level (H), the third transistor T13 is turned on to transmit the third power signal NVGL1 to the fifth node O. When the frame start signal STV or the voltage P(n-1) of the second node P of the gate driving unit at the previous stage is a low level (L), the fourth transistor T12 is turned on to transmit the fourth power signal PVGH to the fifth node O. The fourth power signal PVGH is also a DC signal, and its amplitude is at a high level, that is, the amplitude of the fourth power signal PVGH is greater than the amplitude of the third power signal NVGL1 and the second power signal NVGL2 described later. Figure 3 As shown, a first terminal of the fifth transistor T2 is connected to the fifth node O, a second terminal of the fifth transistor T2 is connected to the first node K, and a control terminal of the fifth transistor T2 is connected to the first clock line. The fifth transistor is configured to transmit the third power signal NVGL1 to the first node via the fifth node or transmit the fourth power signal PVGH to the first node via the fifth node in response to the first clock signal XCK, so as to control the voltage of the first node K.

[0022] For the frequency division module 302, if Figure 2 and Figure 3As shown, the frequency division module 302 may include a first frequency division module 3021 and a second frequency division module 3022, wherein the first frequency division module 3021 is connected to the first output module 3031 of the output module 303 via a third node W, and is configured to connect or disconnect the electrical connection between the first node K and the third node W in response to a first frequency division control signal NLF transmitted by a first frequency division control line. Specifically, as Figure 3 As shown, the first frequency division module 3021 may include a sixth transistor T16, a seventh transistor T11, and a first capacitor C2. The first end of the sixth transistor T16 is connected to the first frequency division control line, the second end of the sixth transistor T16 is connected to the sixth node H, and the control end of the sixth transistor T16 is connected to the second node P of the gate drive unit at this stage. The first end of the seventh transistor T11 is connected to the first node K, the second end of the seventh transistor T11 is connected to the third node W, and the control end of the seventh transistor T11 is connected to the sixth node H. The first capacitor C2 is connected between the third node W and the sixth node H. When the first frequency division control signal NLF is at a first level, the seventh transistor T11 remains in an on state to electrically connect the first node K to the third node W. When the first frequency division control signal NLF is at a second level, the seventh transistor T11 remains in an off state to disconnect the first node from the third node. Here, the first level may be a low level, and the second level may be a high level. How the first frequency-division control signal NLF is at the first level to connect the electrical connection between the first node K and the third node W, and how the first frequency-division control signal NLF is at the second level to disconnect the electrical connection between the first node K and the third node W, will be described in detail in the timing description to be described later and will not be repeated here.

[0023] The gate drive unit 201 can operate in a first mode of non-divided frequency division or in a second mode of divided frequency division, wherein when the first frequency division module 3021 of the frequency division module 302 disconnects the electrical connection between the first node K and the third node W in response to the first frequency division control signal NLF, the first divided frequency division function is turned on, so that the gate drive unit 201 operates in the second mode of divided frequency division; when the first frequency division module 3021 of the frequency division module 302 connects the electrical connection between the first node K and the third node W in response to the first frequency division control signal NLF, the first divided frequency division function is not turned on, so that the gate drive unit 201 operates in the first mode of non-divided frequency division. That is, if the first frequency division control signal NLF transmitted by the first frequency division control line is always at a low level (L), the gate drive unit 201 always operates in the first mode. If the first frequency division control signal NLF is switched from a low level to a high level, the gate drive unit 201 switches from operating in the first mode to operating in the second mode. Based on this, if the gate drive unit 201 operates in the first mode, exemplarily as follows Figure 4 As shown in FIG, the waveforms of the voltages at the first node K and the third node W are consistent. Figure 4 As shown, when the potential of the first node K is low, the potential of the third node W is also low. Conversely, when the potential of the first node K is high (H), the potential of the third node W is also high ( Figure 4 (not shown). This situation is equivalent to the first node K and the third node W being in a connected state all the time. For a detailed understanding, please refer to the subsequent Figure 7 If the gate drive unit 201 switches to operate in the second mode, the gate drive unit 201 is switched to operate in the second mode, as shown in FIG. Figure 5 As shown in FIG, the waveforms of the voltage signals at the first node K and the third node W are inconsistent. Figure 5 As shown, when the first frequency division control signal NLF is at a high level and the voltage (or potential) of the first node K is at a low level, the voltage of the third node W is at a high level. In another case, when the voltage of the first node K is at a high level (H), the voltage of the third node W is still at a high level ( Figure 5 (not shown). In short, the voltage of the third node W does not change with the change of the first node K. This situation is equivalent to the first node K and the third node W being disconnected.

[0024] As for the second frequency dividing module 3022, the second frequency dividing module 3022 includes an input terminal connected to the first node K, a first control terminal connected to the second frequency dividing control line, a second control terminal connected to the second node P of the gate driving unit of this stage, and an output terminal connected to the seventh node M. The second frequency dividing module 3022 can respond to the second frequency dividing control signal PLF transmitted by the second frequency dividing control line to connect or disconnect the electrical connection between the first node K and the seventh node M. Specifically, Figure 3 As shown, the second frequency division module 3022 may include a ninth transistor T20, a tenth transistor T19, and a second capacitor C3. The first end of the ninth transistor T20 is connected to the second frequency division control line, the second end of the ninth transistor T20 is connected to the ninth node X, and the control end of the ninth transistor T20 is connected to the second node P of the gate driving unit at this stage. The first end of the tenth transistor T19 is connected to the first node K, the second end of the tenth transistor T19 is connected to the seventh node M, and the control end of the ninth transistor T19 is connected to the ninth node X. The second capacitor C3 is connected between the ninth node X and the seventh node M. The operating principle of the second frequency-dividing module 3022 is as follows: when the second frequency-dividing control signal PLF transmitted by the second frequency-dividing control line is at a first level, the tenth transistor T19 is maintained in an on state to establish an electrical connection between the first node K and the seventh node M; when the second frequency-dividing control signal PLF transmitted by the second frequency-dividing control line is at a second level, the tenth transistor T19 is maintained in an off state to disconnect the electrical connection between the first node K and the seventh node M, thereby enabling the second frequency-dividing function. It should be noted that the second frequency-dividing module 3022 operates in the same manner as the first frequency-dividing module 3021. Please refer to the aforementioned description of the operating mode of the first frequency-dividing module 3021 for understanding, and will not be repeated here.

[0025] For the output module 303, if Figure 2 and Figure 3 As shown, the output module 303 may include a first output module 3031 and a second output module 3032, wherein Figure 3As shown, the first output module 3031 may include a first inverting submodule 30311, a transistor T17, and a transistor T18. The first inverting submodule 30311 includes a first control terminal and a second control terminal respectively connected to the third node W, a first input terminal connected to a first power line for transmitting a first power signal NVGH, a second input terminal connected to a second power line for transmitting a second power signal NVGL2, and an output terminal for outputting a first gate control signal Nout(n). The amplitude of the first power signal NVGH is greater than the amplitude of the second power signal NVGL2. Thus, the first power signal NVGH can be a high-level DC signal, and the second power signal NVGL2 can be a low-level DC signal. When the first partitioning and frequency-demodulation function is enabled, the first inverting submodule 30311 outputs the second power signal NVGL2 provided by the second input terminal of the first inverting submodule 30311 as the first gate control signal under the voltage control of the third node. It should be noted that the high level mentioned in the embodiment of the present application may refer to the first voltage range that can turn on the N-type transistor. In other words, the level in the first voltage range can turn on the N-type transistor. Similarly, the low level may refer to the second voltage range that cannot turn on the N-type transistor. In other words, the level in the second voltage range cannot turn on the N-type transistor. For the P-type transistor, the opposite is true. The level in the first voltage range cannot turn on the P-type transistor, and the level in the second voltage range can turn on the P-type transistor. The high level and low level described before or after can be understood in accordance with the above description. Figure 3 As shown, the aforementioned first inverting submodule 30311 may include a first transistor T9 and a second transistor T10. Wherein; the first end of the first transistor T9 and the first end of the second transistor T10 are connected to the fourth node Y, the control end of the first transistor T9 and the control end of the second transistor T10 serve as the first control end and the second control end of the first sub-inverting submodule respectively and are commonly connected to the third node W. The second end of the first transistor T9 is connected to the first power line as the first input end of the first inverting submodule 30311. The second end of the second transistor T10 is connected to the second power line as the second input end of the first inverting submodule 30311. As an example, the first transistor T9 may be a P-type indium gallium zinc oxide thin film transistor (IGZON TFT). The second transistor T10 may be an N-type indium gallium zinc oxide thin film transistor (IGZO NTFT). For the connection of transistor T17 and transistor T18, please refer to Figure 3 As shown, the functions of the transistor T17 and the transistor T18 can be found in the subsequent description of the working process of the gate driving unit, which will not be repeated here.

[0026] Based on this, in actual application, the first inverting sub-module 30311 can be used to transmit the first power signal NVGH to the fourth node Y in response to the voltage of the third node W being at a low level, or to transmit the second power signal NVGL2 to the fourth node Y in response to the voltage of the third node W being at a high level. The voltage of the fourth node Y is the first gate control signal Nout(n) output by the first output module 3031.

[0027] As can be seen from the description of the frequency division module 302, the gate driving unit 201 can operate in the second mode of frequency division or the first mode of non-frequency division. When the gate driving unit 201 operates in the second mode, the first gate control signal Nout(n) output by the first output module 3031 needs to be low level so as not to drive the corresponding pixel unit P. It should be noted that according to the above Figure 1 As shown, each gate driving unit 201 drives at least one row of pixel units P in the display panel. Based on this, if each gate driving unit 201 is always operating in the first mode, the display panel is not divided into regions for display, and the entire display area of ​​the entire display panel corresponds to a refresh rate, such as 120 megahertz (MHZ). If the entire display area of ​​the display panel is to be divided into regions for display, and the refresh rate of each region is set to be different, in this case, the gate driving unit 201 corresponding to each region will gradually switch the operating mode from the first mode to the second mode.

[0028] For example, assume that the refresh rate of the display panel is 120 MHz when the frequency is not divided, and the display area of ​​the display panel is expected to be divided into four sub-display areas, namely the first sub-display area, the second sub-display area, the third sub-display area, and the fourth sub-display area, and the refresh rates of each sub-display area are 30 MHz, 60 MHz, 90 MHz, and 120 MHz, respectively. In this case, the operating mode of the gate drive unit 201 corresponding to the first sub-display area is first switched from the first mode to the second mode. Thereafter, the operating modes of the gate drive unit 201 corresponding to the second sub-display area and the gate drive unit 201 corresponding to the third sub-display area are also gradually switched from the first mode to the second mode. The operating mode of the gate drive unit 201 corresponding to the fourth sub-display area remains in the first mode.

[0029] Based on this, if the gate driving unit 201 operates in the first mode, the first gate control signal NLF is always at a low level (L). Figure 4As shown, the voltage waveforms of the first node K and the third node W are consistent. In this case, when the voltage of the first node K is low, the voltage of the third node W is also low. At this time, the first transistor T9 included in the first output module 3031 is turned on in response to the third node W being at a low level, and the first power signal NVGH transmitted by the first power line is output from the first output module 3031 as the first gate control signal Nout(n). At this time, the first gate control signal Nout(n) is high. When the voltage of the first node K is high, the voltage of the third node W is also high. At this time, the second transistor T10 included in the first output module 3031 is turned on in response to the third node W being at a high level, and the second power signal NVGL2 transmitted by the second power signal is output from the first output module 3031 as the first gate control signal Nout(n). At this time, the first gate control signal Nout(n) is low. Moreover, during the entire driving process, the output end of the first output module 3031 either outputs the first power signal NVGH or the second power signal NVGL2, and there will be no passive output state (or, the output end of the first output module 3031 will not be in a floating state).

[0030] If the gate driving unit 201 operates in the second mode, Figure 5As shown, the first gate control signal NLF is at a high level, and the voltage waveforms of the first node K and the third node W are inconsistent. In this case, when the voltage of the first node K is at a low level, due to the presence of the first capacitor C2, the voltage signal of the third node W is coupled to a high level by the first frequency-divided control signal NLF at a high level. At this time, if the control terminal of the second transistor T10 is connected to the first node K, since the first node K is at a low level, the second transistor T10 is cut off. Since the third node W is at a high level due to the coupling effect, the first transistor T9 is also cut off. At this time, the output terminal of the first output module 3031 has a passive output. At this time, if there is a micro-shorting (shorting) or other micro-short circuit inside the display panel, the potential of the output terminal of the first output module 3031 will be coupled to a high level, thereby causing the output of the first output module 3031 to be abnormal, and then, the pixel unit will be abnormally driven. The gate drive circuit 20 provided in the embodiment of the present application connects the control terminal of the second transistor T10 and the first transistor T9 to the third node W. This connection method, as mentioned above, will not affect the gate drive unit 201 operating in the first mode. In addition, after the operating mode of the gate drive unit 201 is switched to the second mode, the third node W will be coupled to a high level according to the first frequency division control signal NLF at a high level. At this time, the second transistor T10 is turned on according to the third node W at a high level, and the second power supply signal NVGL2 is transmitted to the output end of the first output module 3031, so as to eliminate the situation where the output end of the first output module 3031 does not have a passive output when the gate drive unit 201 operates in the second mode, thereby ensuring that the first gate control signal Nout(n) output by the first output module 3031 will not be affected by the micro-short circuit or other micro-short circuits inside the display panel. Specifically, see for example Figure 6 The simulation diagram shown. Figure 6 In the figure, it is assumed that the voltage of the first node K is at a low level, the voltage of the third node W is at a high level, and the control terminals of the second transistor T10 and the first transistor T9 are both connected to the third node. At this time, the second transistor T10 is turned on and the first transistor T9 is turned off. At this time, a micro-shorting interference is added. Because the second transistor T10 can continuously provide a stable second power supply signal NVGL2 to the first output module 3031 when it is turned on, the first gate control signal NOUT(n) output by the first output module 3031 is always at a low level and is not affected by the micro-shorting.

[0031] In actual application, considering the threshold loss of the seventh transistor T11, the potential of the second power signal NVGL2 is greater than the potential of the third power signal NVGL1 to ensure that the second transistor T10 can be turned on when the gate driving unit 201 operates in the second mode.

[0032] In some embodiments, as Figure 3 As shown, the second output module 3032 may include an output submodule 30321, an eighth transistor T8, a transistor T21, a transistor T22, and a third capacitor C1. The first end of the eighth transistor T8 is connected to the seventh node M, the second end of the eighth transistor T8 is connected to the eighth node Q, and the control end of the eighth transistor T8 is connected to the second node P of the first two stages of the gate driving unit. Based on this, the eighth transistor T8 can be used to transmit the voltage of the seventh node M to the eighth node Q in response to the voltage P(n-2) of the second node P of the first two stages of the gate driving unit. The output submodule 30321 may include a first control terminal connected to the seventh node Q, a second control terminal connected to the second node P of the gate driving unit at this stage, a first input terminal connected to a fourth power line for transmitting a fourth power signal PVGH, a second input terminal connected to a second clock line, and an output terminal for outputting a second gate control signal Pout(n). The output submodule 30321 may be configured to output the fourth power signal PVGH as the second gate control signal Pout(n) in response to the voltage P(n) of the second node P of the gate driving unit at this stage, or to output the second clock signal CK transmitted by the second clock line as the second gate control signal Pout(n) in response to the voltage of the eighth node Q. Specifically, see Figure 3 As shown, the output submodule 30321 may include an eleventh transistor T6 and a twelfth transistor T7. The first end of the eleventh transistor T6 is connected to the second clock line, the second end of the eleventh transistor T6 and the first end of the twelfth transistor T7 are connected to the tenth node F, the control end of the eleventh transistor T6 is connected to the eighth node Q, the second end of the twelfth transistor T7 is connected to the fourth power line, and the control end of the twelfth transistor T7 is connected to the second node P of the gate driving unit at this level, wherein the second gate control signal (Pout(n)) is the voltage signal of the tenth node F. It should be noted that the connection of the transistor T21, the transistor T22 and the third capacitor C1 can be seen in Figure 3 As shown, the functions of the transistor T21 , the transistor T22 and the third capacitor C1 can be found in the subsequent description of the working process of the gate driving unit, which will not be repeated here.

[0033] In some embodiments, for the self-stabilizing module 304, see Figure 2 and Figure 3As shown, the self-stabilizing module 304 can be connected to the shift register module 301 via the first node K, and is used to control the potential of the first node K together with the shift register module 301. Finally, the voltage of the first node K is used to control the first gate control signal Nout(n) at the output end of the first output module 3031 and the second gate control signal Pout(n) at the output end of the second output module 3032, thereby controlling the opening state of multiple pixel units P in the display panel. Specifically, as Figure 3 As shown, the self-stabilizing module 304 may include: a thirteenth transistor T5, a fourteenth transistor T4, a transistor T14, a transistor T15, and a third inverting submodule 3041. The control end of the thirteenth transistor T5 and the control end of the transistor T14 are connected to the second node of the gate driving unit of the current stage, which is controlled by the voltage of the first node; the first end of the thirteenth transistor T5 is connected to the fourth power line, and the second end of the thirteenth transistor T5 is connected to the first node via the fourteenth transistor T4; the first end of the transistor T14 is connected to the fifth power line for transmitting the fifth power signal NVGL, and the second end of the transistor T14 is connected to the first node K; the amplitude of the fourth power signal PVGH is greater than the amplitude of the fifth power signal NVGL; the amplitude of the fifth power signal NVGL is less than the amplitude of the second power signal NVGL2; and When the voltage of the first node K is at the first level, the voltage of the second node P of the gate driving unit at this level is at the second level, and the transistor T14 is turned on according to the second level of the voltage of the second node P of the gate driving unit at this level, and transmits the fifth power signal NVGL to the first node K to maintain the voltage of the first node K at the first level; when the voltage of the first node K is at the second level, the voltage of the second node P of the gate driving unit at this level is at the first level, and the thirteenth transistor T5 is turned on according to the first level of the voltage of the second node P of the gate driving unit at this level, and transmits the fourth power signal PVGH to the first node K to maintain the voltage of the first node K at the second level.

[0034] In the self-stabilizing module 304, a first terminal of transistor T15 is connected to the fourth power line, a second terminal of transistor T15 is connected to the first node K, and a control terminal of transistor T15 is connected to a control line for transmitting a power-on control signal. The third inverting submodule 1041 may include a transistor T3 and a transistor T1, wherein a first terminal of transistor T3 and a first terminal of transistor T1 are connected to the second node P of the gate drive unit at this stage, a control terminal of transistor T3 and a control terminal of transistor T1 are connected to the first node K, and a second terminal of transistor T3 is connected to the fourth power line; a second terminal of transistor T1 is connected to a sixth power line for transmitting a sixth power signal PVGL; wherein the fourth power signal is a high-level DC signal, and the sixth power signal is a low-level DC signal, i.e., the amplitude of the fourth power signal PVGH is greater than the amplitude of the sixth power signal PVGL. Based on this, the third inverting sub-module 3041 can be used to transmit the sixth power signal PVGL to the second node P of the gate driving unit 201 of this stage in response to the voltage of the first node K being a high level, or to transmit the fourth power signal PVGH to the second node P of the gate driving unit 201 of this stage in response to the voltage of the first node K being a low level.

[0035] In the embodiment of the present application, the types of the above-mentioned multiple transistors, the signals loaded by the multiple transistors and capacitors, and the connection relationship can refer to but are not limited to Figure 3 Shown only as an example, based on Figure 3 The types of the multiple transistors listed, such as transistor T1, the fourteenth transistor T4, transistor T10, transistor T13, transistor T14, transistor T17, and transistor T21 are N-type transistors. Transistor T2, transistor T3, the thirteenth transistor T5, transistor T6, transistor T7, transistor T8, transistor T9, transistor T11, transistor T12, transistor T15, transistor T16, the sixth transistor T18, transistor T19, transistor T20, and transistor T22 are P-type transistors. The waveform diagrams of the corresponding multiple signals and nodes can be referred to respectively. Figure 7 Of course, if the transistor type is different from Figure 3 As shown, the corresponding signals and node waveforms also need to be changed accordingly.

[0036] In order to better illustrate the working principle of the gate driving circuit 20 in the display device 100 of the present invention, the gate driving circuit 20 is shown in FIG. Figure 3 The gate drive unit 201 structure shown and Figure 7 The waveform diagram shown takes the n-th stage gate driving unit 201 as an example to illustrate the working process as follows.

[0037] After power-on, the power-on control signal Control is used to control transistor T15 to conduct, thereby transmitting the high level of the fourth power signal PVGH transmitted by the fourth power line to the first node K, turning off transistor T3 and turning on transistor T1. The low level of the sixth power signal PVGL transmitted by the sixth power line is then transmitted to the second node P of the local gate driver unit 201, turning on the sixth transistor T16 and the ninth transistor T20. At this time, if the first frequency division control signal NLF and the second frequency division control signal PLF are both at corresponding low levels, the seventh transistor T11 and the tenth transistor T19 are turned on, and the voltage W(n) at the third node W is at a high level, as is the voltage M(n) at the seventh node M. This turns off the second transistor T9 and turns on the third transistor T10 based on the high level of the third node W, thereby outputting the second power signal NVGL2 as the first gate control signal Nout(n). At this time, the first gate control signal Nout(n) is at a low level. It should be noted that, at this time, it can be considered that the voltage P(n-2) of the second node P of the (n-2)-th level gate driving unit 201 is also at a corresponding low level, so that the eighth transistor T8 is turned on, the eighth node Q is at a high level, so that the eleventh transistor T6 is turned off, and at the same time, the voltage P(n) of the second node P of the current level gate driving unit 201 is at a low level, so that the twelfth transistor T7 is turned on, so as to output the fourth power signal PVGH transmitted by the fourth power line as the second gate control signal Pout(n).

[0038] During time period t1, the first clock signal XCK transmitted by the first clock line is at a corresponding high level, the second clock signal CK transmitted by the second clock line is at a corresponding low level, and the frame start signal STV or the voltage P(n-1) at the second node P of the (n-1)-th gate driver unit 201 is at a corresponding high level. The third transistor T13 is turned on, transmitting the third power signal NVGL1 transmitted by the third power line to the fifth node O. The fifth transistor T2 is turned off in response to the high first clock signal. At this time, the voltage of the fifth node O cannot be transmitted to the first node K. The voltage of the first node K remains at the previous high level (the fourth power signal PVGH), causing the voltage P(n) at the second node P of the gate driver unit 201 of this stage to remain at the previous low level (the sixth power signal PVGL). If the first frequency division control signal NLF and the second frequency division control signal PLF are both at corresponding low levels, the voltages of the third node W and the seventh node M are also at high levels. At this time, the first output module 3031 still outputs the low-level first gate control signal Nout(n) (the second power signal NVGL2). It should be noted that at this time, the voltage P(n-2) at the second node P of the (n-2)-th stage gate driver unit 201 is also at a corresponding high level, the eighth transistor T8 is turned off, and the eighth node Q remains at a high level, causing the eleventh transistor T6 to be turned off. At the same time, the voltage P(n) at the second node P of the gate driver unit 201 of this stage, with the twelfth transistor T7 at a low level, is turned on to output the fourth power signal PVGH transmitted by the fourth power line as the second gate control signal Pout(n). At the same time, the thirteenth transistor T5, the transistor T18, and the transistor T22 are all turned on, and the fourteenth transistor T4, the transistor T17, and the transistor T21 are all turned on under the control of the first clock signal to transmit the fourth power signal PVGH transmitted by the fourth power line to the first node K, the third node W, and the seventh node M, thereby maintaining the first node K, the third node W, and the seventh node M at a stable high level. The fifteenth transistor T14 is cut off according to the voltage of the second node P of the gate driving unit 201 of this level which is at a low level, so as to avoid transmitting the low level of the fifth power supply signal to the first node K, the third node W, and the seventh node M to affect the high level of the first node K, the third node W, and the seventh node M.

[0039] In period t2, the first clock signal XCK is at a corresponding low level, the second clock signal CK is at a corresponding high level, and the frame start signal STV or the voltage of the second node P of the (n-1)th gate driving unit 201 is at a corresponding high level, then the third transistor T13 is turned on to transmit the third power signal NVGL1 transmitted by the third power line to the fifth node O. The fifth transistor T2 is turned on in response to the first clock signal at a low level, and transmits the third power signal NVGL1 transmitted by the third power line to the first node K, so that the voltage of the first node K is at a low level. At this time, transistor T3 is turned on based on the low level of first node K, while transistor T1 is turned off. The fourth power signal PVGH transmitted by the fourth power signal is transmitted to the second node P of the gate driver unit 201 of this stage, causing the sixth transistor T16 and the ninth transistor T20 to be turned off, while the seventh transistor T11 and the tenth transistor T19 remain turned on. Therefore, the voltage signals at the third node W and the seventh node M are also low. Therefore, the third transistor T10 is turned off and the second transistor T9 is turned on, outputting the first power signal NVGH transmitted by the first voltage signal as the first gate control signal Nout(n). Simultaneously, the twelfth transistor T7 is turned off, and the eleventh transistor T6 remains off, so the second gate control signal Pout(n) remains high. Simultaneously, the thirteenth transistor T5, the transistor T18, and the transistor T22 are all turned off, and the fourteenth transistor T4, the transistor T17, and the transistor T21 are all turned off under the control of the first clock signal, thereby preventing the high level of the fourth power signal from being transmitted to the first node K, the third node W, and the seventh node M, thereby affecting the low levels of the first node K, the third node W, and the seventh node M. The fifteenth transistor T14 is turned on according to the voltage of the second node P of the gate driving unit 201 of this stage which is at a high level, and transmits the fifth power signal NVGL to the first node K to maintain a stable low level.

[0040] During period t3, the first clock signal XCK is at a corresponding high level, the second clock signal CK is at a corresponding high level, and the frame start signal STV or the voltage of the second node P of the (n-1)-th gate driving unit 201 is at a corresponding high level, then the third transistor T13 is turned on, transmitting the third power signal NVGL1 transmitted by the third power line to the fifth node O. However, the fifth transistor T2 is turned off in response to the first clock signal at a high level, so the voltage signal of the fifth node O cannot be transmitted to the first node K. Therefore, the first node K maintains the previous low level, and the second node P of the gate driving unit 201 of this stage maintains the previous high level, so the third node W and the seventh node M maintain the previous low level, so the operating states of the other transistors and the potentials of the nodes can be the same as those in period t2;

[0041] During period t4, the first clock signal XCK is at a corresponding high level, the second clock signal CK is at a corresponding low level, and the frame start signal STV or the voltage P(n-1) of the second node P of the (n-1)th gate driving unit 201 is at a corresponding high level. The third transistor T13 is turned on to transmit the third power signal NVGL1 transmitted by the third power line to the fifth node O. The fifth transistor T2 is turned off. The remaining analysis can be similarly referred to the analysis of period t3.

[0042] During period t5, the first clock signal XCK is at a corresponding low level, the second clock signal CK is at a corresponding high level, and the frame start signal STV or the potential of the second node P of the (n-1)th gate driving unit 201 is at a corresponding high level. Then, the third transistor T13 is turned on to transmit the third power signal NVGL1 transmitted by the third power line to the fifth node O. The fifth transistor T2 is turned on, and the remaining analysis can be similarly referred to the analysis of period t2.

[0043] In time period t6, the timing is similar to that of the aforementioned time period t3, and the analysis of the aforementioned time period 3 may be referred to for details.

[0044] In time period t7, the difference from time period t3 and time period t6 is that the frame start signal STV or the potential P(n-1) of the second node P of the (n-1)-th stage gate driving unit 201 is a corresponding high level, and the potential P(n-2) of the second node P of the first two stages of the gate driving unit 201 is a corresponding low level, so that the eighth transistor T8 is turned on, the potential of the eighth node Q is a low level, so that the eleventh transistor T6 is turned on, and the twelfth transistor T7 remains off, so the high level of the second clock signal CK is output as the second gate control signal Pout(n), and the first gate control signal Nout(n) remains high.

[0045] During period t8, the difference from period t7 is that the second clock signal CK is at a corresponding low level, so the low level of the second clock signal CK is output as the second gate control signal Pout(n), and the first gate control signal Nout(n) maintains a high level.

[0046] In time period t9, the first clock signal XCK is at a corresponding low level, the second clock signal CK is at a corresponding high level, and the frame start signal STV or the voltage of the second node P of the (n-1)th stage gate driving unit 201 is at a corresponding low level, then the fourth transistor T12 is turned on, and the fourth power signal PVGH transmitted by the fourth power line is transmitted to the fifth node O. And the fifth transistor T2 is turned on, transmitting the high-level fourth power supply signal to the second node K. Referring to the relevant discussion of "after power-on" above, it can be seen that the transistor T3 is turned off, the transistor T1 is turned on, the sixth transistor T16 and the ninth transistor T20 are turned on, and if the first frequency-division control signal NLF and the second frequency-division control signal PLF are both corresponding low levels, then the seventh transistor T11 and the tenth transistor T19 are turned on, then the signals M(n) at the third node W and the seventh node M are also high levels, the low-level output of the second power supply signal is used as the first gate control signal Nout(n), the eighth transistor T8 is turned on, the eleventh transistor T6 is turned off, the twelfth transistor T7 is turned on, and the high-level output of the third power supply signal is used as the second gate control signal Pout(n).

[0047] It should be noted that the above analysis is based on the assumption that both the first frequency-division control signal NLF and the second frequency-division control signal PLF are at corresponding low levels. This means that the frequencies in all regions can be equalized, for example, achieving a refresh rate of 120 MHz for the entire display panel, indicating that the gate driver unit 201 operates in the first mode without frequency-division division. However, if at least one of the first frequency-division control signal NLF and the second frequency-division control signal PLF is at a corresponding high level, then even if at least one of the sixth transistor T16 and the ninth transistor T20 is turned on, at least one of the corresponding third node W and seventh node M is electrically disconnected from the second node K, resulting in the gate frequency-division module 302 in the gate driver unit 201 being unable to be controlled in real time by the first node K to output gate pulses. This allows the frequency-division division setting within the display area of ​​the display device 100 to be achieved, indicating that the gate driver unit 201 operates in the second mode of frequency-division division.

[0048] The gate drive circuit provided in the embodiment of the present application includes a large number of inverting sub-modules, which can realize the function of partitioned frequency division and when the partitioned frequency division function is turned on, if the first gate control signal Nout(n) requires an L level, and the low level cannot be provided from the third transistor T10, that is, the output end of the first output module will have a passive output. At this time, if there is a micro-shorting in the display panel or other factors affecting Nout(n), the waveform will be abnormal during the time period when the passive output appears at the output end of the first output module. The second transistor T10 included in the gate drive circuit provided in the embodiment of the present application is controlled according to the third node W in both non-partitioned frequency division and partitioned frequency division. Regardless of whether it is non-partitioned frequency division or partitioned frequency division, the second transistor T10 can be turned on so that the output end of the first output module is not in the floating time period, thereby avoiding the coupling influence of micro-short circuits.

[0049] An embodiment of the present invention further provides a display device, which may include: a plurality of pixel units arranged in an array and a gate driving circuit as described above, wherein each gate driving unit is configured to drive at least one row of pixel units.

[0050] The gate drive circuit and display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The invention comprises a plurality of cascaded gate driving units, wherein the gate driving unit comprises: a shift register module, a frequency dividing module and an output module, wherein; The shift register module is connected to the frequency dividing module via a first node, and is configured to transmit a frame start signal transmitted by a frame start line or a voltage of a second node of the gate driving unit at a previous stage to the first node in response to a first clock signal transmitted by the first clock line; The frequency division module includes a first frequency division module; the first frequency division module is connected to the output module via a third node, and is configured to connect or disconnect the electrical connection between the first node and the third node in response to a first frequency division control signal transmitted by a first frequency division control line; when the first frequency division module disconnects the electrical connection between the first node and the third node in response to the first frequency division control signal, a first frequency division function is enabled; The output module includes a first output module; the first output module includes a first inverting submodule; the first inverting submodule includes a first control terminal and a second control terminal respectively connected to the third node, a first input terminal connected to a first power line for transmitting a first power signal, a second input terminal connected to a second power line for transmitting a second power signal, and an output terminal for outputting a first gate control signal; the amplitude of the first power signal is greater than the amplitude of the second power signal; When the first partition frequency division function is enabled, the first inverting submodule outputs the second power supply signal provided by the second input terminal of the first inverting submodule as the first gate control signal under the voltage control of the third node.

2. The gate drive circuit according to claim 1, wherein: The first inverting submodule includes a first transistor and a second transistor, wherein the first end of the first transistor and the first end of the second transistor are connected to a fourth node, the control end of the first transistor and the control end of the second transistor serve as the first control end and the second control end of the first inverting submodule respectively and are commonly connected to the third node; the second end of the first transistor serves as the first input end of the first inverting submodule and is connected to the first power line, and the second end of the second transistor serves as the second input end of the first inverting submodule and is connected to the second power line; Among them, the first inverting sub-module is used to transmit the first power supply signal to the fourth node in response to the voltage of the third node, or transmit the second power supply signal to the fourth node in response to the voltage of the third node; the voltage of the fourth node is the first gate control signal output by the first output module.

3. The gate drive circuit according to claim 2, wherein: The first transistor is a P-type indium gallium zinc oxide thin film transistor; the second transistor is an N-type indium gallium zinc oxide thin film transistor.

4. The gate drive circuit according to claim 1, wherein: The shift register module includes: a second inverting submodule, the second inverting submodule comprising a third transistor and a fourth transistor, wherein a first end of the third transistor is connected to a third power line for transmitting a third power signal, a second end of the third transistor and a first end of the fourth transistor are connected to a fifth node, a control end of the third transistor and a control end of the fourth transistor are connected to the frame start line or the second node of the gate driving unit of the previous stage; and a second end of the fourth transistor is connected to a fourth power line; In which, the second inverting sub-module is used to transmit the third power signal transmitted by the third power line to the fifth node or transmit the fourth power signal transmitted by the fourth power line to the fifth node in response to the frame start signal or the voltage of the second node of the gate driving unit of the previous level; the amplitude of the second power signal is greater than the amplitude of the third power signal; the amplitude of the third power signal and the second power signal are less than the amplitude of the fourth power signal.

5. The gate driving circuit according to claim 4, wherein: The shift register module also includes: a fifth transistor, a first end of the fifth transistor is connected to the fifth node, a second end of the fifth transistor is connected to the first node, and a control end of the fifth transistor is connected to the first clock line; wherein, the fifth transistor is used to be turned on in response to the first clock signal, and transmit the third power supply signal to the first node via the fifth node or transmit the fourth power supply signal to the first node via the fifth node to control the voltage of the first node.

6. The gate driving circuit according to claim 1, wherein: The first frequency division module includes a sixth transistor, a seventh transistor, and a first capacitor, wherein: a first end of the sixth transistor is connected to the first frequency division control line, a second end of the sixth transistor is connected to a sixth node, and a control end of the sixth transistor is connected to the second node of the gate driving unit at this level; a first end of the seventh transistor is connected to the first node, a second end of the seventh transistor is connected to the third node, and a control end of the seventh transistor is connected to the sixth node; and the first capacitor is connected between the third node and the sixth node; Among them, when the first frequency division control signal is at a first level, the seventh transistor is maintained in an on state to connect the electrical connection between the first node and the third node; when the first frequency division control signal is at a second level, the seventh transistor is maintained in an off state to disconnect the electrical connection between the first node and the third node.

7. The gate driving circuit according to claim 1, wherein: The frequency division module further includes a second frequency division module; the second frequency division module includes a ninth transistor, a tenth transistor, and a second capacitor, wherein a first end of the ninth transistor is connected to the second frequency division control line, a second end of the ninth transistor is connected to a ninth node, and a control end of the ninth transistor is connected to the second node of the gate driving unit at the current level; a first end of the tenth transistor is connected to the first node, a second end of the tenth transistor is connected to a seventh node, and a control end of the ninth transistor is connected to the ninth node; and the second capacitor is connected between the ninth node and the seventh node; In which, when the second frequency-division control signal transmitted by the second frequency-division control line is at a first level, the tenth transistor is maintained in an on state to connect the electrical connection between the first node and the seventh node; when the second frequency-division control signal transmitted by the second frequency-division control line is at a second level, the tenth transistor is maintained in an off state to disconnect the electrical connection between the first node and the seventh node and turn on the second frequency-division function.

8. The gate driving circuit according to claim 7, wherein: The output module also includes a second output module; the second output module includes an output submodule and an eighth transistor; wherein the first end of the eighth transistor is connected to the seventh node, the second end of the eighth transistor is connected to the eighth node, and the control end of the eighth transistor is connected to the second nodes of the first two stages of the gate driving unit; the eighth transistor is used to transmit the voltage of the seventh node to the eighth node in response to the voltage of the second nodes of the first two stages of the gate driving unit; the output submodule includes an eleventh transistor and a twelfth transistor, wherein the first end of the eleventh transistor is connected to the second clock line, the second end of the eleventh transistor and the first end of the twelfth transistor are connected to the tenth node, and the control end of the eleventh transistor is connected to the eighth node; the second end of the twelfth transistor is connected to the fourth power line for transmitting the fourth power signal, and the control end of the twelfth transistor is connected to the second node of the gate driving unit of this stage, wherein the second gate control signal is the voltage signal of the tenth node.

9. The gate driving circuit according to claim 8, wherein: The gate drive unit further includes a self-stabilizing module; the self-stabilizing module includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, wherein the control end of the thirteenth transistor and the control end of the fifteenth transistor are connected to the second node of the gate drive unit at this level which is controlled by the voltage of the first node; the first end of the thirteenth transistor is connected to the fourth power line, and the second end of the thirteenth transistor is connected to the first node via the fourteenth transistor; the first end of the fifteenth transistor is connected to the fifth power line for transmitting a fifth power signal, and the second end of the fifteenth transistor is connected to the first node; the amplitude of the fourth power signal is greater than the amplitude of the fifth power signal; the amplitude of the fifth power signal is greater than the amplitude of the fifth power signal The value is less than the amplitude of the second power supply signal; wherein, when the voltage of the first node is at the first level, the voltage of the second node of the gate driving unit at this level is at the second level, the fifteenth transistor is turned on according to the second level of the voltage of the second node of the gate driving unit at this level, and transmits the fifth power supply signal to the first node to maintain the voltage of the first node at the first level; when the voltage of the first node is at the second level, the voltage of the second node of the gate driving unit at this level is at the first level, the thirteenth transistor is turned on according to the first level of the voltage of the second node of the gate driving unit at this level, and transmits the fourth power supply signal to the first node to maintain the voltage of the first node at the second level.

10. A display device, characterized in that: The invention comprises a plurality of pixel units arranged in an array and a gate driving circuit according to any one of claims 1 to 9, wherein each of the gate driving units is used to drive at least one row of the pixel units.

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