Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a plurality of pixel groups arranged along a first direction; wherein the pixel group comprises N sub-pixel columns, and one sub-pixel column is connected with one data signal line; a plurality of multiplexing circuits, each multiplexing circuit comprises N multiplexing units, each multiplexing unit comprises M signal input ends, a signal output end and M shunt control ends, and in the same multiplexing circuit, the mth signal input end in the sth multiplexing unit is coupled with the mth signal input end in the tth multiplexing unit; the M shunt control ends respectively receive different shunt control signals, and the signal output ends of the multiplexing units are correspondingly connected with the data signal lines; and the at least one selection control line group comprises N selection control line units, each selection control line unit comprises M selection control lines, and the selection control lines are connected with the shunt control end. The power consumption of the display panel is low.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, three-dimensional (3D) display technology is gaining increasing attention. 3D display technology can make displayed images appear three-dimensional and realistic. Its principle is to use the left and right eyes to receive a left-eye image and a right-eye image with a certain parallax. When these two parallax images are received by the left and right eyes, the brain superimposes and fuses the image information to create a 3D visual display effect.

[0003] However, the three-dimensional display device in the related art has the problem of high power consumption. Summary of the Invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to reduce the power consumption of the display panel.

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] A plurality of pixel groups, wherein the plurality of pixel groups are arranged along a first direction; wherein the pixel groups include N sub-pixel columns;

[0007] A plurality of data signal lines, wherein each sub-pixel column is connected to a corresponding data signal line;

[0008] Multiple multiplexing circuits, each comprising N multiplexing units, each multiplexing unit comprising M signal input terminals, one signal output terminal, and M branch control terminals, wherein, in the same multiplexing circuit, the m-th signal input terminal of the s-th multiplexing unit is coupled to the m-th signal input terminal of the t-th multiplexing unit; the M branch control terminals receive different branch control signals; the signal output terminals of the multiplexing units are connected to data signal lines; and at the same time, the M signal input terminals receive data signals of different magnitudes, 3≤M<N, 1≤s≠t≤N, 1≤m≤M, and M, N, m, s, and t are all integers;

[0009] At least one selection control line group includes N selection control line units, each selection control line unit includes M selection control lines, and each selection control line is connected to the branch control terminal.

[0010] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0011] The display panel provided by an embodiment of the present application includes multiple pixel groups, multiple data signal lines, multiple multiplexing circuits, and at least one selection control line group. Among them, the multiple pixel groups are arranged along a first direction, and each pixel group includes N sub-pixel columns respectively. Each sub-pixel column is correspondingly connected to a data signal line. The selection control line group includes N selection control line units. Each selection control line unit includes M selection control lines. One multiplexing circuit includes N multiplexing units. Each multiplexing unit includes M signal input ends, one signal output end, and M shunt control ends. In the present application, by setting that the m-th signal input end in the s-th multiplexing unit in the same multiplexing circuit is coupled to the m-th signal input end in the t-th multiplexing unit, the channels for inputting data signals of the multiplexing units in one multiplexing circuit can be multiplexed. One multiplexing circuit only needs M channels for inputting data signals. Further, by setting M < N, compared with the related art in which an independent channel for transmitting data signals is separately configured for each data signal line, the present application can reduce the number of channels for inputting data signals, thereby reducing the driving power consumption. In addition, in the present application, by controlling that the data signals received by the M signal input ends are different in magnitude at the same time, the diversity of the data signals can be ensured, and data redundancy at the signal input ends can be avoided. When multiple sub-pixels require the same data signal, the corresponding signal input end and the signal data end are conducted through the shunt control signal, so that multiple sub-pixels can share the data signal, avoiding redundant driving to further reduce the driving power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic plan view of a display panel provided by an embodiment of the present application;

[0013] Figure 2 is a schematic plan view of another display panel provided by an embodiment of the present application;

[0014] Figure 3 is a schematic plan view of yet another display panel provided by an embodiment of the present application;

[0015] Figure 4 is a schematic plan view of still another display panel provided by an embodiment of the present application;

[0016] Figure 5 is a schematic plan view of a pixel island provided by an embodiment of the present application;

[0017] Figure 6 is a schematic plan view of a display device provided by an embodiment of the present application;

[0018] Figure 7 is a schematic cross-sectional view of a display device provided by an embodiment of the present application;

[0019] Figure 8 A schematic cross-sectional view of another display panel provided in an embodiment of the present application.

[0020] Description of reference numerals:

[0021] 10-pixel group, 11-sub-pixel column, 111-pixel island, 1111-sub-pixel, 21-data signal line, 30-multiplexing circuit, 31-multiplexing unit, 40-selection control line group, 41-selection control line unit, 411-selection control line, 50-data fan-out line group, 51-data fan-out line, 511-first data fan-out line, 512-second data fan-out line, 5121-second A data fan-out line, 5122-second B data fan-out line, 201-column lens structure, 2011-column lens, 202-flat layer, 100-display panel, 200-display device. DETAILED DESCRIPTION

[0022] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the disclosure of the present application.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0024] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Furthermore, when a layer is referred to as being "under" another layer, it can be directly under or one or more intervening elements may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening elements may also be present.

[0025] In the case of using “including,” “having,” and “comprising” described herein, another component may be added unless a clear limiting term such as “only,” “consisting of,” etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as having one number.

[0026] It should be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this application.

[0027] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately," "approximately," or "substantially" can mean within one or more standard deviations, and is not limited here.

[0028] Furthermore, in the specification, the phrase “planar distribution diagram” refers to a drawing when the target portion is viewed from above, and the phrase “cross-sectional diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0029] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0030] As described in the background section, 3D display devices in related art consume high power when displaying images. The inventors discovered that this phenomenon occurs because, in related art, each data signal line is configured with an independent channel for transmitting data signals. However, in actual use, many different data signal transmission channels transmit the same image information, resulting in redundant image information transmitted by many different data signal transmission channels, which in turn leads to high driving power consumption of the display panel.

[0031] Based on the above technical problems, the inventors have found through research that by multiplexing the channels of the transmission data signals for transmitting the same picture information, the power consumption of the display panel can be reduced. Based on this, the inventors have further developed the technical solution of the embodiments of the present application. Specifically, the display panel provided by the embodiments of the present application includes a plurality of pixel groups arranged along a first direction, a plurality of data signal lines, a plurality of multiplexing circuits, and at least one selection control line group. Each pixel group includes N sub-pixel columns, and each sub-pixel column is correspondingly connected to a data signal line; the multiplexing circuit includes N multiplexing units, and each multiplexing unit includes M signal input terminals, one signal output terminal, and M branch control terminals. Among them, in the same multiplexing circuit, the m-th signal input terminal in the s-th multiplexing unit is coupled to the m-th signal input terminal in the t-th multiplexing unit; the M branch control terminals receive different branch control signals respectively, the signal output terminal of the multiplexing unit is correspondingly connected to the data signal line, and at the same moment, the magnitudes of the data signals received by the M signal input terminals are different, 3≤M<N, 1≤m≤M, and M, N, and m are all integers; the selection control line group includes N selection control line units, and each selection control line unit includes M selection control lines, and the selection control lines are connected to the branch control terminals. By adopting the above technical solution, by setting that the m-th signal input terminal in the s-th multiplexing unit is coupled to the m-th signal input terminal in the t-th multiplexing unit in the same multiplexing circuit, it can be made that each multiplexing unit in the same multiplexing circuit shares the channel of the input data signal, and only M input data signal channels are required for one multiplexing circuit. Further, by setting M<N in the present application, the number of channels of the input data signal in one multiplexing circuit is less than the number of channels of the output data signal in the multiplexing circuit. Compared with the related art in which an independent channel for transmitting the data signal is separately configured for each data signal line, the number of channels for transmitting the data signal can be reduced, thereby reducing the driving power consumption.

[0032] The above is the core idea of the present application. Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0033] In some exemplary embodiments, please refer to Figure 1 , the present application provides a display panel, including: a plurality of pixel groups 10, a plurality of data signal lines 21, a plurality of multiplexing circuits 30, and at least one selection control line group 40.

[0034] Among them, each pixel group 10 is arranged along a first direction, and each pixel group 10 includes N sub-pixel columns 11, and each sub-pixel column 11 is correspondingly connected to a data signal line 21.

[0035] The multiplexing circuit 30 includes N multiplexing units 31. Each multiplexing unit 31 includes M signal input terminals, one signal output terminal, and M branch control terminals. In the same multiplexing circuit 30, the m-th signal input terminal of the s-th multiplexing unit is coupled to the m-th signal input terminal of the t-th multiplexing unit. The M branch control terminals receive different branch control signals MUX. The signal output terminals of the multiplexing units 31 are connected to the data signal lines 21. At the same time, the M signal input terminals receive different data signals (source). 3≤M<N, 1≤m≤M, 1≤s≤N, 1≤t≤N, s≠t, and M, N, m, s, and t are all integers.

[0036] The selection control line group 40 includes N selection control line units 41 . The selection control line unit 41 includes M selection control lines 411 . The selection control lines 411 are connected to the branch control terminals.

[0037] In this embodiment, each pixel group 10 is arranged along the first direction, each pixel group 10 includes a plurality of sub-pixel columns 11 arranged along the first direction, each sub-pixel column 11 includes a plurality of sub-pixels arranged along the second direction, and each sub-pixel column 11 is connected to a corresponding data signal line 21. Figure 1 The X-axis direction shown in the figure, the second direction is Figure 1 . Each pixel group 10 corresponds to a multiplexing circuit 30, and each sub-pixel column 11 corresponds to a data signal line 21 connected to a multiplexing unit 31. Each multiplexing unit 31 includes M signal input terminals, a signal output terminal, and M branch control terminals. Each signal input terminal is used to receive a data signal source. At the same time, the M signal input terminals of a multiplexing unit 31 receive data signals of different sizes. Under the action of the branch control signal MUX, the multiplexing unit 31 can select a path between the signal output terminal and the corresponding signal input terminal to transmit the corresponding data signal source to the data signal line.

[0038] In an example, see Figure 1, optionally, N=5, M=3, each pixel group 10 includes five sub-pixel columns 11, a multiplexing circuit 30 includes five multiplexing units 31, each multiplexing unit 31 includes three signal input terminals, one signal output terminal and three branch control terminals, the selection control line group 40 includes five selection control line units 41, and each selection control line unit 41 includes three selection control lines 411. In addition, taking the multiplexing circuit 30-1 on the left side of the figure as an example, the first signal input end of each multiplexing unit 31 accepts the same data signal source1, the second signal input end of each multiplexing unit 31 accepts the same data signal source2, and the third signal input end of each multiplexing unit 31 accepts the same data signal source3; similarly, taking the multiplexing circuit 30-2 on the right side of the figure as an example, the first signal input end of each multiplexing unit 31 accepts the same data signal source4, the second signal input end of each multiplexing unit 31 accepts the same data signal source5, and the third signal input end of each multiplexing unit 31 accepts the same data signal source6. It can be understood that the present application is set in the same multiplexing circuit 30, and the m-th signal input terminal in the s-th multiplexing unit is coupled to the m-th signal input terminal in the t-th multiplexing unit, so that the number of channels for receiving data signals in a multiplexing circuit 30 can be less than the number of channels for outputting data signals in the multiplexing circuit 30, thereby reducing the number of channels for transmitting data signals.

[0039] Furthermore, the present application arranges that at the same moment, the sizes of the data signals received by M signal input terminals are different. For example, at the same moment, the sizes of data signal source1, data signal source2 and data signal source3 are different, and the sizes of data signal source4, data signal source5 and data signal source6 are different. In this way, the redundancy of the data signals transmitted by each signal input terminal of the multiplexing circuit 30 can be improved. When multiple sub-pixels require the same data signal, it is only necessary to control the conduction of the corresponding signal input terminal and signal data terminal through the branch control signal, so that the same data signal can be written into each sub-pixel that requires the same data signal, thereby avoiding redundant driving and reducing driving power consumption.

[0040] The display panel provided by the embodiment of the present application includes a plurality of pixel groups, a plurality of data signal lines, a plurality of multiplexing circuits, and at least one selection control line group. Among them, the plurality of pixel groups are arranged along the first direction, and each pixel group includes N sub-pixel columns respectively. Each sub-pixel column is correspondingly connected to a data signal line. The selection control line group includes N selection control line units. The selection control line unit includes M selection control lines. One multiplexing circuit includes N multiplexing units. The multiplexing unit includes M signal input ends, one signal output end, and M shunt control ends. In the present application, by setting that the m-th signal input end in the s-th multiplexing unit in the same multiplexing circuit is mutually coupled with the m-th signal input end in the t-th multiplexing unit, the channels for inputting data signals by each multiplexing unit in one multiplexing circuit can be multiplexed. One multiplexing circuit only needs M channels for inputting data signals. Further, by setting M < N, compared with the related technology in which an independent channel for transmitting data signals is separately configured for each data signal line, the present application can reduce the number of channels for transmitting data signals, thereby reducing the driving power consumption. In addition, in the present application, by controlling that the data signals received by the M signal input ends at the same moment are different in size, the diversity of the data signals can be ensured, and the data redundancy at the signal input end can be avoided. When multiple sub-pixels require the same data signal, the corresponding signal input end and the signal data end are connected through the shunt control signal, so that multiple sub-pixels can share the data signal, avoiding redundant driving to further reduce the driving power consumption.

[0041] In some exemplary embodiments, please refer to Figure 2 , the multiplexing unit 31 includes M switching transistors. The first pole of the switching transistor corresponds to the signal input end. The second pole of the switching transistor is connected to the data signal line. The second pole of the switching transistor corresponds to the signal output end. The gate of the switching transistor corresponds to the shunt control end.

[0042] Among them, the first pole of the switching transistor is used to receive the data signal. The second pole of the switching transistor is connected to the data signal line 21. The second pole of the switching transistor is used to output the data signal. The gate of the switching transistor is connected to the selection control line 411. The gate of the switching transistor is used to receive the shunt control signal.

[0043] In this embodiment, in a multiplexing unit 31, the first electrode of each switching transistor is connected to the corresponding signal input terminal, the second electrode of each switching transistor is connected to the same data signal line 21, and the gate of each switching transistor is connected to the corresponding selection control line 411. Furthermore, under the action of the branch control signal MUX received by each branch control terminal, a switching transistor in the multiplexing unit 301 is turned on to charge the data signal line through the signal output terminal and the corresponding signal input terminal. The switching transistor can be a P-type transistor or an N-type transistor.

[0044] In some exemplary embodiments, please continue to participate Figure 1 and Figure 2 The display panel also includes multiple data fan-out line groups 50, each of which includes M data fan-out lines 51. The data fan-out lines 51 are used to transmit data signals (source). The i-th signal input terminal of the multiplexing unit 31 in the multiplexing circuit 30 is connected to the i-th data fan-out line in the corresponding data fan-out line group 50, where 1≤i≤M, and i is an integer. It is understood that each data fan-out line group 50 includes M data fan-out lines 51. Within the same data fan-out line group 50, the data signals output by each data fan-out line 51 at the same time can be different in magnitude, thereby preventing the data fan-out line group 50 from having channels transmitting redundant data signals. In an embodiment of the present application, one multiplexing circuit 30 corresponds to one data fan-out line group 50, and one multiplexing circuit 30 includes N multiplexing circuits 31. The present application multiplexes the data fan-out lines 51 by setting the i-th signal input end of each multiplexing unit 31 in the multiplexing circuit 30 to be connected to the i-th data fan-out line in the corresponding data fan-out line group 50. Each data fan-out line 51 in the data fan-out line group 50 is connected to the signal input end of each multiplexing circuit 31 of the corresponding multiplexing circuit 30. Therefore, for sub-pixels that need to receive the same data signal, under the action of the branch control signal MUX, different sub-pixels can receive the same data signal through the same data fan-out line, thereby reducing the number of channels for transmitting data signals and reducing driving power consumption.

[0045] In some exemplary embodiments, please refer to Figure 2 The data fan-out line group 50 includes a first data fan-out line 511 and a plurality of second data fan-out lines 512 .

[0046] The first data fan-out line 511 is used to transmit a first data signal, source-black. When a sub-pixel receives the first data signal, source-black, the sub-pixel is in a black state. The first data fan-out lines 511 of at least some data fan-out line groups are the same data fan-out line 51, and the second data fan-out lines 512 in each data fan-out line group 50 are different data fan-out lines.

[0047] In actual applications, when the human eye views the image displayed on a three-dimensional display panel, there may be some sub-pixels located at the junction of the left-eye viewing area and the right-eye viewing area of ​​the human eye. The light emitted by these sub-pixels is refracted by the cylindrical lens and covers both the left-eye viewing area and the right-eye viewing area. Assuming that one of the sub-pixels is closer to the right eye, the light emitted by this sub-pixel should all be received by the right eye, but in reality 60% of the light is given to the right eye and 40% of the light leaks to the left eye. That is, only 60% of the light emitted by this sub-pixel is effective light and can enter the right eye, and the remaining 40% of the light is invalid light and is received by the left eye, resulting in a low optical utilization rate of the sub-pixel. In addition, the 40% invalid light received by the left eye may also form a ghosting in the left eye imaging, resulting in a poor viewing experience for the user.

[0048] Based on this, the present application designs a data fan-out line group 50 that includes a first data fan-out line 511 for transmitting black-state image information. When a sub-pixel receives the first data signal source-black, the sub-pixel is in a black state, thereby improving the overall image display effect by sacrificing the local brightness of the display panel. Continuing with the above example, for a sub-pixel in which 60% of the emitted light is valid light and 40% is invalid light, in this example, the sub-pixel can be controlled to receive the first data signal source-black, so that the sub-pixel is in a black state and does not emit light. As a result, only a small amount of edge brightness is lost by the right eye. Since the human eye is not sensitive to changes in edge brightness, this will not affect the image display effect, and can also improve ghosting in the left eye imaging, thereby improving the user's viewing experience.

[0049] Among them, since the size of the first data signal source-black is fixed, only a small number of first data fan-out lines 511 for transmitting the first data signal source-black can be designed in the present application. For example, only one first data fan-out line 511 can be designed, and each data fan-out line group 50 reuses the same first data fan-out line 511 to further reduce the number of data fan-out lines 51 in the display panel and reduce the driving power consumption of the display panel.

[0050] In some exemplary embodiments, the display panel has multiple refresh phases. In each refresh phase, among the branch control signals output by a selection control line unit, one branch control signal is at a valid level, and the remaining branch control signals are at invalid levels.

[0051] In actual implementation, in the multiplexing unit 31, a branch control terminal controls the on / off between a signal input terminal and a signal output terminal. Figure 1 For example, for the multiplexing unit 31 closest to the multiplexing circuit 30-2 in the multiplexing circuit 30-1, it is assumed that the branch control signal MUX51 controls the on-off between the signal input terminal and the signal output terminal of the multiplexing unit 31 receiving the data signal source1, the branch control signal MUX52 controls the on-off between the signal input terminal and the signal output terminal of the multiplexing unit 31 receiving the data signal source2, and the branch control signal MUX53 controls the on-off between the signal input terminal and the signal output terminal of the multiplexing unit 31 receiving the data signal source3. In a refresh phase, only one of the shunt control signal MUX51, the shunt control signal MUX52 and the shunt control signal MUX53 is at a valid level. For example, in a certain refresh phase, the shunt control signal MUX51 is at a valid level, and the shunt control signal MUX52 and the shunt control signal MUX53 are at invalid levels, so as to turn on the path between the signal input end and the signal output end of the multiplexing unit 31 receiving the data signal source3, so that the data signal line corresponding to the multiplexing unit 31 receives the data signal source3.

[0052] In some exemplary embodiments, M=3, where

[0053] The multiplexing circuit 30 includes N multiplexing units 31, and the multiplexing unit 31 includes three signal input terminals, one signal output terminal, and three branch control terminals; wherein, in the same multiplexing circuit 30, the mth signal input terminal of the sth multiplexing unit is coupled to the mth signal input terminal of the tth multiplexing unit; the three branch control terminals respectively receive different branch control signals MUX, and the signal output terminal of the multiplexing unit 31 is correspondingly connected to the data signal line 21.

[0054] The selection control line group 40 includes N selection control line units 41 . The selection control line unit 41 includes three selection control lines 411 . The selection control lines 411 are connected to the branch control terminal.

[0055] The data fan-out line group 50 includes three data fan-out lines 51, which are used to output the data signal source; wherein the i-th signal input terminal of the multiplexing unit 31 in the multiplexing circuit 30 is connected to the i-th data fan-out line 51 in the corresponding data fan-out line group 50, and at the same time, the data signals transmitted by the three data fan-out lines 51 are of different sizes, 1≤i≤3, and i is an integer.

[0056] The multiplexing unit 31 includes three switching transistors. The plurality of second data fan-out lines 512 include a second A data fan-out line 5121 and a second B data fan-out line 5122. The first data fan-out line 511, the second A data fan-out line 5121, and the second B data fan-out line 5122 are respectively connected to the first electrodes of the three switching transistors of the multiplexing unit 31. At the same time, the first data signal source-black transmitted by the first data fan-out line 511, the second A data signal source-1 transmitted by the second A data fan-out line 5121, and the second B data signal source-2 transmitted by the second B data fan-out line 5122 have different magnitudes. The first data fan-out lines 511 of at least some of the data fan-out line groups are the same data fan-out line 51. For example, the first data fan-out line 511 of the nth data fan-out line group 50-n and the first data fan-out line 511 of the n+1th data fan-out line group 50-(n+1) are the same data fan-out line. Each second data fan-out line 512 in each data fan-out line group 50 is a different data fan-out line. For example, the second A data fan-out line 5121 and the second B data fan-out line 5122 of the n-th data fan-out line group 50-n and the second A data fan-out line 5121 and the second B data fan-out line 5122 of the n+1-th data fan-out line group 50-(n+1) are different data fan-out lines. The second A data signal source-n-1 and the second A data signal source-n-2 transmitted by the second A data fan-out line 5121 and the second B data fan-out line 5122 of the n-th data fan-out line group 50-n, and the second A data signal source-(n+1)-1 and the second B data fan-out line 5122 transmitted by the second A data fan-out line 5121 and the second A data signal source-(n+1)-2 transmitted by the second A data fan-out line 5122 of the n+1-th data fan-out line group 50-(n+1) are different data signals.

[0057] Please continue reading Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of the planar structure of the display panel when N=5 and M=3 in an example. Figure 2 1 is a schematic diagram of a planar structure of an n-th pixel group 10 - n and a corresponding n-th multiplexing circuit 30 - n in a display panel when N=5 and M=3 in an example, where n is a positive integer.

[0058] from Figure 2As can be seen, pixel group 10-n includes five subpixel columns 11: subpixel column 11-1, subpixel column 11-2, subpixel column 11-3, subpixel column 11-4, and subpixel column 11-5. Subpixel column 11-1 is connected to data signal line 21-1, subpixel column 11-2 is connected to data signal line 21-2, subpixel column 11-3 is connected to data signal line 21-3, subpixel column 11-4 is connected to data signal line 21-4, and subpixel column 11-5 is connected to data signal line 21-5. Multiplexing circuit 30-n includes five multiplexing circuits 31: multiplexing unit 31-1, multiplexing unit 31-2, multiplexing unit 31-3, multiplexing unit 31-4, and multiplexing unit 31-5. Among them, the output end of the multiplexing unit 31-1 is connected to the data signal line 21-1, the output end of the multiplexing unit 31-2 is connected to the data signal line 21-2, the output end of the multiplexing unit 31-3 is connected to the data signal line 21-3, the output end of the multiplexing unit 31-4 is connected to the data signal line 21-4, and the output end of the multiplexing unit 31-5 is connected to the data signal line 21-5.

[0059] The first signal input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are connected to the first data fan-out line 51 in the data fan-out line group 50-n, that is, the first input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are all connected to the first data signal line 511 to receive the first data signal source-black. The second signal input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are connected to the second data fan-out line 51 in the data fan-out line group 50-n, that is, the second input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are all connected to the second A data signal line 5121 to receive the second A data signal source-n-1. The third signal input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are connected to the third data fan-out line 51 in the data fan-out line group 50-n, that is, the third input ends of the multiplexing unit 31-1, the multiplexing unit 31-2, the multiplexing unit 31-3, the multiplexing unit 31-4 and the multiplexing unit 31-5 are all connected to the second B data signal line 5122 to receive the second B data signal source-n-2.

[0060] Specifically, the multiplexing unit 31-1 includes a switching transistor T1, a switching transistor T2, and a switching transistor T3. The first electrode of the switching transistor T1 is connected to the first data signal line 511 to receive the first data signal source-black, the second electrode of the switching transistor T1 is connected to the data signal line 21-1, and the gate of the switching transistor T1 is used to receive the branch control signal MUX11. The first electrode of the switching transistor T2 is connected to the second data signal line A 5121 to receive the second data signal source-n-1, the second electrode of the switching transistor T2 is connected to the data signal line 21-1, and the gate of the switching transistor T2 is used to receive the branch control signal MUX12. The first electrode of the switching transistor T3 is connected to the second data signal line B 5122 to receive the second data signal source-n-2, the second electrode of the switching transistor T3 is connected to the data signal line 21-1, and the gate of the switching transistor T3 is used to receive the branch control signal MUX13.

[0061] Multiplexing unit 31-2 includes switching transistors T4, T5, and T6. A first electrode of switching transistor T4 is connected to first data signal line 511 to receive a first data signal, source-black; a second electrode of switching transistor T4 is connected to data signal line 21-2; and a gate of switching transistor T4 is configured to receive a branch control signal, MUX21. A first electrode of switching transistor T5 is connected to second data signal line A 5121 to receive a second data signal, source-n-1; a second electrode of switching transistor T5 is connected to data signal line 21-2; and a gate of switching transistor T5 is configured to receive a branch control signal, MUX22. A first electrode of switching transistor T6 is connected to second data signal line B 5122 to receive a second data signal, source-n-2; a second electrode of switching transistor T6 is connected to data signal line 21-2; and a gate of switching transistor T6 is configured to receive a branch control signal, MUX23.

[0062] Multiplexing unit 31-3 includes switching transistors T7, T8, and T9. A first electrode of switching transistor T7 is connected to first data signal line 511 to receive first data signal source-black, a second electrode of switching transistor T7 is connected to data signal line 21-3, and a gate of switching transistor T7 is used to receive a branch control signal MUX31. A first electrode of switching transistor T8 is connected to second data signal line A 5121 to receive second data signal source-n-1, a second electrode of switching transistor T8 is connected to data signal line 21-3, and a gate of switching transistor T8 is used to receive a branch control signal MUX32. A first electrode of switching transistor T9 is connected to second data signal line B 5122 to receive second data signal source-n-2, a second electrode of switching transistor T9 is connected to data signal line 21-3, and a gate of switching transistor T9 is used to receive a branch control signal MUX33.

[0063] Multiplexing unit 31-4 includes a switching transistor T10, a switching transistor T11, and a switching transistor T12. A first electrode of switching transistor T10 is connected to first data signal line 511 to receive a first data signal, source-black. A second electrode of switching transistor T10 is connected to data signal line 21-4. A gate of switching transistor T10 is configured to receive a branch control signal, MUX41. A first electrode of switching transistor T11 is connected to second data signal line A 5121 to receive a second data signal, source-n-1. A second electrode of switching transistor T11 is connected to data signal line 21-4. A gate of switching transistor T11 is configured to receive a branch control signal, MUX42. A first electrode of switching transistor T12 is connected to second data signal line B 5122 to receive a second data signal, source-n-2. A second electrode of switching transistor T12 is connected to data signal line 21-4. A gate of switching transistor T12 is configured to receive a branch control signal, MUX43.

[0064] Multiplexing unit 31-5 includes switching transistors T13, T14, and T15. A first electrode of switching transistor T13 is connected to first data signal line 511 to receive first data signal source-black, a second electrode of switching transistor T13 is connected to data signal line 21-5, and a gate of switching transistor T13 is configured to receive a branch control signal MUX51. A first electrode of switching transistor T14 is connected to second data signal line A 5121 to receive second data signal source-n-1, a second electrode of switching transistor T14 is connected to data signal line 21-5, and a gate of switching transistor T14 is configured to receive a branch control signal MUX52. A first electrode of switching transistor T15 is connected to second data signal line B 5122 to receive second data signal source-n-2, a second electrode of switching transistor T15 is connected to data signal line 21-5, and a gate of switching transistor T15 is configured to receive a branch control signal MUX53.

[0065] In a refresh phase, only one of the shunt control signal MUX11, the shunt control signal MUX12 and the shunt control signal MUX13 is at a valid level, and the rest are at invalid levels; similarly, only one of the shunt control signal MUX21, the shunt control signal MUX22 and the shunt control signal MUX23 is at a valid level, and the rest are at invalid levels; only one of the shunt control signal MUX31, the shunt control signal MUX32 and the shunt control signal MUX33 is at a valid level, and the rest are at invalid levels; only one of the shunt control signal MUX41, the shunt control signal MUX42 and the shunt control signal MUX43 is at a valid level, and the rest are at invalid levels; only one of the shunt control signal MUX51, the shunt control signal MUX52 and the shunt control signal MUX53 is at a valid level, and the rest are at invalid levels.

[0066] In one example, during a refresh phase, the shunt control signals MUX12, MUX22, MUX31, MUX43, and MUX53 are at valid levels, and the remaining shunt control signals are at invalid levels, so that the data signal line 21-1 and the data signal line 21-2 receive the second A data signal source-n-1, the data signal line 21-3 receives the first data signal source-black, and the data signal line 21-4 and the data signal line 21-5 receive the second B data signal source-n-2. In this way, when multiple sub-pixels require the same data signal, the same data signal can be written into each sub-pixel that requires the same data signal by simply controlling the corresponding signal input terminal and signal data terminal through the shunt control signal, thereby avoiding redundant driving and reducing driving power consumption.

[0067] It can be understood that in actual applications, the number N of sub-pixel columns in the pixel group in the display panel can be specifically set by relevant technical personnel according to needs. Preferably, N is a positive even number; similarly, the number M of signal input terminals in the multiplexing unit of the multiplexing circuit is not limited to 3, and can be specifically set by relevant technical personnel according to needs. For example, M can also be equal to 4, or M can also be equal to 5. The above embodiments are only examples.

[0068] In some exemplary embodiments, the display panel includes a plurality of sub-display areas in the first direction, and the sub-display areas include at least one pixel group 10 .

[0069] The number of sub-display areas is the same as the number of selection control line groups 40, and each sub-display area corresponds to each selection control line group 40. The multiplexing unit 31 corresponding to the k-th sub-pixel column 11 in each pixel group 10 in the sub-display area is connected to the k-th selection control line unit 41 in the selection control line group 40 corresponding to the sub-display area; 1 ≤ k ≤ N, where k is an integer. The width of each sub-display area relative to the user's viewing angle can be approximately 1 to 5 degrees.

[0070] See also Figure 3 In one example, the display panel includes at least two sub-display areas in a first direction: a first sub-display area AA1 and a second sub-display area AA2. The display panel includes at least two selection control line groups 40: a selection control line group 40-1 and a selection control line group 40-2. The first sub-display area AA1 corresponds to the selection control line group 40-1, and the second sub-display area AA2 corresponds to the selection control line group 40-2. The first sub-display area AA1 includes at least one pixel group 10-n, and the second sub-display area AA2 includes at least one pixel group 10-(n+1). Pixel group 10-n and pixel group 10-(n+1) are adjacent in the first direction. Pixel group 10-n corresponds to multiplexing circuit 30-n, and pixel group 10-(n+1) corresponds to multiplexing circuit 30-(n+1). It can be seen that the branch control ends of each multiplexing unit 31 in the multiplexing circuit 30-n are respectively connected to the corresponding selection control lines in the selection control line group 40-1, and the branch control ends of each multiplexing unit 31 in the multiplexing circuit 30-(n+1) are respectively connected to the corresponding selection control lines in the selection control line group 40-2.

[0071] In this embodiment, by providing a corresponding selection control line group for each sub-display area and independently controlling each sub-display area, the non-uniform visual perception characteristics of the human eye can be simulated, optimizing the display effect by dynamically matching the human eye's viewing angle. It is understood that the human eye's visual perception is characterized by high resolution in the center and low resolution in the periphery. The fovea is a small area on the retina with a diameter of approximately 1.5 mm (corresponding to a field of view of approximately 2°), densely populated with cones (responsible for high resolution and color vision), and is the area with the highest visual acuity in the retina. The farther away from the fovea, the fewer cones there are in the periphery, resulting in lower visual acuity. In other words, as the user's gaze moves, only the small central area of ​​the display panel (the area where the user's eyes are focused) requires high-definition display, while the peripheral areas can reduce resolution to conserve resources. For example, when the user's gaze point is biased toward the left side of the display panel, the corresponding selection control line group of the sub-display area on the left side of the display panel can switch the branch control signal at a high frequency to ensure that the sub-pixels in the sub-display area on the left side of the display panel respond quickly, while the corresponding selection control line group of the sub-display area on the left side of the display panel can reduce the frequency of switching the branch control signal to reduce power consumption.

[0072] In some exemplary embodiments, see Figure 4 The display panel includes a selection control line group 40 , and the display panel includes at least a first sub-display area AA1 and a second sub-display area AA2 in the first direction; the first sub-display area AA1 and the second sub-display area AA2 each include at least one pixel group 10 .

[0073] The multiplexing unit 31 corresponding to the j-th sub-pixel column in the pixel group 10 in the first sub-display area AA1 is connected to the j-th selection control line unit 41 in the selection control line group 40 .

[0074] The multiplexing unit corresponding to the j-th sub-pixel column in each pixel group 10 in the second sub-display area AA2 is connected to the j+1-th selection control line unit 41 in the selection control line group 40; the multiplexing unit 31 corresponding to the N-th sub-pixel column 11 in each pixel group 10 in the second sub-display area AA2 is connected to the first selection control line unit 41 in the selection control line group 40, 1≤j<N, and j is an integer.

[0075] See also Figure 4In one example, the display panel includes at least two sub-display areas in the first direction: a first sub-display area AA1 and a second sub-display area AA2, and the display panel includes a selection control line group 40. The sub-display area AA1 includes at least one pixel group 10-n, and the sub-display area AA2 includes at least one pixel group 10-(n+1). The pixel group 10-n and the pixel group 10-(n+1) are adjacent in the first direction. The pixel group 10-n corresponds to the multiplexing circuit 30-n, and the pixel group 10-(n+1) corresponds to the multiplexing circuit 30-(n+1). It can be seen that in the first sub-display area AA1, the multiplexing unit 31 corresponding to the first sub-pixel column 11 in the pixel group 10 is connected to the first selection control line unit 41 in the selection control line group 40; ...; the multiplexing unit 31 corresponding to the fifth sub-pixel column 11 in the pixel group 10 in the first sub-display area AA1 is connected to the fifth selection control line unit 41 in the selection control line group 40. In the second sub-display area AA2, the multiplexing unit 31 corresponding to the first sub-pixel column 11 in the pixel group 10-(n+1) is connected to the second selection control line unit 41 in the selection control line group 40;...; the multiplexing unit 31 corresponding to the fourth sub-pixel column in the pixel group 10-(n+1) is connected to the fifth selection control line unit 41 in the selection control line group 40; the multiplexing unit corresponding to the fifth sub-pixel column in the pixel group 10-(n+1) is connected to the first selection control line unit 41 in the selection control line group 40.

[0076] It can be understood that the number of sub-display areas included in the display panel may not be limited to two. For example, the display panel may also include a third sub-display area. The multiplexing unit corresponding to the p-th sub-pixel column in each pixel group 10 in the third sub-display area is connected to the p-1-th selection control line unit 41 in the selection control line group 40; the multiplexing unit 31 corresponding to the first sub-pixel column 11 in each pixel group 10 in the second sub-display area AA2 is connected to the last selection control line unit 41 in the selection control line group 40, 1<p≤N, and p is an integer.

[0077] In applications, the number of sub-display areas included in the display panel can be set as needed by those skilled in the art, and the connection relationship between each sub-pixel column in each sub-display area and each selection control line unit 41 in the selection control line group 40 can also be set as needed by those skilled in the art, and this application does not impose any restrictions on this.

[0078] During application, when a user moves, the viewing angles of both eyes for different areas of the screen will change. In this embodiment, by staggering the connection relationship between the first sub-display area AA1 and the second sub-display area AA2 and the selection control line unit 41 in the selection control line group 40, the sub-pixels of different sub-display areas can be more continuously matched with the visual trajectory of both eyes during the user's movement, thereby reducing the discontinuity or blur of the picture caused by changes in viewing angle.

[0079] In some exemplary embodiments, please refer to Figure 4 The pixel group 10 includes a plurality of pixel islands 111 arranged along the second direction. The length of the pixel islands 111 in the first direction is less than the first length threshold and greater than the second length threshold.

[0080] The first length threshold is greater than the second length threshold, the first length threshold and the second length threshold are related to the length of the pixel island in the second direction, and the first direction and the second direction intersect.

[0081] It is understood that a three-dimensional display device is typically composed of a display panel and a cylindrical lens structure. The cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array along a first direction. The number of cylindrical lenses is equal to the number of pixel groups 10, and each cylindrical lens is provided in a one-to-one correspondence with each pixel group 10. Due to the difference in optical properties of the cylindrical lenses in the first direction and the second direction, if the length of the pixel island 111 in the first direction differs significantly from the length of the pixel island 111 in the second direction, it may lead to inconsistent focusing effects of light in the two directions, resulting in optical distortion or crosstalk, resulting in poor display quality of the display panel.

[0082] To improve the display quality of the display panel, the embodiment of the present application sets the length of the pixel island 111 in the first direction to be correlated with the length of the pixel island 111 in the second direction. In one example, this embodiment assumes that the length of the pixel island 111 in the first direction is L1, the length of the pixel island 111 in the second direction is L2, the first length threshold is 1.4L2, and the second length threshold is 0.7L2, where 0.7L2 < L1 < 1.4L2. Preferably, the length L1 of the pixel island 111 in the first direction is equal to the length L2 of the pixel island in the second direction, that is, L1 = L2.

[0083] This embodiment improves the focusing effect of the light emitted by the pixel island 111 in two directions by setting the proportional relationship between the length of the pixel island 111 in the first direction and the length of the pixel island 111 in the second direction. The diffusion angle of the light after the cylindrical lens is more uniform, thereby reducing crosstalk between adjacent viewpoints.

[0084] In some exemplary embodiments, see Figure 5The pixel group 10 includes a plurality of sub-pixels 1111, the sub-pixel 1111 is in the shape of a quadrilateral, the sub-pixel 111 includes adjacent first and second sides, the first side of the sub-pixel 1111 is parallel to the first direction, the second side of the sub-pixel 1111 is tilted relative to the second direction, and the first direction and the second direction intersect.

[0085] It is understood that the display panel also includes a black matrix (BM). The black matrix is ​​an opaque structure that separates adjacent sub-pixels 1111. Its core function is to prevent light leakage between sub-pixels 1111 and improve contrast. If the sub-pixels 1111 are rectangular (i.e., the first side of the sub-pixel 1111 is parallel to the first direction, and the first side of the sub-pixel 1111 is parallel to the second direction), under the rectangular arrangement of sub-pixels 1111, the black matrix will form a regular grid structure that is highly symmetrical in both the horizontal and vertical directions. When this regular grid structure of the black matrix is ​​superimposed on the cylindrical lens structure, moiré fringes will be formed. Moiré fringes are a wavy interference pattern caused by the interference of two periodic patterns, which will destroy the clarity of the image and affect the user's viewing experience.

[0086] In order to improve the display effect, the present application designs the shape of the sub-pixel 1111 to be an inclined parallelogram. Figure 5 , Figure 5 FIG. 1 is a schematic diagram of a planar structure of a pixel island 111 in a display panel provided by the present application in an example. Figure 5 As can be seen in the figure, the first side of sub-pixel 1111 is parallel to the X-axis, and the second side of sub-pixel 1111 is tilted relative to the Y-axis. By designing the sub-pixels 1111 as tilted parallelograms, the black matrix separating these sub-pixels 1111 is also tilted in the second direction. This tilted black matrix grid breaks the strong regularity in the horizontal and vertical directions, thereby suppressing the generation of moiré fringes and improving the display quality of the display panel.

[0087] Based on the same application concept, an embodiment of the present application also provides a display device. Figure 6 This is a schematic diagram of the planar structure of the display device 200 provided in an embodiment of the present application, as shown in FIG. Figure 6 As shown, the display device 200 includes the display panel 100 in any of the above embodiments. Figure 6 As shown, the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiment. The similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0088] The display device 200 provided in the embodiment of the present application can be Figure 6The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiments of this application do not specifically limit this.

[0089] In some exemplary embodiments, see Figure 7 , the display device further includes a cylindrical lens structure 201.

[0090] The cylindrical lens structure 201 is located on the light-emitting side of the display panel 100. The cylindrical lens structure 201 includes a plurality of cylindrical lenses 2011 arranged in an array along a first direction. The number of cylindrical lenses 2011 is the same as the number of pixel groups 10. Each cylindrical lens 2011 is arranged in a one-to-one correspondence with each pixel group 10. The length direction of the cylindrical lens 2011 is the second direction, and the first direction and the second direction intersect.

[0091] It can be understood that the cylindrical lens structure 201 is located on one side of the display panel 100 in the third direction and on the light-emitting side of the display panel 100. The third direction is the thickness direction of the display panel 100, that is, Figure 7 In the Z-axis direction shown in , the first direction, the second direction and the third direction intersect with each other.

[0092] In applications, the side of the cylindrical lens structure 201 away from the display panel 100 may also include a flat layer 202. The flat layer 202 may be made of a transparent, low-scattering material, such as optical-grade resin or glass, so that the light refracted by the cylindrical lens 2011 can be emitted more regularly, avoiding additional scattering caused by tiny defects on the surface of the cylindrical lens (such as burrs during manufacturing).

[0093] In some exemplary embodiments, the orthographic projection of the pixel group 10 on the target plane at least partially overlaps with the orthographic projection of the corresponding cylindrical lens 2011 on the target plane, wherein the target plane is a plane formed by the intersection of a straight line extending along the first direction and a straight line extending along the second direction.

[0094] In actual implementation, when the shape of the sub-pixel 1111 is a rectangle, the orthographic projection of the pixel group 10 on the target plane overlaps with the orthographic projection of the corresponding cylindrical lens 2011 on the target plane. When the shape of the sub-pixel 1111 is an inclined parallelogram, the orthographic projection of the pixel group 10 on the target plane partially overlaps with the orthographic projection of the corresponding cylindrical lens 2011 on the target plane, as shown in FIG. Figure 8 As shown, the orthographic projection of the cylindrical lens 2011 on the target plane partially covers the corresponding pixel group 10.

[0095] In a detailed embodiment, the present application provides a display device 200 , which includes a display panel 100 , a cylindrical lens structure 201 located on the light-emitting side of the display panel 100 , and a flat layer 202 located on a side of the cylindrical lens structure 201 away from the display panel 100 .

[0096] The cylindrical lens structure 201 includes a plurality of cylindrical lenses 2011 arranged in an array along a first direction. The display panel 100 includes a plurality of pixel groups 10 arranged in an array along the first direction. The number of cylindrical lenses 2011 is equal to the number of pixel groups 10, and each cylindrical lens 2011 is provided in a one-to-one correspondence with each pixel group 10. The pixel groups 10 include a plurality of pixel islands 111 arranged in an array along a second direction. The length L1 of the pixel islands 111 in the first direction is equal to the length L2 of the pixel islands in the second direction. The pixel islands 111 include a plurality of sub-pixels 1111. The sub-pixels 1111 are shaped as tilted parallelograms, with the first sides of the sub-pixels 1111 being parallel to the first direction and the second sides being tilted relative to the second direction. By setting the length of the pixel islands 111 in the first direction equal to the length of the pixel islands in the second direction and setting the sub-pixels 1111 in the tilted parallelogram shape, the focusing effect of light emitted by the pixel islands 111 in two directions can be improved, the generation of moiré fringes can be suppressed, and the display quality of the display panel can be enhanced.

[0097] The display panel includes multiple pixel groups 10, multiple multiplexing circuits 30, and multiple data fan-out line groups 50. The number of pixel groups 10, the number of multiplexing circuits 30, and the number of data fan-out line groups 50 are the same, and each multiplexing circuit 30 is provided in a one-to-one correspondence with each pixel group 10, and each multiplexing circuit 30 is provided in a one-to-one correspondence with each data fan-out line group 50. The pixel group 10 includes N sub-pixel columns, and each sub-pixel column 11 is respectively connected to a corresponding data signal line 21. The multiplexing circuit 30 includes N multiplexing units 31. The data fan-out line group 50 includes M data fan-out lines 51. Specifically, the data fan-out line group 50 includes a first data fan-out line 511 and multiple second data fan-out lines 512. For a pixel group 10, the data signal line 21 connected to each sub-pixel column is respectively connected to the signal output end of the corresponding multiplexing unit 31.

[0098] The display panel also includes at least two sub-display areas: a first sub-display area AA1 and a second sub-display area AA2. The display panel also includes at least two selection control line groups 40. The number of selection control line groups 40 is equal to the number of sub-display areas, with one selection control line group 40 corresponding to each sub-display area. Each sub-display area includes at least one pixel group 10. The number of pixel groups 10 in different sub-display areas can be different or the same. The selection control line group 40 includes N selection control line units 41, each of which includes M selection control lines 411.

[0099] The multiplexing unit 31 includes M switching transistors. In a multiplexing unit 31, the second electrode of each switching transistor is connected to the same data signal line 21, the first electrode of each switching transistor is connected to a different data fan-out line, and the gate of each switching transistor is connected to a different selection control line 411. In a multiplexing circuit 30, the i-th signal input terminal in each multiplexing unit 31 is connected to the i-th data fan-out line in the corresponding data fan-out line group 50.

[0100] In an example, see Figure 2 In a multiplexing circuit 30-n, the first signal input end of each multiplexing unit 31 (the first electrode of the switch transistor T1, the first electrode of the switch transistor T4, the first electrode of the switch transistor T7, the first electrode of the switch transistor T10, and the first electrode of the switch transistor T13) is connected to the first data fan-out line in the data fan-out line group 50-n, that is, the first data signal line 511, to receive the first data signal source-black; the second signal input end of each multiplexing unit 31 (the first electrode of the switch transistor T2, the first electrode of the switch transistor T5, the first electrode of the switch transistor T8, and the first electrode of the switch transistor T11) is connected to the first data fan-out line in the data fan-out line group 50-n, that is, the first data signal line 511, to receive the first data signal source-black; The first electrode of the switching transistor T3, the first electrode of the switching transistor T6, the first electrode of the switching transistor T9, the first electrode of the switching transistor T12, and the first electrode of the switching transistor T15) are all connected to the second data fan-out line in the data fan-out line group 50-n, that is, the second A data signal line 5121-n, to receive the second A data signal source-n-1; the third signal input end in each multiplexing unit 31 (the first electrode of the switching transistor T3, the first electrode of the switching transistor T6, the first electrode of the switching transistor T9, the first electrode of the switching transistor T12, and the first electrode of the switching transistor T15) are all connected to the third data fan-out line in the data fan-out line group 50-n, that is, the second B data signal line 5122-n, to receive the second B data signal source-n-2.

[0101] It can be understood that in a refresh phase, among the shunt control signals transmitted by each selection control line in a selection control line unit, only one shunt control signal is at a valid level, and the remaining shunt control signals are at an invalid level. For example, in a certain refresh phase, the shunt control signal MUX12, the shunt control signal MUX22, the shunt control signal MUX31, the shunt control signal MUX43, and the shunt control signal MUX53 are at a valid level, and the remaining shunt control signals are at an invalid level, and then the data signal line 21-1 and the data signal line 21-2 receive the second A data signal source-n-1, the data signal line 21-3 receives the first data signal source-black, and the data signal line 21-4 and the data signal line 21-5 receive the second B data signal source-n-2. In this way, when multiple sub-pixels require the same data signal, it is only necessary to control the conduction of the corresponding signal input terminal and the signal data terminal through the shunt control signal, so that the same data signal can be written into each sub-pixel that requires the same data signal, thereby avoiding redundant driving and reducing driving power consumption.

[0102] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0103] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A display panel, characterized in that: include: A plurality of pixel groups, wherein the plurality of pixel groups are arranged along a first direction; wherein the pixel groups include N sub-pixel columns; A plurality of data signal lines, wherein each sub-pixel column is connected to a corresponding data signal line; Multiple multiplexing circuits, each comprising N multiplexing units, each comprising M signal input terminals, one signal output terminal, and M branch control terminals, wherein, in the same multiplexing circuit, the m-th signal input terminal of the s-th multiplexing unit is coupled to the m-th signal input terminal of the t-th multiplexing unit; the M branch control terminals respectively receive different branch control signals; the signal output terminals of the multiplexing units are correspondingly connected to the data signal lines; and at the same time, the M signal input terminals respectively receive data signals of different sizes, 3≤M<N, 1≤s≠t≤N, 1≤m≤M, and M, N, m, s, and t are all integers; At least one selection control line group, the selection control line group includes N selection control line units, the selection control line unit includes M selection control lines, and the selection control lines are connected to the branch control end.

2. The display panel according to claim 1, wherein: The multiplexing unit includes M switching transistors, the first electrode of the switching transistor corresponds to the signal input end, the second electrode of the switching transistor is connected to the data signal line, the second electrode of the switching transistor corresponds to the signal output end, and the gate of the switching transistor corresponds to the branch control end.

3. The display panel according to claim 2, wherein: The display panel further includes: A plurality of data fan-out line groups, each comprising M data fan-out lines, each of which is used to output the data signal; wherein the i-th signal input terminal of the multiplexing unit in the multiplexing circuit is connected to the i-th data fan-out line in the corresponding data fan-out line group, 1≤i≤M, and i is an integer.

4. The display panel according to claim 3, wherein: The data fan-out line group includes a first data fan-out line and a plurality of second data fan-out lines; Wherein, the first data fan-out lines of at least part of the data fan-out line groups are the same data fan-out line.

5. The display panel according to claim 4, wherein: The first data fan-out line is used to transmit a first data signal. When a sub-pixel receives the first data signal, the sub-pixel is in a black state.

6. The display panel according to claim 4, wherein: M=3, where The multiplexing circuit includes N multiplexing units, each of which includes three signal input terminals, one signal output terminal, and three branch control terminals. In the same multiplexing circuit, the mth signal input terminal of the sth multiplexing unit is coupled to the mth signal input terminal of the tth multiplexing unit. The three branch control terminals receive different branch control signals. The signal output terminals of the multiplexing units are connected to the data signal lines. The selection control line group includes N selection control line units, each of which includes three selection control lines connected to the branch control terminal; The data fan-out line group includes three data fan-out lines, which are used to output data signals; wherein i signal input terminals of the multiplexing unit in the multiplexing circuit are connected to the i-th data fan-out line in the corresponding data fan-out line group, and at the same time, the data signals transmitted by the three data fan-out lines have different sizes, 1≤i≤3, and i is an integer.

7. The display panel according to claim 6, wherein: The multiplexing unit includes three switch transistors; the plurality of second data fan-out lines include a second A data fan-out line and a second B data fan-out line; The first data fan-out line, the second data fan-out line A and the second data fan-out line B are respectively connected to the first electrodes of the three switch transistors of the multiplexing unit; Wherein, at the same time, the sizes of data signals transmitted by the first data fan-out line, the second data fan-out line A and the second data fan-out line B are different.

8. The display panel according to claim 1, wherein: The display panel includes a plurality of sub-display areas in a first direction; the sub-display area includes at least one pixel group; Among them, the number of sub-display areas is the same as the number of selection control line groups, each sub-display area corresponds to each selection control line group one by one, and the multiplexing unit corresponding to the k-th sub-pixel column in each pixel group in the sub-display area is connected to the k-th selection control line unit in the selection control line group corresponding to the sub-display area; 1≤k≤N, and k is an integer.

9. The display panel according to claim 1, wherein: The display panel includes a selection control line group, and the display panel includes at least a first sub-display area and a second sub-display area in the first direction; the first sub-display area and the second sub-display area each include at least one pixel group; Wherein, the multiplexing unit corresponding to the j-th sub-pixel column in the pixel group in the first sub-display area is connected to the j-th selection control line unit in the selection control line group; The multiplexing unit corresponding to the j-th sub-pixel column in each pixel group in the second sub-display area is connected to the j+1-th selection control line unit in the selection control line group; the multiplexing unit corresponding to the N-th sub-pixel column in each pixel group in the second sub-display area is connected to the first selection control line unit in the selection control line group, 1≤j<N, and j is an integer.

10. The display panel according to claim 1, wherein The display panel has a plurality of refresh phases. In each refresh phase, among the branch control signals output by a selection control line unit, one branch control signal is at a valid level, and the other branch control signals are at invalid levels.

11. The display panel according to claim 1, wherein The pixel group includes a plurality of pixel islands arranged along the second direction, and the length of the pixel islands in the first direction is less than a first length threshold and greater than a second length threshold; The first length threshold is greater than the second length threshold, the first length threshold and the second length threshold are related to the length of the pixel island in the second direction, and the first direction and the second direction intersect.

12. The display panel according to claim 11, wherein: The length of the pixel island in the first direction is equal to the length of the pixel island in the second direction.

13. The display panel according to claim 1, wherein: N is a positive even number.

14. The display panel according to claim 1, wherein The pixel group includes multiple sub-pixels, each sub-pixel is in the shape of a quadrilateral, and each sub-pixel includes adjacent first and second sides. The first side of the sub-pixel is parallel to the first direction, and the second side of the sub-pixel is inclined relative to the second direction, and the first direction and the second direction intersect.

15. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 14.

16. The display device according to claim 15, wherein: Also includes: A cylindrical lens structure is located on the light-emitting side of the display panel, wherein the cylindrical lens structure includes a plurality of cylindrical lenses arranged in an array along a first direction, the number of the cylindrical lenses is the same as the number of the pixel groups, and each cylindrical lens is arranged in a one-to-one correspondence with each pixel group. The length direction of the cylindrical lens is a second direction, and the first direction and the second direction intersect.

17. The display device according to claim 16, wherein: The orthographic projection of the pixel group on the target plane at least partially overlaps with the orthographic projection of the corresponding cylindrical lens on the target plane, wherein the target plane is a plane formed by the intersection of a straight line extending along the first direction and a straight line extending along the second direction.

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