Display device

Abstract

The invention provides a display device, which comprises a plurality of pixels and at least one gate driving circuit, the gate driving circuit comprises cascaded multiple levels of gate driving sub-circuits, the ith level of gate driving sub-circuit comprises a level transmission signal output unit, at least one gate driving signal output unit and at least one light-emitting control signal output unit, and the ith level of gate driving sub-circuit comprises a level transmission signal output unit, at least one gate driving signal output unit and at least one light-emitting control signal output unit. The output units are electrically connected with a first node, and the at least one level transmission signal output unit and the at least one gate drive signal output unit are further electrically connected with a third node and a fourth node. According to the technical scheme, the occupied area of the gate drive circuit is remarkably reduced, and the narrow frame design of the display panel can be achieved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display device. Background Art

[0002] The gate-driver on array (GOA) circuit in a traditional display panel includes multiple stages of gate driver sub-circuits. Each stage typically includes multiple independent driver units, including a stage transmission signal output unit, a gate drive signal output unit, and a light-emission control signal output unit. For example, these units may include two stage transmission signal output units, two gate drive signal output units, and one light-emission control signal output unit. The stage transmission signal output unit, gate drive signal output unit, and light-emission control signal output unit are used to generate the stage transmission signal, gate drive signal, and light-emission control signal, respectively, to control the pixels of the display panel.

[0003] Each driver unit in a traditional gate drive circuit has its own independent input module and output module. Because these driver units each include independent input modules (such as input terminals, transistors, nodes, etc.), the entire gate drive circuit occupies a large area, which is extremely unfavorable for achieving a narrow-frame design for display panels. Especially for display panels that require multiple types of driver units, achieving a narrow frame is even more difficult, which has become a major technical bottleneck restricting the development of display panels. In addition, for spliced ​​display panels, since multiple types of driver units need to be placed within the display area, the independent design of the driver units results in a large gate drive circuit area, which can easily lead to uneven display and affect the overall display effect.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Summary of the Invention

[0005] The embodiment of the present application aims to provide a display device, aiming to solve the technical problem that the gate driving circuit in the traditional display device occupies a large area.

[0006] An embodiment of the present application provides a display device, wherein the display device includes a plurality of pixels and at least one gate driving circuit, wherein the plurality of pixels are arranged in rows and columns, and the gate driving circuit includes a cascade of multiple gate driving sub-circuits, wherein the first-stage gate driving sub-circuit is electrically connected to the plurality of pixels, and the i-th-stage gate driving sub-circuit in the multiple-stage gate driving sub-circuit includes a level transmission signal output unit, at least one gate driving signal output unit, and at least one light-emitting control signal output unit, where i is a positive integer; wherein one of the level transmission signal output units, at least one gate driving signal output unit, and at least one light-emitting control signal output unit are all electrically connected to a first node, and one of the level transmission signal output units and at least one gate driving signal output unit are electrically connected to a first node. The signal output unit is also electrically connected to a third node and a fourth node; the stage transfer signal output unit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, and the first node is a node where the first transistor, the second transistor, the fifth transistor, the sixth transistor and the seventh transistor are electrically connected together; the gate drive signal output unit includes a thirteenth transistor and a fifteenth transistor, the third node is a node where the fifteenth transistor is electrically connected together with the fifth transistor, the eighth transistor and the tenth transistor, and the fourth node is a node where the thirteenth transistor is electrically connected together with the seventh transistor and the ninth transistor.

[0007] In the above-mentioned display device, the level-transmitting signal output unit further includes a third transistor, a fourth transistor, a first capacitor and a second capacitor, or the level-transmitting signal output unit further includes a third transistor, a fourth transistor, an eleventh transistor, a twelfth transistor, a first capacitor and a second capacitor; the gate drive signal output unit further includes a fourteenth transistor, a sixteenth transistor, a seventeenth transistor and a third capacitor; the light-emitting control signal output unit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; the first transistor to the tenth transistor and the thirteenth transistor to the twenty-third transistor are all P-type transistors or are all N-type transistors, or the first transistor to the twenty-third transistor are all P-type transistors or are all N-type transistors.

[0008] In the above-mentioned display device, the gate of the thirteenth transistor is electrically connected to the gate drive signal output terminal of the ia-th level gate drive sub-circuit, the source of the thirteenth transistor is electrically connected to the fourth node, the drain of the thirteenth transistor is electrically connected to the fifth node, the gate of the fourteenth transistor is electrically connected to the fifth node, the source of the fourteenth transistor is electrically connected to the gate drive source signal input terminal, the drain of the fourteenth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, the gate of the fifteenth transistor is electrically connected to the third node, and the tenth transistor is electrically connected to the gate drive source signal input terminal. The drain of the fifth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, the gate of the sixteenth transistor is electrically connected to the sixth node, the drain of the sixteenth transistor is electrically connected to the fifth node, the gate of the seventeenth transistor is electrically connected to the sixth node, the drain of the seventeenth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, one plate of the third capacitor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, and the other plate of the third capacitor is electrically connected to the fifth node, and a is a positive integer.

[0009] In the above-mentioned display device, when the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are all P-type transistors, the source of the fifteenth transistor is electrically connected to the high-level power input terminal, the source of the sixteenth transistor is electrically connected to the high-level power input terminal, and the source of the seventeenth transistor is electrically connected to the high-level power input terminal; when the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are all N-type transistors, the source of the fifteenth transistor is electrically connected to the low-level power input terminal, the source of the sixteenth transistor is electrically connected to the low-level power input terminal, and the source of the seventeenth transistor is electrically connected to the low-level power input terminal.

[0010] In the above-mentioned display device, the gate of the 20th transistor is electrically connected to the first node, the drain of the 20th transistor is electrically connected to the drain of the 18th transistor, the gate of the 21st transistor is electrically connected to the drain of the 18th transistor, the drain of the 21st transistor is electrically connected to the drain of the 19th transistor, the gate of the 22nd transistor is electrically connected to the drain of the 18th transistor, the drain of the 22nd transistor is electrically connected to the light-emitting control signal output terminal of the light-emitting control signal output unit, the gate of the 23rd transistor is electrically connected to the drain of the 19th transistor, and the drain of the 23rd transistor is electrically connected to the light-emitting control signal output terminal of the light-emitting control signal output unit.

[0011] In the above-mentioned display device, when the eighteenth to twenty-third transistors are all P-type transistors, the gate and source of the eighteenth transistor are both electrically connected to the low-level power input terminal, the gate and source of the nineteenth transistor are both electrically connected to the low-level power input terminal, the source of the twentieth transistor is electrically connected to the high-level power input terminal, the source of the twenty-first transistor is electrically connected to the high-level power input terminal, the source of the twenty-second transistor is electrically connected to the high-level power input terminal, and the source of the twenty-third transistor is electrically connected to the low-level power input terminal; when the eighteenth to twenty-third transistors are all N-type transistors, the gate and source of the eighteenth transistor are both electrically connected to the high-level power input terminal, the gate and source of the nineteenth transistor are both electrically connected to the high-level power input terminal, the source of the twentieth transistor is electrically connected to the low-level power input terminal, the source of the twenty-first transistor is electrically connected to the low-level power input terminal, the source of the twenty-second transistor is electrically connected to the low-level power input terminal, and the source of the twenty-third transistor is electrically connected to the high-level power input terminal.

[0012] In the above-mentioned display device, the gate of the first transistor is electrically connected to the stage transmission signal output terminal of the ib-th stage gate driving sub-circuit, the source of the first transistor is electrically connected to the first control signal input terminal, the drain of the first transistor is electrically connected to the first node, the gate of the second transistor is electrically connected to the stage transmission signal output terminal of the i+c-th stage gate driving sub-circuit, the source of the second transistor is electrically connected to the second control signal input terminal, the drain of the second transistor is electrically connected to the first node, the gate of the third transistor is electrically connected to the first control signal input terminal, the source of the third transistor is electrically connected to the first clock signal input terminal, the drain of the third transistor is electrically connected to the second node, the gate of the fourth transistor is electrically connected to the second control signal input terminal, the source of the fourth transistor is electrically connected to the second clock signal input terminal, the drain of the fourth transistor is electrically connected to the second node, and the gate of the fifth transistor is electrically connected to the third node , the drain of the fifth transistor is electrically connected to the first node, the gate of the sixth transistor is electrically connected to the first node, the drain of the sixth transistor is electrically connected to the third node, the source of the seventh transistor is electrically connected to the first node, the drain of the seventh transistor is electrically connected to the fourth node, the gate of the eighth transistor is electrically connected to the second node, the drain of the eighth transistor is electrically connected to the third node, the gate of the ninth transistor is electrically connected to the fourth node, the source of the ninth transistor is electrically connected to the third clock signal input terminal, the drain of the ninth transistor is electrically connected to the stage-pass signal output terminal of the stage-pass signal output unit, the gate of the tenth transistor is electrically connected to the third node, the drain of the tenth transistor is electrically connected to the stage-pass signal output terminal of the stage-pass signal output unit, one plate of the first capacitor is electrically connected to the first node, and one plate of the second capacitor is electrically connected to the third node. b and c are both positive integers.

[0013] In the above-mentioned display device, when the first transistor to the tenth transistor are all P-type transistors, the source of the fifth transistor is electrically connected to the high-level power input terminal, the source of the sixth transistor is electrically connected to the high-level power input terminal, the gate of the seventh transistor is electrically connected to the low-level power input terminal, the source of the eighth transistor is electrically connected to the low-level power input terminal, the source of the tenth transistor is electrically connected to the high-level power input terminal, the source of the twelfth transistor is electrically connected to the high-level power input terminal, the other plate of the first capacitor is electrically connected to the high-level power input terminal, and the other plate of the second capacitor is electrically connected to the high-level power input terminal. end is electrically connected; in the case where the first transistor to the tenth transistor are all N-type transistors, the source of the fifth transistor is electrically connected to the low-level power input terminal, the source of the sixth transistor is electrically connected to the low-level power input terminal, the gate of the seventh transistor is electrically connected to the high-level power input terminal, the source of the eighth transistor is electrically connected to the high-level power input terminal, the source of the tenth transistor is electrically connected to the low-level power input terminal, the source of the twelfth transistor is electrically connected to the low-level power input terminal, the other plate of the first capacitor is electrically connected to the low-level power input terminal, and the other plate of the second capacitor is electrically connected to the low-level power input terminal.

[0014] In the above-mentioned display device, the gate of the eleventh transistor is electrically connected to the level transfer control signal input terminal, the source of the eleventh transistor is electrically connected to the level transfer control signal input terminal, the drain of the eleventh transistor is electrically connected to the level transfer signal output terminal of the level transfer signal output unit, the gate of the twelfth transistor is electrically connected to the level transfer control signal input terminal, and the drain of the twelfth transistor is electrically connected to the third node.

[0015] In the above-mentioned display device, when the twelfth transistor is a P-type transistor, the source of the twelfth transistor is electrically connected to the high-level power input terminal; when the twelfth transistor is an N-type transistor, the source of the twelfth transistor is electrically connected to the low-level power input terminal.

[0016] The display device provided in the embodiments of the present application integrates a level transmission signal output unit, at least one gate drive signal output unit and at least one light-emitting control signal output unit in the i-th level gate drive sub-circuit, and enables these units to share nodes, thereby realizing a miniaturized design of the gate drive circuit, effectively solving the technical problem that the traditional gate drive circuit occupies a large area.

[0017] Specifically, the technical solution of the present application eliminates the redundancy brought about by the independent setting of input modules for each driving unit in traditional technology by electrically connecting a level transmission signal output unit, at least one gate drive signal output unit and at least one light-emitting control signal output unit to the same first node, and at least one level transmission signal output unit and at least one gate drive signal output unit are also electrically connected to the third node and the fourth node. While ensuring functional integrity, the number of transistors and nodes in the circuit is significantly reduced, making the circuit layout more compact and further reducing the overall occupied area of ​​the gate drive circuit.

[0018] In summary, the display device of the present application achieves a significant reduction in the area occupied by the gate driving circuit while maintaining the integrity of the gate driving function. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a schematic diagram of a display device provided in an embodiment of the present application.

[0020] Figure 2 4 is a circuit diagram of a first embodiment of a gate driving sub-circuit in a display device provided in this application.

[0021] Figure 3 4 is a circuit diagram of a second embodiment of a gate driving sub-circuit in a display device provided in this application.

[0022] Figure 4 yes Figure 2 or Figure 3 The waveform diagram of the first embodiment or the second embodiment of the gate driving sub-circuit is shown.

[0023] Figure 5 4 is a circuit diagram of a third embodiment of a gate driving sub-circuit in a display device provided in this application.

[0024] Figure 6 4 is a circuit diagram of a fourth embodiment of a gate driving sub-circuit in a display device provided in the present application.

[0025] Figure 7 yes Figure 5 or Figure 6 The waveform diagram of the third embodiment or the fourth embodiment of the gate driving sub-circuit shown. DETAILED DESCRIPTION

[0026] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0027] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0028] The embodiments of the present application may be combined with each other.

[0029] The embodiments of the present application provide a display device for solving the technical problems in the prior art that a gate driving circuit occupies a large area, is not conducive to achieving a narrow frame, and affects display uniformity.

[0030] The display device provided in the embodiments of the present application is one of an OLED display device, a Mini-LED display device, and a Micro-LED display device. The embodiments of the present application are described using the OLED display device as an example.

[0031] like Figure 1 As shown, the display device provided by the embodiment of the present application includes a display panel, a timing controller, and a source driver circuit. The display panel includes at least one gate driver circuit and a plurality of pixels PX. The gate driver circuit includes multiple stages of cascaded gate driver subcircuits.

[0032] The display panel includes a display area and a non-display area, the non-display area being located around the display area, and the display area being provided with a plurality of pixels PX arranged in an array. The display panel also includes a plurality of gate lines Gout, a plurality of data lines Data, and a plurality of light-emitting control signal lines EM. The plurality of gate lines Gout and the plurality of light-emitting control signal lines EM extend along a first direction and are arranged along a second direction, and the plurality of data lines Data extend along a second direction and are arranged along the first direction, with the first direction being perpendicular to the second direction. A gate drive circuit is provided in the non-display area and is electrically connected to the plurality of gate lines Gout. A source drive circuit is electrically connected to the plurality of data lines Data via a flexible printed circuit board. A timing controller is electrically connected to the gate drive circuit and the source drive circuit.

[0033] The display panel includes an organic light-emitting diode array substrate and an encapsulation layer. The organic light-emitting diode array substrate includes a base substrate, a buffer layer disposed on the base substrate, an active layer disposed on the buffer layer, a gate insulating layer disposed on the active layer, a first metal layer disposed on the gate insulating layer, an interlayer insulating layer disposed on the first metal layer, a second metal layer disposed on the interlayer insulating layer, a planarization layer disposed on the second metal layer, a first electrode layer disposed on the planarization layer, a pixel defining layer disposed on the first electrode layer, an organic light-emitting layer disposed in an opening area defined by the pixel defining layer, and a second electrode layer disposed on the organic light-emitting layer. The first metal layer includes a gate line Gout and a gate. The second metal layer includes a data line Data, a source electrode, and a drain electrode. The encapsulation layer is sealed and connected to the organic light-emitting diode array substrate.

[0034] Each pixel PX includes a pixel driving circuit and a light-emitting device. The pixel driving circuit includes at least two transistors and a storage capacitor. One of the transistors functions as a switching transistor, with its gate electrically connected to the corresponding gate line Gout and its source electrically connected to the corresponding data line Data. The other transistor functions as a driving transistor, with its gate electrically connected to the drain of the switching transistor, its source electrically connected to the first power supply voltage line, and its drain electrically connected to the anode of the light-emitting device. One end of the storage capacitor is electrically connected to the gate of the driving transistor, and the other end is electrically connected to the source or drain of the driving transistor. The cathode of the light-emitting device is electrically connected to the second power supply voltage line.

[0035] Each gate driver sub-circuit is electrically connected to a gate line Gout. Under the control of a timing controller, the gate driver sub-circuit sequentially outputs scan signals, progressively scanning each row of pixels PX in the display area. Under the control of the timing controller, the source driver circuit generates and outputs data signals based on image data. The timing controller receives and processes externally input image data and timing signals, generates control signals, and transmits the image data to the source driver circuit.

[0036] Multiple pixels are arranged in rows and columns, and a first-level gate driving subcircuit is electrically connected to multiple pixels in a row of pixels. The i-th level gate driving subcircuit in the multi-level gate driving subcircuit includes a level transmission signal output unit 101, a gate driving signal output unit 102 and a light-emitting control signal output unit 103, where i is a positive integer.

[0037] The first-level gate driver subcircuit of the present application is electrically connected to at least one row of pixels. The first-level gate driver subcircuit includes a level transmission signal output unit 101, a gate drive signal output unit 102, and a light-emitting control signal output unit 103. At this time, the first-level gate driver subcircuit outputs a level transmission signal, a gate drive signal, and a light-emitting control signal. The level transmission signal is provided to the next-level level transmission signal output unit 101, and the gate drive signal and the light-emitting control signal are provided to a row of pixels. This reduces the occupied area of ​​the gate driver subcircuit in a one-to-one application scenario (a first-level gate driver subcircuit driving a row of pixels).

[0038] The first-level gate driver subcircuit may also include a level transmission signal output unit 101, multiple gate drive signal output units 102, and multiple light-emitting control signal output units 103. In this case, the first-level gate driver subcircuit outputs a level transmission signal, multiple gate drive signals, and multiple light-emitting control signals. The level transmission signal is provided to the next-level level transmission signal output unit 101, and the multiple gate drive signals and the multiple light-emitting control signals are provided to one or more rows of pixels. In this way, in the application scenario where the first-level gate driver subcircuit drives one or more rows of pixels, the occupied area of ​​the gate driver subcircuit is reduced. Embodiments 1 to 4 are all explained using the application scenario where the first-level gate driver subcircuit drives a row of pixels as an example.

[0039] The level transmission signal output unit 101, the gate drive signal output unit 102, and the light emission control signal output unit 103 are all electrically connected to a first node Q1. The level transmission signal output unit 101 and the gate drive signal output unit 102 are also electrically connected to a third node P1 and a fourth node Q2. The level transmission signal output unit 101 includes a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a tenth transistor T10. The first node Q1 is a node to which the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are electrically connected. The gate drive signal output unit 102 includes a thirteenth transistor T13 and a fifteenth transistor T15. The third node P1 is a node to which the fifteenth transistor T15 is electrically connected together with the fifth transistor T5, the eighth transistor T8, and the tenth transistor T10. The fourth node Q2 is a node to which the thirteenth transistor T13 is electrically connected together with the seventh transistor T7 and the ninth transistor T9.

[0040] The level-transmission signal output unit 101 further includes a third transistor T3, a fourth transistor T4, a first capacitor C1, and a second capacitor C2, or the level-transmission signal output unit 101 further includes a third transistor T3, a fourth transistor T4, an eleventh transistor T11, a twelfth transistor T12, a first capacitor C1, and a second capacitor C2. The gate drive signal output unit 102 further includes a fourteenth transistor T14, a sixteenth transistor T16, a seventeenth transistor T17, and a third capacitor C3. The light-emission control signal output unit 103 includes an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, a twenty-first transistor T21, a twenty-second transistor T22, and a twenty-third transistor T23.

[0041] The first to tenth transistors T10 and the thirteenth to twenty-third transistors T13 to T23 are all P-type transistors or N-type transistors, or the first to twenty-third transistors T1 to T23 are all P-type transistors or N-type transistors.

[0042] First embodiment like Figure 2 As shown, the i-th stage gate driving sub-circuit in the multi-stage gate driving sub-circuit includes a first transistor T1 to a twenty-third transistor T23 and a first capacitor C1 to a third capacitor C3. The first transistor T1 to the twenty-third transistor T23 are all P-type transistors.

[0043] The i-th stage gate driver sub-circuit includes a stage transmission signal output unit 101, a gate drive signal output unit 102, and a light emission control signal output unit 103. The stage transmission signal output unit 101 includes first to twelfth transistors T1 to T12, as well as a first capacitor C1 and a second capacitor C2. The gate drive signal output unit 102 includes thirteenth to seventeenth transistors T13 to T17 and a third capacitor C3. The light emission control signal output unit 103 includes eighteenth to twenty-third transistors T18 to T23.

[0044] In the stage-transmission signal output unit 101, the gate of the first transistor T1 is electrically connected to the stage-transmission signal output terminal ST(ib) of the ib-th stage gate driver sub-circuit, the source of the first transistor T1 is electrically connected to the first control signal input terminal U2D, and the drain of the first transistor T1 is electrically connected to the first node Q1. b is a positive integer, for example, b=2. The gate of the second transistor T2 is electrically connected to the stage-transmission signal output terminal ST(i+c) of the i+c-th stage gate driver sub-circuit, the source of the second transistor T2 is electrically connected to the second control signal input terminal D2U, and the drain of the second transistor T2 is electrically connected to the first node Q1. c is a positive integer, for example, c=2. The gate of the third transistor T3 is electrically connected to the first control signal input terminal U2D, the source of the third transistor T3 is electrically connected to the first clock signal input terminal CK(j+e), and the drain of the third transistor T3 is electrically connected to the second node A. e is a positive integer, for example, e=2. The gate of the fourth transistor T4 is electrically connected to the second control signal input terminal D2U, the source of the fourth transistor T4 is electrically connected to the second clock signal input terminal CK(jf), and the drain of the fourth transistor T4 is electrically connected to the second node A, where f is a positive integer, for example, f=2. The gate of the fifth transistor T5 is electrically connected to the third node P1, the source of the fifth transistor T5 is electrically connected to the high-level power input terminal VGH, and the drain of the fifth transistor T5 is electrically connected to the first node Q1. The gate of the sixth transistor T6 is electrically connected to the first node Q1, the source of the sixth transistor T6 is electrically connected to the high-level power input terminal VGH, and the drain of the sixth transistor T6 is electrically connected to the third node P1. The gate of the seventh transistor T7 is electrically connected to the low-level power input terminal VGL, the source of the seventh transistor T7 is electrically connected to the first node Q1, and the drain of the seventh transistor T7 is electrically connected to the fourth node Q2. The gate of the eighth transistor T8 is electrically connected to the second node A, the source of the eighth transistor T8 is electrically connected to the low-level power supply input terminal VGL, and the drain of the eighth transistor T8 is electrically connected to the third node P1. The gate of the ninth transistor T9 is electrically connected to the fourth node Q2, the source of the ninth transistor T9 is electrically connected to the third clock signal input terminal CK(j), and the drain of the ninth transistor T9 is electrically connected to the stage-transmission signal output terminal ST(i) of the gate driver sub-circuit of the current stage (the i-th stage). The gate of the tenth transistor T10 is electrically connected to the third node P1, the source of the tenth transistor T10 is electrically connected to the high-level power supply input terminal VGH, and the drain of the tenth transistor T10 is electrically connected to the stage-transmission signal output terminal ST(i) of the gate driver sub-circuit of the current stage (the i-th stage). The gate of the eleventh transistor T11 is electrically connected to the stage transmission control signal input terminal Gas1, the source of the eleventh transistor T11 is electrically connected to the stage transmission control signal input terminal Gas1, and the drain of the eleventh transistor T11 is electrically connected to the stage transmission signal output terminal ST(i) of the gate driving sub-circuit of this stage (the i-th stage).The gate of the twelfth transistor T12 is electrically connected to the stage transfer control signal input terminal Gas1, the source of the twelfth transistor T12 is electrically connected to the high-level power input terminal VGH, and the drain of the twelfth transistor T12 is electrically connected to the third node P1. One plate of the first capacitor C1 is electrically connected to the high-level power input terminal VGH, and the other plate is electrically connected to the first node Q1. One plate of the second capacitor C2 is electrically connected to the high-level power input terminal VGH, and the other plate is electrically connected to the third node P1.

[0045] In the gate drive signal output unit 102, the gate of the thirteenth transistor T13 is electrically connected to the gate drive signal output terminal Gout(ia) of the ia-th gate drive sub-circuit, the source of the thirteenth transistor T13 is electrically connected to the fourth node Q2, and the drain of the thirteenth transistor T13 is electrically connected to the fifth node Q3. Where a is a positive integer, for example, a=2. The gate of the fourteenth transistor T14 is electrically connected to the fifth node Q3, the source of the fourteenth transistor T14 is electrically connected to the gate drive source signal input terminal (for example, the clock signal input terminal) CKS(k), and the drain of the fourteenth transistor T14 is electrically connected to the gate drive signal output terminal Gout(i) of the current (i-th) gate drive sub-circuit. The gate of the fifteenth transistor T15 is electrically connected to the third node P1, the source of the fifteenth transistor T15 is electrically connected to the high-level power supply input terminal VGH, and the drain of the fifteenth transistor T15 is electrically connected to the gate drive signal output terminal Gout(i) of the current (i-th) gate drive sub-circuit. The gate of the sixteenth transistor T16 is electrically connected to the sixth node P2, which is electrically connected to the gate drive signal output terminal Gout(i+d) of the i+d-th gate driver sub-circuit. The source of the sixteenth transistor T16 is electrically connected to the high-level power supply input terminal VGH, and the drain of the sixteenth transistor T16 is electrically connected to the fifth node Q3, where d is a positive integer, for example, d=2. The gate of the seventeenth transistor T17 is electrically connected to the sixth node P2, the source of the seventeenth transistor T17 is electrically connected to the high-level power supply input terminal VGH, and the drain of the seventeenth transistor T17 is electrically connected to the gate drive signal output terminal Gout(i) of the current (i-th) gate driver sub-circuit. One plate of the third capacitor C3 is electrically connected to the gate drive signal output terminal Gout(i) of the current (i-th) gate driver sub-circuit, and the other plate is electrically connected to the fifth node Q3.

[0046] In the light-emission control signal output unit 103, the gate of the eighteenth transistor T18 is electrically connected to the low-level power input terminal VGL, and the source of the eighteenth transistor T18 is electrically connected to the low-level power input terminal VGL. The gate of the nineteenth transistor T19 is electrically connected to the low-level power input terminal VGL, and the source of the nineteenth transistor T19 is electrically connected to the low-level power input terminal VGL. The gate of the twentieth transistor T20 is electrically connected to the first node Q1, the source of the twentieth transistor T20 is electrically connected to the high-level power input terminal VGH, and the drain of the twentieth transistor T20 is electrically connected to the drain of the eighteenth transistor T18. The gate of the twenty-first transistor T21 is electrically connected to the drain of the eighteenth transistor T18, the source of the twenty-first transistor T21 is electrically connected to the high-level power input terminal VGH, and the drain of the twenty-first transistor T21 is electrically connected to the drain of the nineteenth transistor T19. The gate of the twenty-second transistor T22 is electrically connected to the drain of the eighteenth transistor T18. The source of the twenty-second transistor T22 is electrically connected to the high-level power input terminal VGH. The drain of the twenty-second transistor T22 is electrically connected to the light-emission control signal output terminal EM(i) of the gate driver sub-circuit of the current stage (the i-th stage). The gate of the twenty-third transistor T23 is electrically connected to the drain of the nineteenth transistor T19. The source of the twenty-third transistor T23 is electrically connected to the low-level power input terminal VGL. The drain of the twenty-third transistor T23 is electrically connected to the light-emission control signal output terminal EM(i) of the gate driver sub-circuit of the current stage (the i-th stage).

[0047] The gate drive source signal input terminal (e.g., clock signal input terminal) CKS(k) and the third clock signal input terminal CK(j) can be the same clock signal input terminal or different clock signal input terminals, where j and k are positive integers. If the gate drive source signal input terminal (e.g., clock signal input terminal) CKS(k) and the third clock signal input terminal CK(j) are different clock signal input terminals, the gate drive signal output terminal Gout(i) of the current stage (i-th stage) gate drive sub-circuit, which is electrically connected to a large load, is prevented from affecting the waveform of the clock signal at the third clock signal input terminal CK(j), thereby preventing the gate drive signal output terminal ST(i) of the current stage (i-th stage) gate drive sub-circuit from affecting the waveform of the stage transmission signal outputted from the stage transmission signal output terminal ST(i) of the current stage (i-th stage) gate drive sub-circuit.

[0048] Second embodiment like Figure 3 As shown, the i-th stage gate driver sub-circuit in the multi-stage gate driver sub-circuit includes first to tenth transistors T1 to T10, thirteenth to twenty-third transistors T13 to T23, and first to third capacitors C1 to C3. The first to tenth transistors T10 and the thirteenth to twenty-third transistors T13 to T23 are all P-type transistors.

[0049] The second embodiment differs from the first embodiment in that the stage-transmitting signal output unit 101 of the second embodiment does not include the eleventh transistor T11 and the twelfth transistor T12. Specifically, the stage-transmitting signal output unit 101 includes first to tenth transistors T10 and a first capacitor C1 and a second capacitor C2. The gate drive signal output unit 102 includes thirteenth to seventeenth transistors T13 to T17 and a third capacitor C3. The light-emission control signal output unit 103 includes eighteenth to twenty-third transistors T18 to T23.

[0050] The connection relationship between the transistors and the capacitors in the second embodiment is the same as that of the corresponding transistors and capacitors in the first embodiment, except that the eleventh transistor T11 and the twelfth transistor T12 are not included.

[0051] like Figure 4As shown, corresponding to the first and second embodiments of the present application, in the gate driving circuit of the display device provided by the present application, the first clock signal input terminal CK1 to the fourth clock signal input terminal CK4 sequentially transmit four low-level pulses staggered in time, the fifth clock signal input terminal CKS1 to the eighth clock signal input terminal CKS4 also sequentially transmit four low-level pulses staggered in time, the timing of the low-level pulse of the fifth clock signal input terminal CKS1 is the same as the timing of the low-level pulse of the first clock signal input terminal CK1, and the sixth clock signal input terminal The timing of the low level pulse of CKS2 is the same as the timing of the low level pulse of the second clock signal input terminal CK2, the timing of the low level pulse of the seventh clock signal input terminal CKS3 is the same as the timing of the low level pulse of the third clock signal input terminal CK3, the timing of the low level pulse of the eighth clock signal input terminal CKS4 is the same as the timing of the low level pulse of the fourth clock signal input terminal CK4, and the three low level pulses staggered in time are transmitted from the starting stage signal input terminal ST0 to the second stage signal input terminal ST2 in sequence. The low level pulse of the starting stage signal input terminal ST0 is the same as the timing of the low level pulse of the third clock signal input terminal CK3, and the low level pulse of the eighth clock signal input terminal CKS4 is the same as the timing of the low level pulse of the fourth clock signal input terminal CK4. The timing of the level pulse is the same as the timing of the low level pulse of the fourth clock signal input terminal CK4, the timing of the low level pulse of the first-stage transmission signal input terminal ST1 is the same as the timing of the low level pulse of the first clock signal input terminal CK1, the timing of the low level pulse of the second-stage transmission signal input terminal ST2 is the same as the timing of the low level pulse of the second clock signal input terminal CK2, and the three low level pulses staggered in time are transmitted in sequence from the starting gate drive signal input terminal Gout0 to the second gate drive signal input terminal Gout2. The starting gate drive signal input terminal Go is The timing of the low level pulse of ut0 is the same as the timing of the low level pulse of the eighth clock signal input terminal CKS4, the timing of the low level pulse of the first gate drive signal input terminal Gout1 is the same as the timing of the low level pulse of the fifth clock signal input terminal CKS1, the timing of the low level pulse of the second gate drive signal input terminal Gout2 is the same as the timing of the low level pulse of the sixth clock signal input terminal CKS2, and the first light-emitting control signal input terminal EM1 to the second light-emitting control signal input terminal EM2 sequentially transmit two low level pulses that partially overlap in time.

[0052] Third embodiment like Figure 5 As shown, the i-th stage gate driving sub-circuit in the multi-stage gate driving sub-circuit includes a first transistor T1 to a twenty-third transistor T23 and a first capacitor C1 to a third capacitor C3. The first transistor T1 to the twenty-third transistor T23 are all N-type transistors.

[0053] The third embodiment differs from the first embodiment in that the third embodiment uses N-type transistors, and accordingly, the power supply connection relationship changes. Specifically, the stage transmission signal output unit 101 includes first to twelfth transistors T1 to T12, and a first capacitor C1 and a second capacitor C2. The gate drive signal output unit 102 includes thirteenth to seventeenth transistors T13 to T17 and a third capacitor C3. The light emission control signal output unit 103 includes eighteenth to twenty-third transistors T18 to T23.

[0054] In the third embodiment, the source of the fifth transistor T5 is electrically connected to the low-level power input terminal VGL, the source of the sixth transistor T6 is electrically connected to the low-level power input terminal VGL, the gate of the seventh transistor T7 is electrically connected to the high-level power input terminal VGH, the source of the eighth transistor T8 is electrically connected to the high-level power input terminal VGH, the source of the tenth transistor T10 is electrically connected to the low-level power input terminal VGL, the source of the twelfth transistor T12 is electrically connected to the low-level power input terminal VGL, the source of the fifteenth transistor T15 is electrically connected to the low-level power input terminal VGL, the source of the sixteenth transistor T16 is electrically connected to the low-level power input terminal VGL, and the source of the seventeenth transistor T17 is electrically connected to the low-level power input terminal VGL. The gate of the eighteenth transistor T18 is electrically connected to the high-level power input terminal VGH, the source of the eighteenth transistor T18 is electrically connected to the high-level power input terminal VGH, the gate of the nineteenth transistor T19 is electrically connected to the high-level power input terminal VGH, the source of the nineteenth transistor T19 is electrically connected to the high-level power input terminal VGH, the source of the twentieth transistor T20 is electrically connected to the low-level power input terminal VGL, the source of the twenty-first transistor T21 is electrically connected to the low-level power input terminal VGL, the source of the twenty-second transistor T22 is electrically connected to the low-level power input terminal VGL, and the source of the twenty-third transistor T23 is electrically connected to the high-level power input terminal VGH. One plate of the first capacitor C1 is electrically connected to the low-level power input terminal VGL, and one plate of the second capacitor C2 is electrically connected to the low-level power input terminal VGL.

[0055] Fourth embodiment like Figure 6 As shown, the i-th stage gate driver sub-circuit in the multi-stage gate driver sub-circuit includes first to tenth transistors T1 to T10, thirteenth to twenty-third transistors T13 to T23, and first to third capacitors C1 to C3. The first to tenth transistors T10 and the thirteenth to twenty-third transistors T13 to T23 are all N-type transistors.

[0056] The fourth embodiment differs from the third embodiment in that the stage-transmitting signal output unit 101 of the fourth embodiment does not include the eleventh transistor T11 and the twelfth transistor T12. Specifically, the stage-transmitting signal output unit 101 includes first to tenth transistors T10, a first capacitor C1, and a second capacitor C2. The gate drive signal output unit 102 includes thirteenth to seventeenth transistors T13 to T17 and a third capacitor C3. The light-emission control signal output unit 103 includes eighteenth to twenty-third transistors T18 to T23.

[0057] The connection relationship between the transistors and the capacitors in the fourth embodiment is the same as the connection relationship between the corresponding transistors and the capacitors in the third embodiment, except that the eleventh transistor T11 and the twelfth transistor T12 are not included.

[0058] like Figure 7As shown, corresponding to the third embodiment and the fourth embodiment of the present application, in the gate driving circuit of the display device provided by the present application, the first clock signal input terminal CK1 to the fourth clock signal input terminal CK4 sequentially transmit four high-level pulses staggered in time, the fifth clock signal input terminal CKS1 to the eighth clock signal input terminal CKS4 also sequentially transmit four high-level pulses staggered in time, the timing of the high-level pulse of the fifth clock signal input terminal CKS1 is the same as the timing of the high-level pulse of the first clock signal input terminal CK1, the timing of the high-level pulse of the sixth clock signal input terminal CKS2 is the same as the timing of the high-level pulse of the second clock signal input terminal CK2, the timing of the high-level pulse of the seventh clock signal input terminal CKS3 is the same as the timing of the high-level pulse of the third clock signal input terminal CK3, the timing of the high-level pulse of the eighth clock signal input terminal CKS4 is the same as the timing of the high-level pulse of the fourth clock signal input terminal CK4, the starting stage transmission signal input terminal ST0 to the second stage transmission signal input terminal ST2 sequentially transmit three high-level pulses staggered in time, the high level pulse of the starting stage transmission signal input terminal ST0 is the same as the timing of the high level pulse of the first clock signal input terminal CK1, the timing of the high level pulse of the sixth clock signal input terminal CKS2 is the same as the timing of the high level pulse of the second clock signal input terminal CK2, the timing of the high level pulse of the seventh clock signal input terminal CKS3 is the same as the timing of the high level pulse of the third clock signal input terminal CK3, the timing of the high level pulse of the eighth clock signal input terminal CKS4 is the same as the timing of the high level pulse of the fourth clock signal input terminal CK4, the starting stage transmission signal input terminal ST0 to the second stage transmission signal input terminal ST2 sequentially transmit three high level pulses staggered in time, The timing of the high-level pulse is the same as the timing of the high-level pulse of the fourth clock signal input terminal CK4, the timing of the high-level pulse of the first-level signal input terminal ST1 is the same as the timing of the high-level pulse of the first clock signal input terminal CK1, the timing of the high-level pulse of the second-level signal input terminal ST2 is the same as the timing of the high-level pulse of the second clock signal input terminal CK2, the starting gate drive signal input terminal Gout0 to the second gate drive signal input terminal Gout2 sequentially transmit three high-level pulses staggered in time, the timing of the high-level pulse of the starting gate drive signal input terminal Gout0 is the same as the timing of the high-level pulse of the eighth clock signal input terminal CKS4, the timing of the high-level pulse of the first gate drive signal input terminal Gout1 is the same as the timing of the high-level pulse of the fifth clock signal input terminal CKS1, the timing of the high-level pulse of the second gate drive signal input terminal Gout2 is the same as the timing of the high-level pulse of the sixth clock signal input terminal CKS2, and the first light-emitting control signal input terminal EM1 to the second light-emitting control signal input terminal EM2 sequentially transmit two high-level pulses that partially overlap in time.

[0059] Through the above technical solution, the gate drive circuit of the present application integrates a level transmission signal output unit 101, at least one gate drive signal output unit 102, and at least one light-emitting control signal output unit 103 into a single gate drive subcircuit, and these units share some transistors and nodes, thereby reducing the overall occupied area of ​​the gate drive circuit, facilitating the realization of a narrow bezel for the display panel while improving display uniformity. The level transmission signal output unit 101, at least one gate drive signal output unit 102, and at least one light-emitting control signal output unit 103 achieve circuit integration by sharing a first node Q1. The at least one level transmission signal output unit 101 and at least one gate drive signal output unit 102 further reduce circuit complexity and occupied area by sharing a third node P1 and a fourth node Q2.

[0060] The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be understood as limiting the scope of protection of the present application.

Claims

1. A display device, characterized in that: The display device includes a plurality of pixels and at least one gate driving circuit, wherein the plurality of pixels are arranged in rows and columns, the gate driving circuit includes a plurality of cascaded gate driving sub-circuits, wherein a first-stage gate driving sub-circuit is electrically connected to the plurality of pixels, and an i-th-stage gate driving sub-circuit in the plurality of stages of the gate driving sub-circuit includes a stage transmission signal output unit, at least one gate driving signal output unit, and at least one light emission control signal output unit, where i is a positive integer; wherein one of the level transmission signal output units, at least one of the gate drive signal output units, and at least one of the light-emitting control signal output units are electrically connected to a first node, and one of the level transmission signal output units and at least one of the gate drive signal output units are further electrically connected to a third node and a fourth node; The stage transfer signal output unit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor, and the first node is a node to which the first transistor, the second transistor, the fifth transistor, the sixth transistor and the seventh transistor are electrically connected; The gate drive signal output unit includes a thirteenth transistor and a fifteenth transistor, the third node is a node where the fifteenth transistor is electrically connected to the fifth transistor, the eighth transistor, and the tenth transistor, and the fourth node is a node where the thirteenth transistor is electrically connected to the seventh transistor and the ninth transistor.

2. The display device according to claim 1, wherein The level-transmission signal output unit further includes a third transistor, a fourth transistor, a first capacitor and a second capacitor, or the level-transmission signal output unit further includes a third transistor, a fourth transistor, an eleventh transistor, a twelfth transistor, a first capacitor and a second capacitor; The gate drive signal output unit further includes a fourteenth transistor, a sixteenth transistor, a seventeenth transistor and a third capacitor; The light emitting control signal output unit includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, a twenty-first transistor, a twenty-second transistor and a twenty-third transistor; The first to tenth transistors and the thirteenth to twenty-third transistors are all P-type transistors or all N-type transistors, or the first to twenty-third transistors are all P-type transistors or all N-type transistors.

3. The display device according to claim 2, wherein: The gate of the thirteenth transistor is electrically connected to the gate drive signal output terminal of the ia-th level gate drive sub-circuit, the source of the thirteenth transistor is electrically connected to the fourth node, the drain of the thirteenth transistor is electrically connected to the fifth node, the gate of the fourteenth transistor is electrically connected to the fifth node, the source of the fourteenth transistor is electrically connected to the gate drive source signal input terminal, the drain of the fourteenth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, the gate of the fifteenth transistor is electrically connected to the third node, the drain of the fifteenth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, the gate of the sixteenth transistor is electrically connected to the sixth node, the drain of the sixteenth transistor is electrically connected to the fifth node, the gate of the seventeenth transistor is electrically connected to the sixth node, the drain of the seventeenth transistor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, one plate of the third capacitor is electrically connected to the gate drive signal output terminal of the gate drive signal output unit, and the other plate of the third capacitor is electrically connected to the fifth node. a is a positive integer.

4. The display device according to claim 3, wherein: In the case where the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are all P-type transistors, the source of the fifteenth transistor is electrically connected to the high-level power input terminal, the source of the sixteenth transistor is electrically connected to the high-level power input terminal, and the source of the seventeenth transistor is electrically connected to the high-level power input terminal; When the fifteenth transistor, the sixteenth transistor and the seventeenth transistor are all N-type transistors, the source of the fifteenth transistor is electrically connected to the low-level power input terminal, the source of the sixteenth transistor is electrically connected to the low-level power input terminal, and the source of the seventeenth transistor is electrically connected to the low-level power input terminal.

5. The display device according to claim 2, wherein The gate of the 20th transistor is electrically connected to the first node, the drain of the 20th transistor is electrically connected to the drain of the 18th transistor, the gate of the 21st transistor is electrically connected to the drain of the 18th transistor, the drain of the 21st transistor is electrically connected to the drain of the 19th transistor, the gate of the 22nd transistor is electrically connected to the drain of the 18th transistor, the drain of the 22nd transistor is electrically connected to the light-emitting control signal output terminal of the light-emitting control signal output unit, the gate of the 23rd transistor is electrically connected to the drain of the 19th transistor, and the drain of the 23rd transistor is electrically connected to the light-emitting control signal output terminal of the light-emitting control signal output unit.

6. The display device according to claim 5, wherein: In the case where the eighteenth to twenty-third transistors are all P-type transistors, the gate and source of the eighteenth transistor are both electrically connected to the low-level power input terminal, the gate and source of the nineteenth transistor are both electrically connected to the low-level power input terminal, the source of the twentieth transistor is electrically connected to the high-level power input terminal, the source of the twenty-first transistor is electrically connected to the high-level power input terminal, the source of the twenty-second transistor is electrically connected to the high-level power input terminal, and the source of the twenty-third transistor is electrically connected to the low-level power input terminal; In the case where the eighteenth to twenty-third transistors are all N-type transistors, the gate and source of the eighteenth transistor are both electrically connected to the high-level power input terminal, the gate and source of the nineteenth transistor are both electrically connected to the high-level power input terminal, the source of the twentieth transistor is electrically connected to the low-level power input terminal, the source of the twenty-first transistor is electrically connected to the low-level power input terminal, the source of the twenty-second transistor is electrically connected to the low-level power input terminal, and the source of the twenty-third transistor is electrically connected to the high-level power input terminal.

7. The display device according to claim 2, wherein: The gate of the first transistor is electrically connected to the stage transmission signal output terminal of the ib-th stage gate driving sub-circuit, the source of the first transistor is electrically connected to the first control signal input terminal, the drain of the first transistor is electrically connected to the first node, the gate of the second transistor is electrically connected to the stage transmission signal output terminal of the i+c-th stage gate driving sub-circuit, the source of the second transistor is electrically connected to the second control signal input terminal, the drain of the second transistor is electrically connected to the first node, the gate of the third transistor is electrically connected to the first control signal input terminal, the source of the third transistor is electrically connected to the first clock signal input terminal, and the drain of the third transistor is electrically connected to the second node, the gate of the fourth transistor is electrically connected to the second control signal input terminal, the source of the fourth transistor is electrically connected to the second clock signal input terminal, and the drain of the fourth transistor is electrically connected to the second node, the gate of the fifth transistor is electrically connected to the third node, and the fifth transistor is electrically connected to the third node. a drain of the transistor is electrically connected to the first node, a gate of the sixth transistor is electrically connected to the first node, a drain of the sixth transistor is electrically connected to the third node, a source of the seventh transistor is electrically connected to the first node, a drain of the seventh transistor is electrically connected to the fourth node, a gate of the eighth transistor is electrically connected to the second node, a drain of the eighth transistor is electrically connected to the third node, a gate of the ninth transistor is electrically connected to the fourth node, a source of the ninth transistor is electrically connected to the third clock signal input terminal, a drain of the ninth transistor is electrically connected to the stage-pass signal output terminal of the stage-pass signal output unit, a gate of the tenth transistor is electrically connected to the third node, a drain of the tenth transistor is electrically connected to the stage-pass signal output terminal of the stage-pass signal output unit, a plate of the first capacitor is electrically connected to the first node, and a plate of the second capacitor is electrically connected to the third node. b and c are both positive integers.

8. The display device according to claim 7, wherein: In the case where the first to tenth transistors are all P-type transistors, the source of the fifth transistor is electrically connected to the high-level power input terminal, the source of the sixth transistor is electrically connected to the high-level power input terminal, the gate of the seventh transistor is electrically connected to the low-level power input terminal, the source of the eighth transistor is electrically connected to the low-level power input terminal, the source of the tenth transistor is electrically connected to the high-level power input terminal, the source of the twelfth transistor is electrically connected to the high-level power input terminal, the other plate of the first capacitor is electrically connected to the high-level power input terminal, and the other plate of the second capacitor is electrically connected to the high-level power input terminal; In the case where the first transistor to the tenth transistor are all N-type transistors, the source of the fifth transistor is electrically connected to the low-level power input terminal, the source of the sixth transistor is electrically connected to the low-level power input terminal, the gate of the seventh transistor is electrically connected to the high-level power input terminal, the source of the eighth transistor is electrically connected to the high-level power input terminal, the source of the tenth transistor is electrically connected to the low-level power input terminal, the source of the twelfth transistor is electrically connected to the low-level power input terminal, the other plate of the first capacitor is electrically connected to the low-level power input terminal, and the other plate of the second capacitor is electrically connected to the low-level power input terminal.

9. The display device according to claim 7, wherein: The gate of the eleventh transistor is electrically connected to the level transfer control signal input terminal, the source of the eleventh transistor is electrically connected to the level transfer control signal input terminal, the drain of the eleventh transistor is electrically connected to the level transfer signal output terminal of the level transfer signal output unit, the gate of the twelfth transistor is electrically connected to the level transfer control signal input terminal, and the drain of the twelfth transistor is electrically connected to the third node.

10. The display device according to claim 9, wherein In the case where the twelfth transistor is a P-type transistor, the source of the twelfth transistor is electrically connected to the high-level power input terminal; In the case that the twelfth transistor is an N-type transistor, the source of the twelfth transistor is electrically connected to the low-level power input terminal.

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