Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel is composed of a plurality of pixel units, a plurality of data lines, a plurality of gate lines and a gate drive circuit. Wherein the pixel units are arranged in an array mode, the pixel units in each pixel row have the same color, the pixel units in the same pixel column have different colors, and the pixel units are arranged in an alternating mode. In addition, each data line is connected with the pixel units in at least one pixel column and used for transmitting data signals. And each gate line is connected with the pixel unit in one pixel row and is used for transmitting a scanning signal. The gate drive circuit provides the same scanning signal for at least two pixel rows with the same color at the same time in a refresh cycle of the display panel. Therefore, the pixel units in the at least two pixel rows with the same color can be turned on at the same time, so that the cost can be reduced, and the refresh rate can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the rapid development of the display panel industry, in order to maintain their advantages in the highly competitive market, major display panel manufacturers are still constantly exploring methods that can both reduce production costs and increase the refresh rate of display panels to meet consumers' demand for high-quality display effects.

[0003] To this end, the industry continues to explore various methods, such as using low-cost materials, simplifying process flows, and launching new panel designs. Among them, the Trigate (three-gate line) pixel architecture design is widely favored by many panel manufacturers because it can achieve extreme cost reduction. Compared with the original 1G1D (single-gate line) design, this architecture triples the number of gate drive rows by allowing the Data signal to connect to more pixels, and the number of data signal columns is reduced to one-third of the original, thereby reducing the number of data ICs and achieving the purpose of cost reduction. At the same time, consumers' requirements for display quality are increasing, and high refresh rate is also an important indicator that display panels need to take into account in order to provide a smoother and clearer visual experience and meet the needs of consumers in scenarios such as e-sports and high-definition video playback.

[0004] Therefore, achieving a panel design that can achieve both extreme cost reduction and high refresh rate has become a critical issue that the industry urgently needs to address. However, while the existing Trigate pixel architecture excels in cost control, it has certain limitations in compatibility with high refresh rates. Summary of the Invention

[0005] The embodiments of the present application provide a display panel and a display device, which can reduce production costs while improving the refresh rate of the display panel.

[0006] In a first aspect, an embodiment of the present application provides a display panel, comprising: a plurality of pixel units arranged in an array; the pixel units arranged along a first direction are defined as pixel rows; the pixel units in the same pixel row have the same color; the pixel units arranged along a second direction are defined as pixel columns; the pixel units in the same pixel column have different colors, and the pixel units of different colors are arranged alternately; a plurality of data lines arranged along the first direction; each data line is connected to the pixel units in at least one pixel column for transmitting data signals; a plurality of gate lines arranged along the second direction; each gate line is connected to the pixel units in a pixel row for transmitting scan signals; and a gate drive circuit for providing the same scan signal to at least two pixel rows of the same color at the same time within a refresh cycle of the display panel, so as to turn on the pixel units in the at least two pixel rows of the same color at the same time, and transmit the data signal to the pixel units in the at least two pixel rows of the same color through the corresponding data lines.

[0007] In a second aspect, an embodiment of the present application further provides a display device, comprising: a display panel as described in any one of the above items and a timing controller, wherein the timing controller is used to receive an image signal and generate a driving signal for driving the display panel based on the image signal; the driving signal includes at least one of a data signal and a clock signal.

[0008] The display panel provided by the embodiment of the present application adopts a Trigate pixel architecture design, in which the pixel cells in the same pixel row have the same color, the pixel cells in the same pixel column have different colors, and each data line is connected to the pixel cells in at least one pixel column, and each gate line is connected to the pixel cells in a pixel row. This can effectively reduce the number of source driver chips used to drive data signal transmission, thereby reducing costs. At the same time, the gate driver circuit included in the display panel provided by the embodiment of the present application can simultaneously activate the pixel cells in at least two pixel rows of the same color, thereby shortening the refresh cycle and significantly improving the refresh rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0010] Figure 1 This is a structural block diagram of the display panel provided in an embodiment of the present application.

[0011] Figure 2The exemplary embodiment of the present application provides a connection relationship between gate lines, data lines and pixel units in a display panel.

[0012] Figure 3 This is an exemplary circuit diagram of a gate driving unit included in a gate driving circuit included in a display panel provided in an embodiment of the present application.

[0013] Figure 4 Schematic diagram of the connection relationship between the gate driving unit and the pixel unit in the Trigate pixel architecture provided in an embodiment of the present application.

[0014] Figure 5 A timing diagram for simultaneously turning on pixel units in two rows of pixels of the same color provided in an embodiment of the present application.

[0015] Figure 6 A timing diagram of an exemplary clock signal provided in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making any creative efforts shall fall within the scope of protection of this application.

[0017] The terms "first," "second," and the like in this application are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or modules is not limited to the listed steps or modules, but may optionally include steps or modules not listed, or may optionally include other steps or modules inherent to the process, method, product, or apparatus.

[0018] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0019] As mentioned above, in order to maintain their advantage in the highly competitive market, major display panel manufacturers need display panels that can reduce production costs while increasing refresh rates.

[0020] Based on this, the embodiment of the present application provides a display panel that can reduce production costs while increasing refresh rate. Figure 1 As shown, the display panel 100 may include a pixel unit array 10, a plurality of gate lines 20, a plurality of data lines 30 and a gate driving circuit 40. The pixel unit array 10 may include a plurality of pixel units, and these pixel units are arranged in an array and arranged along a first direction (exemplarily as Figure 2 The pixel units 201 arranged in the horizontal direction (shown in FIG. 1 ) can be defined as pixel rows, and the pixel units 201 arranged in the second direction (exemplarily as FIG. Figure 2 The pixel units arranged in the longitudinal direction (as shown) can be defined as pixel columns. The pixel units in the same pixel row have the same color, the pixel units in the same pixel column have different colors, and the pixel units of different colors are alternately arranged along the second direction.

[0021] For an understanding of the arrangement of the above-mentioned multiple pixel units, please refer to the following example: Figure 2 As shown, the pixel unit array 10 may include a plurality of pixel units 201, and the plurality of pixel units 201 include red (R) pixel units, green (G) pixel units, and blue (B) pixel units. The red pixel units, the green pixel units, and the blue pixel units are alternately arranged in sequence along the second direction to form a plurality of pixel columns, such as a pixel column connected to the data line D1 (30), a pixel column connected to the data line D2 (30), and so on. Pixel units of the same color among the red pixel units, the green pixel units, and the blue pixel units are arranged along the first direction to form a plurality of pixel rows, such as a red pixel row connected to the gate line G1 (20), a green pixel row connected to the gate line G2 (20), a blue pixel row connected to the gate line G3 (20), and so on.

[0022] See also Figure 1 As shown, the plurality of gate lines in the display panel 100 are arranged along the second direction, and each gate line is connected to a pixel unit in a pixel row for transmitting a scan signal. The plurality of data lines in the display panel 100 are arranged along the first direction, and each data line is connected to the pixel unit in at least one pixel column for transmitting a data signal. For example, Figure 2 As shown, the plurality of gate lines 20 may exemplarily include gate line G1 (20), gate line G2 (20), ..., gate line Gn (20). The plurality of data lines 30 may exemplarily include data line D1 (30), data line D2 (30), ..., data line Dm (30). Figure 2The pixel architecture shown can be called a Trigate pixel architecture. Since the data lines need to be connected to a relatively expensive source driver chip (source IC) to transmit data signals to the pixel units, the cost will inevitably increase when there are more data lines. Figure 2 In the Trigate pixel architecture, the number of data lines is smaller than the number of gate lines. This design can reduce the number of source ICs by multiplexing data lines, achieving an ultimate cost reduction.

[0023] See also Figure 1 As shown, the gate driving circuit 40 of the display panel 100 may include a plurality of cascaded gate driving units; each gate driving unit is connected to at least one of the gate lines for providing the scanning signal. In an optional embodiment, each gate driving unit is connected to a gate line, such as Figure 2 As shown, the gate line G1 (20), the gate line G2 (20), ..., the gate line Gn (20) are respectively connected by a gate driving unit.

[0024] Based on the above pixel architecture, in order to improve the refresh rate of the display panel 100, the embodiment of the present application also provides a scanning method for pixel units. Specifically, the gate drive circuit 40 of the display panel 100 can be used to provide the same scanning signal to at least two pixel rows of the same color at the same time within a refresh cycle of the display panel, so as to turn on the pixel units in the at least two pixel rows of the same color at the same time, and transmit the data signal to the pixel units in the at least two pixel rows of the same color through the corresponding data lines; it can also be used to alternately provide the scanning signal to pixel rows of different colors to alternately turn on pixel rows of different colors. In other words, the driving method provided by the embodiment of the present application can be that the gate drive circuit 40 turns on all the pixel units in at least two pixel rows of the same color at the same time within the refresh cycle, and turns on pixel rows of different colors alternately along the longitudinal direction. It should be noted that the refresh cycle can refer to the time required to complete a frame of image display, that is, the duration of each frame of image display. In layman's terms, the time required to display a frame of image can be the time required to scan all pixel rows of the display panel 100. Since the total number of pixel rows included in the display panel 100 is certain when the display panel is manufactured to form a product, according to the scanning method provided in the embodiment of the present application, two or more pixel rows are scanned at the same time, and the time taken to scan all the pixel rows of the display panel 100 will be shortened, that is, the refresh cycle will be shortened. Since the refresh rate is the inverse of the refresh cycle, the refresh rate of the display panel will increase, thereby improving the refresh rate of the display panel.

[0025] For example, it is assumed that the gate driving circuit provides the scanning signal to two adjacent pixel rows of the same color at the same time in the refresh cycle. Figure 2 The pixel rows connected to the gate line G1 (20) and the pixel rows connected to the gate line G4 (20) shown can be defined as two adjacent pixel rows of the same color. Based on this, the pixel rows connected to the gate line G2 (20) and the pixel rows connected to the gate line G5 (20) are also two adjacent pixel rows of the same color, and so on. At the same time in the refresh cycle, providing the scanning signal to the two adjacent pixel rows of the same color is exemplarily to simultaneously turn on the pixel rows connected to the gate line G1 (20) and the pixel rows connected to the gate line G4 (20), and simultaneously turn on the pixel rows connected to the gate line G2 (20) and the pixel rows connected to the gate line G5 (20), and so on. Based on this, as Figure 2 The display panel with the Trigate pixel architecture shown can be scanned from top to bottom (e.g., in a forward scan order): pixel row 1 & pixel row 4 → pixel row 2 & pixel row 5 → pixel row 3 & pixel row 6 → pixel row 7 & pixel row 10 → ...; or, from bottom to top (e.g., in a reverse scan order): pixel row n & pixel row n-3 → pixel row n-1 & pixel row n-4 → .... This scanning method can halve the pixel row scanning time, shortening the display time of each frame (i.e., shortening the refresh cycle), thereby improving the refresh rate of the display panel.

[0026] To understand the scanning method provided by the embodiment of the present application under the above pixel architecture, see Figure 3 , which shows a circuit diagram of the gate driving unit of the Nth stage in the gate driving circuit. Figure 4 , which shows Figure 3 Schematic diagram of the connection relationship between the gate driving unit and the pixel unit in the Trigate pixel architecture. Figure 5 As shown, it shows an implementation sequence of the scanning method provided in the embodiment of the present application. It should be noted that, Figures 3 to 5 The gate driving unit and driving timing shown can realize turning on two adjacent pixel rows of the same color at the same time during the refresh cycle.

[0027] Specifically, if Figure 3As shown, the gate driving unit may include: a first transistor T11, a second transistor T21, a third transistor T41, a fourth transistor T31, a fifth transistor T22, a transistor T44, a transistor T51, a transistor T52, a transistor T53, a transistor T54, a transistor T72, a transistor T32, a transistor T42, a transistor T43, a transistor T33, a transistor T73, a transistor T63, a transistor T64, a transistor T61, a transistor T62 and a capacitor C bt .

[0028] The first electrode of the first transistor T11 is connected to the first output terminal of the gate driver unit of the preceding X stages for outputting the scan signal, the second electrode of the first transistor T11 is connected to the pull-up node Q, and the control electrode of the first transistor T11 is connected to the second output terminal of the gate driver unit of the preceding X stages for outputting the stage signal. The first electrode of the second transistor T21 is connected to the clock line CK for transmitting the clock signal, the second electrode of the second transistor T21 is connected to the first output terminal of the gate driver unit of the current stage, and the control electrode of the second transistor T21 is connected to the pull-up node Q. The first electrode of the third transistor T41 is connected to the pull-up node Q, the second electrode of the third transistor T41 is connected to the first power line for transmitting the first power supply voltage VSSQ, and the control electrode of the third transistor T41 is connected to the second output terminal of the gate driver unit of the next X stages. The first electrode of the fourth transistor T31 is connected to the first output terminal of the gate driver unit of the current stage, the second electrode of the fourth transistor T31 is connected to the second power line VSSG for transmitting the second power supply voltage, and the control electrode of the fourth transistor T31 is connected to the second output terminal of the gate driver unit of the next X stages. The first electrode of the fifth transistor T22 is connected to the clock line, the first electrode of the fifth transistor T22 is connected to the second output end of the gate driving unit at this stage, and the control electrode of the fifth transistor T22 is connected to the pull-up node Q.

[0029] The control electrode and first electrode of transistor T51 are connected to a first low-frequency clock line for transmitting a first low-frequency clock signal LC1. The second electrode of transistor T51 is connected to the first electrode of transistor T52 and the control electrode of transistor T53, respectively. The second electrode of transistor T52 is connected to the first power line, and the control electrode of transistor T52 is connected to a pull-up node Q. The first electrode of transistor T53 is connected to the first low-frequency clock line, and the second electrode of transistor T53 is connected to a first node P. The first electrode of transistor T54 is connected to the first node P, the second electrode of transistor T54 is connected to the first power line, and the control electrode of transistor T54 is connected to the pull-up node Q. The first electrode of transistor T72 is connected to the second output terminal of the current-stage gate driver unit, the second electrode of transistor T72 is connected to the first power line, and the control electrode of transistor T72 is connected to the first node P. The first electrode of transistor T32 is connected to the first output terminal of the current-stage gate driver unit, the second electrode of transistor T32 is connected to the second power line, and the control terminal of transistor T32 is connected to the first node P. A first electrode of transistor T42 is connected to the pull-up node Q, a second electrode of transistor T42 is connected to the first power line, and a control terminal of transistor T42 is connected to the first node P. A first electrode of transistor T43 is connected to the pull-up node Q, a second electrode of transistor T43 is connected to the first power line, and a control terminal of transistor T43 is connected to a second node H. A first electrode of transistor T33 is connected to the first output terminal of the gate drive unit of this stage, a second electrode of transistor T33 is connected to the second power line, and a control terminal of transistor T33 is connected to the second node H. A first electrode of transistor T73 is connected to the second output terminal of the gate drive unit of this stage, a second electrode of transistor T73 is connected to the first power line, and a control terminal of transistor T73 is connected to the second node H. A first electrode of transistor T63 is connected to a second low-frequency clock line for transmitting a second low-frequency clock signal LC2, and a second electrode of transistor T63 is connected to the second node H. A first electrode of transistor T64 is connected to the second node H, a second electrode of transistor T64 is connected to the first power line, and a control terminal of transistor T64 is connected to the pull-up node Q. The first electrode and control electrode of transistor T61 are connected to the second low-frequency clock line, and the second electrode of transistor T61 is connected to the first electrode of transistor T62. The second electrode of transistor T62 is connected to the first power line, and the control electrode of transistor T62 is connected to the pull-up node Q. Capacitor C bt The first output terminal of the gate driving unit is connected to the pull-up node Q and the first output terminal of the gate driving unit of this stage.

[0030] It should be noted that the first transistor T11, the second transistor T21, the third transistor T41 and the fourth transistor T31 can be thin film transistors, wherein the active layer of the thin film transistor includes an amorphous silicon material or an oxide material. The remaining transistors can also be thin film transistors whose active layers include an amorphous silicon material or an oxide material. The active layer (ActiveLayer) mentioned here can refer to the semiconductor layer located between the source (Source) and the drain (Drain) in the transistor, and its core function is to form a conductive channel and control the on and off of the current through the gate (Gate) voltage. Furthermore, Figure 3 The transistor of the gate driving unit shown may be an N-type transistor, which may be turned on at a high level and turned off at a low level.

[0031] in, Figure 3 The gate driving unit shown is only an exemplary circuit structure for implementing the scanning method provided in the embodiment of the present application. Figure 3 The first transistor T11, second transistor T21, and third transistor T41 in the gate driver unit shown are essential for normal operation. The remaining transistors can be selectively omitted based on actual design requirements without affecting the normal operation of the GOA. The basic operating principle of the gate driver unit can be as follows: when the level transmission signal output by the gate driver unit of the previous X stages is at an active level, the first transistor T11 turns on, and the scan signal output by the gate driver unit of the previous X stages is transmitted to the pull-up node Q. The second transistor T21 turns on, and the clock signal is output from the first output terminal of the gate driver unit of the current stage as the scan signal of the gate driver unit of the current stage. When the level transmission signal output by the gate driver unit of the next X stages is at an active level, the third transistor T41 and the fourth transistor T31 turn on, and the first power supply voltage VSSQ is transmitted to the pull-up node Q. The second transistor T21 turns off according to the first power supply voltage VSSQ, and the second power supply voltage is transmitted to the first output terminal of the gate driver unit of the current stage, thereby pulling down the potential of the first output terminal of the gate driver unit of the current stage, where X is an integer greater than 0. When the stage transmission signal output by the gate driving unit of the previous X stages is at an effective level, the fifth transistor T22 outputs the stage transmission signal of the gate driving unit of the current stage according to the voltage of the pull-up node Q.

[0032] See also Figure 4 As shown, the gate driving circuit 40 provided in the embodiment of the present application may include a plurality of cascaded gate driving units connected by a stage transmission line for transmitting a stage transmission signal ST, and one gate driving unit is connected to each pixel unit in a pixel row through a gate line. Figure 4The connection relationship between the gate driving unit and the six pixel rows is shown only as an example. Figure 4 D1 and D2 are data lines, and G1, G2, G3, G4, G5, and G6 are gate lines.

[0033] Based on this, in order to realize the aforementioned scanning mode of simultaneously opening two adjacent pixel rows of the same color and alternately opening pixel rows of different colors, see Figure 5 In the scanning timing shown, at the same time in the refresh cycle, the gate drive units connected to two pixel rows of the same color output the same scanning signal to turn on the pixel units in the two pixel rows of the same color at the same time. The scanning signals output by the gate drive units connected to pixel rows of different colors have a certain delay in sequence. It should be noted that Figure 5 The scan timing shown is also only an exemplary description and is not intended to limit the present application. Figure 5 As shown, pixel rows 1 and 4 are turned on at the same time by G1 and G4 outputted from the first output terminal of the corresponding gate driving unit, respectively. Pixel rows 2 and 5 are turned on at the same time by G2 and G5 outputted from the first output terminal of the corresponding gate driving unit, respectively. Pixel rows 3 and 6 are turned on at the same time by G3 and G6 outputted from the first output terminal of the corresponding gate driving unit, respectively.

[0034] As described above, when the level-transmitting signal output by the gate driver unit of the previous X stages is at an active level, the first transistor T11 turns on, and the scan signal output by the gate driver unit of the previous X stages is transmitted to the pull-up node Q. When the second transistor T21 turns on, the clock signal is output from the first output terminal of the gate driver unit of the current stage as the scan signal for the gate driver unit of the current stage. In other words, the output waveform of the first output terminal of the gate driver unit is related to the clock signal. To achieve the same signal output from the first output terminals of different gate driver units, these gate driver units can simply be connected to the same clock signal.

[0035] As an example, in the embodiment of the present application, if the gate drive circuit 40 adopts Figure 6 The 12 independent clock signals shown in FIG. 1 are used to drive the display panel in a time-sharing manner. If the display panel 100 includes 12 pixel rows, Figure 5 The G1 shown may correspond to CK1, G2 to CK2, G3 to CK3, G4 to CK4, G5 to CK5, and G6 to CK6. CK7 to CK12 correspond to the subsequent G7 to G12 ( Figure 5(not shown). If the display panel 100 includes a plurality of 12 pixel rows, then the subsequent pixel rows can reuse the previous clock signal. For example, the 13th pixel row can use the CK1 corresponding to the first pixel row, and so on. It should be known that Figure 5 and Figure 6 This is only an exemplary illustration of the corresponding relationship between the two signals and does not reflect the actual effective width of the two signals.

[0036] It should be noted that based on Figure 3 and Figure 4 In the circuit diagram shown, in order to realize the aforementioned scanning order of pixel row 1 & pixel row 4 → pixel row 2 & pixel row 5 → pixel row 3 & pixel row 6 → pixel row 7 & pixel row 10 → ..., X can be set to 6. Figure 2 In the Trigate pixel architecture shown, the pixel rows along the second direction are alternately R pixel rows, G pixel rows, and B pixel rows, and the scanning order is also alternately turned on by R pixel rows, G pixel rows, and B pixel rows. Therefore, after pixel rows 3 and 6 are turned on at the same time, the turning on of pixel rows 7 and 10 depends on the level transmission signal ST(1) of pixel row 1 and the level transmission signal ST(4) of pixel row 4, respectively. Figure 3 and Figure 5 The gate drive unit and scanning timing shown, ST(1) and ST(4) waveforms are also the same, so pixel rows 7 and 10 can be turned on at the same time. Similarly, the above logic can be used to analyze other pixel rows to be turned on simultaneously.

[0037] The display panel provided in the embodiment of the present application can reduce costs and improve refresh rate by adopting a Trigate pixel architecture and simultaneously turning on the pixel units in at least two pixel rows of the same color.

[0038] Based on the same inventive concept, an embodiment of the present application also provides a display device that may include a display panel 100 as described in any one of the above items and a timing controller, wherein the timing controller is used to receive an image signal and generate a driving signal for driving the display panel to display according to the image signal; the driving signal may include at least one of a data signal and a clock signal.

[0039] It should be noted that the display panel 100 included in the display device has been described in detail above and will not be repeated here.

[0040] The display device and driving method thereof provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel units arranged in an array; The pixel units arranged along the first direction are defined as pixel rows; The pixel units in the same pixel row have the same color; the pixel units arranged along the second direction are defined as a pixel column; the pixel units in the same pixel column have different colors, and the pixel units of different colors are arranged alternately; a plurality of data lines arranged along the first direction; each data line being connected to the pixel units in at least one pixel column for transmitting data signals; a plurality of gate lines arranged along the second direction; each gate line is connected to a pixel unit in a pixel row and is used to transmit a scanning signal; as well as A gate drive circuit is used to provide the same scanning signal to at least two pixel rows of the same color at the same time within a refresh cycle of the display panel, so as to turn on the pixel units in the at least two pixel rows of the same color at the same time, and transmit the data signal to the pixel units in the at least two pixel rows of the same color through the corresponding data lines.

2. The display panel according to claim 1, wherein: The gate driving circuit is further configured to alternately provide the scanning signals to pixel rows of different colors during the refresh period, so as to alternately turn on the pixel rows of different colors.

3. The display panel according to claim 2, wherein: The gate driving circuit is further configured to provide the scanning signal to two adjacent pixel rows of the same color at the same time within the refresh period.

4. The display panel according to claim 1, wherein: The number of the data lines is smaller than the number of the gate lines.

5. The display panel according to claim 3, wherein: The plurality of pixel units include a red pixel unit, a green pixel unit, and a blue pixel unit, and the red pixel unit, the green pixel unit, and the blue pixel unit are alternately arranged in sequence along the second direction.

6. The display panel according to claim 5, wherein: The gate driving circuit includes a plurality of cascaded gate driving units; each gate driving unit is connected to at least one gate line and is used to provide the scanning signal; Wherein, at the same time in the refresh period, the gate driving units connected to two pixel rows of the same color output the same scanning signal to turn on the pixel units in the two pixel rows of the same color at the same time.

7. The display panel according to claim 6, wherein: The gate driving unit includes: a first transistor, a second transistor, a third transistor, and a fourth transistor, wherein the first electrode of the first transistor is connected to the first output terminal of the gate driving unit of the previous X stages for outputting the scanning signal, the second electrode of the first transistor is connected to the pull-up node, and the control electrode of the first transistor is connected to the second output terminal of the gate driving unit of the previous X stages for outputting the stage transmission signal; The first electrode of the second transistor is connected to a clock line for transmitting a clock signal, the second electrode of the second transistor is connected to the first output terminal of the gate driving unit of this stage, and the control electrode of the second transistor is connected to the pull-up node; A first electrode of the third transistor is connected to the pull-up node, a second electrode of the third transistor is connected to a first power line for transmitting a first power supply voltage, and a control electrode of the third transistor is connected to a second output terminal of the gate driving unit of the subsequent X stages; A first electrode of the fourth transistor is connected to the first output terminal of the gate driving unit of the current stage, a second electrode of the fourth transistor is connected to a second power line for transmitting a second power supply voltage, and a control electrode of the fourth transistor is connected to the second output terminal of the gate driving unit of the next X stages; Wherein, when the level transmission signal output by the gate driving unit of the previous X stages is at a valid level, the first transistor is turned on, and the scan signal output by the gate driving unit of the previous X stages is transmitted to the pull-up node; the second transistor is turned on, and the clock signal is output from the first output terminal of the gate driving unit of the current stage as the scan signal of the gate driving unit of the current stage; when the level transmission signal output by the gate driving unit of the next X stages is at a valid level, the third transistor and the fourth transistor are turned on, the first power supply voltage is transmitted to the pull-up node, the second transistor is turned off according to the first power supply voltage, and the second power supply voltage is transmitted to the first output terminal of the gate driving unit of the current stage to pull down the potential of the first output terminal of the gate driving unit of the current stage, and X is an integer greater than 0.

8. The display panel according to claim 7, wherein: The first transistor, the second transistor, the third transistor, and the fourth transistor are thin film transistors, wherein active layers of the thin film transistors include amorphous silicon material or oxide material.

9. The display panel according to claim 7, wherein: The gate driving unit further includes a fifth transistor; a first electrode of the fifth transistor is connected to the clock line, a second electrode of the fifth transistor is connected to the second output end of the gate driving unit of the current stage, and a control electrode of the fifth transistor is connected to the pull-up node, wherein when the level transmission signal output by the gate driving unit of the previous X stages is at a valid level, the fifth transistor outputs the level transmission signal of the gate driving unit of the current stage according to the voltage of the pull-up node.

10. A display device, characterized in that: It comprises a display panel and a timing controller as described in any one of claims 1 to 9, wherein the timing controller is used to receive an image signal and generate a drive signal for driving the display panel to display according to the image signal; the drive signal includes at least one of a data signal and a clock signal.

Images