Display devices and their driving methods, driving circuits, equipment, media and program products

Abstract

This invention provides a display device and its driving method, driving circuit, apparatus, medium, and program product, relating to the field of display technology, for reducing the power consumption of display products. The driving method of the display device includes a display panel, the display panel including a gate driving circuit, and the gate driving circuit including a plurality of cascaded shift register units; a screen refresh cycle of the display device includes an active phase and a blanking phase; the driving method includes: generating a frame rate switching instruction based on pre-stored frame rate switching information; sending a corresponding switching timing driving signal to the gate driving circuit during at least part of the blanking phase according to the frame rate switching instruction; and controlling all or some of the shift register units in the gate driving circuit to output scan signals based on the switching timing driving signal.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display device and its driving method, driving circuit, equipment, medium and program product. Background Technology

[0002] Smartphone screen sizes are getting larger and larger, from 2.0 inches in the feature phone era to 3.5 inches, 4.7 inches, and 5.5 inches in the smartphone era. In the era of full-screen displays, due to designs such as hidden cameras and unlock buttons, screen-to-body ratios have further increased, now concentrated between 6.5 inches and 7 inches. With the continuous increase in screen size and the gradual popularization of high refresh rates, screen power consumption is also increasing. Therefore, how to reduce the power consumption of display products has become a pressing technical problem to be solved. Summary of the Invention

[0003] The purpose of this invention is to provide a display device and its driving method, driving circuit, equipment, medium and program product, for reducing the power consumption of display products.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A first aspect of the present invention provides a driving method for a display device, the display device including a display panel, the display panel including a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units; a screen refresh cycle of the display device including an active phase and a blanking phase; the driving method including:

[0006] Generate frame rate switching instructions based on pre-stored frame rate switching information;

[0007] According to the frame rate switching instruction, during at least part of the blanking phase, a corresponding switching timing drive signal is sent to the gate driving circuit; based on the switching timing drive signal, the plurality of shift register units in the gate driving circuit are controlled to output scan signals or some shift register units output scan signals.

[0008] Optionally, the step of generating a frame rate switching instruction based on pre-stored frame rate switching information specifically includes:

[0009] Based on pre-stored frame rate switching information, a frame rate switching signal is generated during at least part of the blanking phase;

[0010] The step of sending a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase according to the frame frequency switching command specifically includes:

[0011] According to the frame rate switching signal, during at least part of the blanking phase, a corresponding switching timing drive signal is sent to the gate drive circuit.

[0012] Optionally, the step of generating a frame rate switching instruction based on pre-stored frame rate switching information specifically includes:

[0013] Based on the pre-stored frame rate switching information, an enable signal is generated during at least a partially active phase or a blanking phase.

[0014] The step of sending a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase according to the frame frequency switching command specifically includes:

[0015] Based on the enable signal, during at least part of the blanking phase, a corresponding switching timing drive signal is generated;

[0016] According to the switching timing drive signal, all or some of the shift register units in the gate drive circuit are driven to output scan signals.

[0017] Optionally, the plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, wherein the driving frequency of the first part of shift register units is greater than the driving frequency of the second part of shift register units.

[0018] The steps for controlling the output scan signal of a portion of the shift register units in the gate drive circuit specifically include:

[0019] During at least one screen refresh cycle, the first part of the shift register unit is controlled to output a scan signal, while the second part of the shift register unit is controlled not to output a scan signal.

[0020] Optionally, the step of the first part of the shift register unit outputting a scan signal and the second part of the shift register unit not outputting a scan signal specifically includes:

[0021] Send a normal clock signal to the first part of the shift register unit to control the first part of the shift register unit to output a scan signal;

[0022] An invalid clock signal is sent to the second part of the shift register unit to control the second part of the shift register unit not to output a scan signal.

[0023] Optionally, the step of the first part of the shift register unit outputting a scan signal and the second part of the shift register unit not outputting a scan signal specifically includes:

[0024] Generate a reset control signal and a first-level signal;

[0025] A reset signal is generated based on the reset control signal and the first level signal;

[0026] After the first part of the shift register unit outputs the scan signal, the reset signal is output to both the first part of the shift register unit and the second part of the shift register unit.

[0027] According to the reset signal, both the first part of the shift register unit and the second part of the shift register unit are controlled to stop outputting.

[0028] Optionally, the driving method further includes:

[0029] During at least part of the blanking phase, a reverse scan instruction is generated;

[0030] According to the inverted scan instruction, an inverted scan signal is generated, which indicates that the next frame of the display screen will start scanning from the last shift register unit among the multiple cascaded shift register units;

[0031] Generate a reverse data signal according to the reverse scan command;

[0032] The step of sending a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase, according to the frame frequency switching instruction, specifically includes:

[0033] Based on the scan reversal signal and the reversal data signal, scanning begins from the last shift register unit among the cascaded multiple shift register units, causing all or some of the multiple shift register units to output scan signals, while simultaneously sending a reversal data signal to the display panel.

[0034] Based on the above-described driving method, a second aspect of the present invention provides a driving circuit for driving a display device. The display device includes a display panel, the display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift register units. A screen refresh cycle of the display device includes an active phase and a blanking phase. The driving circuit includes:

[0035] The generation module is used to generate frame rate switching instructions based on pre-stored frame rate switching information;

[0036] The switching control module is used to send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase according to the frame frequency switching instruction; and based on the switching timing drive signal, control all or some of the shift register units in the gate driving circuit to output scan signals.

[0037] Optionally, the generation module is specifically used to: generate a frame frequency switching signal during at least part of the blanking phase based on pre-stored frame frequency switching information;

[0038] The switching control module includes a driver submodule, which is used to: send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase, according to the frame frequency switching signal.

[0039] Optionally, the generation module is specifically used to: generate an enable signal in at least a partially active phase or a blanking phase based on pre-stored frame frequency switching information;

[0040] The switching control module includes a switching submodule and a driving submodule. The switching submodule is used to generate a corresponding switching timing drive signal during at least part of the blanking phase according to the enable signal. The driving submodule is used to drive all or some of the shift register units in the gate driving circuit to output scan signals according to the switching timing drive signal.

[0041] Optionally, the plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, wherein the driving frequency of the first part of shift register units is greater than the driving frequency of the second part of shift register units; the switching control module is specifically used to: control the first part of shift register units to output a scanning signal and control the second part of shift register units not to output a scanning signal during at least one screen refresh cycle.

[0042] Optionally, the drive submodule in the switching control module is specifically used to: send a normal clock signal to the first part of the shift register unit to control the first part of the shift register unit to output a scan signal; and send an invalid clock signal to the second part of the shift register unit to control the second part of the shift register unit not to output a scan signal.

[0043] Optionally, the drive submodule in the switching control module includes:

[0044] A signal providing unit is used to generate a reset control signal and a first-level signal;

[0045] A signal generation unit is configured to generate a reset signal based on the reset control signal and the first level signal;

[0046] The control unit is configured to output the reset signal to both the first and second part of the shift register unit after the first part of the shift register unit outputs the scan signal; and to control both the first and second part of the shift register unit to stop outputting according to the reset signal.

[0047] Optionally, the generation module is further configured to: generate a reverse scan instruction during at least part of the blanking phase;

[0048] The generation module is further configured to: generate a reverse scan signal according to the reverse scan instruction, wherein the reverse scan signal indicates that the next frame of the display screen starts scanning from the last shift register unit among the multiple cascaded shift register units;

[0049] The generation module is further configured to: generate a reverse data signal according to the reverse scan instruction;

[0050] The drive submodule in the switching control module is used to: scan from the last shift register unit among the multiple cascaded shift register units according to the scan reversal signal and the reversal data signal, so that all or some of the multiple shift register units output scan signals, and at the same time, send the reversal data signal to the display panel.

[0051] Based on the above-described driving circuit technical solution, a third aspect of the present invention provides a display device including the above-described driving circuit.

[0052] Based on the above-described display device driving method, a fourth aspect of the present invention provides an electronic device, comprising: a processor, a memory, and a program stored in the memory and executable on the processor, wherein the program, when executed by the processor, implements the steps of the above-described display device driving method.

[0053] Based on the above-described driving method for the display device, a fifth aspect of the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program, which, when executed by the processor, implements the steps of the above-described driving method for the display device.

[0054] Based on the above-described display device driving method, a sixth aspect of the present invention provides a computer program product including computer instructions, which, when executed by a processor, implement the steps of the above-described display device driving method.

[0055] The technical solution provided by this invention can send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase, based on the frame rate switching instruction. This enables the multiple shift register units in the gate driving circuit to output scanning signals, or some shift register units to output scanning signals, based on the switching timing drive signal. This driving method can control different display areas in the display device to achieve the required scanning frequency, allowing different display areas to better match the scanning frequency while meeting the user's viewing needs, thereby effectively reducing the display power consumption of the display device. Moreover, the technical solution provided by this invention does not require changes to the existing driver IC and display panel structure. It only requires changes to the timing drive signal and the cooperation between the driver IC and the overall AP to achieve the function of using different refresh rates in different areas. This method not only reduces the overall power consumption of the screen but is also simple and convenient, with no additional cost, which is conducive to rapid market launch. Attached Figure Description

[0056] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0057] Figure 1 This is a first schematic diagram of driving sub-pixels in a display device provided in an embodiment of the present invention;

[0058] Figure 2 This is a second schematic diagram of driving sub-pixels in a display device provided in an embodiment of the present invention;

[0059] Figure 3 This is a third schematic diagram of driving sub-pixels in a display device provided in an embodiment of the present invention;

[0060] Figure 4 The corresponding driver provided for the embodiments of the present invention Figure 3 A schematic diagram of cascaded shift register units in the structure;

[0061] Figure 5 This is a first distribution diagram of the high-frequency refresh area and the low-frequency refresh area in the display device provided in an embodiment of the present invention;

[0062] Figure 6 This is a timing diagram illustrating the switching of different frame frequencies provided in an embodiment of the present invention;

[0063] Figure 7 A timing diagram illustrating partitioned different frame rates driven according to an embodiment of the present invention;

[0064] Figure 8 This is a timing diagram illustrating the use of firmware to switch between different frame frequencies, provided in an embodiment of the present invention.

[0065] Figure 9 This is a schematic diagram of the timing control circuit provided in an embodiment of the present invention;

[0066] Figure 10 A timing diagram of the clock signal and reset signal provided in an embodiment of the present invention;

[0067] Figure 11 A schematic diagram of the circuit structure of the shift register unit provided in an embodiment of the present invention;

[0068] Figure 12 This is a second schematic diagram showing the distribution of the high-frequency refresh area and the low-frequency refresh area in a display device provided in an embodiment of the present invention.

[0069] Figure 13 This is a schematic diagram of the inversion drive process provided in an embodiment of the present invention. Detailed Implementation

[0070] To further illustrate the display device and its driving method, driving circuit, equipment, medium and program products provided in the embodiments of the present invention, a detailed description is provided below with reference to the accompanying drawings.

[0071] Currently, there is no precedent for mobile applications displaying different frame rates for different areas; they simply set high or low refresh rates. The main reason why current mobile phones cannot achieve different frame rates for different areas is the limitation of the screen. As a display unit, the screen in current LCD products mainly works by using a gate driving circuit to open the corresponding pixels, and then sending the voltage corresponding to the image to the pixels through the source driving chip to charge them. This drives the liquid crystal to flip, and the transmittance of the corresponding pixels changes from opaque to partially or completely transparent, thus enabling the pixels to emit light.

[0072] Each pixel emits light using the same principle. Analyzing this using current mainstream resolution specifications HD (720*1600) and FHD (1080*2400), for example... Figure 1 As shown, achieving single-pixel control requires 115K or 259K driving units. This poses a significant challenge for screens because it occupies a large amount of space, resulting in a very small actual output pixel count. It should be noted that... Figure 1 The diagram illustrates sub-pixel 10, scan line 11, data line 12, gate drive circuit 13, and source drive circuit 14.

[0073] like Figure 2 As shown, after the improvement, pixels in the same row share a single scan line, and pixels in the same column share a single data line, thus greatly reducing the number of scan lines and data lines. Because... Figure 2The solution still has thousands of scan lines, so it is further optimized to drive scan lines with a fixed interval as a group of driver ICs, such as... Figure 3 and Figure 4 As shown, for example, the driver IC only outputs clock signals CLK1 to CLK16 to control shift register units Gate Circuit 1 to Gate Circuit 16. Gate Circuit 17 and Gate Circuit 1 are cascaded and share the CLK1 drive in a time-sharing manner. Gate Circuit 1 acts as the enable signal for Gate Circuit 17, and Gate Circuit 17 in turn acts as the reset signal for Gate Circuit 1 to prevent data signal misalignment caused by Gate Circuit 1 remaining on when Gate Circuit 17 is on. Gate Circuit 1, Gate Circuit 17, Gate Circuit 33, and Gate Circuit 49 are controlled by the CLK1 signal output from the same driver IC; Gate Circuit 2, Gate Circuit 18, Gate Circuit 34, and Gate Circuit 50 are controlled by the CLK2 signal output from the same driver IC; and so on. It should be noted that... Figure 4 The diagram illustrates multiple cascaded shift register units, namely Gate Circuit 1 to Gate Circuit 1600, and also shows the frame start signal lines STV1, STV2, STV3, and STV4.

[0074] visible, Figure 3 The design significantly improves the area utilization of the display panel and driver IC, and also greatly reduces the difficulty of IC design. However, this solution requires driving the output of each pixel according to strict driving timing, sacrificing the flexibility of the panel. Therefore, it is impossible to achieve different driving for pixels in different areas with the current design unless the cascading relationship of the shift register unit outputs is modified.

[0075] This invention provides a driving method for a display device, the display device including a display panel, the display panel including a gate driving circuit, the gate driving circuit including a plurality of cascaded shift register units; a screen refresh cycle of the display device including an active phase and a blanking phase; the driving method including:

[0076] Generate frame rate switching instructions based on pre-stored frame rate switching information;

[0077] According to the frame rate switching instruction, during at least part of the blanking phase, a corresponding switching timing drive signal is sent to the gate driving circuit; based on the switching timing drive signal, the plurality of shift register units in the gate driving circuit are controlled to output scan signals or some shift register units output scan signals.

[0078] For example, the display panel includes a gate driving circuit, which includes a plurality of cascaded shift register units; the display panel also includes a plurality of sub-pixels arranged in an array, the plurality of sub-pixels being divided into multiple rows of sub-pixels, and the shift register units being used to drive at least one corresponding row of sub-pixels.

[0079] For example, a screen refresh cycle of the display panel provided in this embodiment of the invention includes an active phase and a blanking phase. The active phase is the display frame, also known as the Active phase. The blanking phase is also known as the Blank phase. The Blank phase is distributed between display frames and can be used to prepare and transmit screen data, but does not actually display the screen. More specifically, the Blank phase can be distributed between the last row of pixels in the active display area of ​​the display panel writing data from the previous frame to the first row of pixels writing data for the next frame. The Blank phase is a timing concept, equivalent to scanning multiple rows of virtual pixels in the display panel, which are not actually laid out in the display panel. The number of virtual pixel rows is equal to the number of pixel rows that the scanning signal used to control data writing can scan within the duration of the Blank phase.

[0080] like Figure 5 As illustrated, for example, with the increase in screen size, more apps in portrait mode only display video in a partial area, while the remaining areas do not refresh content. More specifically, in application scenarios where only a partial area displays video, the display area includes a video display area 21 and a non-video display area 22. The video display area 21 uses a high refresh rate to enhance the user's video viewing experience; the non-video display area 22 is generally a black screen or fixed text description, and uses a low refresh rate to prevent users from experiencing noticeable parallax.

[0081] When driving a display device using the above-described driving method, there is no need to change the design of the display panel or modify the driver IC. Its core principle is to refresh data every frame for high refresh rate areas (e.g., video display areas), while for low refresh rate areas (e.g., non-video display areas), data can be refreshed for some frames and not for others. For example, the first frame refreshes data across the entire screen, the second frame only updates the high refresh rate area, and the shift register unit driving the low refresh rate area is directly turned off, stopping display in this frame. The third and fourth frames continue the operation of the previous two frames, and so on in a loop. Over the time span, the high refresh rate area maintains a fixed refresh rate due to continuous data updates, while the low refresh rate area, because it does not output data on even-numbered frames, effectively reduces the frequency by half.

[0082] like Figure 6 As shown, to simultaneously support high-frequency and low-frequency refresh rates, multiple timing registers can be set to implement output at different frame rates. Since the actual data to be displayed in the current frame has already been sent during the Blank phase (including the VFP of the previous frame and the VBP of the next frame), and only empty data packets are sent during the Blank phase, the frame rate switching command can be generated and transmitted during the Blank phase. It should be noted that... Figure 6 The diagram also illustrates a data transmission phase (i.e., an active phase) between adjacent Blank phases, which is used to transmit the data signal Data. This phase corresponds to the display phase, and the Blank phase corresponds to the touch phase of the display device.

[0083] Suppose there are two sets of timing registers, named TableA and TableB respectively. TableA is configured with a normal 120Hz timing drive signal, and TableB is configured with a 60Hz timing drive signal.

[0084] When the refresh rate required for the next frame is 120Hz, a corresponding frame rate switching instruction is generated. This instruction indicates that the timing drive signal in Table A should be executed. According to the frame rate switching instruction, the timing drive signal in Table A (i.e., the timing drive signal is switched) is sent to the gate drive circuit. Based on the timing drive signal in Table A, the multiple shift register units in the gate drive circuit are controlled to output scan signals.

[0085] When the refresh rate required for the next frame is 60Hz, a corresponding frame rate switching instruction is generated. This instruction indicates that the timing drive signal in Table B should be executed. According to the frame rate switching instruction, the timing drive signal in Table B (i.e., the timing drive signal is switched) is sent to the gate drive circuit. Based on the timing drive signal in Table B, some shift register units in the gate drive circuit are controlled to output scan signals.

[0086] More specifically, taking a display device with a screen resolution of 720*1600 as an example, different frame rates are achieved by dividing the screen into 800 rows. Rows 1-800 have a refresh rate of 120Hz, and rows 801-1600 have a refresh rate of 60Hz. When displaying the first frame, the driving timing signals in tableA are executed, outputting 120Hz across the entire screen. When displaying the second frame, the driving timing signals in tableB are executed, driving only the first 800 rows to output, while the last 800 rows are directly turned off and not displayed. Combining the first and second frames, it can be seen that rows 1-800 refresh data in real time at 8.33ms (120Hz), while rows 801-1600 refresh data in real time at 16.67ms (60Hz) because the second frame is not output. This achieves a higher frame rate refresh rate at the top and a lower frame rate refresh rate at the bottom.

[0087] Using the above method, arbitrary switching between multiple frame rates can be achieved. If a lower refresh rate is required for certain areas, simply adjust the period of generating the frame rate switching command. For example, generate a frame rate switching command every two frames (the command indicates execution of table A), then generate a frame rate switching command every one frame (the command indicates execution of table B), and repeat this cycle to achieve table A: 1 frame & table B: 2 frames, which can achieve a low refresh rate of 40Hz; or, generate a frame rate switching command every one frame (the command indicates execution of table A), then generate a frame rate switching command every two frames (the command indicates execution of table B), and repeat this cycle to achieve table A: 2 frames & table B: 1 frame, which can achieve a low refresh rate of 80Hz.

[0088] If you want to change the refresh rate or the number of rows in the partition for other frame rates, you can determine the details of the driver timing settings in the table during the review phase (i.e., the preset phase), and then issue instructions in the blank area to arbitrarily change the number of display rows required for each frame; for example, implement high-frequency refresh for 1 / 3 of the display area, or implement high-frequency refresh for 1 / 4 of the display area, etc.

[0089] In the driving method provided by this invention, a frame rate switching instruction can be generated based on pre-stored frame rate switching information. The frame rate switching information indicates which frame's blanking phase should be switched during the display process of the display device. For example, the frame rate is switched to 120Hz during the blanking phase of odd-numbered frames and to 60Hz during the blanking phase of even-numbered frames, but it is not limited to this. The frame rate switching information can be pre-set or adjusted in real time.

[0090] In the driving method provided by this embodiment of the invention, according to the frame rate switching instruction, during at least a partial blanking phase, a corresponding switching timing drive signal is sent to the gate driving circuit; based on the switching timing drive signal, the plurality of shift register units in the gate driving circuit are controlled to output scan signals, or some shift register units output scan signals. The at least partial blanking phase corresponds to the blanking phase indicated in the frame rate switching information where frame rate switching is required. The switching timing drive signal indicates that a timing drive signal different from the current frame is used for driving the next frame. Multiple timing drive signals can be preset to achieve multiple different frame rate driving modes. Controlling the plurality of shift register units in the gate driving circuit to output scan signals achieves full-screen scanning. Controlling some shift register units in the gate driving circuit to output scan signals achieves partial-screen scanning.

[0091] The driving method provided in this embodiment of the invention can send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase based on the frame rate switching instruction; thereby controlling the multiple shift register units in the gate driving circuit to output scan signals or some shift register units to output scan signals based on the switching timing drive signal. This driving method can control different display areas in the display device to achieve the required scan frequency, so that different display areas can better match the scan frequency while meeting the user's viewing needs, thereby effectively reducing the display power consumption of the display device. Moreover, the driving method provided in this embodiment of the invention does not require changes to the existing driver IC and display panel structure. It only requires changes to the timing drive signal and the cooperation between the driver IC and the overall AP (Application Processor) to achieve the function of using different refresh frequencies in different areas. This method can not only reduce the overall power consumption of the screen, but is also simple and convenient, with no additional cost, which is conducive to rapid market launch.

[0092] In some embodiments, the step of generating a frame frequency switching instruction based on pre-stored frame frequency switching information specifically includes: generating a frame frequency switching signal based on pre-stored frame frequency switching information during at least part of the blanking phase;

[0093] The step of sending a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase according to the frame frequency switching instruction specifically includes: sending a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase according to the frame frequency switching signal.

[0094] For example, the AP generates a frame frequency switching signal during at least part of the blanking phase based on pre-stored frame frequency switching information, and transmits the frame frequency switching signal to the driver chip via the MIPI protocol. The driver chip sends a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase based on the frame frequency switching signal.

[0095] The above-mentioned driving method can directly realize communication between the AP and the driver chip, and can realize timing changes in a simpler way.

[0096] In some embodiments, the step of generating a frame rate switching instruction based on pre-stored frame rate switching information specifically includes:

[0097] Based on the pre-stored frame rate switching information, an enable signal is generated during at least a partially active phase or a blanking phase.

[0098] The step of sending a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase according to the frame frequency switching command specifically includes:

[0099] Based on the enable signal, during at least part of the blanking phase, a corresponding switching timing drive signal is generated;

[0100] According to the switching timing drive signal, all or some of the shift register units in the gate drive circuit are driven to output scan signals.

[0101] like Figure 8 As shown, for example, the AP generates an enable signal during at least a partially active or blanking phase based on pre-stored frame rate switching information; the firmware generates a corresponding switching timing drive signal during at least a partially blanking phase based on the enable signal; and the driver chip drives the plurality of shift register units in the gate drive circuit to output scan signals, or some shift register units to output scan signals, based on the switching timing drive signal. It should be noted that... Figure 8 This illustrates generating an enable signal during at least a partially effective phase, but is not limited to this.

[0102] The above-mentioned driving method can realize communication between the AP and the driver chip through firmware, thereby completing timing changes.

[0103] In some embodiments, the plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, wherein the driving frequency of the first part of shift register units is greater than the driving frequency of the second part of shift register units.

[0104] The steps for controlling the output scan signal of a portion of the shift register units in the gate drive circuit specifically include:

[0105] During at least one screen refresh cycle, the first part of the shift register unit is controlled to output a scan signal, while the second part of the shift register unit is controlled not to output a scan signal.

[0106] For example, the plurality of shift register units are divided into a first part of shift register units and a second part of shift register units. When scanning a frame, the first part of shift register units is scanned first, and then the second part of shift register units is scanned.

[0107] For example, during a portion of the screen refresh cycle, the first portion of the shift register unit is controlled to output a scan signal, while the second portion of the shift register unit is controlled not to output a scan signal. During another portion of the screen refresh cycle, both the first portion of the shift register unit and the second portion of the shift register unit are controlled to output scan signals.

[0108] The above settings control the first part of the shift register unit to output a scan signal and control the second part of the shift register unit not to output a scan signal during at least one screen refresh cycle, thereby enabling low-frequency refresh of the area driven by the second part of the shift register unit.

[0109] In some embodiments, the step of the first part of the shift register unit outputting a scan signal and the second part of the shift register unit not outputting a scan signal specifically includes:

[0110] Send a normal clock signal to the first part of the shift register unit to control the first part of the shift register unit to output a scan signal;

[0111] An invalid clock signal is sent to the second part of the shift register unit to control the second part of the shift register unit not to output a scan signal.

[0112] like Figure 7As shown, in a full-screen refresh frame, normal clock signals are sent to the first part of the shift register unit, such as: clock signal CLK1 has normal high level (G1, G3) and low level switching; clock signal CLK2 has normal high level (G2, G4) and low level switching; normal clock signals are sent to the second part of the shift register unit, such as: clock signal CLK1 has normal high level (G5, G7) and low level switching; clock signal CLK2 has normal high level (G6, G8) and low level switching.

[0113] like Figure 7 As shown, in the partial refresh frame, a normal clock signal is sent to the first part of the shift register unit, such as: clock signal CLK1 has normal high level (G1, G3) and low level switching; clock signal CLK2 has normal high level (G2, G4) and low level switching; an invalid clock signal is sent to the second part of the shift register unit, such as: clock signal CLK1 and clock signal CLK2 no longer switch between high level and low level, and are both in a low level state.

[0114] It should be noted that, Figure 7 The diagram also illustrates the frame start signal STV and the reset signal STV0. Figure 8 The high refresh rate region timing corresponds to the first part of the shift register unit, and the low refresh rate region timing corresponds to the second part of the shift register unit.

[0115] like Figure 11 The diagram illustrates a circuit structure for a shift register unit, which may employ the following circuit structure, but is not limited to it.

[0116] The shift register unit includes:

[0117] The first transistor M1 has its gate coupled to the frame start signal input terminal STV or the output terminal G_out(n-1) of the cascaded previous level shift register unit, its first terminal coupled to the power supply signal input terminal VDD, and its second terminal coupled to the pull-up node PU.

[0118] The second transistor M2 has its gate coupled to the output terminal G_out(n+1) of the cascaded next-stage shift register unit, its first terminal coupled to the second level signal input terminal VSD, and its second terminal coupled to the pull-up node PU.

[0119] The third transistor M3 has its gate coupled to the pull-up node PU, its first terminal coupled to , and its second terminal coupled to the output terminal G_out of its corresponding shift register unit.

[0120] The fourth transistor M4 has its gate coupled to the reset signal output terminal STV0, its first terminal coupled to the pull-up node PU, and its second terminal coupled to the third level signal input terminal VGL.

[0121] The fifth transistor M5 has its gate coupled to the second terminal of the ninth transistor M9, its first terminal coupled to the fourth level signal input terminal GCH, and its second terminal coupled to the pull-down node PD.

[0122] The sixth transistor M6 has its gate coupled to the pull-up node PU, its first terminal coupled to the pull-down node PD, and its second terminal coupled to the third level signal input terminal VGL.

[0123] The seventh transistor M7 has its gate coupled to the reset signal output terminal STV0, its first terminal coupled to the output terminal G_out of its corresponding shift register unit, and its second terminal coupled to the third-level signal input terminal VGL.

[0124] The eighth transistor M8 has its gate coupled to the pull-up node PU, its first terminal coupled to the second terminal of the ninth transistor M9, and its second terminal coupled to the third level signal input terminal VGL.

[0125] The ninth transistor M9 has its gate and first electrode coupled together and is coupled to the fourth level signal input terminal GCH.

[0126] The tenth transistor M10 has its gate coupled to the pull-down node PD, its first terminal coupled to the pull-up node PU, and its second terminal coupled to the third level signal input terminal VGL.

[0127] The eleventh transistor M11 has its gate coupled to the pull-down node PD, its first terminal coupled to the output terminal G_out of its corresponding shift register unit, and its second terminal coupled to the third level signal input terminal VGL.

[0128] Capacitor C1, the first end of which is coupled to the pull-up node PU, and the second end of which is coupled to the output terminal G_out of the shift register unit to which it belongs.

[0129] For example, when displaying a frame, the frame start signal input at the frame start signal input terminal STV charges the pull-up node PU of the first shift register unit. Then, when the clock signal (corresponding to the normal clock signal) transmitted by the clock signal line CLK coupled to the first shift register unit arrives, the voltage of the pull-up node PU is boosted by 1 times through the bootstrap capacitor, turning on the third transistor M3. The output terminal of the first shift register unit outputs this clock signal. The output terminal of the first shift register unit serves as the start signal for the second shift register unit. When the clock signal (corresponding to the normal clock signal) transmitted by the clock signal line CLK coupled to the second shift register unit arrives, the voltage of the pull-up node PU of the second shift register unit is boosted by 1 times through the bootstrap capacitor, turning on the third transistor M3. The output terminal of the second shift register unit outputs this clock signal. Simultaneously, the signal output from the output terminal of the second shift register unit is used to reset the first shift register unit, causing the first shift register unit to stop outputting and preventing other data signals from being incorrectly charged into the sub-pixel row driven by the first shift register unit. Similarly, after the high-frequency display area driven by the first part of the shift register unit is refreshed, an invalid clock signal is sent to the second part of the shift register unit to control the second part of the shift register unit not to output a scan signal.

[0130] The above driving method controls whether the clock signal sent to each shift register unit is normal, and can control whether each shift register unit outputs during the current refresh stage, thereby enabling different areas to be refreshed with different refresh rates.

[0131] like Figure 9 As shown, in some embodiments, the step of the first part of the shift register unit outputting a scan signal and the second part of the shift register unit not outputting a scan signal specifically includes:

[0132] Generate a reset control signal Xoff and a first-level signal VGH;

[0133] A reset signal is generated based on the reset control signal Xoff and the first level signal VGH;

[0134] After the first part of the shift register unit outputs the scan signal, the reset signal is output to both the first part of the shift register unit and the second part of the shift register unit; according to the reset signal, the first part of the shift register unit and the second part of the shift register unit are controlled to stop outputting.

[0135] like Figure 9 As shown, exemplarily, in the existing timing control circuit design, an AND gate is added. The first input of this AND gate receives a reset control signal Xoff, and the second input receives a first level signal VGH. The output of the AND gate is coupled to the reset signal output terminal STV0. This AND gate can generate a reset signal based on the reset control signal Xoff and the first level signal VGH, and transmit this reset signal to the reset signal output terminal STV0. It should be noted that... Figure 9 The diagram also illustrates the clock signals CLK1 to CLK16, the basic clock signal Clock, and the output signal CGOUT received by the register. Figure 9 The boost circuit in the circuit is used to adjust the signal level. For example... Figure 10 The diagram illustrates the timing of some clock signals, including the timing of the base clock signal Clock, the timing of the reset signal output from the reset signal output terminal STV0, and the timing of the enable signal EN.

[0136] More specifically, in the existing timing control circuit design, a signal with a forced shutdown function is added to interrupt the continuous switching of the clock signal. For example, adding a counter reset control signal Xoff can directly control all driver chips to stop outputting the clock signal after the output of the first part of the shift register unit is completed. At the same time, the reset signal is output to both the first part of the shift register unit and the second part of the shift register unit, controlling both the first part of the shift register unit and the second part of the shift register unit to stop outputting.

[0137] The above driving method can control both the first and second shift register units to stop outputting after the first shift register unit outputs, thereby enabling different regions to be refreshed using different refresh rates.

[0138] like Figure 13 As shown, in some embodiments, the driving method further includes:

[0139] During at least part of the blanking phase, a reverse scan instruction is generated;

[0140] According to the inverted scan instruction, an inverted scan signal is generated, which indicates that the next frame of the display screen will start scanning from the last shift register unit among the multiple cascaded shift register units;

[0141] Generate a reverse data signal according to the reverse scan command;

[0142] The step of sending a corresponding switching timing drive signal to the gate drive circuit during at least part of the blanking phase, according to the frame frequency switching instruction, specifically includes:

[0143] Based on the scan reversal signal and the reversal data signal, scanning begins from the last shift register unit among the cascaded multiple shift register units, causing all or some of the multiple shift register units to output scan signals, while simultaneously sending a reversal data signal to the display panel.

[0144] like Figure 12 As shown, in application scenarios where only a partial area displays video, the display area includes a video display area 21 and a non-video display area 22. The video display area 21 uses a high refresh rate, while the non-video display area 22 uses a low refresh rate. The driving method provided in the above embodiments is not limited to the top screen being a high refresh rate area and the bottom screen being a low refresh rate area. In certain application scenarios where it is necessary to implement a low refresh rate area for the top screen and a high refresh rate area for the bottom screen, there are corresponding matching driving timings.

[0145] More specifically, when refreshing the display screen, after completing the last frame scan of a display state, the application switches the top screen to a low refresh rate area and the bottom screen to a high refresh rate area, and then executes the following steps in sequence:

[0146] During at least part of the blanking phase, frame rate switching instructions and inverted scan instructions are generated;

[0147] According to the frame rate switching instruction, during at least part of the blanking phase, a corresponding switching timing drive signal is sent to the gate driving circuit; according to the inverted scan instruction, an inverted scan signal is generated, the inverted scan signal indicating that the next frame of display screen starts scanning from the last shift register unit among the cascaded multiple shift register units; according to the inverted scan instruction, an inverted data signal is generated, the inverted data signal indicating that the data signal of the row of sub-pixels corresponding to the last shift register unit is provided first, then the data signals of each row of sub-pixels are provided sequentially, and finally the data signal of the row of sub-pixels corresponding to the starting shift register unit is provided.

[0148] Based on the switching timing drive signal, the multiple shift register units in the gate drive circuit are controlled to output scan signals, or some shift register units output scan signals. According to the scan inversion signal and the inverted data signal, scanning starts from the last shift register unit in the cascaded multiple shift register units, so that all multiple shift register units output scan signals, or some shift register units output scan signals, and at the same time, the inverted data signal is sent to the display panel.

[0149] It is worth noting that during full-screen refresh, the multiple shift register units in the gate drive circuit all output scan signals, sending the inverted data signal for the entire screen to the display panel. During partial-screen refresh, the inverted data signal for that portion of the screen is sent to the display panel.

[0150] The aforementioned driving method enables a high refresh rate for the bottom screen and a low refresh rate for the top screen, making the display device suitable for more application scenarios.

[0151] In some embodiments, such as Figure 5 As shown, in application scenarios where only a partial area displays video, the display area includes a video display area 21 and a non-video display area 22. The video display area 21 uses a high refresh rate, while the non-video display area 22 uses a low refresh rate. In the driving method provided in the above embodiments, when certain application scenarios require the top screen to be a high refresh rate area and the bottom screen to be a low refresh rate area, there are also corresponding matching driving timings.

[0152] More specifically, when refreshing the display screen, after completing the last frame scan of a display state, the application switches the bottom screen to a low refresh rate area and the top screen to a high refresh rate area, and then executes the following steps in sequence:

[0153] During at least part of the blanking phase, a frame rate switching instruction is generated;

[0154] According to the frame rate switching instruction, during at least part of the blanking phase, a corresponding switching timing drive signal is sent to the gate drive circuit; since there is no reverse scan instruction, the next frame of display is scanned from the start shift register unit among the cascaded multiple shift register units by default; the transmitted data signal indicates that the data signal of the row of sub-pixels corresponding to the start shift register unit is provided first, then the data signals of each row of sub-pixels are provided in sequence, and finally the data signal of the row of sub-pixels corresponding to the end shift register unit is provided.

[0155] Based on the switching timing drive signal, the multiple shift register units in the gate drive circuit are controlled to output scan signals, or some shift register units output scan signals. Scanning begins from the first shift register unit among the cascaded multiple shift register units, causing all or some of the shift register units to output scan signals, while simultaneously sending the data signal to the display panel.

[0156] It is worth noting that during a full-screen refresh, all of the multiple shift register units in the gate drive circuit output scan signals, sending the full-screen data signal to the display panel. During a partial-screen refresh, only the partial-screen data signal is sent to the display panel.

[0157] This invention provides a driving circuit for driving a display device. The display device includes a display panel, the display panel includes a gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift register units. A screen refresh cycle of the display device includes an active phase and a blanking phase. The driving circuit includes:

[0158] The generation module is used to generate frame rate switching instructions based on pre-stored frame rate switching information;

[0159] The switching control module is used to send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase according to the frame frequency switching instruction; and based on the switching timing drive signal, control all or some of the shift register units in the gate driving circuit to output scan signals.

[0160] For example, the driving circuit includes an AP, which includes a generation module, but is not limited thereto.

[0161] The driving circuit provided in this embodiment of the invention can send a corresponding switching timing driving signal to the gate driving circuit during at least part of the blanking phase based on the frame rate switching instruction; thereby controlling the multiple shift register units in the gate driving circuit to output scanning signals or some shift register units to output scanning signals based on the switching timing driving signal. This driving method can control different display areas in the display device to achieve the required scanning frequency, so that different display areas can better match the scanning frequency while meeting the user's viewing needs, thereby effectively reducing the display power consumption of the display device. Moreover, the driving circuit provided in this embodiment of the invention does not require changes to the existing driver IC and display panel structure. Only by changing the timing driving signal and cooperating with the driver IC and the overall AP (Application Processor), the function of using different refresh rates for different areas can be achieved. This method can not only reduce the overall power consumption of the screen, but is also simple and convenient, with no additional cost, which is conducive to rapid market launch.

[0162] In some embodiments, the generation module is specifically configured to: generate a frame frequency switching signal during at least part of the blanking phase based on pre-stored frame frequency switching information;

[0163] The switching control module includes a driver submodule, which is used to: send a corresponding switching timing drive signal to the gate driving circuit during at least part of the blanking phase, according to the frame frequency switching signal.

[0164] For example, the driving circuit includes a driving chip, which includes, but is not limited to, the driving submodule.

[0165] The aforementioned driving circuit can directly enable communication between the AP and the driving chip, and can achieve timing changes in a simpler way.

[0166] In some embodiments, the generation module is specifically configured to: generate an enable signal during at least a partially active phase or a blanking phase, based on pre-stored frame rate switching information;

[0167] The switching control module includes a switching submodule and a driving submodule. The switching submodule is used to generate a corresponding switching timing drive signal during at least part of the blanking phase according to the enable signal. The driving submodule is used to drive all or some of the shift register units in the gate driving circuit to output scan signals according to the switching timing drive signal.

[0168] For example, the drive circuit includes firmware and a drive chip, and the firmware includes, but is not limited to, a switching submodule.

[0169] The aforementioned driving circuit enables communication between the AP and the driver chip via firmware, thereby completing timing changes.

[0170] In some embodiments, the plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, wherein the driving frequency of the first part of shift register units is greater than the driving frequency of the second part of shift register units; the switching control module is specifically used to: control the first part of shift register units to output a scan signal and control the second part of shift register units not to output a scan signal during at least one screen refresh cycle.

[0171] In some embodiments, the driving submodule in the switching control module is specifically used to: send a normal clock signal to the first part of the shift register unit to control the first part of the shift register unit to output a scan signal; and send an invalid clock signal to the second part of the shift register unit to control the second part of the shift register unit not to output a scan signal.

[0172] The aforementioned driving circuit controls whether the clock signal sent to each shift register unit is normal, and can control whether each shift register unit outputs during the current refresh phase, thereby enabling different areas to be refreshed at different refresh rates.

[0173] In some embodiments, the drive submodule in the switching control module includes:

[0174] A signal providing unit is used to generate a reset control signal and a first-level signal;

[0175] A signal generation unit is configured to generate a reset signal based on the reset control signal and the first level signal;

[0176] The control unit is configured to output the reset signal to both the first and second part of the shift register unit after the first part of the shift register unit outputs the scan signal; and to control both the first and second part of the shift register unit to stop outputting according to the reset signal.

[0177] The aforementioned driving circuit can control both the first and second shift register units to stop outputting after the first shift register unit outputs, thereby enabling different regions to be refreshed using different refresh rates.

[0178] In some embodiments, the generation module is further configured to: generate a reverse scan instruction during at least a portion of the blanking phase;

[0179] The generation module is further configured to: generate a reverse scan signal according to the reverse scan instruction, wherein the reverse scan signal indicates that the next frame of the display screen starts scanning from the last shift register unit among the multiple cascaded shift register units;

[0180] The generation module is further configured to: generate a reverse data signal according to the reverse scan instruction;

[0181] The drive submodule in the switching control module is used to: scan from the last shift register unit among the multiple cascaded shift register units according to the scan reversal signal and the reversal data signal, so that all or some of the multiple shift register units output scan signals, and at the same time, send the reversal data signal to the display panel.

[0182] The aforementioned driving circuit enables a high refresh rate for the bottom screen and a low refresh rate for the top screen, making the display device suitable for more application scenarios.

[0183] This invention also provides a display device, including the driving circuit provided in the above embodiments.

[0184] It should be noted that the display device can be any product or component with display function, such as a television, monitor, digital photo frame, mobile phone, or tablet computer. The display device also includes flexible circuit boards, printed circuit boards, and backplanes.

[0185] In the driving circuit provided in the above embodiments, based on the frame rate switching instruction, a corresponding switching timing driving signal can be sent to the gate driving circuit during at least part of the blanking phase; so as to control the multiple shift register units in the gate driving circuit to output scanning signals or some shift register units to output scanning signals based on the switching timing driving signal. This driving method can control different display areas in the display device to achieve the required scanning frequency, so that different display areas can better match the scanning frequency while meeting the user's viewing needs, thereby effectively reducing the display power consumption of the display device. Moreover, the driving circuit provided in the above embodiments does not require changes to the existing driver IC and display panel structure. Only by changing the timing driving signal and cooperating with the driver IC and the overall AP (Application Processor), the function of using different refresh rates in different areas can be achieved. This method can not only reduce the overall power consumption of the screen, but also is simple and convenient, without increasing costs, which is conducive to rapid market launch.

[0186] The display device provided in the embodiments of the present invention, when including the driving circuit provided in the above embodiments, also has the above-mentioned beneficial effects, which will not be repeated here.

[0187] This invention also provides an electronic device, including: a processor, a memory, and a program stored in the memory and executable on the processor, wherein when the program is executed by the processor, it implements the steps of the driving method for the display device provided in the above embodiments.

[0188] This invention also provides a computer-readable storage medium storing a computer program. When the program is executed by the processor, it implements the steps of the display device driving method provided in the above embodiments and achieves the same technical effect. To avoid repetition, it will not be described again here. The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0189] This invention also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, they implement the various processes of the display device driving method provided in the above embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0190] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods of the various embodiments of this application.

[0191] In the various method embodiments of the present invention, the sequence numbers of each step are not intended to limit the order of the steps. For those skilled in the art, any changes in the order of the steps without creative effort are also within the scope of protection of the present invention.

[0192] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are basically similar to the product embodiments, so the description is relatively simple, and the relevant parts can be referred to the description of the product embodiments.

[0193] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connection,” “coupled,” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0194] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0195] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0196] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A driving method of a display device, characterized by, The display device includes a display panel, the display panel includes a gate drive circuit, the gate drive circuit includes a plurality of shift register units in cascade; one picture refresh period of the display device includes an active stage and a blanking stage; the driving method includes: According to the pre-stored frame frequency switching information, generate frame frequency switching instruction; According to the frame frequency switching instruction, in at least part of the blanking stage, corresponding switching timing drive signal is sent to the gate drive circuit; based on the switching timing drive signal, the plurality of shift register units in the gate drive circuit are controlled to output scan signal or part of the shift register units output scan signal; The driving method further includes: In at least part of the blanking stage, generate reverse scanning instruction; According to the reverse scanning instruction, generate reverse scanning signal, the reverse scanning signal indicates that the next frame display picture starts scanning from the last shift register unit in the plurality of shift register units in cascade; According to the reverse scanning instruction, generate reverse data signal; According to the frame frequency switching instruction, in at least part of the blanking stage, corresponding switching timing drive signal is sent to the gate drive circuit, and the step specifically includes: According to the reverse scanning signal and the reverse data signal, scanning is started from the last shift register unit in the plurality of shift register units in cascade, the plurality of shift register units are controlled to output scan signal or part of the shift register units output scan signal, and reverse data signal is sent to the display panel.

2. The driving method of a display device according to claim 1, wherein The step of generating frame frequency switching instruction according to the pre-stored frame frequency switching information specifically includes: According to the pre-stored frame frequency switching information, generate frame frequency switching signal in at least part of the blanking stage; The step of sending corresponding switching timing drive signal to the gate drive circuit according to the frame frequency switching instruction in at least part of the blanking stage specifically includes: According to the frame frequency switching signal, corresponding switching timing drive signal is sent to the gate drive circuit in at least part of the blanking stage.

3. The driving method of a display device according to claim 1, wherein The step of generating frame frequency switching instruction according to the pre-stored frame frequency switching information specifically includes: According to the pre-stored frame frequency switching information, generate enable signal in at least part of the active stage or the blanking stage; The step of sending corresponding switching timing drive signal to the gate drive circuit according to the frame frequency switching instruction in at least part of the blanking stage specifically includes: According to the enable signal, corresponding switching timing drive signal is generated in at least part of the blanking stage; According to the switching timing drive signal, the plurality of shift register units in the gate drive circuit are driven to output scan signal or part of the shift register units output scan signal.

4. The driving method of a display device according to any one of claims 1 to 3, wherein The plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, and the driving frequency of the first part of shift register units is greater than that of the second part of shift register units; The step of controlling part of the shift register units in the gate drive circuit to output scan signal specifically includes: In at least one picture refresh cycle, the first part of the shift register unit outputs a scanning signal, and the second part of the shift register unit does not output a scanning signal.

5. The driving method of a display device according to claim 4, wherein The step of outputting a scanning signal by the first part of the shift register unit and not outputting a scanning signal by the second part of the shift register unit specifically comprises: A normal clock signal is sent to the first part of the shift register unit to control the first part of the shift register unit to output a scanning signal. An invalid clock signal is sent to the second part of the shift register unit to control the second part of the shift register unit to not output a scanning signal.

6. The driving method of a display device according to claim 4, wherein The step of outputting a scanning signal by the first part of the shift register unit and not outputting a scanning signal by the second part of the shift register unit specifically comprises: A reset control signal and a first level signal are generated. A reset signal is generated according to the reset control signal and the first level signal. After the first part of the shift register unit outputs a scanning signal, the reset signal is output to both the first part of the shift register unit and the second part of the shift register unit. According to the reset signal, the first part of the shift register unit and the second part of the shift register unit are controlled to stop outputting.

7. A drive circuit, characterized by A display device is driven, the display device comprising a display panel, the display panel comprising a gate drive circuit, the gate drive circuit comprising a plurality of shift register units connected in cascade; one picture refresh cycle of the display device comprises an effective stage and a blanking stage; the drive circuit comprises: A generation module is configured to generate a frame frequency switching instruction according to pre-stored frame frequency switching information. A switching control module is configured to send a corresponding switching timing drive signal to the gate drive circuit in at least part of the blanking stage according to the frame frequency switching instruction, and control the plurality of shift register units in the gate drive circuit to output a scanning signal or part of the shift register units to output a scanning signal based on the switching timing drive signal. The generation module is further configured to generate an inverted scanning instruction in at least part of the blanking stage. The generation module is further configured to generate an inverted scanning signal according to the inverted scanning instruction, the inverted scanning signal indicating that a next frame of display picture starts scanning from a tail shift register unit of the plurality of shift register units connected in cascade. The generation module is further configured to generate an inverted data signal according to the inverted scanning instruction. A drive sub-module in the switching control module is configured to start scanning from the tail shift register unit of the plurality of shift register units connected in cascade according to the inverted scanning signal and the inverted data signal, to make the plurality of shift register units output a scanning signal or part of the shift register units output a scanning signal, and to send the inverted data signal to the display panel.

8. The drive circuit of claim 7, wherein: The generation module is specifically configured to generate a frame frequency switching signal in at least part of the blanking stage according to pre-stored frame frequency switching information. The switching control module comprises a driving submodule, configured to send a corresponding switching timing driving signal to the gate driving circuit in at least part of the blanking phase according to the frame frequency switching signal.

9. The driving circuit of claim 7, wherein, The generating module is specifically configured to generate an enable signal in at least part of the active phase or the blanking phase according to pre-stored frame frequency switching information; The switching control module comprises a switching submodule and a driving submodule, the switching submodule is configured to generate a corresponding switching timing driving signal in at least part of the blanking phase according to the enable signal, and the driving submodule is configured to drive all the plurality of shift register units in the gate driving circuit to output a scanning signal or some of the plurality of shift register units to output a scanning signal according to the switching timing driving signal.

10. The drive circuit according to any one of claims 7 to 9, characterized by The plurality of shift register units are divided into a first part of shift register units and a second part of shift register units, the driving frequency of the first part of shift register units is greater than the driving frequency of the second part of shift register units, and the switching control module is specifically configured to control the first part of shift register units to output a scanning signal and control the second part of shift register units not to output a scanning signal in at least one picture refresh cycle.

11. The drive circuit according to claim 10, characterized in that, The driving submodule in the switching control module is specifically configured to send a normal clock signal to the first part of shift register units to control the first part of shift register units to output a scanning signal, and send an invalid clock signal to the second part of shift register units to control the second part of shift register units not to output a scanning signal.

12. The drive circuit of claim 10, wherein, The driving submodule in the switching control module comprises: a signal providing unit configured to generate a reset control signal and a first level signal; a signal generating unit configured to generate a reset signal according to the reset control signal and the first level signal; a control unit configured to output the reset signal to the first part of shift register units and the second part of shift register units after the first part of shift register units output a scanning signal, and control the first part of shift register units and the second part of shift register units to stop outputting according to the reset signal.

13. A display device comprising: The driving circuit comprises any one of the driving circuits in claims 7-12.

14. An electronic device, comprising: The display device comprises: a processor, a memory, and a program stored in the memory and executable on the processor, and the program is executed by the processor to implement the steps of the driving method of the display device in any one of claims 1-6.

15. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the program is executed by the processor to implement the steps of the driving method of the display device in any one of claims 1-6.

16. A computer program product, characterised in that, The computer readable storage medium stores a computer program, and the program is executed by the processor to implement the steps of the driving method of the display device in any one of claims 1-6.

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