Sensitive amplifier and memory

Abstract

The application provides a sensitive amplifier and a memory, and relates to the technical field of integrated circuit design. The sensitive amplifier comprises a tail current source, an automatic clamping circuit, a differential pair, an inverter and a latch. The automatic clamping circuit is used for clamping the potential of the first output end or the second output end of the differential pair at a preset potential according to a first voltage signal input by a bit line of the memory and a second voltage signal input by an inverted bit line of the memory in a working stage. The first control end and the second control end of the differential pair are electrically connected with the bit line and the inverted bit line of the memory respectively, so that the potential of the first output end or the second output end of the differential pair can be clamped at the preset potential in the working stage, and then the preset potential can be used for recharging in a pre-charging stage, thereby reducing the dynamic power consumption of the sensitive amplifier.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a sense amplifier and a memory. BACKGROUND

[0002] As a core component of cache, static random access memory (SRAM) is widely used in CPU, GPU, AI accelerator and Internet of Things device, and a sense amplifier is a key module in the read path of SRAM, which is responsible for quickly amplifying a small voltage difference (usually tens of millivolts) on the bit line of a memory cell to a logic level.

[0003] In the prior art, the sense amplifier takes the read voltage on the bit line (BL) and the inverted bit line (BLB) in the SRAM memory array as an input signal when working, and amplifies the voltage through the sense amplifier to make the high voltage amplified as "1" and the low voltage amplified as "0", so as to realize the read signal judgment of the SRAM.

[0004] However, in the existing sense amplifier, the internal node needs to be charged from 0 potential to a specified potential in each precharge stage, so the existing sense amplifier has the problem of high power consumption in the precharge stage, especially when the memory of the static random access memory is larger or the read frequency is higher, the power consumption of this part will also be higher. SUMMARY

[0005] The present application aims at the deficiencies in the prior art, and provides a sense amplifier and a memory, which can reduce the dynamic power consumption of the sense amplifier.

[0006] To achieve the above object, the technical scheme adopted by the embodiments of the present application is as follows:

[0007] In a first aspect, the present application provides a sense amplifier, which comprises a tail current source, an automatic clamp circuit, a differential pair, an inverter and a latch.

[0008] The control end of the tail current source is electrically connected with the sense amplifier enable end of the memory, the input end is grounded, and the output end is respectively electrically connected with the first input end and the second input end of the automatic clamp circuit.

[0009] The first control end of the automatic clamp circuit is electrically connected with the second output end of the differential pair and the second input end of the latch respectively, the second control end of the automatic clamp circuit is electrically connected with the first output end of the differential pair and the first input end of the latch respectively, the first output end of the automatic clamp circuit is electrically connected with the first input end of the differential pair, and the second output end of the automatic clamp circuit is electrically connected with the second input end of the differential pair; the automatic clamp circuit is used for clamping the potential of the first output end or the second output end of the differential pair at a preset potential according to a first voltage signal input by a bit line of the memory and a second voltage signal input by an inverted bit line of the memory in a working stage.

[0010] The first control end of the differential pair is electrically connected with the bit line of the memory, and the second control end is electrically connected with the inverted bit line of the memory, wherein the bit line and the inverted bit line are a pair of differential signal lines.

[0011] The first control end and the second control end of the latch are electrically connected with the enable end of the sense amplifier of the memory respectively, the first output end is electrically connected with the first inverting input end of the inverter, the second output end is electrically connected with the second inverting input end of the inverter, and the third input end is connected with a preset direct current power supply.

[0012] In an optional embodiment, when the enable end of the sense amplifier of the memory is a low-level signal, the sense amplifier is in a pre-charging stage, and the potentials of the first output end and the second output end of the differential pair are lifted to a preset potential.

[0013] When the enable end of the sense amplifier of the memory is a high-level signal, the sense amplifier is in a working stage, if the first voltage signal input by the bit line is greater than the second voltage signal input by the inverted bit line, the automatic clamp circuit is used for clamping the potential of the second output end of the differential pair at a first preset potential; if the first voltage signal input by the bit line is less than the second voltage signal input by the inverted bit line, the automatic clamp circuit is used for clamping the potential of the first output end of the differential pair at a second preset potential.

[0014] In an optional embodiment, the automatic clamp circuit comprises a fifth NMOS tube and a sixth NMOS tube, the gate of the fifth NMOS tube is electrically connected with the second output end of the differential pair and the second input end of the latch respectively, the drain of the fifth NMOS tube is electrically connected with the first input end of the differential pair, and the source of the fifth NMOS tube is electrically connected with the output end of the tail current source.

[0015] The gate of the sixth NMOS transistor is electrically connected with the first output end of the differential pair and the first input end of the latch respectively, the drain of the sixth NMOS transistor is electrically connected with the second input end of the differential pair, and the source of the sixth NMOS transistor is electrically connected with the output end of the tail current source.

[0016] In an optional embodiment, the latch comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor and a second NMOS transistor.

[0017] The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are preset direct current power sources, the gates of the first PMOS transistor and the fourth PMOS transistor are electrically connected with the enable end of the sense amplifier of the memory respectively, the drain of the first PMOS transistor is electrically connected with the drain of the second PMOS transistor, the gate of the third PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor and the first inverting input end of the inverter respectively.

[0018] The gate of the second PMOS transistor is electrically connected with the gate of the first NMOS transistor, the drain of the second NMOS transistor, the drain of the third PMOS transistor, the drain of the fourth PMOS transistor and the second inverting input end of the inverter respectively.

[0019] The source of the first NMOS transistor is electrically connected with the first output end of the differential pair and the second control end of the automatic clamping circuit respectively, and the source of the second NMOS transistor is electrically connected with the second output end of the differential pair and the first control end of the automatic clamping circuit respectively.

[0020] In an optional embodiment, the differential pair comprises a third NMOS transistor and a fourth NMOS transistor, the gate of the third NMOS transistor is electrically connected with the bit line of the memory, the source of the third NMOS transistor is electrically connected with the first output end of the automatic clamping circuit, and the drain of the third NMOS transistor is electrically connected with the first input end of the latch; the gate of the fourth NMOS transistor is electrically connected with the inverted bit line of the memory, the source of the fourth NMOS transistor is electrically connected with the second output end of the automatic clamping circuit, and the drain of the fourth NMOS transistor is electrically connected with the second input end of the latch.

[0021] In an optional embodiment, the inverter is a preset threshold inverter, the conduction threshold of the preset threshold inverter is greater than a preset threshold voltage, and the preset threshold inverter comprises a first preset threshold inverter and a second preset threshold inverter.

[0022] In an optional embodiment, the inverting input terminal of the first preset threshold inverter is electrically connected with the first output terminal of the latch, and the inverting input terminal of the second preset threshold inverter is electrically connected with the second output terminal of the latch.

[0023] In an optional embodiment, the tail current source comprises a seventh NMOS transistor, a gate of the seventh NMOS transistor is electrically connected with a sense amplifier enable terminal of the memory, a source of the seventh NMOS transistor is grounded, and a drain of the seventh NMOS transistor is respectively electrically connected with the first input terminal and the second input terminal of the automatic clamp circuit.

[0024] In a second aspect, the present application provides a memory, which comprises the sense amplifier as any of the foregoing embodiments.

[0025] In an optional embodiment, the memory comprises at least one of the following: a dynamic random access memory, a static random access memory.

[0026] The present application has the following beneficial effects:

[0027] The sensitive amplifier and the memory provided by the embodiment of the application comprise a tail current source, an automatic clamping circuit, a differential pair, an inverter and a latch; wherein the control end of the tail current source is electrically connected with the sensitive amplifier enable end of the memory, the input end is grounded, and the output end is respectively electrically connected with the first input end and the second input end of the automatic clamping circuit; the first control end of the automatic clamping circuit is respectively electrically connected with the second output end of the differential pair and the second input end of the latch, the second control end of the automatic clamping circuit is respectively electrically connected with the first output end of the differential pair and the first input end of the latch, the first output end of the automatic clamping circuit is electrically connected with the first input end of the differential pair, and the second output end of the automatic clamping circuit is electrically connected with the second input end of the differential pair; the automatic clamping circuit is used for clamping the potential of the first output end or the second output end of the differential pair at a preset potential according to the first voltage signal input by the bit line of the memory and the second voltage signal input by the inverted bit line of the memory in the working stage; the first control end of the differential pair is electrically connected with the bit line of the memory, the second control end is electrically connected with the inverted bit line of the memory, the bit line and the inverted bit line are a pair of differential signal lines; the first control end and the second control end of the latch are respectively electrically connected with the sensitive amplifier enable end of the memory, the first output end is electrically connected with the first inverting input end of the inverter, the second output end is electrically connected with the second inverting input end of the inverter, and the third input end is connected with a preset direct current power supply, so that in the working stage, the potential of the first output end or the second output end of the differential pair can be clamped at the preset potential according to the differential voltage signal output by the differential pair, the potential of the first output end and the second output end of the differential pair is prevented from continuously dropping to a lower potential, and then in the pre-charging stage, the sensitive amplifier can be recharged based on the clamped preset potential, so that the dynamic power consumption of the sensitive amplifier is reduced. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0029] Figure 1 A circuit module schematic diagram of a sensitive amplifier provided by the application;

[0030] Figure 2 A circuit structure schematic diagram of a sensitive amplifier provided by the application;

[0031] Figure 3 Another circuit structure schematic diagram of a sensitive amplifier provided by the application;

[0032] Figure 4A circuit timing diagram of a sense amplifier provided for the present application;

[0033] Figure 5 A module schematic diagram of a memory provided for the present application. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0035] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0036] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0037] The sense amplifier is a key module in the SRAM read path, responsible for quickly amplifying the tiny voltage difference (usually tens of millivolts) on the cell bit line to a logic level. However, as the process node enters the nanometer level (such as below 7nm) and the memory density improves, the power consumption problem of the sense amplifier is increasingly prominent.

[0038] In the related art, the sense amplifier is mainly used to take the read voltage on BL and BLB in the SRAM storage array as an input signal during the working period, and amplify it through the sense amplifier to make the voltage high as "1" and the voltage low as "0", so as to realize the read signal judgment of the SRAM. During the pre-charge stage of the sense amplifier, all its internal nodes are charged to VDD, including the "1" voltage and "0" voltage during the working period. Therefore, each read operation will have a process of charging from "0" voltage to VDD, and the larger the memory of the memory or the higher the read frequency, the higher the power consumption of this part, resulting in more energy required by the memory.

[0039] Therefore, the embodiment of the present application provides a sense amplifier, which comprises an automatic clamping circuit 102, and the potential of the first output end or the second output end of a differential pair 103 can be clamped at a preset potential according to a first voltage signal input by a bit line of a memory and a second voltage signal input by an inverted bit line of the memory when the sense amplifier is in a working stage, so that the sense amplifier can be recharged based on the clamped preset potential in a pre-charging stage, and the dynamic power consumption of the sense amplifier can be reduced.

[0040] Figure 1 A circuit module schematic diagram of a sense amplifier is provided in the present application. Figure 1 As shown in the figure, the sense amplifier comprises a tail current source 101, an automatic clamping circuit 102, a differential pair 103, an inverter 104 and a latch 105.

[0041] The control end of the tail current source 101 is electrically connected with a sense amplifier enable end SAEN of a memory, the input end is grounded, and the output end is respectively electrically connected with the first input end and the second input end of the automatic clamping circuit 102.

[0042] The first control end of the automatic clamping circuit 102 is respectively electrically connected with the second output end of the differential pair 103 and the second input end of the latch 105, the second control end of the automatic clamping circuit 102 is respectively electrically connected with the first output end of the differential pair 103 and the first input end of the latch 105, the first output end of the automatic clamping circuit 102 is electrically connected with the first input end of the differential pair 103, and the second output end of the automatic clamping circuit 102 is electrically connected with the second input end of the differential pair 103; the automatic clamping circuit 102 is used for clamping the potential of the first output end or the second output end of the differential pair 103 at a preset potential according to a first voltage signal input by a bit line of a memory and a second voltage signal input by an inverted bit line of the memory in a working stage.

[0043] The first control end of the differential pair 103 is electrically connected with a bit line of a memory, and the second control end is electrically connected with an inverted bit line of the memory, and the bit line and the inverted bit line are a pair of differential signal lines.

[0044] The first control end and the second control end of the latch 105 are respectively electrically connected with a sense amplifier enable end SAEN of a memory, the first output end is electrically connected with the first inverting input end of the inverter 104, the second output end is electrically connected with the second inverting input end of the inverter 104, and the third input end is connected with a preset direct current power supply.

[0045] Optionally, the inverter 104 can be a standard inverter, wherein the standard inverter can be formed by a standard NMOS tube and a standard PMOS tube to form a transistor structure of a complementary symmetric structure.

[0046] The sensitive amplifier is a key circuit in the memory system for detecting and amplifying a weak signal of a bit line, and a working process of the sensitive amplifier can be divided into a pre-charge phase and a working phase.

[0047] The working principle of the sensitive amplifier is as follows: in the pre-charge phase, the sensitive amplifier is mainly used to pre-charge potentials of the first output end and the second output end of the differential pair 103 to an initial voltage level, so as to provide a stable reference for subsequent data reading, and to eliminate the influence of residual signals of a previous operation; in the working phase, when a bit line (BL) and a bit line bar (BLB) of the memory have a small difference due to stored data, the sensitive amplifier detects the difference and amplifies the difference into a standard logic level, so as to complete data reading.

[0048] The tail current source 101 is configured to provide a preset direct current source; and the differential pair 103 is configured to convert a first voltage signal input by the bit line and a second voltage signal input by the bit line bar into a differential voltage signal.

[0049] The latch 105 is configured to latch an output to the inverter 104 when potentials of the first output end and the second output end of the latch 105 are stable; and the inverter 104 is configured to output a first level signal corresponding to the first voltage signal and a second level signal corresponding to the second voltage signal according to the potentials of the first output end and the second output end of the latch 105.

[0050] In combination with the differential pair 103, the automatic clamp circuit 102 is configured to clamp the potential of the first output end or the second output end of the differential pair 103 at a preset potential according to the differential voltage signal output by the differential pair 103 in the working phase, so as to avoid the potentials of the first output end and the second output end of the differential pair 103 from continuously dropping to a lower potential, and thus in the pre-charge phase, the sensitive amplifier can be recharged based on the clamped preset potential, and the dynamic power consumption of the sensitive amplifier can be reduced.

[0051] In summary, the embodiment of the present application provides a sensitive amplification circuit, comprising: a tail current source, an automatic clamping circuit, a differential pair, an inverter and a latch; wherein the control end of the tail current source is electrically connected with the sensitive amplifier enable end of the memory, the input end is grounded, and the output end is respectively electrically connected with the first input end and the second input end of the automatic clamping circuit; the first control end of the automatic clamping circuit is respectively electrically connected with the second output end of the differential pair and the second input end of the latch, the second control end of the automatic clamping circuit is respectively electrically connected with the first output end of the differential pair and the first input end of the latch, the first output end of the automatic clamping circuit is electrically connected with the first input end of the differential pair, and the second output end of the automatic clamping circuit is electrically connected with the second input end of the differential pair; the automatic clamping circuit is used for clamping the potential of the first output end or the second output end of the differential pair at a preset potential according to the first voltage signal input by the bit line of the memory and the second voltage signal input by the inverted bit line of the memory in the working stage; the first control end of the differential pair is electrically connected with the bit line of the memory, and the second control end is electrically connected with the inverted bit line of the memory, the bit line and the inverted bit line are a pair of differential signal lines; the first control end and the second control end of the latch are respectively electrically connected with the sensitive amplifier enable end of the memory, the first output end is electrically connected with the first inverting input end of the inverter, the second output end is electrically connected with the second inverting input end of the inverter, and the third input end is connected with a preset direct current power supply, so that in the working stage, the potential of the first output end or the second output end of the differential pair can be clamped at a preset potential according to the differential voltage signal output by the differential pair, the potential of the first output end and the second output end of the differential pair is prevented from continuously dropping to a lower potential, and then in the pre-charging stage, the sensitive amplifier can be recharged based on the clamped preset potential, so as to reduce the dynamic power consumption of the sensitive amplifier.

[0052] In an optional embodiment, when the sensitive amplifier enable end SAEN of the memory is a low-level signal, the sensitive amplifier is in a pre-charging stage, and the potential of the first output end and the second output end of the differential pair 103 is lifted to a preset potential.

[0053] When the sensitive amplifier enable end SAEN of the memory is a high-level signal, the sensitive amplifier is in a working stage, if the first voltage signal input by the bit line is greater than the second voltage signal input by the inverted bit line, the automatic clamping circuit 102 is used for clamping the potential of the second output end of the differential pair 103 at a first preset potential; if the first voltage signal input by the bit line is less than the second voltage signal input by the inverted bit line, the automatic clamping circuit 102 is used for clamping the potential of the first output end of the differential pair 103 at a second preset potential.

[0054] If the sensitive amplifier enable end SAEN of the memory is a low-level signal, it can be determined that the sensitive amplifier is in a pre-charging stage, and at this time, the first output end and the second output end of the differential pair 103 can be charged to a preset potential by a preset direct current power source connected to the latch 105.

[0055] If the sensitive amplifier enable end SAEN of the memory is a high-level signal, it indicates that the memory is in a reading operation, and it can be determined that the sensitive amplifier is in a working stage. Further, if the first voltage signal input by the bit line of the memory is greater than the second voltage signal input by the inverted bit line (that is, the BL potential is higher than the BLB potential), at this time, the potential of the second output end of the differential pair 103 can be clamped to the first preset potential by the automatic clamping circuit 102, so as to avoid the potential of the second output end of the differential pair 103 from continuously dropping to a lower potential. If the first voltage signal input by the bit line of the memory is less than the second voltage signal input by the inverted bit line (that is, the BL potential is lower than the BLB potential), at this time, the potential of the first output end of the differential pair 103 can be clamped to the first preset potential by the automatic clamping circuit 102, so as to avoid the potential of the first output end of the differential pair 103 from continuously dropping to a lower potential.

[0056] By applying the embodiment of the present application, when the first voltage signal is greater than the second voltage signal, the potential of the second output end of the differential pair 103 can be clamped to the first preset potential by the automatic clamping circuit 102; and when the first voltage signal is less than the second voltage signal, the potential of the first output end of the differential pair 103 can be clamped to the second preset potential by the automatic clamping circuit 102. Therefore, the automatic clamping function of the automatic clamping circuit 102 can be realized when the memory reads various types of data, the dynamic power consumption of the sensitive amplifier is reduced, and the applicability of the sensitive amplifier is improved.

[0057] Figure 2 A circuit structure schematic diagram of a sensitive amplifier is provided in the present application. In an optional embodiment, as shown in FIG. 1, the circuit structure of the sensitive amplifier includes a differential pair 103, a latch 105, an automatic clamping circuit 102, and a memory. Figure 2 As shown in FIG. 1, in an optional embodiment, the differential pair 103 includes a third NMOS tube NM3 and a fourth NMOS tube NM4. The gate of the third NMOS tube NM3 is electrically connected to the bit line of the memory, the source of the third NMOS tube NM3 is electrically connected to the first output end of the automatic clamping circuit 102, and the drain of the third NMOS tube NM3 is electrically connected to the first input end of the latch 105. The gate of the fourth NMOS tube NM4 is electrically connected to the inverted bit line of the memory, the source of the fourth NMOS tube NM4 is electrically connected to the second output end of the automatic clamping circuit 102, and the drain of the fourth NMOS tube NM4 is electrically connected to the second input end of the latch 105.

[0058] The differential pair 103 can be based on a plurality of NMOS transistors, as shown in the figure. Figure 2 The differential pair 103 can include two NMOS transistors, a third NMOS transistor NM3 and a fourth NMOS transistor NM4. When the sensitive amplifier enable terminal of the memory is a low-level signal, the sensitive amplifier is in a pre-charge stage. At this time, the potential of the first output terminal and the second output terminal of the differential pair 103 can be charged to a preset potential by a preset DC power supply connected to the latch 105. Optionally, the preset potential can be the power supply voltage of the preset DC power supply.

[0059] It should be noted that the differential pair 103 is not limited to the above, and can also include a plurality of PMOS transistors or a plurality of PMOS transistors and a plurality of NMOS transistors according to the actual application scenario. The specific configuration is not limited herein and can be flexibly configured according to the actual application scenario.

[0060] As shown in the figure, Figure 2 The automatic clamp circuit 102 includes a fifth NMOS transistor NM5 and a sixth NMOS transistor NM6. The gate of the fifth NMOS transistor NM5 is electrically connected to the second output terminal of the differential pair 103 and the second input terminal of the latch 105, respectively. The drain of the fifth NMOS transistor NM5 is electrically connected to the first input terminal of the differential pair 103. The source of the fifth NMOS transistor NM5 is electrically connected to the output terminal of the tail current source 101.

[0061] The gate of the sixth NMOS transistor NM6 is electrically connected to the first output terminal of the differential pair 103 and the first input terminal of the latch 105, respectively. The drain of the sixth NMOS transistor NM6 is electrically connected to the second input terminal of the differential pair 103. The source of the sixth NMOS transistor NM6 is electrically connected to the output terminal of the tail current source 101.

[0062] In an optional embodiment, the tail current source 101 includes a seventh NMOS transistor NM7. The gate of the seventh NMOS transistor NM7 is electrically connected to the sensitive amplifier enable terminal of the memory. The source of the seventh NMOS transistor NM7 is grounded. The drain of the seventh NMOS transistor NM7 is electrically connected to the first input terminal and the second input terminal of the automatic clamp circuit 102, respectively.

[0063] The working principle of the automatic clamp circuit 102 is as follows: when the sensitive amplifier enable end of the memory is a high-level signal, the sensitive amplifier is in the working stage, at this time, the seventh NMOS tube NM7 is turned on, and the tail current source 101 can provide a discharge loop for the circuit; when the first voltage signal input by the bit line is less than the second voltage signal input by the inverted bit line (that is, the BLB potential is greater than the BL potential), the charge discharge speed of the second output end CB1 of the differential pair 103 will be greater than the charge discharge speed CT1 of the first output end of the differential pair 103, so that the potential of the second output end CB1 of the differential pair 103 is less than the potential of the first output end CT1 of the differential pair 103.

[0064] Further, since the second output end CB1 of the differential pair 103 is connected to the gate of the fifth NMOS tube NM5, and the first output end CT1 of the differential pair 103 is connected to the gate of the sixth NMOS tube NM6, the potential of the second output end CB1 of the differential pair 103 is less than the potential of the first output end CT1 of the differential pair 103, which will make the conduction degree of the fifth NMOS tube NM5 less than the conduction degree of the sixth NMOS tube NM6, and thus further amplify the potential drop speed of the second output end CB1 of the differential pair 103.

[0065] When the potential of the second output end CB1 of the differential pair 103 drops to less than the threshold voltage of the fifth NMOS tube NM5, the fifth NMOS tube NM5 is turned off, the first output end CT1 of the differential pair 103 is clamped to the potential corresponding to the off state of the fifth NMOS tube NM5, and the second output end CB1 of the differential pair 103 continues to discharge; and the preset direct current source connected through the latch 105 can continuously act on the first output end CT1 of the differential pair 103, so that the potential of the first output end CT1 of the differential pair 103 starts to rise and rises to approximately equal to the potential of the first output end of the latch 105, and then starts to stabilize, at this time, the potential of the first output end CT1 of the differential pair 103 will be greater than the threshold voltage of the sixth NMOS tube NM6, therefore, the sixth NMOS tube NM6 will remain in the conduction state, and the second output end CB1 of the differential pair 103 continues to discharge to a lower potential.

[0066] Figure 3 Another schematic circuit structure of a sensitive amplifier provided in the present application. Figure 4 A circuit timing diagram of a sensitive amplifier provided in the present application. In an optional embodiment, as shown in Figure 3 The latch 105 includes a first PMOS tube PM1, a second PMOS tube PM2, a third PMOS tube PM3, a fourth PMOS tube PM4, a first NMOS tube NM1, and a second NMOS tube NM2.

[0067] The source of the first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 is connected to a preset DC power supply, the gate of the first PMOS PM1 and the fourth PMOS PM4 is connected to the sensitive amplifier enable end of the memory, the drain of the first PMOS PM1 is connected to the drain of the second PMOS PM2, the gate of the third PMOS PM3, the drain of the first NMOS NM1, the gate of the second NMOS NM2 and the first inverting input end of the inverter 104.

[0068] The gate of the second PMOS PM2 is connected to the gate of the first NMOS NM1, the drain of the second NMOS NM2, the drain of the third PMOS PM3, the drain of the fourth PMOS NM4 and the second inverting input end of the inverter 104.

[0069] The source of the first NMOS NM1 is connected to the first output end of the differential pair 103 and the second control end of the automatic clamping circuit 102, and the source of the second NMOS NM2 is connected to the second output end of the differential pair 103 and the first control end of the automatic clamping circuit 102.

[0070] In combination with the above circuit, when the sensitive amplifier is in the initial pre-charging stage, the working principle of the latch 105 is as follows: the sensitive amplifier enable end SAEN signal of the memory is low, and the seventh NMOS NM7 is cut off. In the initial stage, the first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 are turned on. The turn-on of the first PMOS PM1 and the fourth PMOS PM4 will raise the potential of the first inverting input end XT1 of the inverter 104 and the second inverting input end XB1 of the inverter 104. When the potential of the first inverting input end XT1 is raised to the threshold voltage of the second PMOS PM2, the second PMOS PM2 is cut off. When the potential of the second inverting input end XB1 is raised to the threshold voltage of the third PMOS PM3, the third PMOS PM3 is cut off.

[0071] Wherein, when the potential of the first inverting input end XT1 is continuously raised, the first preset threshold inverter will be pulled down to a lower potential, and when the potential of the second inverting input end XB1 is continuously raised, the second preset threshold inverter will be pulled down to a lower potential.

[0072] Further, when the potential of the first inverting input terminal XT1 is continuously raised to be greater than the threshold voltage of the first NMOS transistor NM1, the first NMOS transistor NM1 is turned on, at this time, the charge is transmitted to the source of the first NMOS transistor NM1 (i.e., the first output terminal of the differential pair 103), and the first output terminal of the differential pair 103 is raised to the preset potential; when the potential of the second inverting input terminal XB1 is continuously raised to be greater than the threshold voltage of the second NMOS transistor NM2, the second NMOS transistor NM2 is turned on, at this time, the charge is transmitted to the source of the second NMOS transistor NM2 (i.e., the second output terminal of the differential pair 103), and the second output terminal of the differential pair 103 is raised to the preset potential.

[0073] In addition, when the sense amplifier is in the working stage, the working principle of the latch 105 is as follows: the sense amplifier enable end SAEN signal of the memory is at a high potential, if the first voltage signal input by the bit line is less than the second voltage signal input by the inverting bit line, as shown in FIG. 5, at t1, the potential value of BLB is 750 mV, and the potential value of BL is 720 mV, that is, the potential of BLB is greater than the potential of BL, and t2 is a working time of the working stage in which the potential of BLB is less than the potential of BL. Figure 4

[0074] Based on the above description, when the sense amplifier enable end SAEN of the memory is at a low level signal, the sense amplifier is in the pre-charge stage, and there is no voltage difference between the first voltage signal BL input by the bit line of the memory and the second voltage signal BLB input by the inverting bit line of the memory, since the first PMOS transistor PM1 and the fourth PMOS transistor PM4 are turned on, the first inverting input terminal XT1 and the second inverting input terminal XB1 are both pre-charged to the power supply voltage, the turn-on capability of NM1 and NM2 is the same, and therefore CT1 and CB1 are also the same.

[0075] Further, when the first voltage signal BL input by the bit line of the memory is less than the second voltage signal BLB input by the inverting bit line of the memory, there is a voltage difference between BL and BLB, and the sense amplifier enable end SAEN of the memory is at a low level signal, the voltage of the first inverting input terminal XT1 is equal to the voltage of the second inverting input terminal XB1, at this time, since the VGS of the third NMOS transistor NM3 is less than 0 (VGS is the Gate terminal voltage-Source terminal voltage), NM3 is in the cut-off state, and the VGS of NM4 is greater than 0 and less than the corresponding threshold voltage, NM4 is in the leakage state, therefore, due to the cut-off of NM3, the first inverting input terminal XT1 continues to charge CT1, and therefore the potential of CT1 is higher than that of CB1.

[0076] ​For better understanding of the present application, the following will be described in conjunction with a specific timing diagram. When the sense amplifier enable end SAEN of the memory is a high level signal, the sense amplifier is in a working stage, wherein the working stage can be divided into a pre-working stage and a stable stage, and the stable stage is located after the pre-working stage.

[0077] In the pre-working stage, the first PMOS PM1 and the fourth PMOS PM4 are closed, and since the potential of the first inverting input end XT1 is not reduced to the turn-on voltage of the third PMOS PM3, and since the potential of the second inverting input end XB1 is not reduced to the turn-on voltage of the second PMOS PM2, the second PMOS PM2 and the third PMOS PM3 are both closed, at this time, the first inverting input end XT1 and the second inverting input end XB1 are temporarily in a passive state, and since the turn-on capabilities of the first NMOS NM1 and the second NMOS NM2 are the same in the initial stage and are in a weak turn-on state, the potential drop speed of the first drain CT1 of the differential pair 103 is much greater than that of the second drain CB1 of the differential pair 103, thereby causing the potential of the first inverting input end XT1 to reach the threshold voltage of the second PMOS PM2 and the third PMOS PM3 earlier than that of the second inverting input end XB1 when the NM5 is turned off, as shown in FIG. 2, at t1, the potential of the first inverting input end XT1 is 294.9 mV, and the potential of the second inverting input end XB1 is 573.0 mV, the potential of the first inverting input end XT1 is less than that of the second inverting input end XB1, wherein the threshold voltage of the second PMOS PM2 is equal to that of the third PMOS PM3, and the third PMOS PM3 is turned on earlier than the second PMOS PM2. Figure 4

[0078] In addition, since the potential of the first inverting input end XT1 is lower than the threshold voltage of the first NMOS NM1 and the second NMOS NM2 earlier than that of the second inverting input end XB1, the second NMOS NM2 is turned off earlier than the first NMOS NM1, wherein the threshold voltage of the first NMOS NM1 is equal to that of the second NMOS NM2, and after the potential of the second inverting input end XB1 is pulled up to a higher value (for example, 573 mV), the stable stage is entered.

[0079] In the stable stage, the potential of the second inverting input end XB1 will be greater than the threshold value of the inverter 104, the second inverting output end of the inverter 104 will output a logic level 0, and the first inverting output end of the inverter 104 will output a logic level 1, as shown in FIG. 2, at t1, the potential value of BLBO is 737.1 mV, that is, corresponding to a logic level 1, and the potential value of BLO is 1.37 mV, that is, corresponding to a logic level 0. Figure 4

[0080] ​​As can be seen from the embodiments of this application, when BLB is greater than BL, the first inverting output terminal of the inverter 104 will output a logic level of 1, and the second inverting output terminal of the inverter 104 will output a logic level of 0; wherein, when BLB is less than BL, as can be seen from the above working principle, the first inverting output terminal of the inverter 104 will output a logic level of 0, and the second inverting output terminal of the inverter 104 will output a logic level of 1.

[0081] like Figure 4 As shown, it should also be noted that if the current working phase is completed, the sensitive amplifier will enter the next pre-charge cycle. The potential of the first output terminal CT1 of the differential pair 103 will be increased from 294mV to the preset DC power supply voltage, the potential of the second output terminal CB1 of the differential pair 103 will be increased from 61.6mV to the preset DC power supply voltage, the potential of the first inverting input terminal XT1 will be increased from 294.9mV to the preset DC power supply voltage, and the potential of the second inverting input terminal XB1 will be increased from 573.0mV to the preset DC power supply voltage. Compared with the prior art, a certain amount of charge can be retained, avoiding complete discharge during the working phase. This allows charging to be performed based on the currently retained potential in the next pre-charge phase, effectively reducing the power consumption of the sensitive amplifier.

[0082] It should be noted that, as Figure 4 As shown, time t2 is the time point of the working cycle when the BLB potential is greater than the BL potential. For an explanation of time t2, please refer to the relevant content of time t1 above, which will not be repeated here.

[0083] In an optional implementation, inverter 104 is a preset threshold inverter, the conduction threshold of which is greater than a preset threshold voltage. The preset threshold inverter includes a first preset threshold inverter HVT-INV1 and a second preset threshold inverter HVT-INV2.

[0084] The preset threshold inverter 104 can be a high threshold inverter. Compared with a standard inverter, a standard inverter refers to a transistor structure that forms a complementary symmetry structure with one standard NMOS transistor and one standard PMOS transistor. A high threshold inverter is an inverter 104 that forms a complementary symmetry structure with one high threshold NMOS transistor (N-HVT) and one high threshold PMOS transistor (P-HVT).

[0085] like Figure 3 As shown, the high threshold inverter may include: a first preset threshold inverter (i.e., the first high threshold inverter HVT-INV1) and a second preset threshold inverter (i.e., the second high threshold inverter HVT-INV2).

[0086] Based on the above analysis, it can be understood that by setting the above inverter 104 as a high threshold inverter, when the first preset threshold inverter node potential drops, the high threshold PMOS tube in the first preset threshold inverter will be turned on before the third PMOS tube PM3, the first inverting output will output logic level 1, and the second inverting output will output logic level 0 correspondingly. Compared with the existing use of standard inverter 104 elements as the output flip-flop circuit, by setting the use of high threshold inverter as the output flip-flop circuit, the threshold of the high threshold PMOS tube inside the high threshold inverter is less than the threshold voltage of the standard PMOS tube in the standard threshold inverter 104. Therefore, the high threshold inverter can invert the output when the potential of the first inverting input XT1 and the second inverting input XB1 drops lower, avoiding the inverting output caused by the insufficient potential of the first inverting input XT1 and the second inverting input XB1, that is, avoiding the reduction of the output margin of the sensitive amplifier, and can improve the read accuracy of the sensitive amplifier.

[0087] In an optional embodiment, the inverting input end of the first preset threshold inverter is electrically connected with the first output end of the latch 105, and the inverting input end of the second preset threshold inverter is electrically connected with the second output end of the latch 105.

[0088] Referring to the above Figure 3 It is shown that the inverting input end of the first preset threshold inverter is electrically connected with the first output end of the latch 105 (i.e., the drain of the first NMOS tube NM1), and the inverting input end of the second preset threshold inverter is electrically connected with the second output end of the latch 105 (i.e., the drain of the second NMOS tube NM2).

[0089] It should be noted that the present application does not limit the specific setting mode of the above tail current source 101, automatic clamping circuit 102, differential pair 103, inverter 104 and latch 105. According to the actual application scene, for each module, according to the actual application scene, part or all of the PMOS tubes therein can be replaced by NMOS tubes, or part or all of the NMOS tubes therein can be replaced by PMOS tubes, which is not limited here, and can be flexibly set according to the actual application scene.

[0090] Figure 5 A module schematic diagram of a memory provided by the present application is shown in FIG. 2. Figure 5 As shown in the figure, the memory 200 can include the sensitive amplifier 100 of the foregoing embodiments.

[0091] In an optional embodiment, the memory 200 comprises at least one of a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM).

[0092] Of course, it needs to be explained that the present application does not limit the specific type of the memory here, and other types of memories including sensitive amplifiers can also be used according to the actual application scene.

[0093] By applying the embodiments of the present application, the first voltage signal is greater than the second voltage signal, and the potential of the second output end of the differential pair can be clamped at the first preset potential through the automatic clamping circuit; the first voltage signal is less than the second voltage signal, and the potential of the first output end of the differential pair can be clamped at the second preset potential through the automatic clamping circuit, so that the memory can realize the potential clamping function through the automatic clamping circuit when reading various types of data, the dynamic power consumption of the sensitive amplifier is reduced, and then the reading energy consumption of the memory can be reduced.

[0094] It needs to be explained that in this paper, the relationship terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0095] The above is only the preferred embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that similar reference numbers and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. The above is only the preferred embodiment of the present application and is not used to limit the present application. For those skilled in the art, the present application can have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A sensitive amplifier, characterized in that, The sensitive amplifier includes: a tail current source, an automatic clamping circuit, a differential pair, an inverter, and a latch; The control terminal of the tail current source is electrically connected to the enable terminal of the sensitive amplifier of the memory, the input terminal is grounded, and the output terminal is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit, respectively. The first control terminal of the automatic clamping circuit is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively. The second control terminal of the automatic clamping circuit is electrically connected to the first output terminal of the differential pair and the first input terminal of the latch, respectively. The first output terminal of the automatic clamping circuit is electrically connected to the first input terminal of the differential pair, and the second output terminal of the automatic clamping circuit is electrically connected to the second input terminal of the differential pair. The automatic clamping circuit is used to clamp the potential of the first output terminal or the second output terminal of the differential pair at a preset potential according to the first voltage signal input to the bit line of the memory and the second voltage signal input to the inverse phase line of the memory during the working phase. The first control terminal of the differential pair is electrically connected to the bit line of the memory, and the second control terminal is electrically connected to the anti-phase line of the memory. The bit line and the anti-phase line are a pair of differential signal lines. The first control terminal and the second control terminal of the latch are electrically connected to the enable terminal of the sensitive amplifier of the memory, the first output terminal is electrically connected to the first inverting input terminal of the inverter, the second output terminal is electrically connected to the second inverting input terminal of the inverter, and the third input terminal is connected to a preset DC power supply. When the enable terminal of the memory's sensitive amplifier is a low-level signal, the sensitive amplifier is in a pre-charging phase, and the potentials of the first and second output terminals of the differential pair are raised to a preset potential. When the enable signal of the memory's sensitive amplifier is high, the sensitive amplifier is in operation. If the first voltage signal input to the bit line is greater than the second voltage signal input to the anti-phase line, the automatic clamping circuit clamps the potential of the second output terminal of the differential pair to a first preset potential. If the first voltage signal input to the bit line is less than the second voltage signal input to the anti-phase line, the automatic clamping circuit clamps the potential of the first output terminal of the differential pair to a second preset potential.

2. The sensitive amplifier according to claim 1, characterized in that, The automatic clamping circuit includes a fifth NMOS transistor and a sixth NMOS transistor. The gate of the fifth NMOS transistor is electrically connected to the second output terminal of the differential pair and the second input terminal of the latch, respectively. The drain of the fifth NMOS transistor is electrically connected to the first input terminal of the differential pair, and the source of the fifth NMOS transistor is electrically connected to the output terminal of the tail current source. The gate of the sixth NMOS transistor is electrically connected to the first output terminal of the differential pair and the first input terminal of the latch, respectively. The drain of the sixth NMOS transistor is electrically connected to the second input terminal of the differential pair, and the source of the sixth NMOS transistor is electrically connected to the output terminal of the tail current source.

3. The sensitive amplifier according to claim 1, characterized in that, The latch includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are all preset with DC power supplies. The gates of the first PMOS transistor and the fourth PMOS transistor are electrically connected to the enable terminal of the sensitive amplifier of the memory. The drain of the first PMOS transistor is electrically connected to the drain of the second PMOS transistor, the gate of the third PMOS transistor, the drain of the first NMOS transistor, the gate of the second NMOS transistor, and the first inverting input terminal of the inverter. The gate of the second PMOS transistor is electrically connected to the gate of the first NMOS transistor, the drain of the second NMOS transistor, the drain of the third PMOS transistor, the drain of the fourth PMOS transistor, and the second inverting input terminal of the inverter, respectively. The source of the first NMOS transistor is electrically connected to the first output terminal of the differential pair and the second control terminal of the automatic clamping circuit, respectively. The source of the second NMOS transistor is electrically connected to the second output terminal of the differential pair and the first control terminal of the automatic clamping circuit, respectively.

4. The sensitive amplifier according to claim 1, characterized in that, The differential pair includes a third NMOS transistor and a fourth NMOS transistor. The gate of the third NMOS transistor is electrically connected to a bit line of the memory, the source of the third NMOS transistor is electrically connected to the first output terminal of the automatic clamping circuit, and the drain of the third NMOS transistor is electrically connected to the first input terminal of the latch. The gate of the fourth NMOS transistor is electrically connected to the inverse phase line of the memory, the source of the fourth NMOS transistor is electrically connected to the second output terminal of the automatic clamping circuit, and the drain of the fourth NMOS transistor is electrically connected to the second input terminal of the latch.

5. The sensitive amplifier according to claim 1, characterized in that, The inverter is a preset threshold inverter, and the conduction threshold of the preset threshold inverter is greater than the preset threshold voltage. The preset threshold inverter includes a first preset threshold inverter and a second preset threshold inverter.

6. The sensitive amplifier according to claim 5, characterized in that, The inverting input terminal of the first preset threshold inverter is electrically connected to the first output terminal of the latch, and the inverting input terminal of the second preset threshold inverter is electrically connected to the second output terminal of the latch.

7. The sensitive amplifier according to any one of claims 1-6, characterized in that, The tail current source includes a seventh NMOS transistor, the gate of which is electrically connected to the enable terminal of the sensitive amplifier of the memory, the source of which is grounded, and the drain of which is electrically connected to the first input terminal and the second input terminal of the automatic clamping circuit, respectively.

8. A memory, characterized in that, The memory includes a sensitive amplifier as described in any one of claims 1-7.

9. The memory according to claim 8, characterized in that, The memory includes at least one of the following: dynamic random access memory and static random access memory.

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