Memory and preparation method thereof

Abstract

The invention discloses a memory and a preparation method thereof, and belongs to the technical field of semiconductors. The memory comprises at least one word line, at least one bit line, a source line and at least one memory unit, the memory unit comprises two transistors and a memristor; grid electrodes of the two transistors in the memory unit are connected with the same word line, source electrodes of the two transistors in the memory unit are connected with the source line, and drain electrodes of the two transistors in the memory unit are respectively connected with a first electrode of the memristor. And the second electrode of the memristor in the memory unit is connected with one bit line. The driving current of the memristor can be improved, so that the storage performance is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor photoelectric sensors for nuclear technology applications, and in particular to a memory and a method for preparing the same. Background Art

[0002] Memristors are a new type of non-volatile memory. Their structure typically consists of a stacked bottom electrode, a resistive material layer, and a top electrode. Memristors offer advantages such as high speed, low power consumption, simple processing, and amenability to downstream integration, making them a promising new type of semiconductor memory. Memristors store information by switching between conductive (or resistive) states. In practice, applying a voltage pulse of a specific amplitude and pulse width to a memristor changes its resistance, enabling data writing. Data can be read by measuring the resistance of the memristor.

[0003] In related art, memristors are often connected in series with transistors to form a 1-transistor-1-memristor structure (1T1R structure), forming a memory array in the form of a crossbar switch matrix. This memory array usually has multiple crossed word lines (WL) and bit lines (BL), as well as a connected source line (SL). When a memristor is selected, a high voltage Vpass needs to be applied to the corresponding word line to turn on the corresponding transistor, the voltage of other word lines is 0V to turn off other transistors, and an operating voltage Vopr is applied to the corresponding bit line. The voltage of other bit lines is 0V, and the source line voltage is 0V, so that the voltage across the selected memristor reaches the operating voltage Vopr, realizing the memristor read and write function. However, the driving current of this 1T1R structure is relatively small, resulting in poor storage performance of the memristor. Summary of the Invention

[0004] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a memory and a method for manufacturing the same, which can increase the driving current of a memristor, thereby improving storage performance.

[0005] In a first aspect, the present application provides a memory comprising at least one word line, at least one bit line, a source line, and at least one memory cell; the memory cell comprises two transistors and a memristor;

[0006] The gates of the two transistors in the memory cell are connected to the same word line, the sources of the two transistors in the memory cell are connected to the source line, the drains of the two transistors in the memory cell are respectively connected to the first electrode of the memristor, and the second electrode of the memristor in the memory cell is connected to one of the bit lines.

[0007] According to the memory of the present application, a 2T1R structure is formed by setting two transistors and a memristor in the storage unit. Both transistors serve as driving transistors to increase the driving current of the memristor, thereby improving the data reading and writing speed of the memristor and improving storage performance.

[0008] According to one embodiment of the present application, the plurality of memory cells are distributed in multiple rows and columns;

[0009] The second electrodes of the memristors in each row of memory cells are connected to one of the bit lines, the gates of the transistors in each column of memory cells are connected to one of the word lines, and the sources of the transistors in each memory cell are connected to the source line.

[0010] According to one embodiment of the present application, the memory includes:

[0011] A stacked structure comprising a first conductive layer, a first insulating layer, and a composite layer alternately stacked along a first direction, wherein the composite layer comprises a second conductive layer and a second insulating layer stacked along the first direction; the stacked structure comprising a step region, wherein the first conductive layer, the first insulating layer, and the composite layer form a step structure in the step region;

[0012] an electrode structure, comprising an electrode substructure disposed corresponding to a target step formed by the composite layer, the electrode substructure covering a sidewall of the target step;

[0013] a gate structure covering the electrode structure and the step structure;

[0014] The first conductive layer includes the source and the source line connected to each other, the second conductive layer includes the second electrode and the bit line connected to each other, the electrode substructure includes the first electrode and the drain connected to each other, and the gate structure includes the gate and the word line connected to each other.

[0015] According to one embodiment of the present application, the step area is located on one side of the stacking structure along the second direction and extends along a third direction; the third direction, the second direction and the first direction are perpendicular to each other;

[0016] The memory includes a plurality of gate structures, wherein the gate structures extend along the second direction, and the plurality of gate structures are spaced apart and distributed along the third direction.

[0017] According to one embodiment of the present application, the stacked structure includes a plurality of step areas distributed at intervals;

[0018] The memory includes a plurality of electrode structures and a plurality of gate structures, and each step region is correspondingly provided with one electrode structure and one gate structure.

[0019] According to one embodiment of the present application, the electrode substructure includes a resistive switching layer and a third conductive layer;

[0020] The resistive layer covers the sidewalls of the target step and at least a portion of the upper surface of the next step. The third conductive layer covers the resistive layer. The third conductive layer includes the first electrode and the drain electrode connected to each other.

[0021] According to one embodiment of the present application, the gate structure includes a channel layer, a gate dielectric layer and a gate layer;

[0022] The channel layer covers the electrode structure and the step structure, the gate dielectric layer covers the channel layer, the gate layer covers the gate dielectric layer, and the gate layer includes the gate and the word line connected to each other.

[0023] According to one embodiment of the present application, the electrode structure further includes redundant substructures corresponding to each step other than the target step, and the redundant substructures cover the sidewalls of the corresponding step and a portion of the upper surface of the next step.

[0024] According to one embodiment of the present application, the memory further includes:

[0025] A source line connection structure, through which the source lines in the plurality of first conductive layers are connected.

[0026] In a second aspect, the present application provides a method for preparing a memory, wherein the memory includes at least one word line, at least one bit line, a source line, and at least one memory cell; the memory cell includes two transistors and a memristor;

[0027] The method comprises:

[0028] forming a stacked structure, the stacked structure comprising a first conductive layer, a first insulating layer, and a composite layer alternately stacked along a first direction, the composite layer comprising a second conductive layer and a second insulating layer stacked along the first direction; the stacked structure comprising a step region, the first conductive layer, the first insulating layer, and the composite layer forming a step structure in the step region;

[0029] forming an electrode structure in the step region, the electrode structure comprising an electrode substructure arranged corresponding to the target step formed by the composite layer, the electrode substructure covering a sidewall of the target step;

[0030] forming a gate structure covering the electrode structure and the step structure;

[0031] The first conductive layer includes the source of the transistor and the source line connected to each other, the electrode substructure includes the first electrode of the memristor and the drain of the transistor connected to each other, the second conductive layer includes the second electrode of the memristor and the bit line connected to each other, and the gate structure includes the gate of the transistor and the word line connected to each other.

[0032] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0033] By setting two transistors and a memristor in the memory cell to form a 2T1R structure, both transistors act as drive transistors to increase the drive current of the memristor, thereby increasing the data reading and writing speed of the memristor and improving storage performance;

[0034] Furthermore, by providing a stacked structure, a step region of the stacked structure forms a step structure, and an electrode structure and a gate structure are provided on the step structure, so that the memory cells are stacked, thereby effectively improving the integration density of the memory cells.

[0035] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become obvious from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0037] Figure 1 This is one of the circuit diagrams of the memory provided in the embodiment of the present application;

[0038] Figure 2 This is the second circuit diagram of the memory provided in the embodiment of the present application;

[0039] Figure 3 This is one of the cross-sectional schematic diagrams of the memory provided in the embodiment of the present application;

[0040] Figure 4 This is one of the top views of the memory provided in the embodiment of the present application;

[0041] Figure 5 This is the second cross-sectional schematic diagram of the memory provided in the embodiment of the present application;

[0042] Figure 6 This is the second top view of the memory provided in the embodiment of the present application;

[0043] Figure 7 1 is a flow chart of a method for preparing a memory provided in an embodiment of the present application;

[0044] Figure 8 This is one of the structural diagrams of the method for preparing a memory provided in an embodiment of the present application;

[0045] Figure 9 This is the second structural diagram of the method for preparing the memory provided in the embodiment of the present application;

[0046] Figure 10 This is the third structural diagram of the method for preparing the memory provided in the embodiment of the present application;

[0047] Figure 11 This is the fourth structural diagram of the method for preparing the memory provided in the embodiment of the present application. DETAILED DESCRIPTION

[0048] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0049] The memory and its manufacturing method provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0050] Figure 1 and Figure 2 A circuit schematic diagram of the memory provided in an embodiment of the present application.

[0051] like Figure 1 As shown, the memory provided by the embodiment of the present application includes at least one word line WL, at least one bit line BL, a source line SL and at least one memory cell 10. The memory cell 10 includes two transistors T and a memristor R.

[0052] The gates of the two transistors T in the memory cell 10 are connected to the same word line WL, the sources of the two transistors T in the memory cell 10 are connected to the source line SL, the drains of the two transistors T in the memory cell 10 are respectively connected to the first electrode of the memristor R, and the second electrode of the memristor R in the memory cell 10 is connected to a bit line BL.

[0053] Wherein, both transistors T are driving transistors. The transistors T may be classified by material and may include transistors based on different materials (including but not limited to silicon-based transistors, compound semiconductor transistors, thin film oxide transistors, two-dimensional material transistors, etc.). The transistors T may be classified by conductivity type and may include P-type or N-type transistors.

[0054] When reading and writing data in the memory cell 10, a high voltage is applied to the word line WL connected to the memory cell 10 to turn on the two transistors T in the memory cell 10, an operating voltage is applied to the bit line BL connected to the memory cell 10, and a 0V voltage is applied to the source line SL, so that the voltage across the memristor R in the memory cell 10 reaches the operating voltage, thereby realizing the read and write functions of the memristor R.

[0055] In this embodiment, two transistors T are provided in the memory unit 10. By driving the two transistors T to be turned on, the driving current of the memristor R is increased, thereby increasing the data reading and writing speed of the memristor and improving the storage performance.

[0056] In some embodiments, the plurality of memory cells 10 are arranged in multiple rows and columns. Each column of memory cells includes at least one memory cell 10, each row of memory cells includes at least one memory cell 10, and at least one memory cell 10 in each row of memory cells can be arranged in a row or in an array.

[0057] The second electrode of the memristor R in each row of memory cells is connected to a bit line BL, the gate of the transistor T in each column of memory cells is connected to a word line WL, and the source of the transistor T in each memory cell 10 is connected to a source line SL.

[0058] Multiple rows of memory cells are connected to multiple bit lines BL in a one-to-one correspondence, and the second electrodes of all memristors R in each row of memory cells are connected to the same bit line BL. Multiple columns of memory cells are connected to multiple word lines WL in a one-to-one correspondence, and the gates of all transistors T in each column of memory cells are connected to the same word line WL. The sources of the transistors T in all memory cells 10 are connected to a source line SL.

[0059] For example Figure 2 As shown, multiple memory cells 10 are arranged in three rows and three columns. The multiple bit lines BL include a first bit line BL0, a second bit line BL1, and a third bit line BL2, and the multiple word lines WL include a first word line WL0, a second word line WL1, and a third word line WL2. The gates of all transistors T in the first column of memory cells are connected to the first word line WL0, the gates of all transistors T in the second column of memory cells are connected to the second word line WL1, and the gates of all transistors T in the third column of memory cells are connected to the third word line WL2. The second electrodes of all memristors R in the first row of memory cells are connected to the first bit line BL0, the second electrodes of all memristors R in the second row of memory cells are connected to the second bit line BL1, and the second electrodes of all memristors R in the third row of memory cells are connected to the third bit line BL2. The sources of the transistors T in all memory cells 10 are connected to the source line SL.

[0060] When selecting a memory cell 10 (e.g., memory cell 10a in the first row and first column) for data reading or writing, a high voltage is applied to the first word line WL0 connected to memory cell 10a, turning on transistors T in the memory cells in the first column. A 0V voltage is applied to the other word lines (i.e., the second word line WL1 and the third word line WL2), turning off the transistors in the memory cells in the second and third columns. An operating voltage is applied to the first bit line BL0 connected to memory cell 10a, a 0V voltage is applied to the other bit lines (i.e., the second bit line BL1 and the second bit line BL2), and a 0V voltage is applied to the source line SL. The voltage across memristor R in memory cell 10a reaches the operating voltage, enabling the read and write functions of memristor R in memory cell 10a.

[0061] It should be noted that although the transistors in the memory cells other than memory cell 10a in the first column are turned on, no operating voltage is applied to the drains, so that the memristors R in the other memory cells do not perform read or write operations. Although the operating voltage is applied to the drains of the transistors in the memory cells other than memory cell 10a in the first row, no turn-on voltage is applied to the gates, so that the memristors R in the other memory cells do not perform read or write operations. In addition, the memory cells other than memory cell 10a in the first row are not affected by the operating voltage. The voltage drop across the memristor R is reduced to 0V by the two transistors T connected in series in the other memory cells.

[0062] In some embodiments, multiple rows of memory cells may be distributed in a vertical direction, and multiple columns of memory cells may be distributed in a horizontal direction, so that multiple memory cells 10 form a three-dimensional memory array, effectively improving the integration density of the memory cells.

[0063] In some embodiments, as Figure 3 As shown, the memory includes a stack structure 1 , an electrode structure 2 and a gate structure 3 .

[0064] The stacked structure 1 includes a first conductive layer 11, a first insulating layer 12, and a composite layer 13 alternately stacked along a first direction X. The composite layer 13 includes a second conductive layer 14 and a second insulating layer 15 stacked along the first direction X. The number of first conductive layers 11, first insulating layers 12, and composite layers 13 can be multiple. The first conductive layers 11, first insulating layers 12, and composite layers 13 stacked in sequence can constitute a repeating unit, and multiple repeating units are stacked along the first direction X. The first direction X can be a vertical direction.

[0065] The number of first conductive layers 11, first insulating layers 12, and composite layers 13 can be set according to actual needs and are not specifically limited here. The materials of the first conductive layer 11 and the second conductive layer 14 can be the same, including but not limited to inert metal materials such as Pt, Pd, Ir and their alloys, metal materials such as Ta, Hf, Ti, Zr, W, Ru, Al and their alloys, and metallic compound materials such as TiN, TaN, and Poly-Si. The materials of the first insulating layer 12 and the second insulating layer 15 can be the same, including but not limited to silicon oxide, silicon nitride, etc.

[0066] The stacked structure 1 includes a step region A, where the first conductive layer 11, the first insulating layer 12, and the composite layer 13 form a step structure. The step structure includes multiple steps, where each first conductive layer 11, each first insulating layer 12, and each composite layer 13 forms a corresponding step in the step region A.

[0067] The stacking structure 1 also includes a non-step area located outside the step area A. The step direction of the step structure is inclined toward the non-step area, that is, in the direction from the bottom layer to the top layer of the stacking structure 1, the cross-sectional area of ​​the film layer corresponding to multiple steps gradually decreases.

[0068] In some embodiments, the stacked structure 1 further includes a third insulating layer 16 , which is located at the bottom layer of the stacked structure 1 , and the first conductive layer 11 , the first insulating layer 12 and the composite layer 13 are alternately stacked along the first direction X on the third insulating layer 16 .

[0069] Electrode structure 2 includes an electrode substructure 2a disposed corresponding to the target step formed by composite layer 13. Electrode substructure 2a covers the sidewalls of the target step, i.e., electrode substructure 2a contacts the sidewalls of the target step. In other words, electrode substructure 2a contacts the side surfaces of composite layer 13 (including second conductive layer 14 and second insulating layer 15) in step region A. Electrode substructure 2a also covers at least a portion of the upper surface of the next step below the target step, i.e., electrode substructure 2a also covers at least a portion of the upper surface of first insulating layer 12 in step region A.

[0070] The number of electrode substructures 2a in the electrode structure 2 may be the same as the number of composite layers 13. Each composite layer 13 constitutes a target step, and an electrode substructure 2a is provided on the sidewall of each target step.

[0071] The gate structure 3 covers the electrode structure 2 and the step structure. The gate structure 3 extends along the step direction to cover each electrode substructure 2a in the electrode structure 2 and each step in the step structure, so that the gate structure 3 contacts each first conductive layer 11 and each electrode substructure 2a.

[0072] The first conductive layer 11 includes a connected source and source line, that is, the first conductive layer 11 includes the source and source line SL of the transistor T, and the source and source line SL of the transistor T are connected. The second conductive layer 14 includes a connected second electrode and bit line, that is, the second conductive layer 14 includes the second electrode of the memristor R and the bit line BL, and the second electrode of the memristor R and the bit line BL are connected. The electrode substructure 2a includes a connected first electrode and drain, that is, the electrode substructure 2a includes the first electrode of the memristor R and the drain of the transistor T, and the first electrode of the memristor R is connected to the drain of the transistor T. The gate structure 3 includes a connected gate and word line, that is, the gate structure 3 includes the gate of the transistor T and the word line WL, and the gate of the transistor T is connected to the word line WL.

[0073] The electrode substructure 2a contacts the second conductive layer 14 , so that the electrode substructure 2a and the second conductive layer 14 can form a memristor R. The gate structure 3 contacts the first conductive layer 11 and the electrode substructure 2a , so that the gate structure 3 , the first conductive layer 11 and the electrode substructure 2a can form a transistor T.

[0074] In the first conductive layer 11, the first insulating layer 12, the composite layer 13 and the first conductive layer 11 that are continuously stacked, the electrode substructure 2a (including the first electrode) provided at the side wall of the step area A of the composite layer 13 and the second conductive layer 14 (including the second electrode) in the composite layer 13 constitute a memristor R, the electrode substructure 2a (including the drain) and the first conductive layer 11 (including the source) below it and the gate structure 3 (including the gate) therebetween constitute a transistor T, the electrode substructure 2a (including the drain) and the first conductive layer 11 (including the source) above it and the gate structure 3 (including the gate) therebetween constitute another transistor T, and the memristor R is connected to the two transistors T respectively to constitute a storage unit 10.

[0075] By alternately stacking the first conductive layer 11 , the first insulating layer 12 , and the composite layer 13 in the stack structure 1 , a plurality of memory cells 10 may be stacked.

[0076] Related technologies use a planar process to fabricate 1T1R memory cells, forming transistors on the surface of a wafer and memristors on top of them. Limited by the fabrication process and device structure, only one layer of 1T1R memory cells can be fabricated on a single wafer, resulting in a low integration density.

[0077] In this embodiment, by alternately stacking the first conductive layer 11, the first insulating layer 12 and the composite layer 13, the memory cells 10 can be stacked to form a three-dimensional memory array, thereby achieving a multiple increase in the size and integration density of the memory array.

[0078] In some embodiments, the electrode substructure 2a includes a resistive layer 21 and a third conductive layer 22. The resistive layer 21 in the electrode substructure 2a covers the sidewalls of the target step and at least a portion of the upper surface of the next step, and the third conductive layer 22 in the electrode substructure 2a covers the resistive layer 21 in the electrode substructure 2a. The thickness of the resistive layer 21 can be set to be relatively thin, and the height of the electrode substructure 2a along the first direction X can be the same as the height of the target step (i.e., the thickness of the composite layer 13).

[0079] The third conductive layer 22 in the electrode substructure 2a includes a first electrode and a drain electrode that are connected. That is, the third conductive layer 22 in the electrode substructure 2a includes the first electrode of the memristor R and the drain electrode of the transistor R, and the first electrode of the memristor R and the drain electrode of the transistor R are connected. The third conductive layer 22, the first conductive layer 11, and the resistive switching layer 21 therebetween constitute the memristor R.

[0080] The materials of the resistive layer 21 include, but are not limited to, binary transition metal oxides such as HfOx, TaOx, TiOx, and ZrOx, metal oxides such as AlOx, non-metal oxides such as SiOx, and multi-metal oxides, metal-nonmetal mixed oxides, and perovskite oxides composed thereof. The materials of the third conductive layer 22 include, but are not limited to, inert metal materials such as Pt, Pd, and Ir, and their alloys, metal materials such as Ta, Hf, Ti, Zr, W, Ru, and Al, and their alloys, and metallic compound materials such as TiN, TaN, and Poly-Si.

[0081] In some embodiments, the electrode structure 2 further includes redundant substructures 2b corresponding to each step other than the target step. That is, redundant substructures 2b are provided on the sidewalls of the steps corresponding to the first conductive layer 11 and the first insulating layer 12. The redundant substructures 2b cover the sidewalls of the corresponding step and a portion of the upper surface of the next step.

[0082] While the electrode substructure 2a is formed on the sidewall of the target step, a redundant substructure 2b is formed on the sidewalls of other steps. The redundant substructure 2b does not constitute the first electrode of the memristor R or the drain of the transistor T, and may not implement any function.

[0083] It should be noted that the redundant substructure 2b arranged on the step sidewall corresponding to the first insulating layer 12 covers part of the upper surface of the next step (i.e., the step formed by the first conductive layer 11) so that the gate structure 3 is in contact with the first conductive layer 11, and the first conductive layer 11 in contact with the gate structure 3 constitutes the source of the transistor T.

[0084] In some embodiments, the redundant substructure 2b includes a resistive switching layer 21 and a third conductive layer 22. The resistive switching layer 21 in the redundant substructure 2b covers the sidewalls of each step other than the target step and a portion of the upper surface of the next step. The third conductive layer 22 in the redundant substructure 2b covers the resistive switching layer 21 in the redundant substructure 2b. The thickness of the resistive switching layer 21 can be set to be relatively thin, and the height of the redundant substructure 2b along the first direction X can be the same as the height of the corresponding step (i.e., the thickness of the first conductive layer 11 or the first insulating layer 12).

[0085] The resistive switching layer 21 in the redundant substructure 2b is provided on the same layer as the resistive switching layer 21 in the electrode substructure 2a, and the third conductive layer 22 in the redundant substructure 2b is provided on the same layer as the third conductive layer 22 in the electrode substructure 2a.

[0086] In some embodiments, the gate structure 3 includes a channel layer 31, a gate dielectric layer 32, and a gate layer 33. The channel layer 31 covers the electrode structure 2 and the step structure, the gate dielectric layer 32 covers the channel layer 31, and the gate layer 33 covers the gate dielectric layer 32. The gate layer 33 includes a connected gate and word line, that is, the gate layer 33 includes the gate of the transistor T and the word line WL, and the gate of the transistor T and the word line WL are connected.

[0087] The channel layer 31 extends along the step direction to cover each electrode substructure 2a and each step in the step structure. When the electrode structure 2 further includes a redundant substructure 2b, the channel layer 31 at least covers each electrode substructure 2a, each redundant substructure 2b, and each first conductive layer 11 to ensure that the channel layer 31 is in contact with the third conductive layer 22 in each electrode substructure 2a and each first conductive layer 11.

[0088] The drain in the third conductive layer 22 , the source in the first conductive layer 11 , and the channel layer 31 , the gate dielectric layer 32 , and the gate layer 33 therebetween constitute a transistor T.

[0089] In some embodiments, the memory further includes a source line connection structure (not shown in the figure), and the source lines in the plurality of first conductive layers 11 are connected via the source line connection structure.

[0090] The source line connection structure can be located in the non-step region and extend along the first direction X in the stacked structure 1 to connect to the multiple first conductive layers 11 respectively, so that the source lines in the multiple first conductive layers 11 are connected through the source line connection structure. In addition, the source line connection structure can lead the source lines in the multiple first conductive layers 11 out, so that other devices can be connected to the source lines through the source line connection structure.

[0091] In some embodiments, as Figure 4As shown, the step region A is located on one side of the stacked structure 1 along the second direction Y and extends along the third direction Z. That is, the step region A and the non-step region are distributed along the second direction Y. The third direction Z, the second direction Y and the first direction X are perpendicular to each other.

[0092] The memory includes a plurality of gate structures 3 , which extend along a second direction Y. The gate structures 3 may pass through the step region A and extend to the non-step region along the second direction Y. The plurality of gate structures 3 are spaced apart along a third direction Z.

[0093] Each gate structure 3 corresponds to a column of memory cells, so that multiple columns of memory cells are distributed along the third direction Z. The gate structure 3 is a continuous structure extending along the second direction Y, and multiple gate structures 3 are arranged at intervals, so that memory cells in the same column are connected to the same word line, and memory cells in different columns are connected to different word lines.

[0094] Each column of memory cells can include multiple stacked memory cells 10. Memory cells 10 arranged in the same layer constitute a row of memory cells. Memory cells in the same row are distributed along a third direction Z, with multiple rows of memory cells stacked. Memory cells in the same row share a common second conductive layer 14, and multiple second conductive layers 14 are spaced apart, such that memory cells in the same row are connected to the same bit line, while memory cells in different rows are connected to different bit lines. Memory cells in the same row share a common first conductive layer 11, and multiple first conductive layers 11 are connected via a source line connection structure, such that all memory cells are connected to the same source line.

[0095] The number of gate structures 3 can be set according to actual needs and is not specifically limited here.

[0096] In some embodiments, as Figure 5 and Figure 6 As shown, the stacked structure 1 includes multiple step regions A spaced apart from each other, with non-step regions disposed around each step region A. The multiple step regions A may be spaced apart along the second direction Y and / or the third direction Z. Alternatively, the multiple step regions A may be arranged in multiple rows along the second direction Y or the third direction Z, with adjacent rows of step regions staggered. The number and distribution of the step regions A may be determined based on actual needs and are not specifically limited herein.

[0097] The step area A may be an annular area, and the step structure in the stacked structure 1 may also be an annular step structure, that is, the step structure includes multiple annular steps, and the step direction of the step structure may be inclined from the center of the step area A toward the edge.

[0098] The memory includes multiple electrode structures 2 and multiple gate structures 3. Each step region A corresponds to one electrode structure 2 and one gate structure 3. The electrode structure 2 can be an annular structure and is located at each annular step of the corresponding step region A. The multiple gate structures 3 are spaced apart, and each gate structure 3 can completely cover the corresponding step region A.

[0099] Each step region A corresponds to a column of memory cells, so that multiple columns of memory cells are spaced apart along the second direction Y and / or the third direction Z. The gate structure 3 can completely cover the corresponding step region A, and multiple gate structures 3 are spaced apart so that memory cells in the same column are connected to the same word line, and memory cells in different columns are connected to different word lines.

[0100] Each column of memory cells can include multiple stacked memory cells 10. Memory cells 10 arranged in the same layer constitute a row of memory cells. Memory cells in the same row are distributed along the second direction Y and / or the third direction Z, with multiple rows of memory cells stacked. Memory cells in the same row share a common second conductive layer 14, and multiple second conductive layers 14 are spaced apart, such that memory cells in the same row are connected to the same bit line, while memory cells in different rows are connected to different bit lines. Memory cells in the same row share a common first conductive layer 11, and multiple first conductive layers 11 are connected via a source line connection structure, such that all memory cells are connected to the same source line.

[0101] In summary, the memory provided by the embodiments of the present application forms a 2T1R structure by providing two transistors and a memristor in a memory cell. Both transistors act as drive transistors, increasing the drive current of the memristor, thereby improving the data read and write speed of the memristor and enhancing storage performance. By providing a stacked structure, the step region of the stacked structure forms a stepped structure, and an electrode structure and a gate structure are provided on the stepped structure, so that the memory cells are stacked, effectively improving the integration density of the memory cells.

[0102] Accordingly, the present application also provides a method for preparing a memory, which can prepare the memory in the above embodiment. Figure 1 and Figure 2 As shown, the memory includes at least one word line WL, at least one bit line BL, a source line SL, and at least one memory cell 10. The memory cell 10 includes two transistors T and a memristor R. The gates of the two transistors T in the memory cell 10 are connected to the same word line WL, the sources of the two transistors T in the memory cell 10 are connected to the source line SL, the drains of the two transistors T in the memory cell 10 are respectively connected to the first electrode of the memristor R, and the second electrode of the memristor R in the memory cell 10 is connected to a bit line BL.

[0103] like Figure 7As shown, the method for preparing a memory provided in an embodiment of the present application includes steps 110 to 130.

[0104] Step 110: forming a stacking structure, the stacking structure including a first conductive layer, a first insulating layer, and a composite layer alternately stacked along a first direction, the composite layer including a second conductive layer and a second insulating layer stacked along the first direction; the stacking structure including a step region, the first conductive layer, the first insulating layer, and the composite layer forming a step structure in the step region.

[0105] like Figure 8 As shown, first, a first conductive layer 11, a first insulating layer 12, a second conductive layer 14, and a second insulating layer 15 are alternately formed along a first direction X. The second conductive layer 14 and the second insulating layer 15 constitute a composite layer 13, that is, the first conductive layer 11, the first insulating layer 12, and the composite layer 13 are alternately formed along the first direction X.

[0106] Then, if Figure 9 As shown, a photolithography process is used to etch the alternately formed first conductive layer 11, first insulating layer 12, and composite layer 13 to form a step structure in step region A. The etched film layers constitute a stacked structure 1, i.e., the stacked structure 1 includes the step region A, and the first conductive layer 11, first insulating layer 12, and composite layer 13 form a step structure in the step region A. The step structure includes a plurality of steps, and each first conductive layer 11, each first insulating layer 12, and each composite layer 13 forms a corresponding step in the step region A.

[0107] Step 120 : forming an electrode structure in the step region, the electrode structure including an electrode substructure arranged corresponding to the target step formed by the composite layer, and the electrode substructure covering the sidewall of the target step.

[0108] In some embodiments, the electrode structure further includes redundant substructures corresponding to each step except the target step, and the redundant substructures cover the sidewall of the corresponding step and a portion of the upper surface of the next step.

[0109] In some embodiments, the electrode substructure and the redundant substructure both include a resistive switching layer and a third conductive layer. Step 120 of forming an electrode structure in the step region includes:

[0110] forming a resistive switching layer covering the stacked structure;

[0111] forming a third conductive layer covering the initial resistive switching layer;

[0112] The third conductive layer and the resistive layer are etched to form an electrode substructure and a redundant substructure.

[0113] like Figure 10As shown, the resistive switching layer 21 and the third conductive layer 22 are grown isotropically in sequence. The resistive switching layer 21 covers the sidewalls and upper surface of the step structure and the upper surface of the stacked structure 1 , and the third conductive layer 22 covers the resistive switching layer 21 .

[0114] Then, if Figure 11 As shown, anisotropic etching is performed on the third conductive layer 22 and the resistive layer 21, leaving the third conductive layer 22 and the resistive layer 21 on the sidewalls of each step. The remaining film layer on the sidewalls of each step only covers a portion of the upper surface of the next step. The resistive layer 21 and the conductive layer 22 retained on the sidewalls of the target step (i.e., the step formed by the composite layer 13) constitute the electrode substructure 2a, while the resistive layer 21 and the conductive layer 22 retained on the sidewalls of other steps (i.e., the steps formed by the first conductive layer 11 or the first insulating layer 12) constitute the redundant substructure 2b.

[0115] Step 130: Form a gate structure covering the electrode structure and the step structure; wherein the first conductive layer includes the source and source line of the connected transistor, the electrode substructure includes the first electrode of the connected memristor and the drain of the transistor, the second conductive layer includes the second electrode and the bit line of the connected memristor, and the gate structure includes the gate and word line of the connected transistor.

[0116] In some embodiments, the gate structure includes a channel layer, a gate dielectric layer, and a gate layer. The step 130 of forming the gate structure covering the electrode structure and the step structure includes:

[0117] forming a channel layer covering the electrode structure and the stack structure;

[0118] forming a gate dielectric layer covering the channel layer;

[0119] forming a gate layer covering the gate dielectric layer;

[0120] The gate layer, the gate dielectric layer and the channel layer are etched to form a gate structure.

[0121] like Figures 3 to 6 As shown, a channel layer 31, a gate dielectric layer 32, and a gate layer 33 are first grown in sequence. The channel layer 31 covers the surface of the electrode structure 2, the surface of the step structure, and the upper surface of the stacked structure 1, the gate dielectric layer 32 covers the channel layer 31, and the gate layer 33 covers the gate dielectric layer 32.

[0122] Then, the channel layer 31, the gate dielectric layer 32 and the gate layer 33 are etched by photolithography to form a plurality of gate structures 3 distributed at intervals. Figure 4 As shown, the gate structure 3 extends along the second direction Y, and multiple gate structures 3 are distributed at intervals along the third direction Z. Figure 6As shown, the stacked structure 1 includes a plurality of step regions A distributed at intervals, and the plurality of gate structures 3 cover the plurality of step regions A respectively.

[0123] According to the memory fabrication method provided in the embodiments of the present application, two transistors and a memristor are provided in a memory cell to form a 2T1R structure. Both transistors serve as drive transistors, increasing the memristor's drive current, thereby improving the memristor's data read and write speed and enhancing storage performance. By providing a stacked structure, the stepped region of the stacked structure forms a stepped structure, and an electrode structure and gate structure are provided on the stepped structure, allowing the memory cells to be stacked, effectively increasing the integration density of the memory cells.

[0124] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first," "second," and the like generally distinguish objects of a class and do not limit the number of objects. For example, the first object may be one or more.

[0125] In the description of this application, “plurality” means two or more.

[0126] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0127] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and intent of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A memory, characterized in that: The method comprises at least one word line, at least one bit line, a source line and at least one memory cell; the memory cell comprises two transistors and a memristor; The gates of the two transistors in the memory cell are connected to the same word line, the sources of the two transistors in the memory cell are connected to the source line, the drains of the two transistors in the memory cell are respectively connected to the first electrode of the memristor, and the second electrode of the memristor in the memory cell is connected to one of the bit lines.

2. The memory according to claim 1, wherein The plurality of memory cells are distributed in multiple rows and columns; The second electrodes of the memristors in each row of memory cells are connected to one of the bit lines, the gates of the transistors in each column of memory cells are connected to one of the word lines, and the sources of the transistors in each memory cell are connected to the source line.

3. The memory according to claim 1, wherein: The memory includes: A stacked structure comprising a first conductive layer, a first insulating layer, and a composite layer alternately stacked along a first direction, wherein the composite layer comprises a second conductive layer and a second insulating layer stacked along the first direction; the stacked structure comprising a step region, wherein the first conductive layer, the first insulating layer, and the composite layer form a step structure in the step region; an electrode structure, comprising an electrode substructure disposed corresponding to a target step formed by the composite layer, the electrode substructure covering a sidewall of the target step; a gate structure covering the electrode structure and the step structure; The first conductive layer includes the source and the source line connected to each other, the second conductive layer includes the second electrode and the bit line connected to each other, the electrode substructure includes the first electrode and the drain connected to each other, and the gate structure includes the gate and the word line connected to each other.

4. The memory according to claim 3, wherein: The step area is located on one side of the stacking structure along the second direction and extends along the third direction; the third direction, the second direction and the first direction are perpendicular to each other; The memory includes a plurality of gate structures, wherein the gate structures extend along the second direction, and the plurality of gate structures are spaced apart and distributed along the third direction.

5. The memory according to claim 3, wherein: The stacking structure includes a plurality of step areas distributed at intervals; The memory includes a plurality of electrode structures and a plurality of gate structures, and each step region is correspondingly provided with one electrode structure and one gate structure.

6. The memory according to claim 3, wherein: The electrode substructure includes a resistive switching layer and a third conductive layer; The resistive layer covers the sidewalls of the target step and at least a portion of the upper surface of the next step. The third conductive layer covers the resistive layer. The third conductive layer includes the first electrode and the drain electrode connected to each other.

7. The memory according to claim 3, wherein: The gate structure includes a channel layer, a gate dielectric layer and a gate layer; The channel layer covers the electrode structure and the step structure, the gate dielectric layer covers the channel layer, the gate layer covers the gate dielectric layer, and the gate layer includes the gate and the word line connected to each other.

8. The memory according to claim 3, wherein: The electrode structure further includes redundant substructures corresponding to each step except the target step, and the redundant substructures cover the sidewall of the corresponding step and a portion of the upper surface of the next step.

9. The memory according to any one of claims 3 to 8, characterized in that: The memory further comprises: A source line connection structure, through which the source lines in the plurality of first conductive layers are connected.

10. A method for preparing a memory, characterized in that: The memory includes at least one word line, at least one bit line, a source line and at least one memory cell; The memory cell includes two transistors and a memristor; The method comprises: forming a stacked structure, the stacked structure comprising a first conductive layer, a first insulating layer, and a composite layer alternately stacked along a first direction, the composite layer comprising a second conductive layer and a second insulating layer stacked along the first direction; the stacked structure comprising a step region, the first conductive layer, the first insulating layer, and the composite layer forming a step structure in the step region; forming an electrode structure in the step region, the electrode structure comprising an electrode substructure arranged corresponding to the target step formed by the composite layer, the electrode substructure covering a sidewall of the target step; forming a gate structure covering the electrode structure and the step structure; The first conductive layer includes the source of the transistor and the source line connected to each other, the electrode substructure includes the first electrode of the memristor and the drain of the transistor connected to each other, the second conductive layer includes the second electrode of the memristor and the bit line connected to each other, and the gate structure includes the gate of the transistor and the word line connected to each other.

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