Etching method of inner side wall, preparation method of semiconductor device and semiconductor device

Abstract

The invention provides an etching method of an inner side wall, a preparation method of a semiconductor device and the semiconductor device. Wherein the etching method of the inner side wall comprises a deposition process stage, a finishing process stage and an etching process stage, and in the deposition process stage, a polymer is formed on the exposed surface of a fin structure by utilizing first process gas; wherein the exposed surface comprises the top and the side wall of the fin structure and the bottom of the groove; in the trimming process stage, the polymer on the side wall is removed by using the second process gas, in the etching process stage, the inner side wall material on the side wall is removed by using the third process gas to form the inner side wall, and the etching mode has low requirements on the etching selectivity and the longitudinal / transverse etching ratio of the fin structure material, thereby being beneficial to widening the process window and improving the production efficiency. And the process yield is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an inner sidewall etching method, a semiconductor device preparation method, and a semiconductor device. Background Art

[0002] In the manufacturing process of GAAFET (Gate All Around Field Effect Transistor), the inner sidewall is a very important process module, which plays the role of physical isolation and electrical isolation, and is of great significance to improving device performance. In the relevant technical solutions, the inner sidewall is mainly formed by an anisotropic etching process. Since the longitudinal etching amount of the inner sidewall dielectric is often greater than 150nm, and the total lateral deposition amount of the inner sidewall dielectric is only about 5nm, this puts extremely high requirements on the use of anisotropic inner sidewall dielectric etching process: ① The etching process must have extremely high etching selectivity for both hard mask materials and Si materials; ② The etching process must have extremely high anisotropic etching characteristics, that is, an extremely high longitudinal / lateral etching ratio. However, strict process requirements can easily lead to a smaller process window, resulting in poor process repeatability and reduced production yield, which cannot meet actual process requirements. Summary of the Invention

[0003] In view of this, an object of the present invention is to provide an inner sidewall etching method, a semiconductor device manufacturing method and a semiconductor device, so as to alleviate the problem of reduced production yield due to a small process window in the above-mentioned related technical solutions.

[0004] In a first aspect, an embodiment of the present invention provides a method for etching an inner sidewall, which is applied to a semiconductor device, wherein the semiconductor device includes a substrate and a fin structure formed on the substrate, wherein an inner sidewall material is deposited on an exposed surface of the fin structure; the method comprises:

[0005] Deposition process stage: using a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, sidewalls and bottom of the trench of the fin structure;

[0006] trimming process stage: removing the polymer on the sidewall by using a second process gas;

[0007] Etching process stage: using the third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall.

[0008] Optionally, the first process gas includes a gas containing carbon and hydrogen elements.

[0009] Optionally, the second process gas is a gas containing oxygen.

[0010] Optionally, the third process gas includes a halogen etching gas.

[0011] Optionally, the halogen etching gas includes at least one of the following: nitrogen trifluoride, carbon tetrafluoride, trifluoromethane and fluoromethane.

[0012] Optionally, a thickness of the polymer on the top of the fin structure and the bottom of the trench is greater than a thickness of the polymer on the sidewall.

[0013] Optionally, during the trimming process stage and the etching process stage, the power of the lower RF power supply is 0W.

[0014] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, the method comprising:

[0015] epitaxially growing a fin structure on a substrate; wherein the fin structure includes a sacrificial layer;

[0016] Laterally etching the sacrificial layer to form a filling cavity of a preset length;

[0017] depositing an inner sidewall material in the filled cavity and on the exposed surface of the fin structure;

[0018] The inner sidewall etching method of the first aspect is adopted to remove the inner sidewall material outside the filling cavity to form the inner sidewall.

[0019] Optionally, the step of epitaxially growing a fin structure on a substrate includes: forming a stacked portion and a dummy gate on the substrate; wherein the stacked portion is located on the surface of the substrate, and the sacrificial layer and the channel layer are alternately arranged in a direction away from the substrate, and the dummy gate is located on the surface of the stacked portion away from the substrate; depositing a hard mask on the outer surface of the dummy gate, and using the stacked portion, the dummy gate and the hard mask as the fin structure.

[0020] In a third aspect, an embodiment of the present invention further provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device according to the second aspect.

[0021] The embodiments of the present invention bring the following beneficial effects:

[0022] An embodiment of the present invention provides an inner sidewall etching method, a semiconductor device preparation method, and a semiconductor device; wherein, the inner sidewall etching method includes a deposition process stage, a trimming process stage, and an etching process stage. The deposition process stage utilizes a first process gas to form a polymer on the exposed surface of the fin structure; wherein, the exposed surface includes the top, sidewall, and groove bottom of the fin structure; the trimming process stage utilizes a second process gas to remove the polymer on the sidewall, and the etching process stage utilizes a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall. This etching method has low requirements on the etching selectivity and longitudinal / lateral etching ratio of the material of the fin structure, which is conducive to widening the process window and improving the process yield.

[0023] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description and the drawings.

[0024] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 Schematic diagram of TEM and EDS in the related technical solution;

[0027] Figure 2 A flow chart of an inner sidewall etching method provided by an embodiment of the present invention;

[0028] Figure 3 A schematic diagram of a semiconductor device after a deposition process stage is completed according to an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of a semiconductor device after a trimming process stage is completed according to an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a semiconductor device after an etching process stage is completed according to an embodiment of the present invention;

[0031] Figure 6A schematic diagram of a semiconductor device after complete removal of polymer provided by an embodiment of the present invention;

[0032] Figure 7 A schematic diagram of a semiconductor device after inner sidewalls are formed according to an embodiment of the present invention;

[0033] Figure 8 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0034] Figure 9 A schematic diagram of forming a filled cavity in a semiconductor device provided by an embodiment of the present invention;

[0035] Figure 10 A schematic diagram of a semiconductor device after the inner sidewall material deposition is completed provided by an embodiment of the present invention.

[0036] icon:

[0037] 31 - substrate; 32 - channel layer; 33 - sacrificial layer; 34 - spacer layer; 35 - dummy gate; 36 - hard mask; 37 - inner sidewall material; 381 - polymer on the sidewall; 382 - polymer at the bottom of the trench; 383 - polymer at the top; 39 - inner sidewall; 40 - filling the cavity. DETAILED DESCRIPTION

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0039] With the continuous development of Moore's Law, after the semiconductor process has developed to the technology node of 3nm and below, GAAFET is considered to be an effective replacement for FinFET (Fin Field Effect Transistor). Among them, in the manufacturing process of GAAFET, the inner wall is a very important process module, and its role can be divided into two aspects: physical isolation and electrical isolation. On the one hand, according to the manufacturing process of GAAFET, the channel release process is located after the inner wall and the selective epitaxy to form the source / drain. When the channel release process selectively removes the sacrificial layer, the inner wall has physically isolated the source / drain and the sacrificial layer in the gate area, preventing the source / drain from being subjected to uncontrollable extended etching during the channel release process. Therefore, the inner wall is particularly important for devices where the source / drain and the sacrificial layer are made of the same material. On the other hand, without the inner sidewall structure, there would be only a thin gate oxide layer between the gate metal and the source / drain between the nanosheets, which would greatly increase the parasitic capacitance and leakage current of the device. Therefore, the inner sidewall located between the source / drain and the gate can play the role of electrical isolation, thereby greatly reducing the parasitic capacitance and leakage current between the source / drain and the gate, and improving the dynamic performance of the device.

[0040] Regarding the formation process of the inner sidewall, the relevant technical solution uses silicon nitride (SiN) material as the inner sidewall dielectric as an example. Among them, an anisotropic etching process is adopted. According to the etching gas combination (difluoromethane (CH2F2) / methane (CH4) / oxygen (O2) / argon (Ar)), and by optimizing the ratio of each gas in the mixed gas and the process pressure, an inner sidewall structure with ultra-high etching selectivity (SiN:Si>1:100, SiN:SiO2>1:30) and ultra-high vertical / lateral etching ratio (vertical:lateral>80:1) is obtained, such as Figure 1 Schematic diagrams of TEM (Transmission Electron Microscope) and EDS (Energy Dispersive Spectrometer) are shown; in which, the left side of (a) is the TEM image after SiN filling the cavity, and the right side is the EDS image; the left side of (b) is the TEM image after SiN back etching, and the right side is the EDS image, and the distribution of carbon (C), germanium (Ge), nitrogen (N), oxygen (O) and silicon (Si) is shown in each EDS image.

[0041] In practical applications, the vertical etch depth of the inner sidewall dielectric is often greater than 150nm, while the total lateral deposition depth of the inner sidewall dielectric is only about 5nm. This places extremely high demands on the anisotropic inner sidewall dielectric etch process: ① The etch process must have extremely high etch selectivity for both the hard mask material and the Si material; ② The etch process must have highly anisotropic etching characteristics, that is, a very high vertical / lateral etch ratio. However, these stringent process requirements can easily lead to a small process window, resulting in poor process repeatability and reduced production yield, which cannot meet actual process needs.

[0042] Based on this, an embodiment of the present invention provides an inner sidewall etching method, a semiconductor device preparation method and a semiconductor device; wherein, the inner sidewall etching method includes a deposition process stage, a trimming process stage and an etching process stage. The deposition process stage uses a first process gas to form a polymer on the exposed surface of the fin structure; wherein, the exposed surface includes the top, sidewall and groove bottom of the fin structure; the trimming process stage uses a second process gas to remove the polymer on the sidewall, and the etching process stage uses a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall. This etching method has lower requirements on the etching selectivity and longitudinal / lateral etching ratio of the material of the fin structure, which is conducive to widening the process window and improving the process yield.

[0043] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0044] Example 1

[0045] An embodiment of the present invention provides an inner sidewall etching method, which is applied to semiconductor devices, where the semiconductor devices include but are not limited to GAAFET and FinFET. In actual applications, the semiconductor device includes a substrate and a fin structure formed on the substrate, wherein the fin structure includes a sacrificial layer, a channel layer, a dummy gate and a hard mask, etc., and the inner sidewall material is deposited on the exposed surface of the fin structure; the specific fin structure can refer to the existing technology, and the embodiment of the present invention will not be described in detail here.

[0046] Based on the above semiconductor devices, such as Figure 2 As shown, the etching method of the inner sidewall provided by the embodiment of the present invention includes the following steps:

[0047] Step S202 , deposition process stage: using a first process gas to form a polymer on the exposed surface of the fin structure.

[0048] Specifically, in the deposition process stage, a polymer is formed on the exposed surface of the fin structure using a first process gas; wherein the exposed surface includes the top, sidewalls and bottom of the trench of the fin structure; the first process gas includes a gas containing carbon (C) elements and hydrogen (H) elements, that is, the first process gas is a hydrocarbon gas, including but not limited to CH4, ethane (C2H6), propane (C3H8), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), fluoromethane (CH3F) and trifluoromethane (CHF3), etc.

[0049] In addition, the first process gas can also be a combination of hydrocarbon gases and inert gases, where the inert gases include but are not limited to Ar and helium (He). In some scenarios, the first process gas can also be a combination of multiple hydrocarbon gases and inert gases, such as CH4 or CH4 / Ar gas combination or CH4 / CHF3 / Ar gas combination. Therefore, a polymer is formed on the exposed surface of the fin structure by the first process gas, where the polymer can also be called a hydrocarbon polymer, so that the top of the fin structure and the bottom of the trench can be protected by the polymer during the subsequent etching process, further ensuring the process effect of the inner wall.

[0050] Step S204 , trimming process stage: using a second process gas to remove the polymer on the sidewall.

[0051] After the deposition process is completed, the trimming process phase begins, where a second process gas is used to remove polymer on the sidewalls. The second process gas is an oxygen-containing gas, such as O2, and can be adjusted based on actual conditions.

[0052] Step S206, etching process stage: using a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall.

[0053] After the trimming is completed, the etching process phase begins. During the etching process phase, a third process gas is used to remove the inner sidewall material on the sidewall to form the inner sidewall. The third process gas includes a halogen etching gas, which includes at least one of the following: nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), CHF3, and CH3F. In addition, the third process gas can also be a combination of a halogen etching gas and an inert gas, or a combination of multiple halogen etching gases and inert gases, such as CF4 or a CF4 / Ar gas combination or a CF4 / CHF3 / Ar gas combination. The specific gas can be set according to actual conditions.

[0054] Therefore, the inner sidewall etching method provided in an embodiment of the present invention includes a deposition process stage, a trimming process stage and an etching process stage. The deposition process stage uses a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, sidewall and bottom of the fin structure; the trimming process stage uses a second process gas to remove the polymer on the sidewall, and the etching process stage uses a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall. This etching method has lower requirements on the etching selectivity and longitudinal / lateral etching ratio of the material of the fin structure, which is conducive to widening the process window and improving the process yield.

[0055] In one embodiment, the polymer thickness at the top of the fin structure and the bottom of the trench is greater than the polymer thickness on the sidewalls.

[0056] Specifically, during the deposition process stage, polymer deposition is completed by one or more different polymer deposition steps, and the final deposition result is that the polymer thickness at the top of the fin structure and the bottom of the groove is greater than the polymer thickness on the side wall. Therefore, when removing the polymer on the side wall during the trimming process stage, it is not only convenient to remove the polymer on the side wall, but also the top of the fin structure and the bottom of the groove are protected by the thicker polymer during the removal process, thereby ensuring the process effect of the inner wall.

[0057] In one embodiment, during the trimming process stage and the etching process stage, the power of the lower RF power supply is 0 W.

[0058] In practical applications, inductively coupled plasma (ICP) etchers are one of the most common etching equipment, typically featuring two RF systems: an upper RF power supply, also known as the source radio frequency (SRF), used to generate and maintain the plasma; and a lower RF power supply, also known as the bias radio frequency (BRF), used to control the energy and directionality of ion bombardment. Because the bias voltage applied by the lower RF power supply to the process stage accelerates ions and bombards them perpendicularly to the wafer surface, etching processes based on ICP etchers exhibit more anisotropic etching characteristics.

[0059] To reduce anisotropic etching characteristics and enhance isotropic etching, the ICP etching equipment can reduce the power of the lower RF power supply. During the trimming and etching stages, this embodiment of the present invention sets the power of the lower RF power supply to 0W and uses the ICP chamber to achieve lateral etching of the inner sidewall material film. Compared with using free radical etching equipment to achieve isotropic etching of the inner sidewall material, it has a significant cost advantage.

[0060] In addition, to ensure the process effect of each process stage, process parameters are also set for each process stage. Among them, in the deposition process stage, to ensure the deposition effect of the polymer, the process parameters include but are not limited to: chamber pressure of 5mT to 100mT, total gas flow of the first process gas of 50sccm to 500sccm, process time of 5s to 60s, upper RF power supply power of 500W to 3000W, and lower RF power supply power of 0W to 1000W. The specific values ​​of each process parameter can be set according to actual conditions.

[0061] Similarly, during the trimming process, in order to ensure the removal effect and efficiency of the polymer on the side wall, the process parameters include but are not limited to: the chamber pressure is 5mT~100mT, the total gas flow rate of the second process gas is 50sccm~500sccm, the process time is 5s~30s, the power of the upper RF power supply is 500W~3000W, and the power of the lower RF power supply is 0W. The specific values ​​of each process parameter can be set according to actual conditions.

[0062] During the etching process, in order to ensure the removal effect and efficiency of the inner wall material on the sidewall, the process parameters include but are not limited to: the chamber pressure is 5mT to 100mT, the total gas flow rate of the third process gas is 50sccm to 500sccm, the process time is 5s to 60s, the power of the upper RF power supply is 500W to 3000W, and the power of the lower RF power supply is 0W. The specific values ​​of each process parameter can be set according to actual conditions.

[0063] Furthermore, by setting the power of the lower RF power supply to 0W, although the isotropic characteristics of the etching process can be greatly enhanced, self-bias voltage will inevitably be generated in the process chamber in actual applications, causing the longitudinal etching rate to be greater than the lateral etching rate. In order to solve the problem of the longitudinal etching rate being greater than the lateral etching rate in the etching process, the etching method of the inner sidewall provided in the embodiment of the present invention mainly includes a multi-step etching process of a deposition process stage, a trimming process stage and an etching process stage; wherein the functions of each process stage are as follows:

[0064] (1) In a deposition process stage, a polymer is formed on the exposed surface of the fin structure using a first process gas.

[0065] In practical applications, such as Figure 3As shown, the semiconductor device includes a substrate 31 and a fin structure formed on the substrate; the fin structure includes a plurality of channel layers 32, a plurality of sacrificial layers 33, a dummy gate 35, a spacer layer 34, and a hard mask 36. The plurality of channel layers 32 and the plurality of sacrificial layers 33 are alternately arranged, the dummy gate 35 spans the plurality of channel layers 32 and the plurality of sacrificial layers 33 stacked in an alternating manner, and the spacer layer 34 is located on both sides of the dummy gate 35 and spans the plurality of channel layers 32 and the plurality of sacrificial layers 33 stacked in an alternating manner. In addition, an inner sidewall material 37 is deposited on the exposed surface of the fin structure. At the same time, an inner sidewall material 37 is also deposited in the filled cavity 40. Here, the inner sidewall material 37 can also be referred to as an inner sidewall dielectric material. It should be noted that the spacer layer 34 can also be referred to as an outer sidewall, the material of the sacrificial layer 33 is silicon germanium (SiGe), and the material of the channel layer 32 is Si. The specific material can be adaptively adjusted according to actual conditions.

[0066] During the deposition process, a first process gas is used to form a polymer on the exposed surface of the fin structure. The polymer includes polymer 381 on the sidewalls, polymer 382 at the bottom of the trench, and polymer 383 at the top. In practical applications, the polymer can be deposited in a single or multiple passes. The final effect is that the polymer thickness is thicker at the top and bottom of the trench of the fin structure, and thinner on the sidewalls. In other words, the thickness of polymer 382 at the bottom of the trench and polymer 383 at the top are both thicker than the thickness of polymer 381 on the sidewalls. The purpose is to strengthen the protection of the top and bottom of the trench by the thicker polymer 382 and polymer 383 at the top of the trench, while facilitating subsequent removal of the thinner polymer 381 on the sidewalls.

[0067] (2) Trimming process stage: using the second process gas to remove the polymer on the side wall.

[0068] During the etching process, the third process gas used to etch the inner sidewall material 37 is primarily a halogen etching gas, and the resulting halogen radicals have a slow etching rate for the polymer. If the etching process for the inner sidewall material 37 is performed directly after the polymer deposition process, the active halogen radicals would need to spend a considerable amount of time removing the polymer 381 on the sidewalls before laterally etching the inner sidewall material 37, resulting in reduced process efficiency and poor repeatability.

[0069] Therefore, the embodiment of the present invention adds a trimming process stage between the deposition process stage and the etching process stage. In the trimming process stage, the polymer 381 on the sidewall is removed by oxidation, thereby achieving the subsequent lateral etching of the inner wall material 37. In practical applications, the process time of the trimming process stage should be appropriate to ensure that the polymer 381 on the sidewall is completely removed, and to ensure that the polymer 382 at the bottom of the trench and the polymer 383 at the top are partially left unremoved, so as to protect the bottom and top of the trench in the subsequent etching process stage. Figure 4 As shown, after the trimming process stage is completed, the polymer 381 on the sidewall is completely removed, and the polymer 382 at the bottom of the trench and the polymer 383 at the top are still partially left.

[0070] (3) Etching process stage: using the third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall.

[0071] After the above trimming process stage is completed, the etching process stage is entered, and the third process gas is used to remove the excess inner sidewall material 37 of the sidewall by lateral etching. Figure 5 As shown, the inner sidewall 39 is formed, that is, the cavity 40 filled with the inner sidewall material 37 is deposited. At this time, the polymer 382 at the bottom of the trench and the polymer 383 at the top will be consumed in the etching process of the inner sidewall material 37 on the sidewall. The remaining polymer 382 at the bottom of the trench and the polymer 383 at the top are removed by dry or wet cleaning. Figure 6 In addition, after the polymer is removed, the inner wall material 37 still remains on the top of the fin structure and the bottom of the trench. At this time, the remaining inner wall material 37 can be removed by dry etching, as shown in FIG. Figure 7 As shown, the inner sidewall 39 of the semiconductor device is finally generated.

[0072] In summary, the inner sidewall etching method provided by the embodiment of the present invention includes a deposition process stage, a trimming process stage, and an etching process stage. When etching back the inner sidewall material, the etching selectivity requirements for Si and SiGe materials are relatively low. The etching selectivity and longitudinal / lateral etching ratio requirements for the hard mask and other materials are also relatively low. This relaxes the requirements for the etching equipment and process engineers in the inner sidewall material back-etching process, thereby facilitating a widening of the process window and improving the process yield. In addition, compared with using free radical etching equipment to achieve isotropic etching of the inner sidewall material, it also has a significant cost advantage.

[0073] Example 2

[0074] Based on the above-mentioned embodiment of the etching method of the inner sidewall, the embodiment of the present invention further provides a method for preparing a semiconductor device, such as Figure 8 As shown, the method includes the following steps:

[0075] Step S802 , epitaxially growing a fin structure on a substrate; wherein the fin structure includes a sacrificial layer.

[0076] Step S804 , laterally etching the sacrificial layer to form a filling cavity of a preset length.

[0077] Step S806 , depositing an inner spacer material in the filled cavity and on the exposed surface of the fin structure.

[0078] Step S808 , using an inner sidewall etching method to remove the inner sidewall material outside the cavity filling, to form the inner sidewall.

[0079] In one embodiment, the step of epitaxially growing a fin structure on a substrate includes: forming a stacked portion and a dummy gate on the substrate; wherein the stacked portion is located on the surface of the substrate and has sacrificial layers and channel layers alternately arranged in a direction away from the substrate, and the dummy gate is located on the surface of the stacked portion away from the substrate; depositing a hard mask on the outer surface of the dummy gate, and forming the stacked portion, dummy gate, and hard mask as a fin structure. The specific fin structure can be referred to the aforementioned embodiment, and the embodiment of the present invention will not be described in detail here.

[0080] In practical applications, the inner sidewall is one of the most important and challenging process modules in the GAAFET manufacturing process. The inner sidewall mainly includes the following three process steps:

[0081] (A1) Cavity etching process step; that is, using a selective etching process to partially remove the sacrificial layer 33 in the laminate structure, such as Figure 9 As shown, a filling cavity 40 for filling the inner sidewall material is formed.

[0082] In order to better achieve current balance in the N / P devices, under ideal conditions, the channel layer 32 material of the NMOS (N-Metal-Oxide-Semiconductor) transistor should be Si, and the sacrificial layer 33 material should be SiGe; the channel layer 32 material of the PMOS (Positivechannel Metal Oxide Semiconductor) transistor should be SiGe, and the sacrificial layer 33 material should be Si. Therefore, a selective etching process is used to partially laterally etch and remove the sacrificial layer 33 in the Si / SiGe stacked structure to form a filling cavity 40 for filling the inner sidewall material. The preset length of the filling cavity 40 can be set according to actual conditions. The selective etching process here can be a wet process or a dry process. The wet process and the dry process can refer to the existing technology, and the embodiments of the present invention will not be described in detail here.

[0083] (A2) Deposition of inner wall material; e.g. Figure 10 As shown, an inner sidewall material 37 is deposited in the filled cavity 40 and on the exposed surface of the fin structure by a deposition process.

[0084] Among them, the inner wall material deposition step requires that the thin film deposition process has good filling performance, which can achieve hole-free and gap-free filling of the cavity 40. Therefore, this step often adopts an atomic layer deposition process with excellent step coverage and conformal filling ability. In order to reduce the parasitic capacitance between the source / drain and the gate to a greater extent, a dielectric with a lower dielectric constant should be used as the material of the inner wall as much as possible. In practical applications, the dielectric material of the inner wall includes but is not limited to silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC) and silicon oxynitride and carbon monoxide (SiOCN), etc., and can be specifically set according to actual conditions. It should be noted that the deposition process of the inner wall material can refer to the existing technology, and the embodiments of the present invention will not be described in detail here.

[0085] (A3) Back etching of the inner sidewall material; that is, using the above-mentioned inner sidewall etching method to remove the inner sidewall material outside the cavity, forming an inner sidewall, such as Figure 7 As shown, in the etching method of the inner side wall, the selective etching process can be an anisotropic etching process or an isotropic etching process. The specific anisotropic etching process and the isotropic etching process can refer to the existing technology, and the embodiments of the present invention will not be described in detail here.

[0086] In summary, the preparation method of the semiconductor device provided by the embodiment of the present invention includes a deposition process stage, a trimming process stage and an etching process stage during the inner sidewall etching process. The deposition process stage uses a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, sidewall and bottom of the fin structure; the trimming process stage uses a second process gas to remove the polymer on the sidewall, and the etching process stage uses a third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall. This etching method has lower requirements on the etching selectivity and longitudinal / lateral etching ratio of the material of the fin structure, which is conducive to widening the process window and improving the process yield of the semiconductor device.

[0087] Furthermore, an embodiment of the present invention also provides a semiconductor device, which is manufactured using the above-mentioned method for manufacturing a semiconductor device.

[0088] The semiconductor device provided by the embodiment of the present invention has the same technical features as the method for preparing the semiconductor device provided by the above embodiment, and therefore can also solve the same technical problems and achieve the same technical effects.

[0089] An embodiment of the present invention also provides an electronic device, including a processor and a memory, wherein the memory stores machine executable instructions that can be executed by the processor, and the processor executes the machine executable instructions to implement the above-mentioned inner sidewall etching method and semiconductor device manufacturing method.

[0090] This embodiment also provides a machine-readable storage medium, which stores machine-executable instructions. When the machine-executable instructions are called and executed by a processor, the machine-executable instructions prompt the processor to implement the above-mentioned inner sidewall etching method and semiconductor device manufacturing method.

[0091] The inner sidewall etching method, semiconductor device manufacturing method and semiconductor device computer program product provided in the embodiments of the present invention include a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0092] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems and devices can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0093] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0094] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0095] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0096] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A method for etching an inner sidewall, applied to a semiconductor device, wherein the semiconductor device comprises a substrate and a fin structure formed on the substrate, wherein an inner sidewall material is deposited on an exposed surface of the fin structure; The method comprises: Deposition process stage: using a first process gas to form a polymer on the exposed surface of the fin structure; wherein the exposed surface includes the top, sidewalls and bottom of the trench of the fin structure; trimming process stage: removing the polymer on the sidewall by using a second process gas; Etching process stage: using the third process gas to remove the inner sidewall material on the sidewall to form the inner sidewall.

2. The method according to claim 1, characterized in that The first process gas includes a gas containing carbon and hydrogen elements.

3. The method according to claim 1, characterized in that The second process gas is a gas containing oxygen.

4. The method according to claim 1, wherein The third process gas includes a halogen etching gas.

5. The method according to claim 4, characterized in that The halogen etching gas includes at least one of the following: nitrogen trifluoride, carbon tetrafluoride, trifluoromethane and fluoromethane.

6. The method according to claim 1, characterized in that The polymer thickness at the top of the fin structure and the bottom of the trench is greater than the polymer thickness on the sidewalls.

7. The method according to claim 1, characterized in that During the trimming process stage and the etching process stage, the power of the lower RF power supply is 0W.

8. A method for preparing a semiconductor device, characterized in that: The method comprises: epitaxially growing a fin structure on a substrate; wherein the fin structure includes a sacrificial layer; Laterally etching the sacrificial layer to form a filling cavity of a preset length; depositing an inner sidewall material in the filled cavity and on the exposed surface of the fin structure; The inner sidewall etching method according to any one of claims 1 to 7 is used to remove the inner sidewall material outside the filled cavity to form the inner sidewall.

9. The method according to claim 8, characterized in that The step of epitaxially growing a fin structure on a substrate comprises: forming a stacked portion and a dummy gate on the substrate; wherein the stacked portion is located on the surface of the substrate and the sacrificial layers and the channel layers are alternately arranged in a direction away from the substrate, and the dummy gate is located on the surface of the stacked portion away from the substrate; A hard mask is deposited on an outer surface of the dummy gate, and the stacked portion, the dummy gate and the hard mask serve as the fin structure.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 8 to 9.

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