3D packaging method and 3D packaging structure

Abstract

The invention provides a 3D packaging method and a 3D packaging structure. A three-dimensional packaging structure based on a lead frame is realized by forming a bottom layer structure and forming at least one lamination structure on the bottom layer structure. The bottom layer structure comprises a lead frame, a bottom layer chip and a bottom layer plastic package layer, the lead frame comprises pins and a base island, and bottom layer vertical bonding wires are welded on the upper surfaces of at least one part of the pins; the laminated structure comprises a laminated chip, a laminated vertical bonding wire and a laminated plastic packaging layer wrapping the laminated chip and the laminated vertical bonding wire. Through the bottom layer vertical bonding wires of the bottom layer structure and the lamination vertical bonding wires of the different lamination structures, the lead frame is connected with the lamination chips of the different lamination structures, and therefore the requirements for size miniaturization and structure and function high integration of the frame type packaging structure are met.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to a 3D packaging method and a 3D packaging structure. Background Art

[0002] With the development of semiconductor technology, miniaturization and high integration of structure and function have become the development trend of semiconductor components, and three-dimensional stacking technology has become a widely used packaging technology.

[0003] In the semiconductor market, frame-type packaging occupies a certain market share due to its relatively simple production process and low frame manufacturing costs. However, frame-type packaging is mainly two-dimensional and has limited package integration.

[0004] However, with the development of semiconductor technology, miniaturization and high integration of structure and function have become the development trend of semiconductor components, and 3D packaging structure can adapt to the trend of miniaturization and integration.

[0005] How to provide a 3D packaging structure and process method based on a lead frame is of great significance to improving the integration of frame-type packaging. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a 3D packaging method and a 3D packaging structure, so that frame-type packaging can achieve miniaturization and high integration of structure and function.

[0007] In order to solve the above problems, the present invention provides a 3D packaging method, comprising:

[0008] A bottom structure is formed, the bottom structure comprising a lead frame, a bottom chip, and a bottom plastic encapsulation layer, the lead frame being located at the bottom of the bottom structure, the lead frame comprising pins and a base island, at least a portion of the upper surfaces of the pins being welded with bottom vertical bonding wires, the bottom chip being disposed on the upper surface of the base island of the lead frame, the bottom plastic encapsulation layer covering the lead frame, the bottom chip, and the bottom vertical bonding wires, and exposing the lower surfaces of the pins and the base island;

[0009] At least one stacked structure is formed on the underlying structure, and the stacked structure includes stacked chips, stacked vertical bonding wires, and a stacked plastic packaging layer covering the stacked chips and the stacked vertical bonding wires. The stacked chips and stacked vertical bonding wires of the bottom stacked structure are connected to the bottom vertical bonding wires of the underlying structure; when multiple layers of the stacked structure are formed on the underlying structure, the stacked chips of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure, and the stacked vertical bonding wires of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure.

[0010] In some embodiments, the steps of forming the underlying structure specifically include: providing the lead frame, the lead frame including the pins and the base island; mounting the underlying chip on the upper surface of the base island; welding wires between the underlying chip and the pins to achieve electrical connection between the underlying chip and the lead frame; welding the underlying vertical bonding wires on the upper surface of at least a portion of the pins; forming the underlying plastic encapsulation layer and exposing the pins and the lower surface of the base island.

[0011] In some embodiments, the step of soldering the bottom vertical bonding wires on the upper surface of at least a portion of the pins further includes soldering the bottom vertical bonding wires on the upper surface of the bottom chip.

[0012] In some embodiments, the step of soldering the bottom vertical bonding wire on the upper surface of at least a portion of the pins further includes soldering the bottom vertical bonding wire on the upper surface of the pin connected to the bonding wire.

[0013] In some embodiments, the step of soldering the bottom vertical bonding wire on the upper surface of at least a portion of the pins further includes soldering the bottom vertical bonding wire on the upper surface of the pins that are not connected to the bonding wire.

[0014] In some embodiments, the step of welding the bottom vertical bonding wire on the upper surface of at least a portion of the pins also includes: welding the bottom vertical bonding wire on the upper surface of the pins that are partially connected to the welding wires and welding the bottom vertical bonding wire on the upper surface of the pins that are not connected to the welding wires.

[0015] In some embodiments, the step of forming at least one stacked structure on the underlying structure includes the step of forming the bottom-most stacked structure on the underlying structure, which step specifically includes: exposing the underlying vertical bonding wires on the underlying structure; forming solder on the upper surface of the underlying vertical bonding wires; forming a stacked chip and a stacked vertical bonding wire on the underlying structure, and the stacked chip and the stacked vertical bonding wires are connected to the underlying vertical bonding wires of the underlying structure through the solder; and forming a stacked plastic encapsulation layer on the underlying structure to cover the stacked chip and the stacked vertical bonding wires.

[0016] In some embodiments, exposing the underlying vertical bonding wires on the underlying structure includes grinding a surface of the underlying structure to expose upper surfaces of the underlying vertical bonding wires.

[0017] In some embodiments, the step of forming a stacked chip and a stacked vertical bonding wire on the underlying structure specifically includes: arranging the stacked chip and the stacked vertical bonding wire on the underlying structure, and performing a welding process so that the stacked chip and the stacked vertical bonding wire are connected to the underlying vertical bonding wire of the underlying structure through the solder.

[0018] In some embodiments, the step of forming at least one stacked structure on the underlying structure includes the step of forming a first stacked structure on the lower stacked structure, which step specifically includes: exposing the stacked vertical bonding wires and solder pads of the stacked chip of the lower stacked structure on the lower stacked structure; forming solder on the upper surface of the stacked vertical bonding wires and solder pads of the stacked chip of the lower stacked structure; arranging the stacked chip and the stacked vertical bonding wire of the first stacked structure on the lower stacked structure, and performing a welding process, the stacked chip of the first stacked structure is connected to the stacked chip and the stacked vertical bonding wire of the lower stacked structure through the solder, and the stacked vertical bonding wire of the first stacked structure is connected to the stacked vertical bonding wire of the lower stacked structure through the solder; and forming a stacked plastic packaging layer of the first stacked structure covering the stacked chip and the stacked vertical bonding wire of the first stacked structure on the lower stacked structure.

[0019] In some embodiments, after the step of forming solder on the upper surfaces of the stacked vertical bonding wires and the pads of the stacked chip in the lower layer of the stacked structure, the method further includes: forming a metal layer on the pads corresponding to the wire bonding areas of the stacked chip in the lower layer of the stacked structure;

[0020] In some embodiments, the steps of arranging the stacked chip and stacked vertical bonding wire of the first stacked structure on the lower stacked structure and performing the welding process include: welding the welding wire between the metal layer and the bonding pad of the stacked chip of the first stacked structure that needs to be wired.

[0021] In some embodiments, the metal layer is formed by electroplating, and the metal layer is a single-layer or multi-layer circuit layer.

[0022] In some embodiments, the stacked chip of the first stacked structure comprises a through silicon via (TSV) therein, and the TSV serves as an electrical interconnection channel between the lower stacked structure and the upper stacked structure of the first stacked structure.

[0023] In some embodiments, in the step of forming the first stacked structure on the lower stacked structure, the first stacked structure is formed on the bottommost stacked structure.

[0024] In some embodiments, the step of forming at least one stacked structure on the underlying structure includes the step of forming a second stacked structure on the lower stacked structure, which specifically includes: exposing the stacked vertical bonding wires of the lower stacked structure and the solder pads of the stacked chip on the lower stacked structure; forming solder on the upper surface of the stacked vertical bonding wires of the lower stacked structure and the solder pads of the stacked chip; arranging the stacked chip of the second stacked structure on the lower stacked structure, and performing a welding process, wherein the stacked chip of the second stacked structure is connected to the stacked chip and the stacked vertical bonding wire of the lower stacked structure; and forming a stacked plastic encapsulation layer of the second stacked structure on the lower stacked structure to cover the stacked chip of the second stacked structure.

[0025] In some embodiments, in the step of forming the second stacked structure on the lower stacked structure, the second stacked structure is formed on the first stacked structure.

[0026] In some embodiments, the stacked chip of the second stacked structure does not include a through silicon via.

[0027] In some embodiments, all the laminated plastic encapsulation layers of the laminated structure are made of the same material as the bottom plastic encapsulation layer.

[0028] In some embodiments, after the step of forming the stacked structure, the method further includes: forming a protection layer on the lower surfaces of the base island and the pins.

[0029] In order to solve the above problems, the present invention further provides a 3D packaging structure, comprising:

[0030] A bottom structure, comprising a lead frame, a bottom chip, and a bottom plastic encapsulation layer, wherein the lead frame is located at the bottom of the bottom structure, the lead frame comprises pins and a base island, at least a portion of the upper surfaces of the pins are welded with bottom vertical bonding wires, the bottom chip is arranged on the upper surface of the base island of the lead frame, the bottom plastic encapsulation layer covers the lead frame, the bottom chip, and the bottom vertical bonding wires, and exposes the lower surfaces of the pins and the base island;

[0031] At least one stacked structure is formed on the underlying structure, the stacked structure includes a stacked chip, a stacked vertical bonding wire and a stacked plastic packaging layer covering the stacked chip and the stacked vertical bonding wire, the stacked chip and the stacked vertical bonding wire of the bottom layer of the stacked structure are connected to the bottom layer vertical bonding wire of the underlying structure; when the stacked structure on the underlying structure is multi-layer, the stacked chip of the upper stacked structure is connected to the stacked chip and / or the stacked vertical bonding wire of the lower stacked structure, and the stacked vertical bonding wire of the upper stacked structure is connected to the stacked chip and / or the stacked vertical bonding wire of the lower stacked structure.

[0032] In some embodiments, the bottom chip and the pins are connected via bonding wires.

[0033] In some embodiments, the upper surface of a portion of the pin connected to the bonding wire is provided with the bottom vertical bonding wire; the upper surface of the pin not connected to the bonding wire is provided with the bottom vertical bonding wire.

[0034] In some embodiments, the bottom layer vertical bonding wires are disposed on the upper surface of the bottom layer chip.

[0035] In some embodiments, a bottom-layer stacked structure is formed on the bottom-layer structure, and bumps and stacked vertical bonding wires of the stacked chips of the bottom-layer stacked structure are welded to the bottom-layer vertical bonding wires of the bottom-layer structure through solder.

[0036] In some embodiments, a first stacked structure is formed on the lower stacked structure, and the stacked chips of the first stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure through solder; the stacked vertical bonding wires of the first stacked structure are connected to the vertical bonding wires of the lower stacked structure through solder.

[0037] In some embodiments, a metal layer is formed on the pad corresponding to the wire bonding pressure area of ​​the stacked chip of the lower stacked structure, and the metal layer and the pad requiring wire bonding of the stacked chip of the first stacked structure are connected via wire bonding wires.

[0038] In some embodiments, the first stacked structure is formed on the bottommost stacked structure.

[0039] In some embodiments, the stacked chips of the first stacked structure include through silicon vias (TSVs).

[0040] In some embodiments, the second stacked structure is formed on the first stacked structure.

[0041] In some embodiments, the second stacked structure is formed on the bottommost stacked structure.

[0042] In some embodiments, all the laminated plastic sealing layers of the laminated structure are made of the same material as the bottom plastic sealing layer, and all the laminated plastic sealing layers of the laminated structure and the bottom plastic sealing layer together serve as an integral plastic sealing layer.

[0043] In some embodiments, a protection layer is provided on the lower surfaces of the base island and the pins.

[0044] The above technical solution forms a bottom structure and at least one stacked structure on the bottom structure. The bottom structure includes a lead frame, a bottom chip, and a bottom plastic encapsulation layer. The lead frame includes pins and a base island, and at least a portion of the top surface of the pins is welded with bottom vertical bonding wires. The stacked structure includes a stacked chip, stacked vertical bonding wires, and a stacked plastic encapsulation layer covering the stacked chip and the stacked vertical bonding wires. The bottom vertical bonding wires of the bottom structure and the stacked vertical bonding wires of different stacked structures are used to connect the lead frame to stacked chips of different stacked structures, thereby realizing a three-dimensional packaging structure based on the lead frame, thereby achieving the requirements of miniaturization, structure, and function high integration of the frame-type packaging structure.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present invention. Technologies, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0047] Figure 1 is a flow chart of a 3D packaging method provided by one embodiment of the present invention;

[0048] Figure 2 is a flowchart of specific steps for forming an underlying structure according to an embodiment of the present invention;

[0049] Figure 3 is a flow chart of specific steps for forming the bottom layer of the stacked structure on the bottom layer structure according to one embodiment of the present invention;

[0050] Figure 4 is a flow chart of specific steps for forming a first stacked structure on the lower stacked structure provided by one embodiment of the present invention;

[0051] Figure 5 is a flow chart of specific steps for forming a second stacked structure on a lower stacked structure according to one embodiment of the present invention;

[0052] Figure 6 is a schematic diagram of the device structure of the lead frame provided by one embodiment of the present invention;

[0053] Figure 7 1 is a schematic diagram of a device structure formed by the step of attaching the bottom chip to the upper surface of the base island according to an embodiment of the present invention;

[0054] Figure 8 1 is a schematic diagram of a device structure formed by the step of welding wires between the bottom chip and the pins provided in one embodiment of the present invention;

[0055] Figure 9 Schematic diagram of a device structure formed by welding the bottom vertical bonding wires on the upper surface of at least a portion of the pins according to an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of a device structure formed by the step of forming the bottom plastic encapsulation layer provided by an embodiment of the present invention;

[0057] Figure 11 1 is a schematic diagram of a device structure formed by exposing the bottom layer vertical bonding wires on the bottom layer structure according to an embodiment of the present invention;

[0058] Figure 12 1 is a schematic diagram of a device structure formed by forming solder on the upper surface of the bottom vertical bonding wire according to an embodiment of the present invention;

[0059] Figure 13 Schematic diagram of a device structure formed by welding the bumps of the stacked chip at the bottom layer of the stacked structure to the vertical bonding wires at the corresponding positions of the bottom layer provided by one embodiment of the present invention;

[0060] Figure 14 Schematic diagram of a device structure formed by welding the bumps of the stacked chip at the bottom layer of the stacked structure to the vertical bonding wires at the corresponding positions of the bottom layer provided by one embodiment of the present invention;

[0061] Figure 15 1. It is a schematic diagram of a device structure formed by the step of forming a laminated plastic encapsulation layer of the bottom layer of the laminated structure on the bottom layer structure provided by one embodiment of the present invention;

[0062] Figure 16Schematic diagram of a device structure formed by exposing the stacked vertical bonding wires and the bonding pads of the stacked chip on the lower stacked structure when forming the first stacked structure according to one embodiment of the present invention;

[0063] Figure 17 Schematic diagram of a device structure formed by forming solder on the upper surfaces of the stacked vertical bonding wires and the bonding pads of the stacked chip in the lower layer of the stacked structure when forming the first stacked structure according to one embodiment of the present invention;

[0064] Figure 18 Schematic diagram of a device structure formed by forming a metal layer on a pad corresponding to a wire bonding pressure zone of a stacked chip of a lower stacked structure according to an embodiment of the present invention;

[0065] Figure 19 Schematic diagram of a device structure formed by welding the stacked chips of the first stacked structure to the stacked chips and stacked vertical bonding wires of the lower stacked structure provided by one embodiment of the present invention;

[0066] Figure 20 1. A schematic diagram of a device structure formed by welding a bonding wire between the metal layer and a bonding pad requiring bonding of a stacked chip of the first stacked structure according to an embodiment of the present invention;

[0067] Figure 21 Schematic diagram of a device structure formed by welding the stacked vertical bonding wires of the first stacked structure and the stacked vertical bonding wires of the lower stacked structure according to an embodiment of the present invention;

[0068] Figure 22 2 is a schematic diagram of a device structure formed by the step of forming the laminated plastic encapsulation layer of the first laminated structure provided by an embodiment of the present invention;

[0069] Figure 23 Schematic diagram of a device structure formed by exposing the stacked vertical bonding wires and the bonding pads of the stacked chip on the lower stacked structure when forming the second stacked structure according to one embodiment of the present invention;

[0070] Figure 24 Schematic diagram of a device structure formed by forming solder on the upper surfaces of the stacked vertical bonding wires and the bonding pads of the stacked chip in the lower layer of the stacked structure when forming the second stacked structure according to one embodiment of the present invention;

[0071] Figure 25 Schematic diagram of a device structure formed by the step of arranging a stacked chip of the second stacked structure on the lower stacked structure provided in one embodiment of the present invention;

[0072] Figure 262 is a schematic diagram of a device structure formed by the steps of forming a second stacked structure of a stacked chip covering a second stacked structure of the second stacked structure according to an embodiment of the present invention;

[0073] Figure 27 It is a schematic diagram of a device structure formed by the step of forming a protective layer on the lower surface of the base island and the pins provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0074] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0075] like Figure 1 As shown, the 3D packaging method includes: step S1, forming a bottom structure, the bottom structure includes a lead frame, a bottom chip and a bottom plastic packaging layer, the lead frame is located at the bottom of the bottom structure, the lead frame includes pins and a base island, at least a portion of the upper surface of the pins is welded with a bottom vertical bonding wire, the bottom chip is arranged on the upper surface of the base island of the lead frame, the bottom plastic packaging layer covers the lead frame, the bottom chip and the bottom vertical bonding wire, and exposes the lower surface of the pins and the base island; step S2, forming a bottom plastic packaging layer on the bottom structure. There is at least one stacked structure, the stacked structure includes a stacked chip, a stacked vertical bonding wire and a stacked plastic packaging layer covering the stacked chip and the stacked vertical bonding wire, the stacked chip and the stacked vertical bonding wire of the bottom layer of the stacked structure are connected to the bottom layer vertical bonding wire of the bottom layer structure; when multiple layers of the stacked structure are formed on the bottom layer structure, the stacked chip of the upper layer of the stacked structure is connected to the stacked chip and / or the stacked vertical bonding wire of the lower layer of the stacked structure, and the stacked vertical bonding wire of the upper layer of the stacked structure is connected to the stacked chip and / or the stacked vertical bonding wire of the lower layer of the stacked structure.

[0076] The underlying structure is a structure formed by encapsulating the frame structure and related devices. The stacked structure is a unit layer, which can be formed directly on the underlying structure or on another stacked structure. A layer of the stacked structure or multiple layers of the stacked structure can be formed on the underlying structure, wherein the stacked structure directly formed on the underlying structure is referred to as the bottom layer of the stacked structure, and the stacked structure located at the top of all the stacked structures is referred to as the top layer of the stacked structure. When multiple layers of the stacked structure are formed on the underlying structure, the stacked structure located above the two adjacent stacked structures is referred to as the upper layer of the stacked structure, and the stacked structure located below is referred to as the lower layer of the stacked structure.

[0077] When two layers of the stacked structure are formed on the underlying structure, the stacked structure directly formed on the underlying structure can be referred to as the bottom layer stacked structure or the lower layer stacked structure, and the stacked structure located on the top layer can be referred to as the upper layer stacked structure or the top layer stacked structure.

[0078] The bottom layer of the stacked structure does not have the lower layer of the stacked structure, but only has the upper layer of the stacked structure; the top layer of the stacked structure does not have the upper layer of the stacked structure, but only has the lower layer of the stacked structure.

[0079] An embodiment of the present invention provides a specific implementation of the 3D packaging method.

[0080] Regarding step S1, Figure 2 As shown, the steps of forming the underlying structure specifically include: step S101, providing the lead frame, the lead frame including the pins and the base island; step S102, mounting the underlying chip on the upper surface of the base island; step S103, welding wires between the underlying chip and the pins to achieve electrical connection between the underlying chip and the lead frame; step S104, welding the underlying vertical bonding wires on the upper surface of at least a portion of the pins; step S105, forming the underlying plastic packaging layer and exposing the pins and the lower surface of the base island.

[0081] Refer to step S101 and Figure 6 , providing the lead frame, which includes the pins 101 and the base island 102. The lead frame is a core component in semiconductor packaging, primarily used to achieve electrical connection between the chip and external circuits, and provide mechanical support and heat dissipation for the chip. The base island 102 is located at the center of the lead frame and serves as a platform for supporting the chip. The pins 101 are distributed around the base island 102.

[0082] Refer to step S102 and Figure 7 , the bottom chip 103 is mounted on the upper surface of the base island 102. The bottom chip 103 faces upward and is bonded to the upper surface of the base island 102 by patch adhesive.

[0083] Refer to step S103 and Figure 8 , welding wires 104 between the bottom chip 103 and the pins 101 to achieve electrical connection between the bottom chip 103 and the lead frame.

[0084] Refer to step S104 and Figure 9 , welding the bottom vertical bonding wire 105 on the upper surface of at least a portion of the pin 101. The bottom vertical bonding wire 105 is used to establish an electrical connection between the lead frame and the stacked structure. This step can be performed as follows: (1) welding the bottom vertical bonding wire 105 on the upper surface of the pin 101 connected to the bonding wire 104; (2) welding the bottom vertical bonding wire 105 on the upper surface of the pin 101 not connected to the bonding wire 104; (3) welding the bottom vertical bonding wire 105 on the upper surface of the pin 101 partially connected to the bonding wire 104 and welding the bottom vertical bonding wire 105 on the upper surface of the pin 101 not connected to the bonding wire 104.

[0085] In this embodiment, this step is performed according to (3). Specifically, Figure 9 As shown, the bottom vertical bonding wire 105 is provided on the upper surface of the pin 101 where the bonding wire 104 is partially provided, and the bottom vertical bonding wire 105 is provided on the upper surface of the pin 101 where the bonding wire 104 is not provided.

[0086] This step also includes welding the bottom vertical bonding wires 105 on the upper surface of the bottom chip 103. The bottom vertical bonding wires 105 on the upper surface of the bottom chip 103 are used to electrically connect the bottom chip with the upper chip.

[0087] The pins 101 or the bottom vertical bonding wires 105 on the bottom chip 103 all correspond to the bumps of the stacked chips formed on the bottom structure. Furthermore, the bumps of the stacked chips of different stacked structures can all match the interconnected bottom vertical bonding wires 105 in the bottom structure.

[0088] Refer to step S105 and Figure 10, forming the bottom plastic encapsulation layer 106 and exposing the bottom surface of the pins 101 and the base island 102. The bottom plastic encapsulation layer 106 covers the lead frame, the bottom chip 103, the bonding wires 104, and the bottom vertical bonding wires 105 to protect the components covered by the bottom plastic encapsulation layer 106.

[0089] The lead frame, the bottom chip 103 , the bonding wires 104 , the bottom vertical bonding wires 105 and the bottom plastic encapsulation layer 106 together form the bottom structure 10 .

[0090] Regarding step S2 , forming at least one stacked structure on the underlying structure 10 at least includes the step of forming the bottommost stacked structure on the underlying structure 10 .

[0091] like Figure 3 As shown, the steps of forming the bottom layer of the stacked structure on the bottom layer structure 10 specifically include: step S201, exposing the bottom layer vertical bonding wire on the bottom layer structure; step S202, forming solder on the upper surface of the bottom layer vertical bonding wire; step S203, forming a stacked chip and a stacked vertical bonding wire on the bottom layer structure, and the stacked chip and the stacked vertical bonding wire are connected to the bottom layer vertical bonding wire of the bottom layer structure through the solder; step S204, forming a stacked plastic packaging layer covering the stacked chip and the stacked vertical bonding wire on the bottom layer structure to form the bottom layer of the stacked structure.

[0092] Refer to step S201 and Figure 11 , exposing the bottom layer vertical bonding wires 105 on the bottom layer structure 10. This step specifically includes: grinding the surface of the bottom layer structure 10 to expose the upper surface of the bottom layer vertical bonding wires 105.

[0093] Refer to step S202 and Figure 12 , forming solder on the upper surface of the bottom vertical bonding wire 105. Specifically, solder paste can be applied on the upper surface of the bottom vertical bonding wire 105 and then solidified to form the solder 112.

[0094] In some embodiments, in step S201, vias are formed on the underlying structure 10, exposing the underlying vertical bonding wires 105 through the vias. The positions of the vias correspond one-to-one with the positions of the underlying vertical bonding wires 105. Accordingly, in step S202, during the step of forming solder on the upper surfaces of the underlying vertical bonding wires 105, solder 112 is formed within the vias.

[0095] Refer to step S203 and Figure 13 、 Figure 14, a stacked chip 113 and a stacked vertical bonding wire 115 are formed on the bottom structure 10, and the stacked chip 113 and the stacked vertical bonding wire 115 are connected to the bottom vertical bonding wire 105 of the bottom structure 10 through the solder 112. Figure 13 As shown, one surface of the bottom-layer stacked chip 113 has bumps 116, and the other surface of the bottom-layer stacked chip 113 has pads 114 for electrical connection to an external circuit. The one surface and the other surface of the stacked chip 113 are located on opposite sides of the stacked chip 113. The bumps 116 and the pads 114 are disposed on opposite sides of the stacked chip 113 in a one-to-one correspondence and are electrically connected to each other.

[0096] In this step, the step of forming the stacked chip 113 and the stacked vertical bonding wire 115 on the underlying structure 10 specifically includes: arranging the stacked chip 113 and the stacked vertical bonding wire 115 on the underlying structure 10, and performing a welding process to connect the stacked chip 113 and the stacked vertical bonding wire 115 to the underlying vertical bonding wire 105 of the underlying structure 10 through the solder 112.

[0097] Specifically, if Figure 13 As shown, the stacked chip 113 of the bottom layer of the stacked structure is flipped on the bottom layer structure 10, and the bumps 116 of the stacked chip 113 of the bottom layer of the stacked structure are welded to the bottom layer vertical bonding wires 105 at corresponding positions through the solder 112, so that the stacked chip 113 of the bottom layer of the stacked structure is electrically connected to the bottom layer structure 10; Figure 14 As shown, the stacked vertical bonding wire 115 of the bottom layer of the stacked structure is welded with the bottom layer vertical bonding wire 105 of the bottom layer structure 10 by the solder 112, and the stacked vertical bonding wire 115 of the bottom layer of the stacked structure is used to electrically connect the upper layer of the stacked structure with the bottom layer structure.

[0098] Refer to step S204 and Figure 15 A laminated plastic encapsulation layer 117 of the bottom layer of the laminated structure 11 is formed on the bottom structure 10, covering the laminated chip 113 and the laminated vertical bonding wires 115 of the bottom layer of the laminated structure 11. The laminated chip 113, the laminated vertical bonding wires 115, and the laminated plastic encapsulation layer 117 together form the bottom layer of the laminated structure 11.

[0099] The laminated plastic encapsulation layer 117 of the bottom layer of the laminated structure 11 is made of the same material as the bottom layer of the plastic encapsulation layer 106. After this step is completed, the laminated plastic encapsulation layer 117 of the bottom layer of the laminated structure 11 and the bottom layer of the plastic encapsulation layer 106 are integrated.

[0100] A plurality of stacked structures may be formed on the bottom stacked structure 11. Except for the bottom stacked structure 11, each stacked structure has a corresponding lower stacked structure.

[0101] In step S1, the step of forming at least one stacked structure on the underlying structure includes the step of forming a first stacked structure on the underlying stacked structure, wherein the first stacked structure is one stacked structure.

[0102] like Figure 4 As shown, the specific steps of forming the first stacked structure on the lower stacked structure include: step S205, exposing the stacked vertical bonding wires of the lower stacked structure and the solder pads of the stacked chip on the lower stacked structure; step S206, forming solder on the upper surface of the stacked vertical bonding wires and the solder pads of the stacked chip of the lower stacked structure; step S207, arranging the stacked chip and the stacked vertical bonding wire of the first stacked structure on the lower stacked structure, and performing a welding process, the stacked chip of the first stacked structure is connected to the stacked chip and the stacked vertical bonding wire of the lower stacked structure through the solder, and the stacked vertical bonding wire of the first stacked structure is connected to the stacked vertical bonding wire of the lower stacked structure through the solder; step S208, forming a stacked plastic packaging layer covering the stacked chip and the stacked vertical bonding wire of the first stacked structure on the lower stacked structure.

[0103] The bottommost stacked structure may be used as the lower stacked structure of the first stacked structure.

[0104] This embodiment provides a step of forming a first stacked structure on the bottom stacked structure 11 .

[0105] Refer to step S205 and Figure 16 The stacked vertical bonding wires 115 of the bottom layer of the stacked structure 11 and the bonding pads 114 of the stacked chip 113 are exposed on the bottom layer of the stacked structure 11 through a grinding process.

[0106] In some embodiments, a laser drilling process is used to form via holes in the bottom layer of the stacked structure 11, exposing the stacked vertical bonding wires 115 of the bottom layer of the stacked structure 11 and the pads 114 of the stacked chip 113 through the via holes. The depth of the holes needs to expose the top surface of the stacked vertical bonding wires 115 of the bottom layer of the stacked structure 11 and the pads 114 of the stacked chip 113.

[0107] Refer to step S206 and Figure 17 , solder 122 is formed on the upper surfaces of the stacked vertical bonding wires 115 of the bottom layer of the stacked structure 11 and the pads 114 of the stacked chip 113. Specifically, solder paste is applied to the upper surfaces of the stacked vertical bonding wires 115 of the bottom layer of the stacked structure 11 and the pads 114 of the stacked chip 113, and then solidified to form the solder 122.

[0108] The following is a further description of step S207.

[0109] like Figure 19 As shown, step S207 includes: step a), soldering the stacked chip 124 of the first stacked structure to the stacked chip 113 and the stacked vertical bonding wire 115 of the bottom stacked structure 11 using the solder 122. The stacked chip 124 of the first stacked structure is flip-chip mounted on the bottom stacked structure 11.

[0110] like Figure 19 As shown, the lower surface of the stacked chip 124 of the first stacked structure has a bump 126, and the upper surface of the stacked chip 124 of the first stacked structure has a solder pad 127. Accordingly, step a) specifically includes: 1) soldering the bump 126 of the stacked chip 124 of the first stacked structure to the solder pad 114 of the stacked chip 113 of the stacked structure 11 at the corresponding bottom position using the solder 122; 2) soldering the bump 126 of the stacked chip 124 of the first stacked structure to the stacked vertical bonding wire 115 of the stacked structure 11 at the corresponding bottom position using the solder 122.

[0111] like Figure 21 As shown, step S207 further includes: step b), soldering the stacked vertical bonding wires 128 of the first stacked structure to the stacked vertical bonding wires 115 of the bottom stacked structure 11 using the solder 122. This allows the stacked chips of the upper stacked structure of the first stacked structure to be electrically connected to the lead frame through the stacked vertical bonding wires 128 of the first stacked structure.

[0112] When the stacked chip of the lower stacked structure has a pressure area that requires wire bonding, after the step of forming solder on the upper surface of the stacked vertical bonding wire of the lower stacked structure and the solder pad of the stacked chip, it includes: step S2061, forming a metal layer on the solder pad corresponding to the pressure area of ​​the wire bonding of the stacked chip of the lower stacked structure.

[0113] Corresponding to step S2061, the step of placing the stacked chip and stacked vertical bonding wires of the first stacked structure on the lower stacked structure and performing a bonding process further includes step S2071 of bonding wires between the metal layer and the bonding pads of the stacked chip of the first stacked structure to be bonded. Here, the order of executing steps S207 is: step a) -> step S2071 -> step b).

[0114] During the process of forming the first stacked structure on the lower stacked structure, step S2061 and step S2071 occur correspondingly.

[0115] The following describes step S2061 and step S2071 in conjunction with the device structure diagram.

[0116] In this embodiment, a first stacked structure is formed on the bottom stacked structure 11. Figure 18 Step S2061 specifically includes electroplating a metal layer 123 on the bonding pads corresponding to the wire bonding areas of the stacked chips 113 of the bottom layer of the stacked structure 11. The metal layer 123 serves as a transition, leading out to the bonding areas of the stacked chips of the lower layer of the stacked structure. The bonding areas are the pad areas of the stacked chips. The metal layer 123 can be a single or multiple circuit layers.

[0117] In some embodiments, the metal layer 123 is formed by attaching a copper sheet.

[0118] In this embodiment, a first stacked structure is formed on the bottom stacked structure 11 . Figure 20 This is a schematic diagram of a device structure formed by welding a wire between the metal layer and the bonding pad of the stacked chip requiring wire bonding provided by an embodiment of the present invention. Figure 20 Step S2071 specifically includes: welding a bonding wire 125 between the metal layer 123 and the bonding pad 127 of the stacked chip 124 of the first stacked structure that needs to be wired.

[0119] Refer to step S208 and Figure 22A laminated plastic encapsulation layer 129 is formed on the lower laminated structure to cover the laminated chips 124 and laminated vertical bonding wires 128 of the first laminated structure, thereby protecting the internal structure of the first laminated structure. The laminated plastic encapsulation layer 129 of the first laminated structure and the components encapsulated therein together form the first laminated structure 12.

[0120] The laminated plastic encapsulation layer 129 of the first laminated structure is made of the same material as the bottom plastic encapsulation layer 106. After this step is completed, the laminated plastic encapsulation layer 129 of the first laminated structure, the laminated plastic encapsulation layer 117 of the bottom laminated structure 11 and the bottom plastic encapsulation layer 106 are integrated.

[0121] The stacked chips 124 of the first stack structure contain through-silicon vias (TSVs) that serve as electrical interconnects between the lower and upper stack structures of the first stack structure. The vertically conductive TSVs enable inter-chip connectivity, reducing interconnect length, signal latency, capacitance, and inductance, enabling low-power, high-speed communication between chips, increasing bandwidth, and achieving miniaturization.

[0122] The first stacked structure formed can serve as the lower stacked structure of another stacked structure. Therefore, steps S205 to S208 can be continued on the first stacked structure to form a new stacked structure. Furthermore, steps S205 to S208 can be performed multiple times to form multiple layers of the stacked structure, thereby achieving chip stacking.

[0123] In step S1 , forming at least one stacked structure on the underlying structure includes forming a second stacked structure on the underlying stacked structure.

[0124] like Figure 5 As shown, the step of forming at least one stacked structure on the underlying structure includes the step of forming a second stacked structure on the lower stacked structure, specifically including: step S209, exposing the stacked vertical bonding wires of the lower stacked structure and the solder pads of the stacked chip on the lower stacked structure; step S210, forming solder on the upper surface of the stacked vertical bonding wires of the lower stacked structure and the solder pads of the stacked chip; step S211, arranging the stacked chip of the second stacked structure on the lower stacked structure, and performing a welding process, and the stacked chip of the second stacked structure is connected to the stacked chip and the stacked vertical bonding wire of the lower stacked structure; step S212, forming a stacked plastic encapsulation layer of the second stacked structure covering the stacked chip of the second stacked structure on the lower stacked structure.

[0125] In this embodiment, in the step of forming the second stacked structure on the lower stacked structure, the first stacked structure 12 is used as the lower stacked structure, and the second stacked structure is formed on the first stacked structure 12 .

[0126] Refer to step S209 and Figure 23 The stacked vertical bonding wires 128 of the first stacked structure 12 and the bonding pads 127 of the stacked chip 124 are exposed on the first stacked structure 12 through a grinding process.

[0127] In some embodiments, a laser drilling process is used to form via holes on the first stacked structure 12 , and the stacked vertical bonding wires 128 of the first stacked structure 12 and the pads 127 of the stacked chip 124 are exposed through the via holes.

[0128] Refer to step S210 and Figure 24 Solder 132 is formed on the upper surfaces of the stacked vertical bonding wires 128 of the first stacked structure 12 and the pads 127 of the stacked chip 124. Specifically, solder paste is applied to the upper surfaces of the stacked vertical bonding wires 128 of the first stacked structure 12 and the pads 127 of the stacked chip 124, and then solidified to form the solder 132.

[0129] Refer to step S211 and Figure 25 The stacked chip of the second stacked structure is placed on the first stacked structure 12, and a welding process is performed to connect the stacked chip 133 of the second stacked structure to the stacked chip 124 and stacked vertical bonding wires 128 of the first stacked structure 12. In this step, the stacked chip 133 of the second stacked structure is flip-chip mounted on the first stacked structure 12.

[0130] like Figure 25 As shown, the lower surface of the stacked chip 133 of the second stacked structure has a bump 134. Accordingly, this step specifically includes: soldering the bump 134 of the stacked chip 133 of the second stacked structure to the pad 127 of the stacked chip 124 of the first stacked structure 12 at the corresponding position using the solder 132; and soldering the bump 134 of the stacked chip 133 of the second stacked structure to the stacked vertical bonding wire 128 of the first stacked structure 12 at the corresponding position using the solder 132.

[0131] Refer to step S212 and Figure 26 A second laminated structure laminated plastic encapsulation layer 135 is formed on the first laminated structure 12 to encapsulate the second laminated structure laminated chips 133, thereby protecting the internal structure of the second laminated structure. The second laminated structure laminated plastic encapsulation layer 135 and the components encapsulated therein together form the second laminated structure 13.

[0132] The laminated plastic encapsulation layer 135 of the second laminated structure is made of the same material as the bottom plastic encapsulation layer 106. After this step is completed, the laminated plastic encapsulation layer 135 of the second laminated structure, the laminated plastic encapsulation layer 129 of the first laminated structure, the laminated plastic encapsulation layer 117 of the bottommost laminated structure 11, and the bottom plastic encapsulation layer 106 are formed into a single body.

[0133] The stacked chip 135 of the second stacked structure 13 does not include through silicon vias. The second stacked structure 13 can serve as the topmost stacked structure. That is, steps S209 to S212 can be used to form the topmost stacked structure.

[0134] like Figure 5 As shown, after the step of forming the stacked structure, the method further includes: step S213, forming a protection layer on the lower surface of the base island and the pin.

[0135] Refer to step S213 and Figure 27 A protection layer 107 is formed on the lower surface of the base island 102 and the pin 101. In this embodiment, the protection layer 107 is formed by tin plating. The protection layer 107 protects the lead frame from oxidation, facilitating the surface mounting process.

[0136] In this embodiment, all the laminated plastic encapsulation layers of the laminated structure are made of the same material as the bottom plastic encapsulation layer 106. Therefore, the bottom plastic encapsulation layer 106 and the laminated plastic encapsulation layers of each of the laminated structures form an integral plastic encapsulation layer, which covers the bottom structure 10 and all the devices in the laminated structure.

[0137] Through the above-mentioned 3D packaging method, a three-dimensional frame packaging method is provided, which realizes miniaturization and high integration of structure and function based on lead frame packaging.

[0138] Based on the same inventive concept, the present application also provides a 3D packaging structure.

[0139] refer to Figure 27 The 3D packaging structure includes: a bottom structure 10 and at least one stacked structure. The bottom structure includes a lead frame, a bottom chip 103, and a bottom plastic encapsulation layer 106. The lead frame is located at the bottom of the bottom structure 10. The lead frame includes pins 101 and a base island 102. At least a portion of the upper surface of the pins 101 is welded with bottom vertical bonding wires 105. The bottom chip 103 is arranged on the upper surface of the base island 102 of the lead frame. The bottom plastic encapsulation layer 106 covers the lead frame, the bottom chip 103, and the bottom vertical bonding wires 105, and exposes the lower surfaces of the pins 101 and the base island 102.

[0140] In this embodiment, the bottom chip 103 and the pins 101 are connected via bonding wires 104 .

[0141] The bottom vertical bonding wire 105 is provided on the upper surface of the portion of the pins 101 connected to the bonding wire 104 ; the bottom vertical bonding wire 105 is provided on the upper surface of the pins 101 not connected to the bonding wire 104 .

[0142] The bottom chip 103 is bonded to the upper surface of the base island 102 by die bonding adhesive, and the bottom vertical bonding wires 105 are provided on the upper surface of the bottom chip 103 .

[0143] The stacked structure is formed on the underlying structure 10, and the stacked structure includes stacked chips, stacked vertical bonding wires, and a stacked plastic packaging layer covering the stacked chips and the stacked vertical bonding wires. The stacked chips and stacked vertical bonding wires of the bottom layer of the stacked structure are connected to the bottom layer vertical bonding wires of the underlying structure; when the stacked structure on the underlying structure is multi-layer, the stacked chips of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure, and the stacked vertical bonding wires of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure.

[0144] The following combination Figure 27 The stacked structure will be described in detail.

[0145] The bottom layer of the laminated structure 11 is formed on the bottom layer structure 10. The laminated chips 113 and laminated vertical bonding wires 115 of the bottom layer of the laminated structure 11 are connected to the bottom layer of the vertical bonding wires 105 of the bottom layer structure 10 via solder. The laminated chips 113 and laminated vertical bonding wires 115 of the bottom layer of the laminated structure 11 are covered by the laminated plastic encapsulation layer 117 of the bottom layer of the laminated structure 11. The laminated plastic encapsulation layer 117 of the bottom layer of the laminated structure 11 is integrally formed with the bottom layer of the plastic encapsulation layer 106.

[0146] The bottom surface of the stacked chip 113 of the bottom stacked structure 11 has bumps 116, and the top surface of the stacked chip 113 of the bottom stacked structure has solder pads 114. The bumps 116 and stacked vertical bonding wires 115 of the stacked chip 113 of the bottom stacked structure 11 are soldered to the bottom vertical bonding wires 105 of the bottom structure 10 via solder.

[0147] Except for the bottom-layer laminated structure 11, each of the laminated structures has a corresponding lower-layer laminated structure.

[0148] In some scenarios, a first stacked structure is formed on the lower stacked structure, and the stacked chips of the first stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure through solder; the stacked vertical bonding wires of the first stacked structure are connected to the vertical bonding wires of the lower stacked structure through solder; the stacked chips and stacked vertical bonding wires of the first stacked structure are covered by the stacked plastic packaging layer of the first stacked structure.

[0149] Figure 27 In the embodiment, the bottom layer of the laminated structure 11 is used as the lower layer of the laminated structure, and the first laminated structure 12 is formed on the bottom layer of the laminated structure 11. Figure 27 As shown, the stacked chips 124 of the first stacked structure 12 are connected to the stacked chips 113 and stacked vertical bonding wires 115 of the bottom stacked structure 11 via solder; the stacked vertical bonding wires 128 of the first stacked structure 12 are connected to the vertical bonding wires 115 of the bottom stacked structure 11 via solder; and the stacked chips 124 and stacked vertical bonding wires 128 of the first stacked structure 12 are covered by the stacked plastic encapsulation layer 129 of the first stacked structure 12. The solder is formed by solidifying tin paste.

[0150] A metal layer is formed on the pad corresponding to the wire bonding pressure area of ​​the stacked chip of the lower stacked structure, and the metal layer and the pad requiring wire bonding of the stacked chip of the first stacked structure are connected via bonding wires.

[0151] Correspondingly, such as Figure 27 As shown, a metal layer 123 is formed on the pad corresponding to the wire bonding pressure area of ​​the stacked chip 113 of the bottom stacked structure 11, and the metal layer 123 is connected to the pad that needs to be wire bonded of the stacked chip 124 of the first stacked structure 12 through a bonding wire 125. The metal layer 123 plays a transition role and is used to lead out the pressure area of ​​the lower chip. Figure 27 In the middle, a pressing area is used to lead out the stacked chip 113 of the stacked structure 11 at the bottom layer.

[0152] The stacked chips 124 of the first stacked structure 12 include through silicon vias (TSVs) therein.

[0153] The first stacked structure 12 can serve as a lower stacked structure of another stacked structure. That is, once formed, the first stacked structure 12 can serve as a lower stacked structure of an upper stacked structure. The first stacked structures 12 can be stacked in multiple layers. In some embodiments, stacking the first stacked structures 12 significantly increases packaging density and reduces overall packaging volume.

[0154] In some scenarios, a second stacked structure is formed on the lower stacked structure, and the stacked chips of the second stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure through solder; the stacked chips of the second stacked structure are covered by the stacked plastic packaging layer of the second stacked structure.

[0155] Figure 27 In the embodiment, the first stacked structure 12 is used as the lower stacked structure, and the second stacked structure 13 is formed on the first stacked structure 12. Figure 27 As shown, the laminated chips 133 of the second laminated structure 13 are connected to the laminated chips 124 and laminated vertical bonding wires 128 of the first laminated structure 12 via solder; the laminated chips 133 of the second laminated structure 13 are covered by the laminated plastic layer 135 of the second laminated structure 13. The second laminated structure 13 can serve as the topmost laminated structure.

[0156] The stacked chips 133 of the second stacked structure 13 do not include through-silicon vias (TSVs).

[0157] In some embodiments, the second stacked structure 13 is formed on the bottom stacked structure 11. The 3D packaging structure includes two stacked structures, namely the bottom stacked structure 11 and the second stacked structure 13.

[0158] All the laminated plastic sealing layers of the laminated structure are made of the same material as the bottom plastic sealing layer, and all the laminated plastic sealing layers of the laminated structure and the bottom plastic sealing layer together form an integral plastic sealing layer. Figure 27 For example, the materials of the bottom laminated plastic sealing layer 117 of the laminated structure 11, the laminated plastic sealing layer 129 of the first laminated structure 12, and the laminated plastic sealing layer 135 of the second laminated structure 13 are the same as the material of the bottom plastic sealing layer 106, and together form an overall plastic sealing layer.

[0159] Continue to refer Figure 27 A protective layer 107 is provided on the lower surface of the base island 102 and the pin 101. The protective layer 107 is a tin layer, which is used to protect the lead frame from oxidation and facilitate the surface mounting process.

[0160] The above-mentioned 3D packaging structure includes a bottom structure and at least one stacked structure on the bottom structure. The bottom structure includes a lead frame, a bottom chip, and a bottom plastic encapsulation layer. The lead frame includes pins and a base island, and at least a portion of the pins are welded to the upper surface of the bottom vertical bonding wire. The stacked structure includes a stacked chip, stacked vertical bonding wires, and a stacked plastic encapsulation layer covering the stacked chip and the stacked vertical bonding wires. The bottom vertical bonding wires of the bottom structure and the stacked vertical bonding wires of different stacked structures are used to connect the lead frame to stacked chips of different stacked structures, thereby achieving the requirements of miniaturization and high structural and functional integration of the frame-type packaging structure.

[0161] It should be noted that, in this document, relational terms such as "first" and "second" are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include," "comprise," or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same or similar parts between the various embodiments can be referenced to each other. Each embodiment focuses on the differences from other embodiments.

[0162] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It should be noted that those skilled in the art may make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A 3D packaging method, characterized in that: include: A bottom structure is formed, the bottom structure comprising a lead frame, a bottom chip, and a bottom plastic encapsulation layer, the lead frame being located at the bottom of the bottom structure, the lead frame comprising pins and a base island, at least a portion of the upper surfaces of the pins being welded with bottom vertical bonding wires, the bottom chip being disposed on the upper surface of the base island of the lead frame, the bottom plastic encapsulation layer covering the lead frame, the bottom chip, and the bottom vertical bonding wires, and exposing the lower surfaces of the pins and the base island; At least one stacked structure is formed on the underlying structure, the stacked structure comprising a stacked chip, stacked vertical bonding wires, and a stacked plastic encapsulation layer covering the stacked chip and the stacked vertical bonding wires, wherein the stacked chip and the stacked vertical bonding wires at the bottom layer of the stacked structure are connected to the bottom layer vertical bonding wires of the underlying structure; When multiple layers of the stacked structure are formed on the underlying structure, the stacked chips of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure, and the stacked vertical bonding wires of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure.

2. The 3D packaging method according to claim 1, wherein: The steps of forming the underlying structure specifically include: Providing the lead frame, wherein the lead frame includes the pins and the base island; Mounting the bottom chip on the upper surface of the base island; Welding wires between the bottom chip and the pins to achieve electrical connection between the bottom chip and the lead frame; welding the bottom vertical bonding wires on the upper surface of at least a portion of the pins; The bottom plastic packaging layer is formed to expose the pins and the lower surface of the base island.

3. The 3D packaging method according to claim 2, wherein: The step of welding the bottom vertical bonding wire on the upper surface of at least a portion of the pins further includes welding the bottom vertical bonding wire on the upper surface of the bottom chip.

4. The 3D packaging method according to claim 2, wherein: The step of welding the bottom vertical bonding wire on the upper surface of at least a portion of the pins further includes welding the bottom vertical bonding wire on the upper surface of the pin connected to the bonding wire.

5. The 3D packaging method according to claim 2, wherein: The step of welding the bottom vertical bonding wire on the upper surface of at least a portion of the pins further includes welding the bottom vertical bonding wire on the upper surface of the pins that are not connected to the bonding wire.

6. The 3D packaging method according to claim 2, wherein: The step of welding the bottom vertical bonding wire on the upper surface of at least a portion of the pins also includes: welding the bottom vertical bonding wire on the upper surface of the pins that are partially connected to the bonding wires and welding the bottom vertical bonding wire on the upper surface of the pins that are not connected to the bonding wires.

7. The 3D packaging method according to claim 1, wherein: The step of forming at least one stacked structure on the underlying structure includes the step of forming the bottommost stacked structure on the underlying structure, which specifically includes: exposing the bottom layer vertical bonding wires on the bottom layer structure; forming solder on the upper surface of the bottom vertical bonding wire; forming a stacked chip and a stacked vertical bonding wire on the underlying structure, wherein the stacked chip and the stacked vertical bonding wire are connected to the underlying vertical bonding wire of the underlying structure through the solder; A laminated plastic packaging layer covering the laminated chips and the laminated vertical bonding wires is formed on the underlying structure.

8. The 3D packaging method according to claim 7, wherein: The step of exposing the underlying vertical bonding wires on the underlying structure includes grinding a surface of the underlying structure to expose upper surfaces of the underlying vertical bonding wires.

9. The 3D packaging method according to claim 7, wherein: The steps of forming stacked chips and stacked vertical bonding wires on the underlying structure specifically include: arranging stacked chips and stacked vertical bonding wires on the underlying structure, and performing a welding process so that the stacked chips and the stacked vertical bonding wires are connected to the underlying vertical bonding wires of the underlying structure through the solder.

10. The 3D packaging method according to claim 1, wherein: The step of forming at least one stacked structure on the underlying structure includes the step of forming a first stacked structure on the underlying stacked structure, which specifically includes: exposing the stacked vertical bonding wires of the lower stacked structure and the bonding pads of the stacked chip on the lower stacked structure; forming solder on the upper surfaces of the stacked vertical bonding wires of the lower stacked structure and the bonding pads of the stacked chip; Arranging the stacked chips and stacked vertical bonding wires of the first stacked structure on the lower stacked structure, and performing a soldering process, wherein the stacked chips of the first stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure via the solder, and the stacked vertical bonding wires of the first stacked structure are connected to the stacked vertical bonding wires of the lower stacked structure via the solder; A laminated plastic packaging layer is formed on the lower laminated structure to cover the laminated chips and laminated vertical bonding wires of the first laminated structure.

11. The 3D packaging method according to claim 10, wherein: After forming solder on the upper surfaces of the stacked vertical bonding wires and the pads of the stacked chip in the lower layer of the stacked structure, the method further includes: forming a metal layer on the pads corresponding to the wire bonding areas of the stacked chip in the lower layer of the stacked structure; The steps of arranging the stacked chips and stacked vertical bonding wires of the first stacked structure on the lower stacked structure and performing a welding process include: A bonding wire is welded between the metal layer and a bonding pad of the stacked chip of the first stacked structure that requires wire bonding.

12. The 3D packaging method according to claim 11, wherein: The metal layer is formed by electroplating, and the metal layer is a single-layer or multi-layer circuit layer.

13. The 3D packaging method according to claim 10, wherein: The stacked chip of the first stacked structure comprises a through silicon via (TSV) therein, and the TSV serves as an electrical interconnection channel between the lower stacked structure and the upper stacked structure of the first stacked structure.

14. The 3D packaging method according to claim 10, wherein: In the step of forming the first stacked structure on the lower stacked structure, the first stacked structure is formed on the lowermost stacked structure.

15. The 3D packaging method according to claim 10, wherein: The step of forming at least one stacked structure on the underlying structure includes the step of forming a second stacked structure on the underlying stacked structure, which specifically includes: exposing the stacked vertical bonding wires of the lower stacked structure and the bonding pads of the stacked chip on the lower stacked structure; forming solder on the upper surfaces of the stacked vertical bonding wires of the stacked structure and the bonding pads of the stacked chip in the lower layer; Arranging the stacked chips of the second stacked structure on the stacked structure of the lower layer, and performing a welding process to connect the stacked chips of the second stacked structure with the stacked chips and stacked vertical bonding wires of the stacked structure of the lower layer; A laminated plastic packaging layer is formed on the lower laminated structure to cover the laminated chips of the second laminated structure.

16. The 3D packaging method according to claim 15, wherein: In the step of forming the second stacked structure on the lower stacked structure, the second stacked structure is formed on the first stacked structure.

17. The 3D packaging method according to claim 15, wherein: The stacked chip of the second stacked structure does not include a through silicon via.

18. The 3D packaging method according to claim 1, wherein: The laminated plastic sealing layers of all the laminated structures are made of the same material as the bottom plastic sealing layer.

19. The 3D packaging method according to claim 1, wherein: After the step of forming the stacked structure, the method further includes: forming a protection layer on the lower surfaces of the base island and the pins.

20. A 3D packaging structure, characterized in that: include: A bottom structure, comprising a lead frame, a bottom chip, and a bottom plastic encapsulation layer, wherein the lead frame is located at the bottom of the bottom structure, the lead frame comprises pins and a base island, at least a portion of the upper surfaces of the pins are welded with bottom vertical bonding wires, the bottom chip is arranged on the upper surface of the base island of the lead frame, the bottom plastic encapsulation layer covers the lead frame, the bottom chip, and the bottom vertical bonding wires, and exposes the lower surfaces of the pins and the base island; At least one stacked structure formed on the underlying structure, the stacked structure comprising a stacked chip, stacked vertical bonding wires, and a stacked plastic encapsulation layer covering the stacked chip and the stacked vertical bonding wires, the stacked chip and stacked vertical bonding wires of the bottom layer of the stacked structure being connected to the bottom layer vertical bonding wires of the underlying structure; When the stacked structure on the underlying structure is multi-layer, the stacked chips of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure, and the stacked vertical bonding wires of the upper stacked structure are connected to the stacked chips and / or stacked vertical bonding wires of the lower stacked structure.

21. The 3D packaging structure according to claim 20, wherein: The bottom chip and the pins are connected via bonding wires.

22. The 3D packaging structure according to claim 21, wherein: The bottom vertical bonding wire is provided on the upper surface of a portion of the pins connected to the bonding wires; and the bottom vertical bonding wire is provided on the upper surface of the pins not connected to the bonding wires.

23. The 3D packaging structure according to claim 20, wherein: The bottom layer vertical bonding wires are arranged on the upper surface of the bottom layer chip.

24. The 3D packaging structure according to claim 20, wherein: The bottom layer of the stacked structure is formed on the bottom layer structure, and the bumps and stacked vertical bonding wires of the stacked chips of the bottom layer of the stacked structure are welded to the bottom layer vertical bonding wires of the bottom layer structure through solder.

25. The 3D packaging structure according to claim 20, wherein: A first stacked structure is formed on the lower stacked structure, and the stacked chips of the first stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure through solder; the stacked vertical bonding wires of the first stacked structure are connected to the vertical bonding wires of the lower stacked structure through solder.

26. The 3D packaging structure according to claim 25, wherein: A metal layer is formed on the pad corresponding to the wire bonding pressure area of ​​the stacked chip of the lower stacked structure, and the metal layer and the pad requiring wire bonding of the stacked chip of the first stacked structure are connected via bonding wires.

27. The 3D packaging structure according to claim 25, wherein: The first stacked structure is formed on the bottom stacked structure.

28. The 3D packaging structure according to claim 25, wherein: The stacked chip of the first stacked structure includes through silicon vias therein.

29. The 3D packaging structure according to claim 25, wherein: A second stacked structure is formed on the lower stacked structure, and the stacked chips of the second stacked structure are connected to the stacked chips and stacked vertical bonding wires of the lower stacked structure through solder.

30. The 3D packaging structure according to claim 29, wherein: The second stacked structure is formed on the first stacked structure.

31. The 3D packaging structure according to claim 29, wherein: The second stacked structure is formed on the bottom stacked structure.

32. The 3D packaging structure according to claim 20, wherein: All the laminated plastic sealing layers of the laminated structure are made of the same material as the bottom plastic sealing layer, and all the laminated plastic sealing layers of the laminated structure and the bottom plastic sealing layer together serve as an integral plastic sealing layer.

33. The 3D packaging structure according to claim 20, wherein: A protection layer is provided on the lower surfaces of the base island and the pins.

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