Hot-pressing bridge sheet three-dimensional fan-out packaging method and structure

Abstract

The invention discloses a hot-pressing bridge piece three-dimensional fan-out packaging method and structure, and belongs to the field of integrated circuit packaging. The heterogeneous chip is surface-mounted on the temporary carrier plate and is encapsulated with a resin molding compound, and a resin wafer is formed through solidification and reconstruction; the reconstructed wafer is removed from the temporary carrier plate through a de-bonding process, and then RDL and UBM are sequentially realized through a multi-layer re-wiring process; carrying out high-precision thermocompression welding and underfilling on the silicon bridge chip and the reconstructed wafer; the resistor and the capacitor are surface-mounted at the PAD of the reconstructed wafer, and surface-mounted welding is completed through a reflow process; the method comprises the following steps: reconfiguring a plurality of layers of resin wafers, reballing at the UBM position of the reconfigured multi-layer resin wafer through a wafer-level balling process, scribing to form a single SIP packaging module, and finally, bonding the SIP packaging module and a substrate in a flip-chip manner through a flip-chip process to form a final packaging body. According to the invention, high-density wiring bridge chip processing is carried out through a previous process, so that the number of wiring layers of a reconstructed wafer can be greatly reduced, the interconnection density of a whole packaging body is improved, and the process difficulty is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to a hot-pressed bridge three-dimensional fan-out packaging method and structure. Background Art

[0002] Advanced semiconductor manufacturing processes are gradually reaching their limits, and the pace of development along Moore's Law is slowing down. Fan-out wafer-level packaging, on the other hand, breaks through the I / O pin limit of traditional fan-in packaging by reconstructing the wafer. It also uses technologies such as multi-layer redistribution wiring (RDL) to reduce pin spacing, thin the package thickness, and reduce high-frequency signal transmission loss, thereby further improving chip integration.

[0003] In recent years, fan-out wafer-level packaging (FLP) has gradually developed into a representative advanced packaging technology in consumer electronics, high-performance computing, and other fields, and is a key technology for continuing Moore's Law. However, the wafer-level fan-out process is complex, including wafer reconstruction, plastic encapsulation, and rewiring. Each critical step can have a significant impact on package reliability.

[0004] Wafer warpage is a key process challenge for fan-out wafer-level packaging (FOP). Due to a mismatch in the thermal expansion coefficients of the chip encapsulation material and the chip material in the reconstructed wafer, the reconstructed wafer warps with temperature fluctuations. During multi-layer wiring, the addition of surface materials and temperature cycling exacerbate this warpage, severely impacting subsequent processes. Wiring processes with more than three layers become significantly more difficult to process, making reliability difficult to guarantee. Summary of the Invention

[0005] The purpose of the present invention is to provide a method and structure for hot-pressed bridge-piece three-dimensional fan-out packaging to solve the problem of large warping of multi-layer wiring in some fan-out three-dimensional packaging.

[0006] To solve the above technical problems, the present invention provides a three-dimensional fan-out packaging method and structure for a thermally pressed bridge, including:

[0007] Providing a heterogeneous heterogeneous chip and a temporary carrier, attaching the heterogeneous heterogeneous chip to the temporary carrier and potting it, and curing and reconstructing it to form a resin wafer;

[0008] The reconstructed wafer is unstuck from the temporary carrier and multi-layer interconnect metal rewiring is formed on the front side of the heterogeneous chip;

[0009] Design and tape out silicon bridge chips, produce high-density copper pillar bumps, and then thin them to form silicon bridge chips with copper pillar bumps;

[0010] The silicon bridge chip is hot-pressed and bonded to the reconstructed wafer, and the gaps between the bumps of the silicon bridge chip at the hot-pressing bonding are filled with underfill glue through an underfill process.

[0011] Mount the resistors and capacitors on the PADs of the reconstructed wafer and complete the surface mount soldering through the reflow process;

[0012] Balls are implanted on the under-bump metallization layer of the reconstructed multi-layer resin wafer, and then the multi-layer reconstructed resin wafer is diced to form a single SIP package module; the SIP package module is flip-chip bonded to the substrate to form a final package body.

[0013] In one embodiment, the multi-layer interconnect metal rewiring is a wiring process in which metal layers and passivation layers overlap multiple times.

[0014] In one embodiment, the multi-layer interconnect metal rewiring is at least one metal layer; the thickness of the passivation layer is greater than the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 3 μm, and the thickness of the passivation layer is not less than 5 μm.

[0015] In one embodiment, the silicon bridge chip is taped out by a front-end process, and copper pillar bumps are made by a back-end process. The diameter pitch of the copper pillar bumps is ≤30μm, and the material of the long bumps of the silicon bridge chip includes one of Cu, CuSn, CuNiSn, CuNiSnAg, SnPb, and SnAgCu.

[0016] In one embodiment, the underfill fills the gaps between the bumps of the flip-chip solder joint, and the underfill process includes a dry film pressing process and a dispensing process.

[0017] In one embodiment, the ball planting at the under bump metallization layer includes wafer-level ball planting, single-chip ball planting and solder paste printing; the composition of the solder ball includes one of SnPb and SnAgCu.

[0018] In one embodiment, the substrate material of the heterogeneous heterogeneous chip includes one of Si, GaAs, GaN, and SiC.

[0019] In one embodiment, the temporary carrier is formed by attaching a pyrolytic bonding film to a steel carrier.

[0020] The present invention also provides a hot-pressed bridge piece three-dimensional fan-out packaging structure, which is prepared based on the above-mentioned hot-pressed bridge piece three-dimensional fan-out packaging method.

[0021] The present invention provides a three-dimensional fan-out packaging method and structure for a hot-pressed bridge chip, which has the following beneficial effects:

[0022] (1) Using the front-end process to process the silicon bridge chip has a smaller line width and line spacing, which can greatly improve the routing density and improve the integration of fan-out;

[0023] (2 Using silicon bridge chips for chip-to-chip interconnection can reduce the number of wafer reconstruction fan-out rewiring layers, reduce the warpage of the reconstructed wafer, greatly reduce the processing difficulty, and improve the reliability of the package. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a schematic diagram of the process of the hot-pressed bridge chip three-dimensional fan-out packaging method provided by the present invention;

[0025] Figure 2 This is a schematic diagram of the heterogeneous chips being mounted on a temporary carrier;

[0026] Figure 3 It is a schematic diagram of wafer-level injection molding;

[0027] Figure 4 It is a schematic diagram of wafer-level rewiring;

[0028] Figure 5 It is a schematic diagram of a silicon-based high-process bridge wafer;

[0029] Figure 6 This is a schematic diagram of the hot-press welding of the bridge piece to the reconstructed wafer;

[0030] Figure 7 This is a schematic diagram of the bridge piece bottom fill after welding;

[0031] Figure 8 This is a schematic diagram of surface-mounting resistors and capacitors on a reconstructed wafer;

[0032] Figure 9 It is a schematic diagram of reconstructing wafer ball planting;

[0033] Figure 10 It is a schematic diagram of the flip-chip bonding between the SIP package module and the substrate. DETAILED DESCRIPTION

[0034] The following, combined with the accompanying drawings and specific embodiments, further details the proposed method and structure for a three-dimensional fan-out package using a thermally compressed bridge. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clarify the purpose of illustrating the embodiments of the present invention.

[0035] The present invention provides a three-dimensional fan-out packaging method for a hot-pressed bridge chip, the process of which is as follows: Figure 1 As shown, the following steps are included:

[0036] Step S11: providing a heterogeneous heterogeneous chip and a temporary carrier, mounting the heterogeneous heterogeneous chip on the temporary carrier, potting the chip, and curing and reconstructing the chip to form a resin wafer;

[0037] Step S12: removing the reconstructed wafer from the temporary carrier and forming multi-layer interconnect metal rewiring on the front side of the heterogeneous chip;

[0038] Step S13: Designing and tape-out the silicon bridge chip, manufacturing high-density copper pillar bumps, and thinning to form a silicon bridge chip with copper pillar bumps;

[0039] Step S14: hot-press bonding the silicon bridge chip to the reconstructed wafer, and using an underfill process to fill gaps between the bumps of the silicon bridge chip at the hot-press bonding point with an underfill adhesive;

[0040] Step S15: Surface mount the resistors and capacitors on the PADs of the reconstructed wafer, and complete surface mount soldering through a reflow process;

[0041] Step S16: planting balls on the under-bump metallization layer of the reconstructed multi-layer resin wafer, then dicing the multi-layer reconstructed resin wafer to form a single SIP package module; and flip-chip bonding the SIP package module to the substrate to form a final package.

[0042] like Figure 2 As shown, a heterogeneous heterogeneous chip 111 and a temporary carrier are provided, and the heterogeneous heterogeneous chip 111 is surface-mounted on the temporary carrier using a die mounter; wherein the temporary carrier is formed by attaching a pyrolytic bonding film on a steel carrier;

[0043] like Figure 3 As shown, the heterogeneous and heterogeneous chips 111 are encapsulated with a resin encapsulation material 112 using a wafer-level encapsulation process, and then cured and reconstructed to form a resin wafer;

[0044] like Figure 4 As shown, the reconstructed wafer is released from the temporary carrier through a debonding process, and Pi glue and wafer-level multi-layer rewiring processes are used to sequentially realize RDL (multi-layer rewiring) and UBM (under bump metallization layer) multi-layer interconnect metal rewiring 113;

[0045] like Figure 5 As shown, the silicon bridge chip 114 is designed and taped out using the front-end process, and then high-density copper pillar bumps are manufactured through the back-end process, and the silicon bridge chip 114 with copper pillar bumps is formed after thinning;

[0046] like Figure 6 As shown, a thermal bonding machine is used to bond the silicon bridge chip 114 to the Figure 4 The reconstructed wafer shown is subjected to high-precision hot-press bonding to connect the copper pillar bumps of the silicon bridge chip 114 to the multi-layer interconnect metal rewiring 113;

[0047] like Figure 7 As shown, through the underfill process, the gaps between the bumps at the thermal compression welding of the silicon bridge chip 114 are filled with underfill glue 115;

[0048] like Figure 8 As shown, the resistor and / or capacitor 116 is surface mounted on the PAD of the reconstructed wafer, and the surface mount soldering is completed through a reflow process;

[0049] like Figure 9 As shown, through the wafer-level ball planting process, the ball 117 is planted at the UBM of the reconstructed multi-layer resin wafer, and then the multi-layer reconstructed resin wafer is diced to form a single SIP package module;

[0050] like Figure 10 As shown, the SIP package module is finally flip-chip bonded to the substrate 118 through a flip-chip process to form a final package body.

[0051] The present invention also provides a three-dimensional fan-out packaging structure of a thermally pressed bridge, which is prepared by the above method and has a structure as follows: Figure 10 shown.

[0052] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A three-dimensional fan-out packaging method for a hot-pressed bridge chip, characterized in that: include: Providing a heterogeneous heterogeneous chip and a temporary carrier, attaching the heterogeneous heterogeneous chip to the temporary carrier and potting it, and curing and reconstructing it to form a resin wafer; The reconstructed wafer is unstuck from the temporary carrier and multi-layer interconnect metal rewiring is formed on the front side of the heterogeneous chip; Design and tape out silicon bridge chips, produce high-density copper pillar bumps, and then thin them to form silicon bridge chips with copper pillar bumps; The silicon bridge chip is hot-pressed and bonded to the reconstructed wafer, and the gaps between the bumps of the silicon bridge chip at the hot-pressing bonding are filled with underfill glue through an underfill process. Mount the resistors and capacitors on the PADs of the reconstructed wafer and complete the surface mount soldering through the reflow process; Balls are implanted on the under-bump metallization layer of the reconstructed multi-layer resin wafer, and then the multi-layer reconstructed resin wafer is diced to form a single SIP package module; the SIP package module is flip-chip bonded to the substrate to form a final package body.

2. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The multi-layer interconnect metal rewiring is a wiring process in which metal layers and passivation layers overlap multiple times.

3. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 2, characterized in that: The multi-layer interconnect metal rewiring is at least one metal layer; the thickness of the passivation layer is greater than the formed metal layer, and the passivation layer covers the metal layer; the thickness of the metal layer is not less than 3μm, and the thickness of the passivation layer is not less than 5μm.

4. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The silicon bridge chip is taped out by the front-end process and copper pillar bumps are made by the back-end process. The diameter pitch of the copper pillar bumps is ≤30μm. The material of the long bumps of the silicon bridge chip includes one of Cu, CuSn, CuNiSn, CuNiSnAg, SnPb, and SnAgCu.

5. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The underfill fills the gaps between the bumps of the flip-chip solder joint, and the underfill process includes a dry film pressing process and a dispensing process.

6. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The ball is planted at the under-bump metallization layer, and the ball planting process includes wafer-level ball planting, single-chip ball planting and solder paste printing; the composition of the solder ball includes one of SnPb and SnAgCu.

7. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The substrate material of the heterogeneous heterogeneous chip includes one of Si, GaAs, GaN, and SiC.

8. The hot-pressed bridge-piece three-dimensional fan-out packaging method according to claim 1, characterized in that: The temporary carrier is formed by attaching a pyrolytic bonding film to a steel carrier.

9. A three-dimensional fan-out packaging structure with a thermally pressed bridge, characterized in that: It is prepared based on the hot-pressed bridge-piece three-dimensional fan-out packaging method according to any one of claims 1-8.

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