Semiconductor device and method of manufacturing semiconductor device

Abstract

A semiconductor device and a method of manufacturing the same. In one example, an electronic device may include a substrate, a first passivation structure over the substrate and defining a first opening, and a first conductive pattern formed in the first opening. A second passivation structure may be disposed over the first conductive pattern and the first passivation structure. The second passivation structure may include a high resolution material and a high functionality material. The high resolution material of the second passivation structure may define a second opening. A second conductive pattern may be disposed in the second opening of the second passivation structure. The high function material may be disposed between the first conductive pattern and the second conductive pattern. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly to semiconductor devices and methods for fabricating semiconductor devices. Background Art

[0002] Previous semiconductor packages and methods for forming semiconductor packages are inadequate, for example resulting in excessive cost, reduced reliability, relatively low performance, or excessively large package sizes. Other limitations and disadvantages of these methods will become apparent to those skilled in the art by comparing conventional and traditional methods with the present disclosure and referring to the accompanying drawings. Summary of the Invention

[0003] Various aspects of the present disclosure provide an electronic device comprising: a substrate; a first passivation structure overlying the substrate and defining a first opening; a first conductive pattern formed in the first opening; a second passivation structure overlying the first conductive pattern and the first passivation structure, wherein the second passivation structure comprises a high-resolution material and a high-function material, wherein the high-resolution material of the second passivation structure defines a second opening; and a second conductive pattern disposed in the second opening of the second passivation structure, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern. In the electronic device, the high-function material defines a first via extending through the second passivation structure to the first conductive pattern, wherein the high-resolution material defines a second via extending through the first via of the second passivation structure to the first conductive pattern. The electronic device further comprises a seed layer extending through the first via and the second via to the first conductive pattern, wherein the high-resolution material is between the high-function material and the seed layer. In the electronic device, the high-function material comprises a dielectric constant (Dk) of less than 3.0. In the electronic device, the high-function material comprises a dissipation factor (Df) of less than 0.004. In the electronic device, the high-resolution material includes a material that can be patterned with a resolution value of less than 2 microns. In the electronic device, the high-function material includes a first organic substance, and the high-resolution material includes a second organic substance. In the electronic device, the substrate includes: an electronic component; and an encapsulant disposed around the lateral sides of the electronic component. The electronic device further includes: a thermal adhesive coupled to the top side of the electronic component; and a heat sink coupled to the thermal adhesive. The electronic device further includes a base substrate electrically coupled to the electronic component via the first conductive pattern and the second conductive pattern, wherein the heat sink is coupled to the base substrate. The electronic device further includes an underfill disposed between the electronic component and the first passivation structure. In the electronic device, the high-resolution material includes a positive photosensitive polyimide (PSPI).

[0004] Various aspects of the present disclosure provide an electronic device comprising: a substrate; a first dielectric material overlying the substrate and defining a first opening; a first conductive pattern formed in the first opening; a second dielectric material disposed over the first conductive pattern and the first dielectric material, wherein the second dielectric material comprises a high-function material defining a second opening; a third dielectric material disposed over the second dielectric material and extending into the second opening, wherein the third dielectric material comprises a high-resolution material defining a third opening; and a second conductive pattern disposed in the third opening of the high-resolution material, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern. In the electronic device, the high-function material defines a first via extending through the second dielectric material to the first conductive pattern, wherein the high-resolution material defines a second via extending through the first via to the first conductive pattern. In the electronic device, the high-function material comprises a dielectric constant (Dk) of less than 3.0. In the electronic device, the high-function material comprises a dissipation factor (Df) of less than 0.004. In the electronic device, the high-resolution material comprises a material capable of being patterned with a resolution value less than or equal to 2 microns.

[0005] Various aspects of the present disclosure provide a method for manufacturing a semiconductor device, comprising: providing a substrate; providing a first dielectric material over the substrate, wherein the first dielectric material defines a first opening; providing a first conductive pattern in the first opening; providing a second dielectric material over the first conductive pattern and the first dielectric material, wherein the second dielectric material comprises a high-function material and defines a second opening; providing a third dielectric material over the second dielectric material and extending into the second opening, wherein the third dielectric material comprises a high-resolution material and defines a third opening; and providing a second conductive pattern, the second conductive pattern being disposed in the third opening of the third dielectric material, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern. In the method, the high-function material comprises a dielectric constant (Dk) of less than 3.0 and a dissipation factor (Df) of less than 0.004. In the method, the high-resolution material comprises a material capable of being patterned with a resolution value less than or equal to 2 microns. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 Shows a cross-sectional view of an example electronic assembly.

[0007] Figures 2A to 2T An example method for manufacturing an example electronic assembly is presented using cross-sectional views.

[0008] Figure 3Shows a cross-sectional view of an example electronic assembly.

[0009] Figure 4 A cross-sectional view of an example electronic device is shown.

[0010] Figure 5 A cross-sectional view of an example electronic device is shown.

[0011] Figure 6 A cross-sectional view of an example electronic device is shown.

[0012] Figure 7 A cross-sectional view of an example electronic device is shown.

[0013] The following discussion provides various examples of semiconductor devices and methods of manufacturing semiconductor devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0014] The figures illustrate general constructions and may omit descriptions and details of well-known features and techniques to avoid unnecessarily obscuring the present disclosure. Furthermore, the elements in the figures are not necessarily drawn to scale. For example, the dimensions of some elements in the various figures may be exaggerated relative to other elements to help improve understanding of the examples discussed in this disclosure. Identical reference numerals in different figures denote identical elements.

[0015] The term "or" means any one or more items in a list connected by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0016] The terms “including” and “comprising” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0017] The terms "first," "second," etc. may be used herein to describe various elements; however, elements described using the terms "first," "second," etc. should not be limited by these terms. The terms "first," "second," etc. are only used to distinguish one element from another. For example, a first element discussed in the present disclosure could be referred to as a second element without departing from the teachings of the present disclosure.

[0018] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled through one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B through an intervening element C. Similarly, the terms "over" or "on" may be used to describe two elements that are in direct contact with each other, or to describe two elements that are indirectly coupled through one or more other elements. As used herein, the term coupled may refer to either electrical coupling or mechanical coupling. DETAILED DESCRIPTION

[0019] An example electronic device may include a substrate, a first passivation structure over the substrate and defining a first opening, and a first conductive pattern formed in the first opening. A second passivation structure may be disposed over the first conductive pattern and the first passivation structure. The second passivation structure may include a high-resolution material and a high-function material. The high-resolution material of the second passivation structure may define a second opening. The second conductive pattern may be disposed in the second opening of the second passivation structure. The high-function material may be disposed between the first conductive pattern and the second conductive pattern.

[0020] In various examples, the high-functionality material defines a first through-hole extending through the second passivation structure to the first conductive pattern. The high-resolution material may define a second through-hole extending through the first through-hole of the second passivation structure to the first conductive pattern. The seed layer may extend through the first through-hole and the second through-hole to the first conductive pattern. The high-resolution material may be between the high-functionality material and the seed layer. The high-functionality material may include a dielectric constant (Dk) of less than 3.0. The high-functionality material may include a dissipation factor (Df) of less than 0.004. The high-resolution material may include a material that can be patterned with a resolution value of less than 2 microns. The high-functionality material may include a first organic matter, and the high-resolution material may include a second organic matter.

[0021] In some examples, the substrate includes an electronic component and an encapsulant disposed around lateral sides of the electronic component. A thermal adhesive may be coupled to a top side of the electronic component, and a heat sink may be coupled to the thermal adhesive. A redistribution layer (RDL) substrate may be electrically coupled to the electronic component via a first conductive pattern and a second conductive pattern. The heat sink may be coupled to the RDL substrate. An underfill may be between the electronic component and the first passivation structure. The high-functionality material may include positive photosensitive polyimide (PSPI).

[0022] Another example electronic device may include a substrate, a first dielectric material over the substrate and defining a first opening, and a first conductive pattern formed in the first opening. A second dielectric material may be disposed over the first conductive pattern and the first dielectric material. The second dielectric material may include a high-function material defining the second opening. A third dielectric material may be disposed over the second dielectric material and may extend into the second opening. The third dielectric material may include a high-resolution material defining the third opening. The second conductive pattern may be disposed in the third opening of the high-resolution material. The high-function material may be between the first conductive pattern and the second conductive pattern.

[0023] An example method for manufacturing a semiconductor device includes the following steps: providing a substrate; providing a first dielectric material over the substrate, wherein the first dielectric material defines a first opening; and providing a first conductive pattern in the first opening. A second dielectric material may be disposed over the first conductive pattern and the first dielectric material. The second dielectric material may include a high-function material and define a second opening. A third dielectric material may be disposed over the second dielectric material and extend into the second opening. The third dielectric material may include a high-resolution material and define a third opening. The example method may also include providing a second conductive pattern, the second conductive pattern disposed in a third opening of the third dielectric material. The high-function material may be disposed between the first conductive pattern and the second conductive pattern.

[0024] Other examples are included in the present disclosure and can be found in the drawings, claims, or detailed description of the present disclosure.

[0025] The devices and methods of the present disclosure tend to suppress signal noise and electron migration between adjacent conductive components of an electronic device. Embedded traces can be formed with a heterogeneous passivation structure. The heterogeneous passivation structure can enable the formation of high-resolution traces with high-resolution insulating materials (e.g., high-resolution polyimide). The heterogeneous passivation structure can also prevent undesirable electromagnetic communication between adjacent traces with high-functional insulating materials (e.g., high-functional polyimide). The high-functional insulating materials and the high-resolution insulating materials can be staggered, layered, selectively placed, or otherwise structured to increase the reliability and electrical performance of the traces (e.g., in an embedded trace redistribution layer).

[0026] Figure 1 A cross-sectional view of an example electronic assembly 10 is shown. Figure 1 In the example shown, the electronic assembly 10 may include a substrate 11 and a build-up redistribution layer (RDL) 12. The build-up RDL 12 may include a dielectric structure 120, a conductive structure 130, and a device interconnect 150.

[0027] The dielectric structure 120 may include a first (or inner) passivation structure 121, one or more second (or intermediate) passivation structures 122, and an outer passivation structure 123. The first passivation structure 121 may include a first dielectric material 121a and a second dielectric material 121b. Each second passivation structure 122 may include a first dielectric material 122a and a second dielectric material 122b.

[0028] The conductive structure 130 may include a first conductive pattern 131, one or more second conductive patterns 132, and an outer conductive pattern 133. The first conductive pattern 131 may include a seed layer 131s, a trace 131t, a pad 131p, and a via 131v. Each second conductive pattern 132 may include a seed layer 132s, a trace 132t, a pad 132p, and a via 132v. The outer conductive pattern 133 may include a seed layer 133s and a pad 133p.

[0029] The second passivation structure 122 and the second conductive pattern 132 may be repeatedly stacked to form a stacked RDL 12. The stacked RDL 12 including the dielectric structure 120, the conductive structure 130, and the device interconnect 150 may be referred to as a semiconductor package. In some examples, the semiconductor package may protect the substrate 11 from external elements or environmental exposure. In some examples, the semiconductor package may electrically couple external electrical components to the substrate 11.

[0030] Figures 2A to 2T A cross-sectional view of an example method for manufacturing electronic assembly 10 is shown. Figure 2A A cross-sectional view of electronic assembly 10 is shown at an early stage of manufacture.

[0031] exist Figure 2AIn the example shown, a first dielectric material 121a can be provided on the substrate 11. In some examples, the substrate 11 can include or be referred to as a wafer, a reconstructed wafer, or a removable carrier. For example, the substrate 11 can be a wafer having a plurality of semiconductor dies separated by saw streets, and can be used to manufacture electronic devices including wafer-level packages (WLPs) or wafer-level chip-size packages (WLCSPs). In some examples, the substrate 11 can be a reconstructed wafer including a plurality of known good semiconductor dies that are aggregated and reconstructed (e.g., encapsulated) to form the substrate 11 (e.g., the encapsulant can be located between adjacent semiconductor dies). The reconstructed wafer can be used to manufacture electronic devices including, for example, wafer-level fan-out (WLFO) devices. In some examples, the substrate 11 can include a removable (or temporary) carrier, and can be used to manufacture electronic devices including an RDL substrate or an interposer (e.g., a stacked RDL 12), on which electronic components (e.g., semiconductor dies, passive devices, or other electronic packages) are coupled. In such examples, the removable carrier (i.e., substrate 11) can be formed of, for example, silicon, glass, ceramic, or metal, and can be removed from the RDL substrate (e.g., build-up RDL 12) after the electronic components have been attached to the RDL substrate. The thickness of substrate 11 can be in the range of about 200 microns (μm) to about 1000 μm. In some examples, the thickness of substrate 11 can be in the range of about 20 μm to about 1000 μm. As used herein with a numerical value or percentage, the term "about" can mean + / - 5%, + / - 10%, + / - 15%, + / - 20%, or + / - 25%.

[0032] According to various examples, the first dielectric material 121a can be applied or spin-coated in liquid form or laminated onto the substrate 11 as a preformed film. In some examples, the substrate 11 can be a wafer or a reconstituted wafer, and the first dielectric material 121a can be disposed over the component interconnects 171A of the substrate 11. In some examples, the first dielectric material 121a can include or be referred to as a photoimageable organic passivation material, PI (polyimide), BCB (benzocyclobutene), PBO (polybenzoxazole), phenolic resin, or ABF (Ajinomoto Buildup Film). In some examples, the first dielectric material 121a can include one or more layers of a high-functioning dielectric material, such as high-functioning PI or other high-reliability materials. As used herein, phrases such as "high-functioning," "highly functional," or similar phrases may be used to refer to low-loss materials, such as Asahi BL301. High-functioning materials can have properties such as a dielectric constant (Dk) <3.0 or a dissipation factor (Df) <0.004. The dielectric constant can represent the degree of polarization of a material. The dissipation factor can represent the energy loss caused by the reverse polarization of a material. In some examples, the first dielectric material 121a can provide high functionality. In some examples, high functionality can include low dielectric properties or insulating properties, such as low Dk (i.e., less than about 3) or low Df (i.e., less than about 0.004). In some examples, high functionality can include high mechanical properties, such as an elongation value greater than about 40% or a tensile strength value greater than about 130 megapascals (MPa). In some examples, high functionality can include high heat resistance, such as a weight loss of 5% at a temperature greater than about 300°C or a glass transition temperature (Tg) greater than about 200°C. In some examples, high functionality can include high reliability or adhesion, such as a hygroscopicity of less than about 1% or an adhesion greater than about 70 MPa. High functionality can also describe other desirable physical properties of the dielectric material 121a.

[0033] In some examples, the first dielectric material 121a may include positive-type photosensitive polyimide (PSPI). PSPI may be a polyimide material that is sensitive to light, allowing the PSPI to be patterned via a photolithography process. PSPI may include positive-type PSPI, negative-type PSPI, or chemically amplified PSPI. In positive-type PSPI, the polymer may become more soluble in the exposed area, and the upper area of ​​the opening formed after development is relatively wide. In negative-type PSPI, the polymer may become insoluble in the exposed area, and the lower area of ​​the opening may be formed relatively wide after development. Chemically amplified PSPI may use a chemical amplification process to enhance the material's sensitivity to light. Chemically amplified PSPI may allow for improved resolution and sensitivity in patterning. Chemically amplified PSPI may be used when the microfabrication process requires fine features or high resolution. The thickness of the first dielectric material 121a may be in the range of approximately 3 μm to approximately 100 μm.

[0034] Figure 2B A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2B In the example shown, a through hole 121a1 can be provided in the first dielectric material 121a. In some examples, the through hole 121a1 can be formed through the first dielectric material 121a using a patterning process. The patterning process can include, for example, exposure, development, and curing.

[0035] In some examples, a mask having a pattern corresponding to the location of via 121a1 can be positioned over first dielectric material 121a and exposed to ultraviolet light, thereby transferring the pattern to first dielectric material 121a. Portions of first dielectric material 121a containing the transferred pattern (or, in some examples, portions not containing the transferred pattern) are then developed and cured, leaving via 121a1 patterned in first dielectric material 121a. Portions of substrate 11 can be exposed through via 121a1. In some examples, substrate 11 can include component interconnect 171A, and via 121a1 can be located above component interconnect 171A and can expose the component interconnect.

[0036] Figure 2C A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2CIn the example shown, the second dielectric material 121b can be disposed on the first dielectric material 121a and the substrate 11. The second dielectric material 121b can cover or fill the through hole 121a1 in the first dielectric material 121a. The second dielectric material 121b can be applied or spin-coated in liquid form, or laminated on the first dielectric material 121a and the substrate 11 as a preformed film. In some examples, the second dielectric material 121b can be similar to the first dielectric material 121a. In some examples, the second dielectric material 121b can include one or more layers of high-resolution dielectric material, such as high-resolution PI (e.g., a high-resolution material having a resolution that can be patterned with a resolution value of less than or equal to about 2 μm). The higher-resolution material described herein refers to patterning at a lower resolution value (e.g., a resolution value of 2 μm represents a higher-resolution material than a resolution value of 3 μm, but a resolution value of 2 μm is less than a resolution value of 3 μm).

[0037] In some examples, the second dielectric material 121b may include positive-type chemically amplified PSPI or negative-type chemically amplified PSPI. The thickness of the second dielectric material 121b may be in a range of about 3 μm to about 100 μm. The second dielectric material 121b may have a resolution of approximately 2 μm. The second dielectric material 121b may support the first conductive pattern 131 to be provided in a later process. In some examples, the second dielectric material 121b may include a high-resolution material. In some examples, the high-resolution material may lack the characteristics of a high-functionality material. In some examples, the solubility of the second dielectric material 121b in the developer is higher than the solubility of the first dielectric material 121a in the developer, and thus the pattern resolution of the second dielectric material 121b may be higher than the pattern resolution of the first dielectric material 121a.

[0038] Figure 2D A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2DIn the example shown, the second dielectric material 121b can be exposed to UV radiation. In some examples, a patterned mask can be positioned over the second dielectric material 121b and can block the UV radiation, thereby selectively forming a pattern in the second dielectric material 121b. In some examples, in the case of positive-tone PSPI, the exposed portion can undergo a chemical reaction, weakening the polymer bonds. In some examples, in the case of negative-tone PSPI, the exposed portion can undergo a chemical reaction, strengthening the polymer bonds. For reference, light passing through the mask can diffuse due to diffraction, and due to the catalyst within the PSPI, the resulting chemical reaction can spread to surrounding areas other than the portion receiving the light. Therefore, in some examples, the chemical reaction can occur around the portion receiving the light. The resulting pattern can include walls that are tilted or angled relative to the surface of the substrate 11. Furthermore, because light can be received from the top, chemical bonds can weaken around the top of the light-receiving portion in the case of positive-tone PSPI, while they can strengthen around the top of the light-receiving portion in the case of negative-tone PSPI. Positive-tone PSPI can provide a pattern in which the upper portion is additionally developed. In the case of negative-tone PSPI, a configuration can be provided in which the upper portion is reasonably developed or minimally developed. Figure 2D In the example, light can be provided on the positive PSPI.

[0039] Figure 2E A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2E In the example shown, the RDL pattern 121b1 and the via 121b2 are disposed in the second dielectric material 121b. According to various examples, the second dielectric material 121b can be patterned to form openings (e.g., the RDL pattern 121b1 and the via 121b2) in the second dielectric material 121b. In some examples, the second dielectric material 121b can be patterned in a manner similar to or identical to a dual damascene process. The patterning process can include a development and curing process. The via 121b2 can extend through the via 122a1 in the first dielectric material 121a.

[0040] In some examples, the transferred portion or the non-transferred portion of the second dielectric material 121b can be developed and cured, and the second dielectric material 121b can include a pattern. In this way, a plurality of RDL patterns 121b1 and through-holes 121b2 can be formed in or through the second dielectric material 121b. A portion of the substrate 11 (e.g., component interconnect 171A) can be exposed through the through-hole 121b2. In some examples, the dual-damascene patterning process can be performed by repeating the process multiple times. Due to the dual-damascene patterning process, the depth of the through-hole 121b2 can be greater than the depth of the RDL pattern 121b1, and the portion of the substrate 11 can be exposed through the through-hole 121b2. In some examples, the portion of the substrate 11 corresponding to the through-hole 121b2 can include a component interconnect 171A. The component interconnect 171A can include a pad, a platform, an UBM (under bump metal), a pillar, a bump, or a pillar.

[0041] In some examples involving positive-tone PSPI, the lower portion of the PI may not be exposed, thereby allowing the lower region of the PI to remain unchanged during the development process. In some examples involving negative-tone PSPI, even if the lower portion of the PI remains unexposed, the upper PI may prevent development, thereby allowing the lower portion of the PI to be developed subtly. In some examples, negative-tone PSPI can be used to provide a denser pattern than positive-tone PSPI.

[0042] In some examples, a first passivation structure 121 including a first dielectric material 121a and a second dielectric material 121b can be formed as described above. The first dielectric material 121a can include a high-function PI, and the second dielectric material 121b can include a high-resolution PI. The first dielectric material 121a can be disposed around a portion of the second dielectric material 121b, with the via 121b2 extending through both the first dielectric material 121a and the second dielectric material 121b.

[0043] Figure 2F A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2FIn the example shown, the seed layer 131s of the first conductive pattern 131 is disposed on the first passivation structure 121. The first passivation structure 121 can support the first conductive pattern 131. In some examples, the seed layer 131s can be disposed on the RDL pattern 121b1 and the through-hole 121b2 of the second dielectric material 121b. The seed layer 131s can also be disposed on the portion of the substrate 11 exposed by the through-hole 121b2. In some examples, the first passivation structure 121 and the seed layer 131s on the substrate 11 can be electrically shorted across the entire area. In some examples, the seed layer 131s can include Ti / Cu (titanium / copper), Ta / Cu (thallium / copper), TiW / Cu (titanium tungsten / copper), or Ti / TiN / Cu (titanium / titanium nitride / copper). In some examples, a barrier metal such as Ti, Ta, TiW, or TiN can be initially disposed on the first passivation structure 121 because Cu (copper) tends to diffuse into the second dielectric material 121b. Next, Cu may be disposed on the barrier metal. The barrier metal comprising Ti, Ta, TiW, or TiN may be disposed via ALD (atomic layer deposition), PVD (physical vapor deposition), CVD (chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), or PECVD (plasma enhanced chemical vapor deposition). A seed layer 131s comprising Cu may be disposed via PVD, ALD, CVD, LPCVD, or PECVD. In some examples, the thickness of the seed layer 131s may be in the range of about 0.05 μm to about 1 μm. The seed layer 131s may provide a substrate for electroplating the conductive structure 130 (e.g., Figure 2G The current supply path of the first conductive pattern 131o).

[0044] Figure 2G A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2GIn the example shown, a first conductive pattern 131o can be provided on the seed layer 131s. In some examples, the first conductive pattern 131o can be provided above the substrate 11 and the first passivation structure 121 including the RDL pattern and the vias. In some examples, the first conductive pattern 131o can include or be referred to as an electrodeposited layer or an electrode plating layer. In some examples, the first conductive pattern 131o can include Cu (copper), Ni (nickel), Pd (palladium), Ag (silver), or Au (gold). In some examples, the first conductive pattern 131o can be provided by electrodeposition on the seed layer 131s. In some examples, electrodeposition can be a method of producing an in-situ metal coating by applying an electric current to a conductive material immersed in a solution containing a salt of the metal to be deposited. The thickness of the first conductive pattern 131o can be set to be thicker than the thickness of the RDL pattern and the vias in the first passivation structure 121. In some examples, the thickness of the first conductive pattern 131o can be in the range of about 3 μm to about 200 μm.

[0045] Figure 2H A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2H In the example shown, the top side of the first conductive pattern 131o can be planarized. In some examples, a chemical mechanical polishing pad can grind the top side of the first conductive pattern 131o. The chemical mechanical polishing can be performed until the top side of the first passivation structure 121 (e.g., the second dielectric material 121b) is exposed. In some examples, a portion of the seed layer 131s on the top side of the first passivation structure 121 can also be ground and removed. In some examples, after the chemical mechanical polishing process, the top side of the first conductive pattern 131o and the top side of the first passivation structure 121 can be coplanar. In some examples, portions of the first conductive pattern 131 can be electrically and mechanically isolated from each other. A first conductive pattern 131 having an RDL pattern including traces 131t and pads 131p and a conductive via including a via 131v can be disposed on the first passivation structure 121. In some examples, the via 131v corresponding to the component interconnect 171A of the substrate 11 can include an inward terminal. In some examples, first conductive pattern 131 may include or be referred to as a trace, a pad, a conductive path, or a conductive via. In some examples, the thickness of first conductive pattern 131 may be in a range of about 3 μm to about 100 μm. First conductive pattern 131 may provide horizontal and vertical current paths between electronic component 10 and an external device.

[0046] Figure 2I A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2I In the example shown, the first dielectric material 122 a is disposed on the first conductive pattern 131 and the first passivation structure 121 . Figure 2IThe process shown in Figure 2A and Figure 2B The processes shown in are similar or identical to those described in . In some examples, the first dielectric material 122a can include or be referred to as a photoimageable organic passivation material, PI, BCB, PBO, phenolic resin, or ABF. In some examples, the first dielectric material 122a can include one or more layers of a high-functionality dielectric material, such as high-functionality PI or other high-reliability materials. This high-functionality PSPI can be applied or spin-coated in liquid form, or attached as a preformed film to the first conductive pattern 131 and the first passivation structure 121. According to various examples, through-holes 122a1 can be provided in the first dielectric material 122a. For example, the first dielectric material 122a can be patterned to form the through-holes 122a1. The patterning process can include coating or lamination, exposure, development, and curing processes. In this manner, the first dielectric material 122a including the through-holes 122a1 can be formed, and the first dielectric material can support the second conductive pattern 132, as described in further detail below.

[0047] Figure 2J A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2J In the example shown, the second dielectric material 122 b may be disposed on the first dielectric material 122 a and the first conductive pattern 131 . Figure 2J The process shown in Figure 2C The process shown in is similar or identical to that shown in . The second dielectric material 122b may cover or fill the through hole 122a1 of the first dielectric material 122a. The second dielectric material 122b may be coated or spin-coated in liquid form, or laminated as a preformed film on the first dielectric material 122a and the first conductive pattern 131. In some examples, the second dielectric material 122b may be similar to the second dielectric material 121b. In some examples, the second dielectric material 122b may include one or more layers of high-resolution dielectric material, such as high-resolution PI (for example, a high resolution of less than 2μm is required). In some examples, the second dielectric material 122b may include positive chemical amplification PSPI or negative chemical amplification PSPI. In some examples, the second dielectric material 122b may be selected for higher resolution, and the first dielectric material 122a may be selected for high functionality.

[0048] Figure 2K A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2K In the example shown, the second dielectric material 122b is patterned. In some examples, the second dielectric material 122b can be patterned in a manner similar to or identical to a dual damascene process. In some examples, an RDL pattern 122b1 and a via 122b2 can be provided in the second dielectric material 122b by a patterning process. Figure 2K The process shown in Figure 2D and 2E Through the patterning process, a portion of the first conductive pattern 131 (eg, the pad 131 p ) may be exposed through the via 122 b 2 and through the via 122 a 1 .

[0049] In some examples, a second passivation structure 122 comprising a first dielectric material 122a and a second dielectric material 122b can be formed in this manner. The first dielectric material 122a can include a high-function PI, and the second dielectric material 122b can include a high-resolution PI. The second passivation structure 122 can support a second conductive pattern, as described in further detail below.

[0050] Figure 2L A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2L In the example shown, a seed layer 132s is disposed on the second dielectric material 122b and the first conductive pattern 131 (e.g., the pad 131p). In some examples, the seed layer 132s may cover the exposed portion of the first conductive pattern 131 (e.g., the pad 131p). In some examples, the top side of the first conductive pattern 131 (e.g., the pad 131p) may be covered and contacted by the seed layer 132s. Figure 2L The process shown in Figure 2F The process shown in is similar or identical.

[0051] Figure 2M A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2M In the example shown, the second conductive pattern 132o is disposed on the seed layer 132s. In some examples, the second conductive pattern 132o may be disposed above the second dielectric material 122b including the RDL pattern 122b1 and the via 122b2. In some examples, the second conductive pattern 132o may include or be referred to as an electrodeposited layer or an electrode plating layer. In some examples, the second conductive pattern 132o may include Cu, Ni, Pd, Ag, or Au. Figure 2M The process shown in Figure 2H The process shown in is similar or identical.

[0052] Figure 2N A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2NIn the example shown, the top side of the second conductive pattern 132o can be planarized. In some examples, a chemical mechanical polishing pad can grind the top side of the second conductive pattern 132o. Chemical mechanical polishing can be performed until the top side of the second dielectric material 122b is exposed. In some examples, a portion of the seed layer 132s on the top side of the second dielectric material 122b can also be ground and removed. In some examples, after the chemical mechanical polishing process, the top side of the second conductive pattern 132o and the top side of the second dielectric material 122b can be coplanar. In some examples, portions of the second conductive pattern 132 can be electrically and mechanically isolated from each other in response to the chemical mechanical polishing process. A second conductive pattern 132 having an RDL pattern including traces 132t and pads 132p and a conductive via including via 132v can be disposed on the second passivation structure 122. In some examples, the second conductive pattern 132 can be coupled to the first conductive pattern 131 through the via 132v. Figure 2N The process shown in Figure 2H The process shown in is similar or identical.

[0053] Figure 2O A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2O In the example shown, something like Figure 2I-2N The illustrated manufacturing process can be repeated multiple times to provide a plurality of second passivation structures 122 and a plurality of second conductive patterns 132, each second passivation structure comprising a first dielectric material 122a and a second dielectric material 122b, and each second conductive pattern comprising a seed layer 132s, a pad 132p, a trace 132t, and a via 132v. Thus, the dielectric structure 120 can include a first passivation structure 121 and any number of second passivation structures 122, and the conductive structure 130 can include a first conductive pattern 131 and any number of second conductive patterns 132. According to various examples, the second conductive patterns 132 can be formed on or in the high-resolution second dielectric material 122b, and the high-function first dielectric material 122a can be located above and below the second conductive patterns 132 (e.g., below the pad 132p and above and below the trace 132t). For example, the high-function first dielectric material 122a can be vertically located between adjacent second conductive patterns 132. The high-resolution second dielectric material 122b may allow for the formation of narrow or fine-pitch traces and vias, while the high-functionality first dielectric material 122a suppresses or prevents electrical noise, oxidation, and ion migration between adjacent conductive elements.

[0054] According to various examples, the outer passivation structure 123 may be formed over the last (or top) second passivation structure 122 and the last (or top) second conductive pattern 132. In some examples, the outer passivation structure 123 may include one or more layers of dielectric material, such as PI, BCB, PBO, resin, or solder resist. A plurality of openings 1231 may be provided in the outer passivation structure 123. A portion of the second conductive pattern 132 (e.g., pad 132p) may be exposed through the openings 1231 in the outer passivation structure 123. The process of forming the openings 1231 may be similar to that of the outer passivation structure 123. Figure 2B and 2I The process shown in is similar or identical.

[0055] Figure 2P A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2P In the example shown, a seed layer 133s may be disposed on the outer passivation structure 123 and the second conductive pattern 132 (e.g., the pad 132p). In some examples, the seed layer 133s may cover the exposed portion of the second conductive pattern 132 (e.g., the pad 132p). In some examples, the top side of the second conductive pattern 132 (e.g., the pad 132p) may be contacted by the seed layer 133s. Figure 2P The process shown in Figure 2L The process shown in is similar or identical.

[0056] Figure 2Q A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2Q In the example shown, a photoresist 159 may be coated on the seed layer 133s located on the outer passivation structure 123, and the photoresist 159 may be patterned through exposure, development, etching, and curing processes to expose a portion of the seed layer 132s corresponding to (e.g., vertically overlapping) the pad 132p of the uppermost second conductive pattern 132. In some examples, the width or diameter of the opening in the photoresist 159 may be greater than the width or diameter of the opening 1231 in the outer passivation structure 123.

[0057] Figure 2R A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2RIn the example shown, device interconnect 150 is disposed above seed layer 133s and second conductive pattern 132. In some examples, device interconnect 150 may include contact pad 150a and terminal tip 150b. In some examples, contact pad 150a may be referred to as third conductive pattern 133 or outer conductive pattern 133. Contact pad 150a may be disposed on seed layer 133s. In some examples, contact pad 150a may be disposed on a portion of seed layer 133s exposed by photoresist 159. Contact pad 150a may include Cu, Ni, Pd, Ag, Au, or UBM. In some examples, the thickness of contact pad 150a may be in a range from approximately 3 μm to approximately 500 μm. In some examples, terminal tip 150b may be electrolytically deposited on contact pad 150a. Terminal tip 150b may also be disposed in an opening defined by photoresist 159. In some examples, the terminal tip 150b may include Sn (tin), Ag (silver), Pb (lead), Cu (copper), Sn-Pb, Sn- 37 -Pb, Sn 95 -Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. In some examples, the diameter or width of the terminal tip 150b can be in the range of about 0.01 millimeters (mm) to about 10 mm. The terminal tip 150b can be configured to couple the electronic component 10 to an external device.

[0058] Figure 2S A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2S In the example shown, photoresist 159 is removed. Photoresist 159 can be removed by, for example, a liquid resist stripper. In some examples, the liquid resist stripper can include monoethanolamine and 2-butoxyethanol. In some examples, photoresist 159 can be removed by an oxygen-containing plasma. In some examples, photoresist 159 can also be removed by a 1-methyl-2-pyrrolidone (NMP) solvent. In some examples, once photoresist 159 is dissolved, the solvent can be removed by heating the solvent to approximately 80° C., so that no residue is left. According to various examples, the top side and lateral sides of device interconnect 150 including contact pad 150 a and terminal tip 150 b can be exposed.

[0059] In some examples, the device interconnect 150 can be used as a mask, and portions of the seed layer 133s outside the footprint of the device interconnect 150 can be removed. The seed layer 133s can be removed by a wet or dry etching process. In response to the removal of the seed layer 133s, the top side of the external passivation structure 123 outside the device interconnect 150 can be exposed, and the ends of the seed layer 133s can be exposed and coplanar with the lateral sides of the device interconnect 150.

[0060] Figure 2T A cross-sectional view of the electronic assembly 10 is shown in a later stage of manufacture. Figure 2T In the example shown, the terminal tip 150b of the device interconnect 150 can be formed into a substantially hemispherical shape by a reflow process or a laser-assisted process. In some examples, these processes can include a temperature of about 150°C to about 250°C suitable for reflowing the terminal tip 150b. As used herein with respect to temperature, the term "about" can mean, for example, + / - 5 degrees, + / - 10 degrees, + / - 15 degrees, + / - 20 degrees, or + / - 25 degrees.

[0061] According to various examples, a buildup RDL 12 including a dielectric structure 120, a conductive structure 130, and a device interconnect 150 can be formed on a substrate 11. In some examples, the buildup RDL 12 can include or be referred to as an RDL substrate. The buildup RDL 12 can include embedded traces with a heterogeneous passivation structure. For example, the first conductive pattern 131 and the second conductive pattern 132 can be formed on and / or in a high-resolution second dielectric material 121b, 122b, and the high-functionality first dielectric material 121a, 122a can be located above and below the first conductive pattern 131 and the second conductive pattern 132 (e.g., below the pads 131p, 132p, and above and below the traces 131t, 132t). The high-resolution second dielectric material 122b can allow for the formation of narrow or fine pitch traces and vias, while the high-functionality first dielectric material 122a suppresses or prevents electrical noise, oxidation, and ion migration between adjacent conductive elements.

[0062] According to various examples, individual electronic components 10 can be provided by a singulation process. In some examples, the singulation process can include sawing or cutting through substrate 11, dielectric structure 120, and / or conductive structure 130 using, for example, a diamond blade wheel or a laser beam. In some examples, in response to the singulation, the lateral sides of substrate 11, dielectric structure 120, or conductive structure 130 can be coplanar.

[0063] In examples where the substrate 11 is a removable carrier, the substrate 11 can be separated from the buildup RDL 12. In some examples, a wafer support system can be attached to the buildup RDL 12 (e.g., above the top side of the external passivation structure 123 and the device interconnects 150), and the substrate 11 can then be removed from the opposite side of the buildup RDL 12. In some examples, a temporary bonding layer (e.g., a temporary bonding film, a temporary bonding tape, or a temporary adhesive coating) can be inserted between the buildup RDL 12 and the substrate 11. For example, the temporary bonding layer can be a thermal release tape (film) or an optical release tape (film), where the adhesive strength is weakened or removed by heat or light, respectively. The temporary bonding layer can allow the buildup RDL 12 to be separated from the substrate 11. In some examples, force (e.g., chemical or physical) can also be used to overcome the adhesive strength of the temporary bonding layer. In some examples, the substrate 11 can be removed by mechanical grinding and chemical etching.

[0064] In response to removing or separating the substrate 11 from the buildup RDL 12, the bottom side of the buildup RDL 12 can be exposed (e.g., the bottom side of the first dielectric material 121a and the seed layer 131s can be exposed). In some examples, the bottom side of the seed layer 131s and the bottom side of the first dielectric material 121a can be coplanar. In some examples, the exposed (or bottom) portion of the first conductive pattern 131 can include or be referred to as an internal terminal.

[0065] Figure 3 A cross-sectional view of a portion of an example electronic assembly 10 is shown. Figure 3 In the example shown, a first conductive pattern 131 surrounded by a seed layer 131s on the bottom and lateral sides can be embedded in a second dielectric material 121b (e.g., high-resolution PI). A second conductive pattern 132 surrounded by a seed layer 132s on the bottom and lateral sides can be embedded in a second dielectric material 122b (e.g., high-resolution PI). A first dielectric material 122a (e.g., high-function PI) can be inserted between the first conductive pattern 131 and the second conductive pattern 132, as well as between the dielectric material 121b and the dielectric material 122b. A portion of the second dielectric material 122b can also be located between the second conductive pattern 132 and the dielectric material 121b. Positioning the high-function first dielectric material 122a between the first conductive pattern 131 and the second conductive pattern 132 tends to suppress ion migration between the first conductive pattern 131 and the second conductive pattern 132, while the second dielectric material 122b allows the formation of a second conductive pattern 132 with narrow-pitch traces and vias. The first dielectric material 122a can reduce or prevent oxidation or void formation in the first and second conductive patterns 131 and 132. The first dielectric material 122a can also suppress or prevent electrical noise between the first and second conductive patterns 131 and 132.

[0066] Figure 4 A cross-sectional view of an example electronic device 10A is shown. Figure 4 In the example shown, electronic device 10A may include substrate 11 and buildup RDL 12. Buildup RDL 12 may include dielectric structure 120 and conductive structure 130. In some examples, buildup RDL 12 may also include device interconnect 150. Dielectric structure 120 may include a first passivation structure 121 having a first dielectric material 121a and a second dielectric material 121b, a second passivation structure 122 having a first dielectric material 122a and a second dielectric material 122b, and an outer passivation structure 123. Conductive structure 130 may include a first conductive pattern 131, a second conductive pattern 132, and an outer conductive pattern 133.

[0067] According to various examples, the electronic device 10A may use Figures 2A to 2T In some examples, the electronic device 10A may be manufactured using a process similar to or identical to the process shown and described above. In some examples, the electronic device 10A may include or be referred to as a WLP or WLCSP. In some examples, the substrate 11 of the electronic device 10A may include or be referred to as a semiconductor die, a semiconductor chip, or a semiconductor package. In some examples, the die or chip may include an integrated circuit die separated from a semiconductor wafer having multiple dies. In some examples, the substrate 11 may include a DSP (digital signal processor), a network processor, a power management unit, an audio processor, an RF (radio frequency) circuit, a wireless baseband SoC (system on chip) processor, a sensor, or an ASIC (application-specific integrated circuit). The substrate 11 may perform computing and control processing, store data, or remove noise from electrical signals. The conductive pattern 131 of the conductive structure 130 may be coupled to an I / O terminal (e.g., component interconnect 171A) of the substrate 11.

[0068] Figure 5 A cross-sectional view of an example electronic device 10B is shown. Figure 5 In the example shown, the electronic device 10B includes a substrate 11B and a stacked RLD 12. The substrate 11B may include a reconstructed wafer. For example, the substrate 11B may include an electronic component 170B and an encapsulation 160B. In some examples, the electronic device 10B may include or be referred to as a WLFO. In some examples, the electronic component 170B of the electronic device 10B may include or be referred to as a semiconductor die, a semiconductor chip, or a semiconductor package. In some examples, the electronic component 170B may include a DSP, a network processor, a power management unit, an audio processor, an RF circuit, a wireless baseband SoC processor, a sensor, or an ASIC. The electronic component 170B may perform computing and control processing, store data, or remove noise from an electrical signal. The conductive pattern 131 of the conductive structure 130 may be coupled to an I / O terminal (e.g., component interconnect 171A) of the electronic component 170B.

[0069] The buildup RDL 12 may include a dielectric structure 120 and a conductive structure 130. In some examples, the buildup RDL 12 may also include a device interconnect 150. The dielectric structure 120 may include a first passivation structure 121 having a first dielectric material 121a and a second dielectric material 121b, a second passivation structure 122 having a first dielectric material 122a and a second dielectric material 122b, and an outer passivation structure 123. The conductive structure 130 may include a first conductive pattern 131, a second conductive pattern 132, and an outer conductive pattern 133.

[0070] According to various examples, Figure 5 The electronic device 10B in the embodiment may be similar to Figure 4 In some examples, the electronic device 10B can be connected to the electronic device 10A by Figures 2A-2T The process is similar or the same as that shown in Figures 2A-2T The processing occurs over substrate 11B (eg, over encapsulated electronic component 170B).

[0071] In some examples, encapsulant 160B may include epoxy or phenolic resins, carbon black, or silica fillers. In some examples, encapsulant 160B may include or be referred to as a molding compound, a resin, a sealant, a filler-reinforced polymer, or an organic body. In some examples, encapsulant 160B may contact or cover the bottom side or lateral sides of electronic assembly 170B. In some examples, the bottom side of encapsulant 160B may be lower than the bottom side of electronic assembly 170B. In some examples, the bottom side of encapsulant 160B and the bottom side of electronic assembly 170B may be coplanar, and the bottom side of electronic assembly 170B may be exposed from the bottom side of encapsulant 160B.

[0072] Encapsulant 160B may be provided by transfer molding, compression molding, liquid encapsulant molding, vacuum lamination, paste printing, film-assisted molding, or any other suitable deposition process. The thickness of encapsulant 160B may be in the range of about 100 μm to about 2000 μm. Encapsulant 160B may protect electronic assembly 170B from the external environment or environmental exposure and may dissipate heat from electronic assembly 170B.

[0073] According to various examples, a stacked RDL 12 including conductive structures 130 and dielectric structures 120 may be disposed over the top side of the encapsulant 160B and over the top side of the electronic component 170B. In some examples, a stacked RDL 12 including conductive structures 130 and dielectric structures 120 may be implemented over the top side of the electronic component 170B and over the top side of the encapsulant 160B. Figures 2A-2T. In some examples, the top side of electronic component 170B and the top side of encapsulant 160B can be coplanar. In some examples, one or more of device interconnects 150 or portions of conductive structure 130 can be vertically located above the top side of encapsulant 150B. In some examples, first passivation structure 121 (e.g., first dielectric material 121a) can contact encapsulant 160B. Conductive pattern 131 of conductive structure 130 can provide internal terminals of stacked RDL 12 (i.e., terminals opposite device interconnect 150) and can be coupled to I / O terminals of electronic component 170B (e.g., component interconnect 171A).

[0074] According to various examples, individual electronic devices 10B can be provided by a singulation process. In some examples, singulation can include sawing or cutting through the encapsulant 160B and the build-up RDL 12. In some examples, the lateral sides of the encapsulant 160B, the dielectric structure 120, and / or the conductive structure 130 can be coplanar.

[0075] Figure 6 A cross-sectional view of an example electronic device 10C is shown. Figure 6 In the example shown, the electronic device 10C may include an electronic component 170C, a build-up RDL 12, an encapsulant 160C, and an underfill 180C. The build-up RDL 12 may include a dielectric structure 120 and a conductive structure 130. In some examples, the build-up RDL 12 may also include a device interconnect 150. The dielectric structure 120 may include a first passivation structure 121 having a first dielectric material 121a and a second dielectric material 121b, a second passivation structure 122 having a first dielectric material 122a and a second dielectric material 122b, and an outer passivation structure 123. The conductive structure 130 may include a first conductive pattern 131, a second conductive pattern 132, and an outer conductive pattern 133. The build-up RDL 12 may be formed as previously described with reference to FIG. Figures 2A-2T described. Figure 6 The electronic device 10C in the embodiment may be similar to Figure 5 The electronic device 10B is shown, but the build-up RDL 12 is provided before coupling the electronic component 170C to the build-up RDL 12.

[0076] According to various examples, Figure 2T After the process shown, the substrate 11 can be removed from the built-up RDL 12 ( Figure 2T). In some examples, the stacked RDL 12 can be flipped (i.e., rotated 180°), and the electronic component 170C can be attached to the internal terminal 130a of the stacked RDL 12. According to various examples, the exposed portion of the first conductive pattern 131, which can include the seed layer 131s, can provide or be referred to as the internal terminal 130a of the stacked RDL 12. In some examples, the electronic component 170C can include or be referred to as a bare die, a chip, a package, or a passive element. In some examples, the thickness of the electronic component 170C can be in the range of about 20 μm to about 1000 μm.

[0077] According to various examples, component interconnect 171C of electronic component 170C can be coupled to internal terminal 130a of stacked RDL 12. In some examples, component interconnect 171C can include or be referred to as a bump, a pad, or a pillar. In some examples, the thickness of component interconnect 171C can be in the range of about 1 μm to about 10 μm. In some examples, component interconnect 171C can be coupled to or contact seed layer 131s. In some examples, component interconnect 171C can be coupled to internal terminal 130a via solder. In some examples, component interconnect 171C can be coupled to internal terminal 130a by a thermocompression bonding process, an ultrasonic bonding process, a laser-assisted bonding process, or a hybrid bonding process. In some examples, a conductive structure, such as a UBM or a bonding pad, can be formed over internal terminal 130a after removing substrate 11, and component interconnect 171C can be coupled to or contact the conductive structure.

[0078] An underfill 180C may be disposed between the buildup RDL 12 and the electronic component 170C. In some examples, the underfill 180C may contact the buildup RDL 12 (e.g., the dielectric structure 120 or the conductive structure 130), the component interconnect 171C, or the electronic component 170C. In some examples, the underfill 180C may include or be referred to as a CUF (capillary underfill), an NCP (non-conductive paste), an NCF (non-conductive film), or an ACF (anisotropic conductive film). In some examples, after the electronic component 170C is coupled to the buildup RDL 12, the underfill 180C may be inserted into the gap between the electronic component 170C and the buildup RDL 12. In some examples, the underfill 180C may be pre-applied to the buildup RDL 12 before the electronic component 170C is coupled to the buildup RDL 12. In some examples, underfill 180C may be pre-applied on electronic component 170C before electronic component 170C is coupled to build-up RDL 12. In some examples, a curing process (eg, a thermal curing process or a photocuring process) of underfill 180C may be performed.

[0079] In some examples, encapsulant 160C may be positioned above buildup RDL 12, electronic component 170C, and underfill 180C. Encapsulant 160C may cover buildup RDL 12, electronic component 170C, and underfill 180C. In some examples, encapsulant 160C may contact buildup RDL 12, electronic component 170C, and underfill 180C. In some examples, underfill 180C may be omitted, and encapsulant 160C may be filled between electronic component 170C and buildup RDL 12. In some examples, encapsulant 160C may be located above the top side of electronic component 170C. In some examples, encapsulant 160C may be coplanar with the top side of electronic component 170C.

[0080] Figure 7 A cross-sectional view of an exemplary electronic device 10D is shown. Figure 7 In the example shown, the electronic device 10D may include one or more electronic components 170D, component interconnects 171D, a buildup RDL 12, an encapsulant 160D, an underfill 180D, a base substrate 320D, an external interconnect 330D, an underfill 190, a cover 310D, and interface materials 315D and 316D. The buildup RDL 12 includes a dielectric structure 120, a conductive structure 130, and a device interconnect 150, as previously described. Figures 2A-2T As described. Figure 7 In the example shown, the electronic device 10D may be formed by providing the build-up RDL 12 before coupling the electronic component 170D to the build-up RDL 12 .

[0081] According to various examples, base substrate 320D may include dielectric structures 321D and conductive structures 322D. In some examples, dielectric structure 321D may include one or more layers of dielectric material interleaved with layers of conductive structure 322D. In some examples, the dielectric material may include PI, BCB, PBO, resin, or ABF. In some examples, conductive structure 322D may include one or more conductive layers defining signal distribution elements (e.g., traces, vias, pads, conductive paths, or UBMs). Conductive structure 322D may include substrate-inward terminals 324D1 and substrate-outward terminals 324D2. In some examples, substrate-inward terminals 324D1 may include pads, platforms, UBMs, or pillars. In some examples, substrate-outward terminals 324D2 may include pads, platforms, or UBMs. External interconnects 330D may include solder balls, bumps, pads, pillars, solder-coated copper core balls, or solder-capped copper pillars. The external interconnect 330D may be coupled to the substrate-outward terminal 324D2 of the base substrate 320D. In some examples, the outward terminal 324D2 may include an LGA (Land Grid Array).

[0082] In some examples, base substrate 320D may be a preformed substrate. A preformed substrate may be manufactured before attachment to an electronic device and may include a dielectric layer between corresponding conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick, non-photodefinable layer and may be attached as a preformed film rather than as a liquid. It may contain a resin with fillers such as strands, woven fabric, or other inorganic particles for rigidity and / or structural support. Because the dielectric layer is non-photodefinable, features such as through-holes or openings may be formed using a drill or laser. In some examples, the dielectric layer may include prepreg material or ABF. The preformed substrate may include a permanent core structure or carrier, such as a dielectric material including BT or FR4, and the dielectric and conductive layers may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate that omits the permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before attachment to the electronic device. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate.Such a preformed substrate may be formed via a semi-additive process or a modified semi-additive process.

[0083] In some examples, the base substrate 320D can be an RDL substrate. The RDL substrate can include one or more conductive layers and one or more dielectric layers, and (a) can be formed layer by layer above the electronic device to which the RDL substrate is to be electrically coupled, or (b) can be formed layer by layer above a carrier that can be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate can be manufactured layer by layer as a wafer-level substrate using a wafer-level process on a circular wafer, and / or as a panel-level substrate using a panel-level process on a rectangular or square panel carrier. The RDL substrate can be formed by an additive buildup process and can include one or more dielectric layers alternately stacked with one or more conductive layers, and define corresponding conductive patterns or traces that are configured to collectively (a) fan the electrical traces out of the footprint of the electronic device, and / or (b) fan the electrical traces into the footprint of the electronic device. The conductive pattern can be formed using a plating process such as an electroplating process or an electroless plating process. The conductive pattern can include a conductive material such as copper or other plateable metal. The locations of the conductive patterns can be made using a photopatterning process, such as a photolithography process, and a photoresist material used to form a photolithography mask. The dielectric layer of the RDL substrate can be patterned using a photopatterning process and can include a photolithography mask through which light is exposed to the desired features of the photopattern, such as vias in the dielectric layer. The dielectric layer can be made of a photodefinable organic dielectric material, such as PI, BCB, or PBO. These dielectric materials can be spin-coated or otherwise applied in liquid form rather than attached as a preformed film. To allow the desired photodefinable features to be properly formed, these photodefinable dielectric materials can omit structural reinforcements or can be filler-free, without strands, woven fabrics, or other particles that may interfere with the light from the photopatterning process. In some examples, these filler-free properties of the filler-free dielectric material can allow the vertical thickness or height of the resulting dielectric layer to be reduced. Although the photodefinable dielectric materials described above can be organic materials, in some examples, the dielectric material of the RDL substrate can include one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). The inorganic dielectric layer may be formed not by using a photodefined organic dielectric material but by growing the inorganic dielectric layer using an oxidation or nitridation process. Such inorganic dielectric layers may be filler-free and free of strands, woven fabrics, or other dissimilar inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material including bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates.

[0084] The device interconnects 150 of the buildup RDL 12 can be coupled to the substrate inward terminals 324D1 of the base substrate 320D. In some examples, the device interconnects 150 can be coupled to the inward terminals 324D1 by thermocompression bonding, ultrasonic bonding, laser-assisted bonding, or hybrid bonding. In some examples, solder can be inserted between the device interconnects 150 and the inward terminals 324D1. In some examples, an underfill 190 can be inserted between the buildup RDL 12 and the base substrate 320D. In some examples, the underfill 190 can be located above or cover the lateral sides of the buildup RDL 12.

[0085] In some examples, the cover 310D can be coupled to the electronic component 170D via an interface material 315D. The cover 310D can be coupled to the base substrate 320D via an interface material 316D. In some examples, the cover 310D can include a heat sink and can be coupled (e.g., thermally and / or mechanically) to the electronic component 170D via the thermally conductive interface material 315D. For example, the interface material 315D can include a thermal interface material (TIM). In some examples, the interface material 315D can also be inserted between the encapsulant 160D and the cover 310D. The cover 310D can include or be referred to as a cover, housing, or shell. In some examples, the cover 310D can provide electromagnetic interference (EMI) shielding. The height of the cover 310D can range from approximately 100 μm to approximately 1000 μm. The interface material 316D can couple the cover 310D to the upper side of the base substrate 320D. The interface material 316D can include, for example, an adhesive. In some examples, interface material 316D can be electrically insulating. In some examples, interface material 316D can be electrically conductive and can couple cover 310D to conductive structures 322D of base substrate 320D. In some examples, cover 310D can be conformally applied (e.g., including applying a conformal coating) over the top side and / or lateral sides of electronic component 170D, encapsulant 160D, buildup RDL 12, underfill 190, and / or base substrate 320D. Cover 310D can dissipate heat from electronic component 170D and / or can protect buildup RDL 12 and electronic component 170D from the external environment.

[0086] A heterogeneous multi-passivation structure may include a high-function dielectric and a high-resolution dielectric. The high-function dielectric may be placed between adjacent conductive elements of an electronic device (e.g., traces or other conductive structures in a high-resolution material). The high-function dielectric tends to suppress electrical noise, oxidation, and ion migration between adjacent conductive elements. For example, embedded traces may be formed in a high-resolution dielectric material of a heterogeneous passivation structure. The high-function insulating material and the high-resolution insulating material may be interleaved, layered, selectively placed, or otherwise selectively located in the heterogeneous passivation structure to increase the reliability and electrical performance of fine-pitch traces or other conductive elements.

[0087] This disclosure includes references to certain examples. However, those skilled in the art will appreciate that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but rather that the disclosure encompasses all examples within the scope of the appended claims.

Claims

1. An electronic device comprising: substrate; a first passivation structure over the substrate and defining a first opening; a first conductive pattern formed in the first opening; a second passivation structure over the first conductive pattern and the first passivation structure, wherein the second passivation structure comprises a high-resolution material and a high-functionality material, wherein the high-resolution material of the second passivation structure defines a second opening; as well as A second conductive pattern is disposed in the second opening of the second passivation structure, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern.

2. The electronic device of claim 1 , wherein the high-function material defines a first via extending through the second passivation structure to the first conductive pattern, wherein the high-resolution material defines a second via extending through the first via of the second passivation structure to the first conductive pattern. 3 . The electronic device according to claim 2 , further comprising a seed layer extending through the first and second vias to the first conductive pattern, wherein the high-resolution material is between the high-function material and the seed layer. 4 . The electronic device of claim 1 , wherein the high-functionality material comprises a dielectric constant (Dk) of less than 3.

0. 5 . The electronic device of claim 1 , wherein the high-function material comprises a dissipation factor (Df) of less than 0.

004.

6. The electronic device of claim 1, wherein the high-resolution material comprises a material capable of being patterned with a resolution value less than 2 microns. 7 . The electronic device according to claim 1 , wherein the high-function material comprises a first organic substance, and the high-resolution material comprises a second organic substance.

8. The electronic device according to claim 1, wherein the substrate comprises: electronic components; as well as An encapsulant is disposed around the lateral sides of the electronic component.

9. The electronic device according to claim 8, further comprising: a thermal adhesive coupled to the top side of the electronic component; as well as A heat sink is coupled to the thermal adhesive. 10 . The electronic device of claim 9 , further comprising a base substrate electrically coupled to the electronic component via the first conductive pattern and the second conductive pattern, wherein the heat sink is coupled to the base substrate. 11 . The electronic device of claim 8 , further comprising an underfill disposed between the electronic component and the first passivation structure.

12. The electronic device of claim 1, wherein the high-resolution material comprises positive photosensitive polyimide (PSPI).

13. An electronic device comprising: substrate; a first dielectric material overlying the substrate and defining a first opening; a first conductive pattern formed in the first opening; a second dielectric material disposed over the first conductive pattern and the first dielectric material, wherein the second dielectric material comprises a highly functional material defining a second opening; a third dielectric material disposed over the second dielectric material and extending into the second opening, wherein the third dielectric material comprises a high-resolution material defining a third opening; as well as A second conductive pattern is disposed in the third opening of the high-resolution material, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern. 14 . The electronic device of claim 13 , wherein the high-function material defines a first via extending through the second dielectric material to the first conductive pattern, wherein the high-resolution material defines a second via extending through the first via to the first conductive pattern.

15. The electronic device of claim 13, wherein the high-functionality material comprises a dielectric constant (Dk) less than 3.

0.

16. The electronic device of claim 13, wherein the high-function material comprises a dissipation factor (Df) less than 0.

004.

17. The electronic device of claim 13, wherein the high-resolution material comprises a material capable of being patterned with a resolution value less than or equal to 2 microns.

18. A method of manufacturing a semiconductor device, comprising: providing a substrate; providing a first dielectric material over the substrate, wherein the first dielectric material defines a first opening; providing a first conductive pattern in the first opening; providing a second dielectric material over the first conductive pattern and the first dielectric material, wherein the second dielectric material comprises a highly functional material and defines a second opening; providing a third dielectric material over the second dielectric material and extending into the second opening, wherein the third dielectric material comprises a high-resolution material and defines a third opening; and A second conductive pattern is provided, the second conductive pattern being disposed in the third opening of the third dielectric material, wherein the high-function material is disposed between the first conductive pattern and the second conductive pattern.

19. The method of claim 18, wherein the high-functionality material comprises a dielectric constant (Dk) less than 3.0 and a dissipation factor (Df) less than 0.

004.

20. The method of claim 18, wherein the high-resolution material comprises a material capable of being patterned with a resolution value less than or equal to 2 microns.

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