Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a first semiconductor structure which comprises a first substrate having a first surface; the conductive layer at least fills the first through hole, and the first through hole at least extends from the first surface to the interior of the first substrate and at least penetrates through the first substrate; the first protection layer covers the side wall of the first through hole and is positioned between the side wall of the first through hole and the conductive layer; the second protection layer is located between the first protection layer and the conductive layer, and part of the first protection layer further covers the surface, away from the first surface, of the second protection layer.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, the feature size of integrated circuits continues to shrink, and the device interconnection density continues to increase. Traditional two-dimensional packaging can no longer meet the needs of the industry. Therefore, the stacked packaging method based on vertical interconnection of through silicon vias (TSV) has become the mainstream direction of packaging technology development with its key technical advantages of short-distance interconnection and high-density integration.

[0003] However, in actual operation, there are still many problems in the through silicon via manufacturing process that need to be improved. Summary of the Invention

[0004] An embodiment of the present disclosure provides a semiconductor structure, including: a first semiconductor structure, wherein the first semiconductor structure includes:

[0005] a first substrate having a first surface;

[0006] a first through hole and a conductive layer at least filling the first through hole, wherein the first through hole extends at least from the first surface toward the interior of the first substrate and at least penetrates the first substrate;

[0007] a first protection layer covering the sidewall of the first through hole and located between the sidewall of the first through hole and the conductive layer;

[0008] The second protection layer is located between the first protection layer and the conductive layer, and a portion of the first protection layer also covers a surface of the second protection layer away from the first surface.

[0009] In some embodiments, the thickness of the second protective layer located at the opening of the first through hole is greater than or equal to zero, and is less than the thickness of the second protective layer located at other positions of the first through hole; the difference between the thickness of the first protective layer located at the opening of the first through hole and the thickness of the first protective layer located at other positions of the first through hole is within a preset range.

[0010] In some embodiments, when the thickness of the second protection layer at the first through-hole opening is greater than zero, the thickness of the first protection layer at the first through-hole opening is equal to or substantially equal to the thickness of the first protection layer at other locations of the first through-hole.

[0011] In some embodiments, when the thickness of the second protective layer at the first through-hole opening is equal to zero, the difference between the thickness of the first protective layer at the first through-hole opening and the thickness of the first protective layer at other positions of the first through-hole is less than or equal to 50 nm.

[0012] In some embodiments, a ratio of a thickness of the first protective layer at other locations of the first through hole to a thickness of the second protective layer at other locations of the first through hole is in a range of 1.5 to 5; and / or,

[0013] The thickness of the first protection layer at other positions of the first through hole ranges from 150 nm to 250 nm.

[0014] In some embodiments, the first substrate further includes a second surface opposite to the first surface, and the first semiconductor structure further includes:

[0015] a dielectric layer located on the second surface of the first substrate, wherein the first through hole extends into the dielectric layer and penetrates a portion of the dielectric layer;

[0016] a metal interconnect structure located on a surface of the dielectric layer facing away from the first substrate;

[0017] The second through hole is located in the dielectric layer and extends from the bottom of the first through hole to the metal interconnection structure. Part of the dielectric layer surrounding the second through hole covers the surface of the first protective layer facing away from the first surface. The conductive layer also fills the second through hole and is electrically connected to the metal interconnection structure.

[0018] In some embodiments,

[0019] The thickness of the dielectric layer covering the surface of the first protective layer facing away from the first surface is in a range of 100 nm to 300 nm; and / or,

[0020] The conductive layer includes a diffusion barrier layer and a conductive material layer, the diffusion barrier layer at least covers the side walls of the second protective layer, the side walls of the first protective layer located on the side of the second protective layer away from the first surface, and the side walls and bottom surface of the second through hole, and the conductive material layer covers the diffusion barrier layer and fills the first through hole and the second through hole.

[0021] In some embodiments, the semiconductor structure further includes: a second semiconductor structure, the second semiconductor structure being bonded to a side of the metal interconnect structure in the first semiconductor structure facing away from the first surface.

[0022] The present disclosure also provides a method for manufacturing a semiconductor structure.

[0023] Providing a first semiconductor structure, the providing of the first semiconductor structure comprising: providing a first substrate, the first substrate having a first surface and a second surface opposite to the first surface; forming a dielectric layer on the second surface of the first substrate; forming a metal interconnect structure on a surface of the dielectric layer facing away from the first substrate;

[0024] forming a first through hole, the first through hole extending from at least the first surface of the first substrate into the dielectric layer; the first through hole at least passes through the first substrate and a portion of the dielectric layer;

[0025] forming a first protective material layer covering at least the sidewalls and bottom surface of the first through hole;

[0026] forming a second protective material layer covering the first protective material layer;

[0027] performing a first etching process to remove at least the second protective material layer covering the bottom surface of the first through hole to form a second protective layer;

[0028] performing a second etching process to remove at least the first protective material layer covering the bottom surface of the first through-hole to form a first protective layer, and to remove the dielectric layer exposed by the first through-hole to form a second through-hole, wherein the second through-hole is located within the dielectric layer and exposes a portion of the metal interconnect structure; wherein the first protective layer covers the sidewalls of the first through-hole, the second protective layer covers a portion of the surface of the first protective layer facing away from the sidewalls of the first through-hole, and a portion of the first protective layer also covers a surface of the second protective layer facing away from the first surface; and a portion of the dielectric layer surrounding the second through-hole covers a surface of the first protective layer facing away from the first surface;

[0029] A conductive layer is formed, which at least fills the first through hole and the second through hole and is electrically connected to the metal interconnection structure.

[0030] In some embodiments, in the step of performing the first etching process, an etching selectivity ratio of the second protective material layer to the first protective material layer is greater than or equal to 5;

[0031] In the step of performing the second etching process, an etching selectivity ratio between the first protection material layer and the second protection material layer is greater than or equal to 5.

[0032] In some embodiments, after performing the first etching process, a portion of the second protection material layer located at the first through-hole opening is removed;

[0033] After performing the second etching process, the thickness of the second protective layer located at the opening of the first through hole is greater than or equal to zero, and is less than the thickness of the second protective layer located at other positions of the first through hole; the thickness of the first protective layer located at the opening of the first through hole, and the difference between the thickness of the first protective layer located at other positions of the first through hole are within a preset range.

[0034] In some embodiments, after performing the second etching process, the thickness of the second protective layer located at the first through-hole opening is greater than zero, and the thickness of the first protective layer located at the first through-hole opening is equal to or substantially equal to the thickness of the first protective layer located at other positions of the first through-hole.

[0035] In some embodiments, after performing the second etching process, the thickness of the second protective layer located at the first through-hole opening is equal to zero, and the difference between the thickness of the first protective layer located at the first through-hole opening and the thickness of the first protective layer located at other positions of the first through-hole is less than or equal to 50 nm.

[0036] In some embodiments, after forming the first through hole, the minimum thickness of the remaining dielectric layer ranges from 100 nm to 300 nm; and / or,

[0037] The thickness of the formed first protective material layer is in a range from 150 nm to 250 nm.

[0038] In some embodiments, before forming the first through hole, the method further includes:

[0039] A second semiconductor structure is provided, and the second semiconductor structure is bonded to a side of the metal interconnection structure in the first semiconductor structure that is away from the first surface.

[0040] In some embodiments, forming a conductive layer includes: forming a diffusion barrier layer and a conductive material layer, the diffusion barrier layer at least covering the sidewalls of the second protective layer, the sidewalls of the first protective layer located on the side of the second protective layer away from the first surface, and the sidewalls and bottom surface of the second through hole, the conductive material layer covering the diffusion barrier layer and filling the first through hole and the second through hole, the diffusion barrier layer and the conductive material layer together constitute a conductive layer, and the conductive layer is electrically connected to the metal interconnection structure.

[0041] In the embodiment of the present disclosure, a second protective layer is provided between the first protective layer and the conductive layer. Under the protective effect of the second protective layer, during the etching process of the first protective layer, the etching of the first protective layer located at the first through-hole opening is avoided or reduced, thereby avoiding the dielectric breakdown phenomenon caused by the excessively small thickness of the first protective layer.

[0042] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 A schematic structural diagram of a semiconductor structure provided by some embodiments of the present disclosure;

[0045] Figure 2Schematic diagrams of semiconductor structures provided in other embodiments of the present disclosure;

[0046] Figure 3 A schematic structural diagram of a semiconductor structure provided in some further embodiments of the present disclosure;

[0047] Figure 4 A flowchart of a method for manufacturing a semiconductor structure provided in some embodiments of the present disclosure;

[0048] Figures 5 to 12 A schematic diagram of the structure of a semiconductor structure during the manufacturing process provided by some embodiments of the present disclosure;

[0049] Figure 13 Schematic diagrams of the structure of semiconductor structures during the manufacturing process provided by other embodiments of the present disclosure;

[0050] Figure 14 Schematic diagram of the structure of a semiconductor structure during the manufacturing process provided in some further embodiments of the present disclosure. DETAILED DESCRIPTION

[0051] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0052] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0053] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0054] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0055] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0056] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0057] A semiconductor structure, such as a memory, generally includes a substrate and a dielectric layer located on the substrate, and structures such as devices and metal layers are generally formed in the dielectric layer. In actual processes, through silicon vias (TSVs) can be formed in the semiconductor structure to achieve vertical interconnection between multiple semiconductor structures. Through silicon vias can generally be formed by a through-hole first (TSV First) process, a through-hole middle (TSV Middle) process, or a through-hole last (TSV Last) process. Among them, the through-hole last (Via Last) process generally etches from the back of the substrate into the dielectric layer located on the front of the substrate to form a through-hole, and then deposits an oxide layer on the sidewall and bottom surface of the through-hole. The oxide layer acts as an electrical isolation, and then continues to etch downward from the bottom of the through-hole to expose the metal layer located in the dielectric layer, and then forms a conductive layer for conducting electrical signals in the through-hole to connect the conductive layer with the metal layer.

[0058] However, the applicants of this disclosure have discovered that, during the process of etching downward from the bottom of the via, portions of the oxide layer at the top of the via are also etched away. This can lead to dielectric breakdown due to insufficient oxide layer thickness at the via opening, resulting in leakage. Furthermore, due to the impact of shrinking design dimensions, the oxide layer thickness cannot be designed to be too thick. Otherwise, after the oxide layer is formed, the via bottom opening may be insufficient, thereby increasing the TSV interconnect resistance and failing to meet design requirements.

[0059] Based on this, the technical solution of the embodiment of the present disclosure is proposed. In the embodiment of the present disclosure, by providing a second protective layer between the first protective layer and the conductive layer, under the protective effect of the second protective layer, during the etching process of the first protective layer, etching of the first protective layer located at the opening of the first through hole is avoided or reduced, thereby avoiding dielectric breakdown caused by the thickness of the first protective layer being too small.

[0060] To make the above-mentioned purposes, features, and advantages of the present disclosure more clearly understood, the following detailed description of the specific embodiments of the present disclosure is provided in conjunction with the accompanying drawings. When describing the embodiments of the present disclosure, for ease of explanation, the schematic diagrams may be partially enlarged to a different scale than the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present disclosure.

[0061] like Figure 1As shown, the semiconductor structure includes: a first semiconductor structure 10, wherein the first semiconductor structure 10 includes: a first substrate 11, having a first surface 111; a first through hole 151 and a conductive layer 17 that at least fills the first through hole 151, the first through hole 151 extends at least from the first surface 111 to the interior of the first substrate 11 and at least penetrates the first substrate 11; a first protective layer 161, covering the sidewalls of the first through hole 151 and located between the sidewalls of the first through hole 151 and the conductive layer 17; a second protective layer 162, located between the first protective layer 161 and the conductive layer 17, and part of the first protective layer 161 also covers the surface of the second protective layer 162 facing away from the first surface 111.

[0062] In actual operation, the material of the first substrate 11 may include a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), or a III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), or a II-VI compound semiconductor material, or an organic semiconductor material, or other semiconductor materials known in the art. For example, the first substrate 11 may be a silicon substrate. In some embodiments, the first substrate 11 may be a wafer, for example, a silicon wafer.

[0063] In some embodiments, the first semiconductor structure 10 may further include a dielectric layer 14 located on the first surface 111 of the first substrate 11. In practice, the material of the dielectric layer 14 may include, but is not limited to, oxides, such as silicon oxide. The dielectric layer 14 may be used to protect the first surface 111 of the first substrate 11.

[0064] In some embodiments, the first substrate 11 may further include a second surface 112 opposite to the first surface 111. The first surface 111 may be the back surface of the first substrate 11, and the second surface 112 may be the front surface of the first substrate 11. In actual operation, device structures such as transistors, word lines, bit lines, and capacitors (not shown) may be formed on the second surface 112 of the first substrate 11.

[0065] In some embodiments, the first semiconductor structure 10 may further include: a dielectric layer 12 , which may be located on the second surface 112 of the first substrate 11 ; and a metal interconnect structure 13 , which may be located on a surface of the dielectric layer 12 facing away from the first substrate 11 .

[0066] In actual operation, the dielectric layer 12 may also cover the device structure located on the first surface 111 of the first substrate 11. The dielectric layer 12 may be a multi-layer structure, and may be formed from multiple layers of insulating material in multiple process steps. Multiple metal layers may also be formed within the dielectric layer 12, as well as conductive plugs for electrically connecting two adjacent metal layers. The metal interconnect structure 13 may also be electrically connected to the metal layers located within the dielectric layer 12 through the conductive plugs, and further electrically connected to the device structure located on the first surface 111 of the first substrate 11.

[0067] In actual operation, the material of the dielectric layer 12 may include, but is not limited to, oxides, such as silicon oxide; the material of the metal interconnect structure 13 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), or any other combination thereof.

[0068] In some embodiments, the semiconductor structure may further include: a second semiconductor structure 20 . The second semiconductor structure 20 may be bonded to a side of the metal interconnect structure 13 in the first semiconductor structure 10 facing away from the first surface 111 .

[0069] In actual operation, the first semiconductor structure 10 and the second semiconductor structure 20 can be a wafer containing multiple chips, and the first semiconductor structure 10 and the second semiconductor structure 20 can be bonded together by hybrid bonding. Specifically, the second semiconductor structure 20 may include a second substrate (not shown), an interlayer dielectric layer (not shown) located on the second substrate, and an interconnect structure (not shown) located on the side of the interlayer dielectric layer facing away from the second substrate. The interconnect structure of the second semiconductor structure 20 can be bonded to the metal interconnect structure 13 of the first semiconductor structure 10. However, the present invention is not limited to this. The interconnect structure of the second semiconductor structure 20 and the metal interconnect structure 13 of the first semiconductor structure 10 can also be bonded to each other through conductive bumps.

[0070] In actual operation, after the first semiconductor structure 10 and the second semiconductor structure 20 are bonded, etching can be performed on the side surface of the first semiconductor structure 10 facing away from the second semiconductor structure 20 in a direction toward the second semiconductor structure 20 to form a first through hole 151, that is, the first through hole 151 of the embodiment of the present disclosure can be manufactured using a through-hole last (TSVLast) process.

[0071] In some embodiments, the first through hole 151 may extend into the dielectric layer 12 and penetrate a portion of the dielectric layer 12. In some embodiments, the first through hole 151 may also penetrate the dielectric layer 14, that is, the first through hole 151 may extend from a surface of the dielectric layer 14 facing away from the first surface 111 into the dielectric layer 12, and sequentially penetrate the dielectric layer 14, the first substrate 11, and a portion of the dielectric layer 12.

[0072] In actual operation, after forming the first through hole 151, a first protective material layer covering at least the bottom surface and side wall of the first through hole 151 and a second protective material layer covering the first protective material layer can be first formed, and then the second protective material layer is etched to at least remove the second protective material layer located on the bottom surface of the first through hole 151 to form a second protective layer and expose a portion of the first protective material layer covering the bottom surface of the first through hole 151; then, the exposed first protective material layer located on the bottom surface of the first through hole 151 is further etched to form a first protective layer 161, thereby opening the bottom of the first through hole 151 to expose a portion of the dielectric layer 12, which is convenient for performing subsequent etching processes.

[0073] The first protective layer 161 can electrically isolate the first substrate 11 from the conductive layer 17. In the embodiment of the present disclosure, the second protective layer 162 is located between the first protective layer 161 and the conductive layer 17, and a portion of the first protective layer 161 is located on the surface of the second protective layer 162 facing away from the first surface 111. That is, the second protective layer 162 can protect the first protective layer 161. In this way, under the protective effect of the second protective layer 162, during the process of etching the first protective material layer to form the first protective layer 161 and in subsequent etching processes, etching of the first protective layer 161 located at the opening of the first through hole 151 can be avoided or reduced, thereby avoiding dielectric breakdown caused by the thickness of the first protective layer 161 being too small.

[0074] In some embodiments, the thickness of the second protective layer 162 at the opening of the first through-hole 151 may be greater than or equal to zero, and may be less than the thickness of the second protective layer 162 at other locations of the first through-hole 151. In some embodiments, the thickness of the first protective layer 161 at the opening of the first through-hole 151 may be less than, equal to, or substantially equal to the thickness of the first protective layer 161 at other locations of the first through-hole 151, and the difference between the thickness of the first protective layer 161 at the opening of the first through-hole 151 and the thickness of the first protective layer 161 at other locations of the first through-hole 151 may be within a preset range, for example, the difference may be less than or equal to 50 nm, such as 0, 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, etc.

[0075] Here and below, other positions in the first protective layer 161 located at other positions of the first through hole 151 refer to other positions where the first protective layer 161 is retained except the opening of the first through hole 151; other positions in the second protective layer 162 located at other positions of the first through hole 151 refer to other positions where the second protective layer 162 is retained except the opening of the first through hole 151.

[0076] like Figure 1 As shown, in some embodiments, when the thickness of the second protective layer 162 at the opening of the first through-hole 151 is greater than zero, the thickness of the first protective layer 161 at the opening of the first through-hole 151 may be equal to or substantially equal to the thickness of the first protective layer 161 at other locations of the first through-hole 151. It can be understood that the thickness of the second protective layer 162 at the opening of the first through-hole 151 is greater than zero, that is, the second protective layer 162 at the opening of the first through-hole 151 is not completely consumed, and it has a sufficient protective effect on the first protective layer 161 at the opening of the first through-hole 151. Therefore, the first protective layer 161 at the first through-hole 151 will not be consumed during the etching process, thereby further avoiding dielectric breakdown.

[0077] But not limited to this, such as Figure 2 and Figure 3 As shown, in some other embodiments of the present disclosure, the second protective layer 162 located at the opening of the first through hole 151 can also be completely consumed to expose the first protective layer 161 located at the opening of the first through hole 151, that is, the thickness of the second protective layer 162 located at the opening of the first through hole 151 can be equal to zero, and the first protective layer 161 located at the opening of the first through hole 151 can be not consumed or partially consumed.

[0078] In some embodiments, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 is less than or equal to 50nm, for example, 0, 10nm, 20nm, 30nm, 40nm, 50nm, etc.

[0079] Specifically, such as Figure 2As shown, in some embodiments, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the thickness of the first protective layer 161 located at the opening of the first through hole 151 can be equal to or substantially equal to the thickness of the first protective layer 161 located at other positions of the first through hole 151, that is, the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 can be 0.

[0080] But not limited to this, such as Figure 3 As shown, in other embodiments, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the thickness of the first protective layer 161 located at the opening of the first through hole 151 may also be less than the thickness of the first protective layer 161 located at other positions of the first through hole 151, and the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 is less than or equal to 50nm.

[0081] In this way, in the embodiment of the present disclosure, through the protective effect of the second protective layer 162, the difference between the thickness of the first protective layer 161 at the opening of the first through hole 151 and the thickness of the first protective layer 161 at other positions of the first through hole 151 is within a preset range, which can avoid the dielectric breakdown phenomenon caused by the thin thickness of the first protective layer 161.

[0082] In some embodiments, the thickness of the first protective layer 161 at other locations of the first through hole 151 ranges from 150 nm to 250 nm (inclusive), for example, 150 nm, 200 nm, 250 nm, etc. By controlling the thickness of the first protective layer 161 at other locations of the first through hole 151 within the above range, the electrical isolation effect of the first protective layer 161 can be improved, and dielectric breakdown can be avoided. At the same time, the first protective layer 161 can be prevented from being too thick, which would result in a smaller bottom opening of the space defined by the first protective layer 161 within the first through hole 151 and fail to meet design requirements.

[0083] In some embodiments, the ratio of the thickness of the first protective layer 161 at other locations of the first through-hole 151 to the thickness of the second protective layer 162 at other locations of the first through-hole 151 is in a range of 1.5 to 5 (inclusive), for example, 1.5, 3, 4, 5, etc. By controlling the ratio within this range, the second protective layer 162 can protect the first protective layer 161 while preventing the second protective layer 162 from being too thick, which would result in a smaller bottom opening of the space defined by the second protective layer 162 within the first through-hole 151 and fail to meet design requirements.

[0084] In some embodiments, the thickness of the second protection layer 162 at other locations of the first through hole 151 ranges from 50 nm to 100 nm (including endpoints), for example, 50 nm, 60 nm, 80 nm, 100 nm, etc.

[0085] In some embodiments, the material of the first protection layer 161 and the material of the second protection layer 162 are different.

[0086] In some embodiments, the material of the first protective layer 161 may include, but is not limited to, an oxide, such as silicon oxide. In some embodiments, the material of the second protective layer 162 may be an insulating material. The material of the second protective layer 162 may include one or a combination of nitrides (e.g., silicon nitride), carbonitrides (e.g., silicon carbonitride), oxynitrides (e.g., silicon oxynitride), etc. However, the material of the second protective layer 162 may also be a diffusion barrier material, such as one or a combination of tantalum, titanium, tantalum nitride, titanium nitride, etc.

[0087] In some embodiments, the first semiconductor structure 10 may further include: a second through hole 152 located in the dielectric layer 12 and extending from the bottom of the first through hole 151 to the metal interconnect structure 13, and a portion of the dielectric layer 12 surrounding the second through hole 152 covers the surface of the first protective layer 161 facing away from the first surface 111.

[0088] In actual operation, after etching the exposed first protective material layer at the bottom of the first through hole 151 to open the bottom of the first through hole 151, the exposed portion of the dielectric layer 12 can be further removed to expose a portion of the metal connection structure 13 to form a second through hole 152.

[0089] In the embodiment of the present disclosure, under the protection of the first protective layer 161 and the second protective layer 162, a portion of the dielectric layer 12 located on the side of the first protective layer 161 facing away from the first surface 111 is retained. The retained portion of the dielectric layer 12 surrounds the second through hole 152 and covers the surface of the first protective layer 161 facing away from the first surface 111.

[0090] In some embodiments, the thickness of the dielectric layer 12 covering the surface of the first protective layer 161 facing away from the first surface 111 is in the range of 100 nm to 300 nm (including endpoint values), for example, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc. By controlling the thickness within the above range, the etching time is avoided from being too long in the step of continuing to etch the dielectric layer 12 downward from the bottom of the first through hole 151, thereby further reducing the loss of the first protective layer 161 located at the opening of the first through hole 151.

[0091] like Figure 1As shown, in some embodiments, the conductive layer 17 further fills the second through hole 152 and is electrically connected to the metal interconnection structure 13 for transmitting electrical signals.

[0092] In some embodiments, the conductive layer 17 includes a diffusion barrier layer 171 and a conductive material layer 172. The diffusion barrier layer 171 covers at least the side walls of the second protective layer 162, the side walls of the first protective layer 161 located on the side of the second protective layer 162 away from the first surface 111, and the side walls and bottom surface of the second through hole 152. The conductive material layer 172 covers the diffusion barrier layer 171 and fills the first through hole 151 and the second through hole 152.

[0093] In actual operation, the material of the diffusion barrier layer 171 may include one or a combination of tungsten, titanium, tungsten nitride, titanium nitride, etc., which is used to prevent the material of the conductive material layer 172 from diffusing into the first protective layer 161 and the first substrate 11; the material of the conductive material layer 172 may include tungsten (W), copper (Cu), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), metal silicide, metal alloy or any combination thereof, such as copper.

[0094] In some embodiments, when the material of the second protective layer 162 includes a diffusion barrier material, the second protective layer 162 can also serve to block the material of the conductive material layer 172 from diffusing into the first protective layer 161 and the first substrate 11. Therefore, compared with the case where the material of the second protective layer 162 includes an insulating material, when the material of the second protective layer 162 includes a diffusion barrier material, the thickness of the diffusion barrier layer 171 can be smaller.

[0095] like Figure 2 and Figure 3 As shown, in other embodiments of the present disclosure, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the first protective layer 161 located at the opening of the first through hole 151 is exposed by the second protective layer 162, and the diffusion barrier layer 171 can also cover the side wall of the first protective layer 161 located at the opening of the first through hole 151 facing the conductive layer 17, and the surface of the second protective layer 162 facing the first surface 111.

[0096] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 4 As shown, the method includes the following steps:

[0097] Step S101: providing a first semiconductor structure, wherein providing the first semiconductor structure includes: providing a first substrate, the first substrate having a first surface and a second surface opposite to the first surface; forming a dielectric layer on the second surface of the first substrate; and forming a metal interconnect structure on a surface of the dielectric layer facing away from the first substrate.

[0098] Step S102: forming a first through hole, wherein the first through hole extends from at least the first surface of the first substrate into the dielectric layer; the first through hole penetrates at least the first substrate and a portion of the dielectric layer;

[0099] Step S103: forming a first protective material layer covering at least the sidewalls and bottom surface of the first through hole;

[0100] Step S104: forming a second protective material layer covering the first protective material layer;

[0101] Step S105: performing a first etching process to remove at least the second protective material layer covering the bottom surface of the first through hole to form a second protective layer;

[0102] Step S106: performing a second etching process to remove at least the first protective material layer covering the bottom surface of the first through hole to form a first protective layer, and to remove the dielectric layer exposed by the first through hole to form a second through hole, wherein the second through hole is located within the dielectric layer and exposes a portion of the metal interconnect structure; wherein the first protective layer covers the sidewalls of the first through hole, the second protective layer covers a portion of the surface of the first protective layer facing away from the sidewalls of the first through hole, and a portion of the first protective layer also covers a surface of the second protective layer facing away from the first surface; and a portion of the dielectric layer surrounding the second through hole covers a surface of the first protective layer facing away from the first surface;

[0103] Step S107 : forming a conductive layer, wherein the conductive layer at least fills the first through hole and the second through hole and is electrically connected to the metal interconnection structure.

[0104] The manufacturing method provided by the present disclosure is described in detail below with reference to the accompanying drawings.

[0105] First, execute step S101, as Figure 5 As shown, a first semiconductor structure 10 is provided, and providing the first semiconductor structure 10 includes: providing a first substrate 11, the first substrate 11 having a first surface 111 and a second surface 112 opposite to the first surface 111; forming a dielectric layer 12 on the second surface 112 of the first substrate 11; and forming a metal interconnection structure 13 on the surface of the dielectric layer 12 facing away from the first substrate 11.

[0106] The material of the first substrate 11 is as described above and will not be repeated here.

[0107] In actual operation, the first surface 111 can be the back side of the first substrate 11, and the second surface 112 can be the front side of the first substrate 11. Transistors, word lines, bit lines, capacitors and other device structures (not shown) can also be formed on the second surface 112 of the first substrate 11, and the dielectric layer 12 can cover these device structures.

[0108] In actual operation, the dielectric layer 12 may be a multi-layer structure, and may be formed from multiple layers of insulating materials in multiple process steps. The material of the dielectric layer 12 includes but is not limited to oxides, such as silicon oxide.

[0109] In actual operation, multiple metal layers and conductive plugs for connecting two adjacent metal layers can be formed in the dielectric layer 12. The metal interconnection structure 13 can also be electrically connected to the metal layer located in the dielectric layer 12 through the conductive plug, and then electrically connected to the device structure located on the first substrate 11.

[0110] In actual operation, the material of the metal interconnect structure 13 may include tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag) and other materials or any other combination.

[0111] See again Figure 5 In some embodiments, a first semiconductor structure 10 is provided, further comprising: forming a dielectric layer 14 on the first surface 111 of the first substrate 11. In practice, the material of the dielectric layer 14 may include, but is not limited to, an oxide, such as silicon oxide. The dielectric layer 14 may be used to protect the first surface 111 of the first substrate 11 during subsequent processes.

[0112] Next, execute step S102, as shown in FIG. Figure 7 As shown, a first through hole 151 is formed. The first through hole 151 extends at least from the first surface 111 of the first substrate 11 to the dielectric layer 12 . The first through hole 151 at least penetrates the first substrate 11 and a portion of the dielectric layer 12 .

[0113] like Figure 6 As shown, in some embodiments, before forming the first through hole 151, the method further includes:

[0114] A second semiconductor structure 20 is provided, and the second semiconductor structure 20 is bonded to a side of the metal interconnect structure 13 in the first semiconductor structure 10 facing away from the first surface 111 .

[0115] In actual operation, the first semiconductor structure 10 and the second semiconductor structure 20 can be a wafer containing multiple chips, and the first semiconductor structure 10 and the second semiconductor structure 20 can be bonded together by hybrid bonding. Specifically, the second semiconductor structure 20 may include a second substrate (not shown), an interlayer dielectric layer (not shown) located on the second substrate, and an interconnect structure (not shown) located on the side of the interlayer dielectric layer facing away from the second substrate. The interconnect structure of the second semiconductor structure 20 can be bonded to the metal interconnect structure 13 of the first semiconductor structure 10. However, the present invention is not limited to this. The interconnect structure of the second semiconductor structure 20 and the metal interconnect structure 13 of the first semiconductor structure 10 can also be bonded to each other through conductive bumps.

[0116] In the embodiment of the present disclosure, after bonding the first semiconductor structure 10 and the second semiconductor structure 20, etching can be performed from a side surface of the first semiconductor structure 10 facing away from the second semiconductor structure 20 in a direction toward the second semiconductor structure 20 to form a first through hole 151. That is, the first through hole 151 in the embodiment of the present disclosure can be formed by adopting a through-via last (TSV Last) process, and the manufacturing method provided by the present disclosure can be applied to the through-via last (TSV Last) process.

[0117] In actual operation, a patterned mask layer (not shown) may be formed on the dielectric layer 14 . The material of the patterned mask layer may be photoresist. The dielectric layer 14 , the first substrate 11 and the dielectric layer 12 are then etched using the patterned mask layer as a mask to form the first through hole 151 .

[0118] like Figure 7 As shown, in some embodiments, the first through hole 151 may further penetrate the dielectric layer 14 , and a portion of the dielectric layer 12 may remain at the bottom of the first through hole 151 and not be removed.

[0119] In some embodiments, after forming the first through hole 151, the minimum thickness of the remaining dielectric layer 12 is in the range of 100 nm to 300 nm (including the end points), such as 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc. That is, after forming the first through hole 151, the thickness of the dielectric layer 12 located at the bottom of the first through hole 151 that is not removed is in the range of 100 nm to 300 nm. By retaining a portion of the dielectric layer 12 at the bottom of the first through hole 151, the metal interconnect structure 13 can be protected during the formation of the first through hole 151 and the subsequent first etching process. By controlling the thickness within the above range, a long etching time is avoided in the subsequent second etching process for etching the dielectric layer 12, thereby reducing the damage to the first protective material layer 161' (see Figure 8 ) loss.

[0120] In some embodiments, the orthographic projection of the first through hole 151 on the plane of the first substrate 11 can fall within the orthographic projection range of the metal interconnection structure 13 on the plane of the first substrate 11. In subsequent processes, etching can continue downward from the bottom of the first through hole 151 to expose part of the metal interconnection structure 13.

[0121] Next, execute step S103, as shown in FIG. Figure 8 As shown, a first protection material layer 161 ′ is formed to cover at least the sidewalls and bottom surface of the first through hole 151 .

[0122] In some embodiments, a portion of the first protective material layer 161 ′ may also be located on the first surface 111 and cover a surface of the dielectric layer 14 facing away from the first substrate 11 .

[0123] In practice, the material of the first protective material layer 161' may include, but is not limited to, oxides, such as silicon oxide. The first protective material layer 161' may be conformally formed on the inner surface of the first through hole 151 and the surface of the dielectric layer 14 using one or a combination of processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0124] The first protective material layer 161' can be used to electrically isolate the first substrate 11 from the subsequently formed conductive layer 17 (see Figure 1 ), to avoid dielectric breakdown. In some embodiments, the thickness of the formed first protective material layer 161' ranges from 150nm to 250nm (including the endpoint values), for example, 150nm, 200nm, 250nm, etc. By controlling the thickness of the first protective material layer 161' within the above range, the electrical isolation effect of the first protective material layer 161' can be improved, and the dielectric breakdown phenomenon can be avoided. At the same time, the thickness of the first protective material layer 161' is avoided to be too large, resulting in a small bottom opening of the space defined by the first protective material layer 161' in the first through hole 151, which cannot meet the design requirements.

[0125] Next, execute step S104, as shown in FIG. Figure 9 As shown, a second protection material layer 162 ′ is formed to cover the first protection material layer 161 ′.

[0126] In actual operation, the material of the second protective material layer 162' is different from that of the first protective material layer 161', and the material of the second protective material layer 162' can be an insulating material. The material of the second protective material layer 162' can include one or a combination of nitrides (e.g., silicon nitride), carbonitrides (e.g., silicon carbonitride), and oxynitrides (e.g., silicon oxynitride). However, the material of the second protective material layer 162' can also be a diffusion barrier material, such as one or a combination of tantalum, titanium, tantalum nitride, and titanium nitride.

[0127] In actual operation, one or a combination of processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, and evaporation can be used to conformally form the second protective material layer 162' on the surface of the first protective material layer 161'.

[0128] In some embodiments, the ratio of the thickness of the first protective material layer 161' to the thickness of the second protective material layer 162' is in a range of 1.5 to 5 (inclusive), for example, 1.5, 3, 4, 5, etc. By controlling the ratio within this range, the second protective material layer 162' can protect the first protective material layer 161' while also preventing the second protective material layer 162' from being too thick, which would result in a smaller bottom opening of the space defined by the second protective material layer 162' within the first through hole 151 and fail to meet design requirements.

[0129] In some embodiments, the thickness of the second protection material layer 162 ′ ranges from 50 nm to 100 nm (inclusive), such as 50 nm, 60 nm, 80 nm, 100 nm, etc.

[0130] Next, execute step S105, as shown in FIG. Figure 10 As shown, a first etching process is performed to remove at least the second protection material layer 162 ′ covering the bottom surface of the first through hole 151 to form a second protection layer 162 .

[0131] In some embodiments, during the first etching process, the second protection material layer 162 ′ on the first surface 111 is removed, and the remaining second protection material layer 162 ′ (ie, the second protection layer 162 ) is located on the sidewall of the first through hole 151 .

[0132] In some embodiments, after performing the first etching process, part of the second protective material layer 162' located at the opening of the first through hole 151 is removed, that is, during the execution of the first etching process, the second protective material layer 162' located at the opening of the first through hole 151 will be partially lost. After performing the first etching process, the thickness of the second protective material layer 162' located at the opening of the first through hole 151 is less than the thickness of the second protective material layer 162' located at other positions. The remaining second protective material layer 162' located at the opening of the first through hole 151 still covers the first protective material layer 161' located at the opening of the first through hole 151, and is used to protect the first protective material layer 161' in subsequent processes.

[0133] In some embodiments, in the step of performing the first etching process, the etching selectivity ratio of the second protective material layer 162' and the first protective material layer 161' is greater than or equal to 5, for example, 5, 10, 20, 50, etc., thereby avoiding or reducing damage to the first protective material layer 161' during the etching process of the second protective material layer 162'.

[0134] Then, execute step S106, as shown in FIG. Figure 11 As shown, a second etching process is performed to remove at least the first protective material layer 161' covering the bottom surface of the first through hole 151 to form a first protective layer 161, and to remove the dielectric layer 12 exposed by the first through hole S1 to form a second through hole 152, the second through hole 152 is located in the dielectric layer 12 and exposes a portion of the metal interconnect structure 13; wherein, the first protective layer 161 covers the sidewalls of the first through hole 151, the second protective layer 162 covers a portion of the surface of the first protective layer 161 away from the sidewalls of the first through hole 151, and a portion of the first protective layer 161 also covers a surface of the second protective layer 162 away from the first surface 111; a portion of the dielectric layer 12 surrounding the second through hole 152 covers a surface of the first protective layer 161 away from the first surface 111.

[0135] See again Figure 11 In some embodiments, during the second etching process, the first protection material layer 161 ′ on the first surface 111 is removed, and the remaining first protection material layer 161 ′ (ie, the first protection layer 161 ) is located within the first through hole 151 .

[0136] In actual operation, the embodiment of the present disclosure first removes the second protective material layer 162' covering the bottom surface of the first through hole 151 to expose a portion of the first protective material layer 161' covering the bottom surface of the first through hole 151, then removes the exposed portion of the first protective material layer 161' covering the bottom surface of the first through hole 151 to expose a portion of the dielectric layer 12, and removes the exposed portion of the dielectric layer 12 to expose a portion of the metal connection structure 13.

[0137] In the embodiment of the present disclosure, a second protective layer 162 is formed before performing the second etching process. Under the protective effect of the second protective layer 162, a portion of the first protective layer 161 located on the side of the second protective layer 162 away from the first surface 111 is retained, and the retained portion of the first protective layer 161 covers the surface of the second protective layer 162 away from the first surface 111. Under the protective effect of the first protective layer 161 and the second protective layer 162, a portion of the dielectric layer 12 located on the side of the first protective layer 161 away from the first surface 111 is retained. The retained portion of the dielectric layer 12 surrounds the second through hole 152 and covers the surface of the first protective layer 161 away from the first surface 111.

[0138] At the same time, in the embodiment of the present disclosure, by forming a second protective material layer 162' covering the first protective material layer 161' before performing the second etching process, after performing the first etching process, the portion of the second protective layer 162 located at the opening of the first through hole 151 protects the portion of the first protective material layer 161' located at the opening of the first through hole 151. In this way, during the execution of the second etching process, the etching of the first protective material layer 161' located at the opening of the first through hole 151 is avoided or reduced, thereby avoiding or reducing the loss of the first protective material layer 161' located at the opening of the first through hole 151, and avoiding the dielectric breakdown phenomenon caused by the excessively small thickness of the first protective layer 161.

[0139] In some embodiments, in the step of performing the second etching process, the etching selectivity ratio of the first protective material layer 161' and the second protective material layer 162' can be greater than or equal to 5, for example, 5, 10, 20, 50, etc., so as to avoid or reduce the damage to the second protective layer 162 during the execution of the second etching process, thereby increasing the protective effect of the second protective layer 162 on the first protective material layer 161'.

[0140] In some embodiments, after performing the second etching process, the thickness of the second protective layer 162 located at the opening of the first through hole 151 may be greater than or equal to zero, and may be less than the thickness of the second protective layer 162 located at other positions of the first through hole 151; and the thickness of the first protective layer 161 located at the opening of the first through hole 151 may be less than, equal to, or substantially equal to the thickness of the first protective layer 161 located at other positions of the first through hole 151, and the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 may be within a preset range, for example, the difference is less than or equal to 50nm, for example, 0, 10nm, 20nm, 30nm, 40nm, 50nm, etc.

[0141] Specifically, such as Figure 11As shown, in some embodiments of the present disclosure, after the second etching process is performed, the thickness of the second protective layer 162 located at the opening of the first through-hole 151 is greater than zero, and the thickness of the first protective layer 161 located at the opening of the first through-hole 151 can be equal to or substantially equal to the thickness of the first protective layer 161 located at other positions of the first through-hole 151. It can be understood that the thickness of the second protective layer 162 located at the opening of the first through-hole 151 is greater than zero, that is, the second protective layer 162 located at the opening of the first through-hole 151 is not completely consumed, and it has a sufficient protective effect on the first protective layer 161 located at the opening of the first through-hole 151. Therefore, during the execution of the second etching process, the first protective layer 161 located at the first through-hole 151 will not be damaged, thereby further avoiding the occurrence of dielectric breakdown.

[0142] But not limited to this, such as Figure 13 and Figure 14 As shown, in some other embodiments of the present disclosure, after performing the second etching process, the second protective layer 162 located at the opening of the first through hole 151 can also be completely consumed to expose the first protective layer 161 located at the opening of the first through hole 151, that is, the thickness of the second protective layer 162 located at the opening of the first through hole 151 can be equal to zero, and the first protective layer 161 located at the opening of the first through hole 151 can be not consumed or partially consumed.

[0143] In some embodiments, after performing the second etching process, the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, and the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 is less than or equal to 50nm, for example, 0, 10nm, 20nm, 30nm, 40nm, 50nm, etc.

[0144] Specifically, such as Figure 13 As shown, after performing the second etching process, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the first protective layer 161 located at the opening of the first through hole 151 may not be lost, and the thickness of the first protective layer 161 located at the opening of the first through hole 151 may be equal to or substantially equal to the thickness of the first protective layer 161 located at other positions of the first through hole 151.

[0145] But not limited to this, such as Figure 14As shown, in some other embodiments of the present disclosure, after performing the second etching process, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the first protective layer 161 located at the opening of the first through hole 151 can be partially etched, and the thickness of the first protective layer 161 located at the opening of the first through hole 151 can be less than the thickness of the first protective layer 161 located at other positions of the first through hole 151, and the difference between the thickness of the first protective layer 161 located at the opening of the first through hole 151 and the thickness of the first protective layer 161 located at other positions of the first through hole 151 is less than or equal to 50nm, for example, 1nm, 10nm, 20nm, 30nm, 40nm, 50nm, etc.

[0146] Thus, in the embodiment of the present disclosure, through the protective effect of the second protective layer 162, the difference between the thickness of the first protective layer 161 at the opening of the first through hole 151 and the thickness of the first protective layer 161 at other positions of the first through hole 151 is within a preset range, thereby avoiding the dielectric breakdown phenomenon caused by the thin thickness of the first protective layer 161.

[0147] Next, execute step S107, as shown in FIG. Figure 12 as well as Figure 1 As shown, a conductive layer 17 is formed. The conductive layer 17 at least fills the first through hole 151 and the second through hole 152 and is electrically connected to the metal interconnection structure 13 .

[0148] Conductive layer 17 is used to transmit electrical signals. In some embodiments, forming conductive layer 17 includes forming a diffusion barrier layer 171 and a conductive material layer 172. Diffusion barrier layer 171 covers at least the sidewalls of second protective layer 162, the sidewalls of first protective layer 161 on the side of second protective layer 162 facing away from first surface 111, and the sidewalls and bottom surface of second through hole 152. Conductive material layer 172 covers diffusion barrier layer 171 and fills first through hole 151 and second through hole 152. Diffusion barrier layer 171 and conductive material layer 172 together constitute conductive layer 17, which is electrically connected to metal interconnect structure 13.

[0149] Specifically, you can first Figure 12 As shown, after the second through hole 152 is formed, a barrier material layer 171' is conformally formed on the inner walls of the first through hole 151 and the second through hole 152 and on the surface of the dielectric layer 14 away from the first surface 111, and a main material layer 172' is formed to cover the barrier material layer 171' and fill the first through hole 151 and the second through hole 152; then a planarization process can be used to remove the barrier material layer 171' and the main material layer 172' located on the surface of the dielectric layer 14 away from the first surface 111 to form a diffusion barrier layer 171 and a conductive material layer 172, respectively, to form a structure as shown in FIG. Figure 1 The structure shown.

[0150] In actual operation, the barrier material layer 171' and the main material layer 172' can be formed by using one or a combination of processes such as chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, chemical plating, sputtering, evaporation, etc.

[0151] In actual operation, the material of the diffusion barrier layer 171 may include one or a combination of tungsten, titanium, tungsten nitride, titanium nitride, etc., which is used to prevent the material of the conductive material layer 172 from diffusing into the first protective layer 161 and the first substrate 11; the material of the conductive material layer 172 may include tungsten (W), copper (Cu), nickel (Ni), tin (Sn), chromium (Cr), gold (Au), silver (Ag), metal silicide, metal alloy or any combination thereof, such as copper.

[0152] In some embodiments, when the material of the second protective layer 162 includes a diffusion barrier material, the second protective layer 162 can also serve to block the material of the conductive material layer 172 from diffusing into the first protective layer 161 and the first substrate 11. Therefore, compared with the case where the material of the second protective layer 162 includes an insulating material, when the material of the second protective layer 162 includes a diffusion barrier material, the thickness of the diffusion barrier layer 171 can be smaller.

[0153] In some embodiments, it is also possible to Figure 13 The structure shown is executed as Figure 12 and Figure 1 The steps shown are to form Figure 2 In other embodiments, the semiconductor structure shown in FIG. Figure 14 The structure shown is executed as Figure 12 and Figure 1 The steps shown are to form Figure 3 The semiconductor structure shown.

[0154] like Figure 2 and Figure 3 As shown, in other embodiments of the present disclosure, when the thickness of the second protective layer 162 located at the opening of the first through hole 151 is equal to zero, the first protective layer 161 located at the opening of the first through hole 151 is exposed by the second protective layer 162, and the diffusion barrier layer 171 can also cover the side wall of the first protective layer 161 located at the opening of the first through hole 151 facing away from the first through hole 151, and the surface of the second protective layer 162 facing the first surface 111.

[0155] The various technical features in the technical solutions described in the various embodiments may be arbitrarily combined unless they conflict. Those skilled in the art will be able to change the order of the steps in the above-mentioned formation method without departing from the scope of protection of this disclosure. The various steps in the embodiments of this disclosure may be performed simultaneously or sequentially unless they conflict.

[0156] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: A first semiconductor structure, wherein The first semiconductor structure comprises: a first substrate having a first surface; a first through hole and a conductive layer at least filling the first through hole, wherein the first through hole extends at least from the first surface toward the interior of the first substrate and at least penetrates the first substrate; a first protection layer, covering the sidewall of the first through hole and located between the sidewall of the first through hole and the conductive layer; The second protective layer is located between the first protective layer and the conductive layer, and a portion of the first protective layer also covers a surface of the second protective layer facing away from the first surface.

2. The semiconductor structure according to claim 1, wherein: The thickness of the second protective layer located at the opening of the first through hole is greater than or equal to zero, and is less than the thickness of the second protective layer located at other positions of the first through hole; the difference between the thickness of the first protective layer located at the opening of the first through hole and the thickness of the first protective layer located at other positions of the first through hole is within a preset range.

3. The semiconductor structure according to claim 2, wherein: When the thickness of the second protective layer at the opening of the first through hole is greater than zero, the thickness of the first protective layer at the opening of the first through hole is equal to or substantially equal to the thickness of the first protective layer at other positions of the first through hole.

4. The semiconductor structure according to claim 2, wherein: When the thickness of the second protective layer at the opening of the first through hole is zero, the difference between the thickness of the first protective layer at the opening of the first through hole and the thickness of the first protective layer at other positions of the first through hole is less than or equal to 50 nm.

5. The semiconductor structure according to any one of claims 2 to 4, characterized in that a ratio of a thickness of the first protective layer at other locations of the first through hole to a thickness of the second protective layer at other locations of the first through hole is in a range of 1.5 to 5; and / or, The thickness of the first protection layer at other positions of the first through hole ranges from 150 nm to 250 nm. The semiconductor structure according to claim 1 , wherein: The first substrate further includes a second surface opposite to the first surface, and the first semiconductor structure further includes: a dielectric layer located on the second surface of the first substrate, wherein the first through hole extends into the dielectric layer and penetrates a portion of the dielectric layer; a metal interconnect structure, located on a surface of the dielectric layer facing away from the first substrate; A second through hole is located in the dielectric layer and extends from the bottom of the first through hole to the metal interconnection structure. The portion of the dielectric layer surrounding the second through hole covers the surface of the first protective layer facing away from the first surface. The conductive layer also fills the second through hole and is electrically connected to the metal interconnection structure.

7. The semiconductor structure according to claim 6, wherein: The thickness of the dielectric layer covering the surface of the first protective layer facing away from the first surface is in a range from 100 nm to 300 nm; and / or, The conductive layer includes a diffusion barrier layer and a conductive material layer, the diffusion barrier layer at least covers the side walls of the second protective layer, the side walls of the first protective layer located on the side of the second protective layer away from the first surface, and the side walls and bottom surface of the second through hole, and the conductive material layer covers the diffusion barrier layer and fills the first through hole and the second through hole.

8. The semiconductor structure according to claim 6 or 7, characterized in that: The semiconductor structure further includes a second semiconductor structure bonded to a side of the metal interconnect structure in the first semiconductor structure facing away from the first surface.

9. A method for manufacturing a semiconductor structure, characterized in that: Providing a first semiconductor structure, the providing the first semiconductor structure comprising: providing a first substrate, the first substrate having a first surface and a second surface opposite to the first surface; forming a dielectric layer on the second surface of the first substrate; and forming a metal interconnect structure on a surface of the dielectric layer facing away from the first substrate; forming a first through hole, wherein the first through hole extends from at least the first surface of the first substrate into the dielectric layer; the first through hole penetrates at least the first substrate and a portion of the dielectric layer; forming a first protective material layer covering at least the sidewalls and bottom surface of the first through hole; forming a second protective material layer covering the first protective material layer; performing a first etching process to remove at least the second protective material layer covering the bottom surface of the first through hole to form a second protective layer; performing a second etching process to remove at least the first protective material layer covering the bottom surface of the first through-hole to form a first protective layer, and to remove the dielectric layer exposed by the first through-hole to form a second through-hole, wherein the second through-hole is located within the dielectric layer and exposes a portion of the metal interconnect structure; wherein the first protective layer covers the sidewalls of the first through-hole, the second protective layer covers a portion of the surface of the first protective layer facing away from the sidewalls of the first through-hole, and a portion of the first protective layer also covers a surface of the second protective layer facing away from the first surface; and a portion of the dielectric layer surrounding the second through-hole covers a surface of the first protective layer facing away from the first surface; A conductive layer is formed, where the conductive layer at least fills the first through hole and the second through hole and is electrically connected to the metal interconnection structure.

10. The manufacturing method according to claim 9, characterized in that: In the step of performing the first etching process, an etching selectivity ratio of the second protective material layer to the first protective material layer is greater than or equal to 5; In the step of performing the second etching process, an etching selectivity ratio between the first protection material layer and the second protection material layer is greater than or equal to 5.

11. The manufacturing method according to claim 9, characterized in that: After performing the first etching process, a portion of the second protection material layer located at the opening of the first through hole is removed; After performing the second etching process, the thickness of the second protective layer located at the opening of the first through hole is greater than or equal to zero, and is less than the thickness of the second protective layer located at other positions of the first through hole; the thickness of the first protective layer located at the opening of the first through hole, and the difference between the thickness of the first protective layer located at other positions of the first through hole are within a preset range.

12. The manufacturing method according to claim 11, characterized in that: After performing the second etching process, the thickness of the second protective layer located at the first through-hole opening is greater than zero, and the thickness of the first protective layer located at the first through-hole opening is equal to or substantially equal to the thickness of the first protective layer located at other positions of the first through-hole.

13. The manufacturing method according to claim 11, characterized in that: After performing the second etching process, the thickness of the second protective layer located at the opening of the first through hole is equal to zero, and the difference between the thickness of the first protective layer located at the opening of the first through hole and the thickness of the first protective layer located at other positions of the first through hole is less than or equal to 50nm.

14. The manufacturing method according to claim 9, characterized in that After forming the first through hole, the minimum thickness of the remaining dielectric layer ranges from 100 nm to 300 nm; and / or, The thickness of the formed first protective material layer is in a range from 150 nm to 250 nm.

15. The manufacturing method according to any one of claims 9 to 14, characterized in that: Before forming the first through hole, the method further includes: A second semiconductor structure is provided, and the second semiconductor structure is bonded to a side of the metal interconnection structure in the first semiconductor structure facing away from the first surface.

16. The manufacturing method according to any one of claims 9 to 14, characterized in that: The forming of the conductive layer includes: forming a diffusion barrier layer and a conductive material layer, the diffusion barrier layer at least covering the sidewalls of the second protective layer, the sidewalls of the first protective layer located on the side of the second protective layer facing away from the first surface, and the sidewalls and bottom surface of the second through hole, the conductive material layer covering the diffusion barrier layer and filling the first through hole and the second through hole, the diffusion barrier layer and the conductive material layer together constitute the conductive layer, and the conductive layer is electrically connected to the metal interconnection structure.

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