Overcurrent protection circuit and display panel

Abstract

This application discloses an overcurrent protection circuit and a display panel. The overcurrent protection circuit includes: a power supply module for providing power voltage to a load; a current detection module disposed between the power supply module and the load for sampling whether the current output from the power supply module to the load exceeds a set threshold; and a first state latching module connected to the power supply module through the current detection module for controlling the power supply module to lock in a disconnected state when the current detection module detects that the current exceeds the set threshold. This circuit achieves low-cost overcurrent protection.

Description

Technical Field

[0001] This invention relates to the field of display panels, and in particular to overcurrent protection circuits and display panels. Background Technology

[0002] In the TFT-LCD field, L-Drivers (Source Driver ICs with integrated Level Shift functionality) are already in mass production for lower-cost notebook screens, offering a significant cost advantage. However, due to cost and size considerations, the Level Shift functionality within the L-Driver cannot incorporate OCP (overcurrent protection) functionality.

[0003] The overcurrent protection threshold of the voltage source is often too high. In the event of a short circuit in the panel, it is difficult to trigger the overcurrent protection function of the voltage source, which can easily cause the short circuit point of the panel to overheat or even cause a fire. Summary of the Invention

[0004] The main technical problem solved by this application is to provide an overcurrent protection circuit and display panel that achieves low-cost overcurrent protection and provides an effective protection mechanism when an overcurrent occurs within the panel.

[0005] To address the aforementioned problems, this application provides an overcurrent protection circuit in a first aspect. The overcurrent protection circuit includes a power supply module for providing a power supply voltage to a load; a current detection module disposed between the power supply module and the load for sampling whether the current output from the power supply module to the load exceeds a set threshold; and a first state latch module connected to the power supply module via the current detection module for controlling the power supply module to lock in a disconnected state when the current detection module detects that the current exceeds the set threshold.

[0006] The first state latching module includes: a switching unit disposed between the power supply module and the load, used to control the on / off state of the power supply module and the load; and a latching control unit connected to both the current detection module and the switching unit, used to control the on / off state of the switching unit based on the current detected by the current detection module.

[0007] The switching unit includes a first MOS transistor, whose gate is connected to the latch control unit, its source is connected to the power module, and its drain is connected to the load; wherein the first MOS transistor is a PMOS transistor.

[0008] The current detection module includes a sampling resistor, one end of which is connected to the power supply module, and the other end of which is connected to the load. The latch control unit includes a first transistor and a second transistor. The base of the first transistor is connected to the other end of the sampling resistor, the emitter of the first transistor is connected to one end of the sampling resistor and the power supply module, and the collector of the first transistor is connected to the base of the second transistor. The base of the second transistor is connected to the collector of the first transistor, and the base of the second transistor is also grounded. The emitter of the second transistor is grounded and connected to the gate of the first MOSFET. The collector of the second transistor is connected to the power supply module and the source of the first MOSFET.

[0009] The first state latch module further includes a timing and pulse counting unit, which is located between the current detection module and the latch control unit of the first state latch module, and is used to control the operation of the first state latch module after the current continues for a certain period of time or the number of pulses exceeds a certain number.

[0010] The timing and pulse counting module includes a storage capacitor and a first diode. The first plate of the storage capacitor is connected to the collector of the first transistor and the base of the second transistor, and the second plate of the storage capacitor is grounded to store the accumulated charge from the first transistor to the base of the second transistor. The anode of the first diode is connected to the collector of the first transistor, and the cathode of the first diode is connected to the first plate of the storage capacitor and the base of the second transistor to prevent charge loss from the storage capacitor.

[0011] The overcurrent protection circuit further includes a control module connected to the control terminal of the current detection module; the current detection module includes a second MOSFET, and the control module is connected to the gate of the second MOSFET. The voltage output by the control module controls the resistance of the second MOSFET, thereby adjusting the current protection threshold in the circuit.

[0012] The overcurrent protection circuit further includes: a second state latch module, connected to the first state latch module and the power supply module, for receiving feedback signals from the first state latch module and controlling the output of the power supply module according to the feedback signals; and a control module, connected to the first state latch module and the second state latch module, for receiving feedback signals from the first state latch module and providing reset signals to the first state latch module and the second state latch module according to the feedback signals, so that the first state latch module and the second state latch module return to their working state.

[0013] The first state latch module further includes a first reset unit, which is connected to the base of the second transistor and is used to reset the first state latch module. The first reset unit includes a third MOSFET connected to the base of the second transistor. The gate of the third MOSFET is connected to the control module, the source of the third MOSFET is connected to the base of the second transistor, and the drain is grounded. This third MOSFET is used to discharge the base of the second transistor when the control module outputs a first reset signal, thereby turning off the second transistor and turning on the first switching module. The first reset unit also includes a protection resistor, through which the drain of the third MOSFET is grounded to protect the third MOSFET.

[0014] To address the aforementioned problems, this application provides a display panel in a second aspect, wherein the display panel includes the overcurrent protection circuit described in any embodiment of the first aspect.

[0015] The beneficial effects of this application are: by connecting a current detection module and a first state latching module in series between the power module and the load, the magnitude of the current in the path can be detected. When an overcurrent occurs, the circuit connection with the load is disconnected through the first state latching module to avoid overheating of the panel short circuit point or causing a fire. In addition, the disconnected state is locked under no special circumstances to avoid the circuit triggering repeated on / off situations. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A schematic diagram of the structure of the first embodiment of the overcurrent protection circuit provided in this application;

[0018] Figure 2 A schematic diagram of the circuit structure of the first embodiment of the overcurrent protection circuit provided in this application;

[0019] Figure 3 for Figure 2 Workflow diagram in the document;

[0020] Figure 4 A schematic diagram of the structure of the second embodiment of the overcurrent protection circuit provided in this application;

[0021] Figure 5 A schematic diagram of the circuit structure of the second embodiment of the overcurrent protection circuit provided in this application;

[0022] Figure 6 for Figure 5 Workflow diagram of the initial state and when OCP is not triggered;

[0023] Figure 7 The waveform of the load current when a pulse overcurrent occurs;

[0024] Figure 8 for Figure 5 Workflow diagram of OCP triggered by medium pulse overcurrent;

[0025] Figure 9 A schematic diagram of the structure of the third embodiment of the overcurrent protection circuit provided in this application;

[0026] Figure 10 A graph showing the resistance of a MOSFET as a function of gate voltage and drain current, provided in this application.

[0027] Figure 11 A schematic diagram of the circuit structure of the third embodiment of the overcurrent protection circuit provided in this application;

[0028] Figure 12 A schematic diagram of the structure of the fourth embodiment of the overcurrent protection circuit provided in this application;

[0029] Figure 13 A circuit structure diagram of a specific embodiment of the first state latch module provided in this application;

[0030] Figure 14 A circuit structure diagram of a specific embodiment of the second state latch module provided in this application;

[0031] Figure 15 This is a schematic diagram of the structure of a specific embodiment of the control module provided in this application;

[0032] Figure 16 for Figure 14 The state locking diagram of the second state latch module triggering the normal working state;

[0033] Figure 17 for Figure 14 The state locking diagram of the second state latching module triggering the overcurrent protection state.

[0034] Symbol explanation:

[0035] 11 Power supply module; 12 Current detection module; 13 First state latch module; 131 Switching unit; 132 Latch control unit; 133 Timing and pulse counting unit; 134 First reset unit; 14 Regulation module; 15 Second state latch module; 16 Control module.

[0036] Q1 is the first MOSFET; Rsense is the sampling resistor; Q2 is the first transistor; Q3 is the second transistor; Q8 is the third MOSFET; Q4 is the second MOSFET; Q7 is the fourth MOSFET; Q6 is the third transistor; Q5 is the fourth transistor; D1 is the first diode; D2 is the second diode.

[0037] C1 is the first capacitor; C2 is the second capacitor / storage capacitor; C3 is the third capacitor; C4 is the fourth capacitor.

[0038] R1 is the first resistor; R2 is the second resistor; R3 is the third resistor; R4 is the fourth resistor; R5 is the fifth resistor; R12 is the protection resistor; R6 is the sixth resistor; R7 is the seventh resistor; R8 is the eighth resistor; R9 is the ninth resistor; R10 is the tenth resistor; R11 is the eleventh resistor. Detailed Implementation

[0039] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. The singular forms “a,” “said,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless otherwise clearly indicated above. “Multiple” generally includes at least two, but does not exclude the inclusion of at least one.

[0041] It should be understood that the term "and / or" used herein is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Furthermore, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship. The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0042] It should be understood that the terms "comprising," "including," or any other variations used herein are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0043] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0044] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in every place in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0045] This application provides an overcurrent protection circuit. The overcurrent protection circuit is connected to a load to supply power to the load and disconnects the power supply path to the load when an overcurrent occurs, thereby protecting the load and preventing overheating and device burnout due to a short circuit. Please refer to the following for details. Figure 1 , Figure 1 This is a schematic diagram of the structure of the first embodiment of the overcurrent protection circuit provided in this application. The overcurrent protection circuit includes: a power supply module 11 connected to the load, a current detection module 12, and a first state latching module 13.

[0046] The power supply module 11 is connected to the load and is used to provide power voltage to the load. The current detection module 12 is disposed between the power supply module 11 and the load and is used to sample whether the current output from the power supply module 11 to the load exceeds a set threshold. The first state latch module 13 is connected to the current detection module 12 and is used to control the power supply module 11 to maintain (lock) the disconnected state between the load and the load when the current detection module 12 detects that the current exceeds the set threshold.

[0047] In this embodiment, the current detection module 12 collects the current output from the power module 11 to the load, and outputs a control signal when the current value exceeds a set threshold to control the first state latch module 13 to disconnect the circuit connection between the power module 11 and the load, and keeps the circuit between the power module 11 and the load in an open state without control, thereby avoiding overheating of the panel short circuit point or causing a fire.

[0048] It can be understood that the load can be the panel, or it can be the driver that powers the panel or the L-Driver (source driver), etc.

[0049] Specifically, the first state latching module 13 includes a switching unit 131, which is disposed between the power module 11 and the load, and is used to control the on / off connection between the power module 11 and the load. Figure 2 As shown.

[0050] The first state latch module 13 also includes a latch control unit 132, which is connected to the current detection module 12 and the switching unit 131 respectively. It is used to output a control signal (including a voltage control signal) according to the current value detected by the current detection module 12, and use the control signal to control the switching unit 131 to turn on and off, thereby controlling the circuit connection between the power supply module 11 and the load.

[0051] Please refer to the details. Figure 2 , Figure 2 This is a schematic diagram of the circuit structure of the first embodiment of the overcurrent protection circuit provided in this application. Figure 2 As shown, the overcurrent protection circuit includes an input terminal Vin and an output terminal Vout. The input terminal Vin is connected to the power supply output terminal, and the output terminal Vout is the input terminal of the load and is connected to the load.

[0052] The switching unit 131 includes a first MOSFET Q1. The gate of the first MOSFET Q1 is connected to the latch control unit 132, the source is connected to the input terminal Vin, and the drain is connected to the output terminal Vout. The first MOSFET Q1 is a PMOS transistor, that is, a P-channel MOSFET.

[0053] The current detection module 12 includes a sampling resistor Rsense, which is positioned between the input terminal Vin and the output terminal Vout. One end of the sampling resistor Rsense is connected to the input terminal Vin, and the other end is connected to the output terminal Vout through the first MOSFET Q1.

[0054] The latch control unit 132 includes a first transistor Q2 and a second transistor Q3. The base of the first transistor Q2 is connected to the other end of the sampling resistor Rsense, its emitter is connected to the input terminal Vin and the sampling resistor Rsense, and its collector is connected to the base of the second transistor Q3. It is used to control whether a control signal (voltage signal) is sent to the base of the second transistor Q3 based on the magnitude of the current in the sampling resistor Rsense. Specifically, when the current in the sampling resistor Rsense is too large, and the voltage difference across Rsense is greater than 0.7V (which is greater than the forward voltage between the base and emitter of the first transistor Q2), the first transistor Q2 turns on, and the voltage signal from the power module is transmitted to the base of the second transistor Q3, thereby controlling the on / off state of the second transistor Q3.

[0055] The base of the second transistor Q3 is connected to the collector of the first transistor Q2 through a resistor. The base of the second transistor Q3 is also grounded through a resistor, and the emitter of the second transistor Q3 is grounded through a resistor. This ensures that when the first transistor Q2 is not conducting, both the base and emitter of the second transistor Q3 are grounded, keeping the second transistor Q3 in a non-conducting state (off state). The collector of the second transistor Q3 is connected to the source of the first MOSFET Q1. The gate of the first MOSFET Q1 is also connected to the emitter of the second transistor Q3.

[0056] When the first transistor Q2 is turned on, the voltage output from the power module is transmitted to the base of the second transistor Q3 through Q2, creating a voltage difference between the base and emitter of Q3. When this voltage difference exceeds the turn-on voltage between the base and emitter of Q3, Q3 turns on, connecting its emitter and collector. This connects the gate and source of the first MOSFET Q1 through the emitter and collector of Q3, making the gate and source voltages of Q1 equal and preventing it from turning on. Therefore, Q1 remains off. Furthermore, the emitter of Q3 is grounded through a resistor, ensuring the power module's output is grounded. This keeps the current across the sampling resistor Rsense above a set threshold, as the load resistance is much larger than the grounding resistance. When the load is grounded, short-circuited, or otherwise affected, the load resistance decreases significantly, and the current in the sampling resistor Rsense surges, exceeding the set threshold. This causes the first transistor Q2 and the second transistor Q3 to conduct. The output of the power module is grounded through the second transistor Q3. Since the grounding resistance is less than the load resistance, the current in the sampling resistor Rsense remains greater than the set threshold, thus keeping the first transistor Q2 and the second transistor Q3 conducting. This keeps the output of the power module grounded, i.e., locked. This locks the output of the power module grounded, keeping the first MOSFET Q1 off.

[0057] It should be noted that the latch control unit 132 also includes a first capacitor C1 and a second capacitor C2. The two plates of the first capacitor C1 are connected to the base and emitter of the first transistor Q2, respectively, to stabilize the voltage between the base and emitter of the first transistor Q2 and prevent the first transistor Q2 from being mistakenly turned on. The two plates of the second capacitor C2 are connected to the base and emitter of the second transistor Q3, respectively, for voltage regulation.

[0058] The latch control unit 132 further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5. The first resistor R1 is located between the sampling resistor Rsense and the base of the first transistor Q2. The second resistor R2 is located between the collector of the first transistor Q2 and ground. The third resistor R3 is located between the collector of the first transistor Q2 and the base of the second transistor Q3. The fourth resistor R4 is located between the emitter of the second transistor Q3 and ground. The fifth resistor R5 is located between the sampling resistor Rsense and the load or output terminal Vout.

[0059] It should be noted that in this embodiment, the sampling resistor Rsense is a resistor with a fixed resistance value. The first MOSFET Q1 is a P-channel MOSFET. When the current i < the set threshold Ip, no overcurrent occurs, and the gate voltage of the first MOSFET Q1 is controlled to be low by R4, and the first MOSFET Q1 supplies power to the load; when i > Ip and an overcurrent occurs, the first MOSFET Q1 is turned off.

[0060] The first transistor Q2 is a PNP transistor, and the second transistor Q3 is an NPN transistor. The first transistor Q2 and the second transistor Q3 constitute the first state latch module. Once the first transistor Q2 is turned on, it will trigger the second transistor Q3 to turn on and the first MOSFET Q1 to turn off. The power module (or input terminal Vin), sampling resistor Rsense, fifth resistor R5, second transistor Q3, fourth resistor R4 and ground line (Vin→Rsense→R5→Q3→R4-GND) form a loop to maintain the voltage drop Vsense on the sampling resistor Rsense ≥ Vth (the threshold voltage of the first transistor Q2), so that the first transistor Q2 continues to conduct.

[0061] The sampling resistor Rsense is used to sense the current. When the voltage drop Vsense across the sampling resistor Rsense is greater than the threshold voltage Vth of the first transistor Q2, the first transistor Q2 is turned on.

[0062] The resistance value of the fifth resistor R5 should not be too large for the following reasons: 1) If the resistance value is too large, the voltage drop across the fifth resistor R5 will be large, which will cause the output voltage Vout to not meet the requirements; 2) After the OCP (overcurrent protection function) occurs, if the fifth resistor R5 is too large, the current i < Ip will be insufficient to keep the first transistor Q2 on, and the first state latching module will not latch the working state after OCP.

[0063] The second resistor R2 is used to keep the second transistor Q3 in the off state when the current i < Ip. The value of the second resistor R2 should not be too small to avoid excessive current in the Vin→Q2→R2→GND path when OCP occurs.

[0064] The first capacitor C1 and the second capacitor C2 are used for noise reduction to prevent the first transistor Q2 and the second transistor Q3 from being mis-activated due to noise interference.

[0065] The first resistor R1 and the third resistor R3 are used to limit the base current of the first transistor Q2 and the second transistor Q3.

[0066] In this embodiment, when OCP does not occur, the current i < the set threshold Ip, the voltage Vsense on the sampling resistor < Vth (the threshold voltage of the first transistor Q2), and the first transistor Q2 is turned off; the second resistor R2 pulls the base voltage of the second transistor Q3 to 0V, and the second transistor Q3 is turned off; the fourth resistor R4 pulls the gate of the first MOSFET Q1 to 0V, the gate voltage is less than the source voltage, and the first MOSFET Q1 is turned on.

[0067] When an OCP occurs, the current i > the set threshold Ip, and the workflow is as follows: Figure 3 As shown, Figure 3 for Figure 2 The flowchart shows the process. When the voltage Vsense on the sampling resistor is greater than Vth (the threshold voltage of the first transistor Q2), the first transistor Q2 is turned on. Assuming the on-resistance of the first transistor Q2 is 0R and the voltage at point c is Vin, the base voltage (junction b) Vb(Q3) of the second transistor Q3 is greater than or equal to Vth, so the second transistor Q3 is turned on. The gate voltage and source voltage of the first MOSFET Q1 are equal, so the first MOSFET Q1 is turned off. Vin→Rsense→R5→Q3→R4→GND form a loop, and the resistance values ​​of the fifth resistor R5 and the fourth resistor R4 are less than a certain value to maintain the current i>Ip and the voltage Vsense>Vth(Q2) on the sampling resistor, so as to ensure that the first state latch module is maintained in the OCP state and the first MOSFET Q1 is turned off after the OCP is triggered.

[0068] In summary, when the current i < Ip, the output terminal Vin of the power module supplies power to the load. When the current i > Ip, OCP is triggered, and the circuit connection between the input terminal Vin and the output terminal Vout is cut off, which means the circuit connection between the power module and the load is cut off, thus achieving the purpose of overcurrent protection.

[0069] Please see further. Figure 4 , Figure 4 This is a schematic diagram of the structure of the second embodiment of the overcurrent protection circuit provided in this application. Figure 4 As shown, the overcurrent protection circuit also includes a timing and pulse counting unit 133, which is located between the current detection module 12 and the latch control unit 132 of the first state latch module 13. This unit is used to control the operation of the first state latch module 13 after the current has been continuously monitored for a certain period or the number of pulses has exceeded a certain number. Specifically, when the current has been continuously monitored for a certain period or the number of pulses has exceeded a certain number, the latch control unit 132 controls the switch unit 131 to close, thus disconnecting the circuit supplying power to the load.

[0070] Please refer to the details. Figure 5 , Figure 5 A schematic diagram of the circuit structure of the second embodiment of the overcurrent protection circuit provided in this application. Figure 5As shown, the overcurrent protection circuit also includes a timing and pulse counting unit 133, which includes a storage capacitor C2 and a first diode D1. It should be noted that, compared to the first embodiment, in this embodiment, the resistance of the third resistor R3 is smaller than that of the second resistor R2, and the capacitance of the storage capacitor C2 is larger, so that the storage capacitor C2 has a certain storage function.

[0071] In this embodiment, the storage capacitor C2 is equivalent to the second capacitor C2 in the first embodiment. The first plate of the storage capacitor C2 is connected to the collector of the first transistor Q2 and the base of the second transistor Q3, and is used to store the accumulated charge that the first transistor Q2 charges into the base of the second transistor Q3 through the third resistor R3. The second plate of the storage capacitor C2 is grounded.

[0072] The positive terminal of the first diode D1 is connected to the collector of the first transistor Q2, and the negative terminal of the first diode Q2 is connected to the first plate of the storage capacitor C2 and the base of the second transistor Q3. This is to prevent the charge on the storage capacitor C2 from being lost, so that the storage capacitor C2 can store the accumulated charge (voltage) that the first transistor Q2 charges into the base of the second transistor Q3.

[0073] In this embodiment, the third resistor R3 and the storage capacitor C2 constitute a charge accumulation circuit. During a pulsed overcurrent, Vin charges the storage capacitor C2 through the path Q2→R3→D2→C2. Specifically, when the overcurrent in the circuit is a pulsed overcurrent, i.e., a non-sustained overcurrent, the first transistor Q2 is intermittently switched on and off. The storage capacitor C2 stores the accumulated charge that the first transistor Q2 has deposited into the base of the second transistor Q3. When a certain amount of charge has accumulated, the second transistor Q3 turns on. In this embodiment, by adding a first diode D1, during a pulsed overcurrent, the first diode D1 prevents the charge in the storage capacitor C2 from leaking through the path R3→R2→GND, ensuring the normal operation of the timing and pulse counting functions.

[0074] In this embodiment, the overcurrent protection circuit further includes a first reset unit 134, which includes a third MOSFET Q8. The gate of the third MOSFET Q8 is connected to the first control signal line Reset1, the source is connected to the base of the second transistor Q3 and the first plate of the storage capacitor C2, and the drain is grounded through a resistor. The third MOSFET Q8 discharges the base of the second transistor Q3 and the storage capacitor C2, which is used to pull down the potential at point b when the system is powered on to maintain the second transistor Q3 in the off state and restore the first MOSFET Q1 to supply power to the load. In one embodiment, the third MOSFET Q8 is an N-channel MOSFET; in other embodiments, the third MOSFET Q8 may also be an N-channel MOSFET, which is not limited here.

[0075] In this embodiment, the first reset unit 134 further includes a protection resistor R12. The drain of the third MOS transistor Q5 is grounded through the protection resistor R12 to prevent excessive current from damaging the third MOS transistor Q8 when it discharges the storage capacitor C2 after the third MOS transistor Q8 is turned on.

[0076] In this embodiment, upon initial power-on, the first control signal line Reset1 is high, turning on the third MOSFET Q8. This pulls the potential at point b to ground (GND), stabilizing the potential on the first plate of the storage capacitor C2 at ground level. The second transistor Q3 is then off, and the first MOSFET Q1 is on. Please refer to [link to details] for further information. Figure 6 , Figure 6 for Figure 5 Workflow diagram of the initial state and when OCP is not triggered.

[0077] 1. When OCP does not occur, i < Ip, the voltage Vsense on the sampling resistor is < Vth (the threshold voltage of the first transistor Q2), and the first transistor Q2 is turned off; the second resistor R2 pulls the base voltage of the second transistor Q3 to 0V, and the second transistor Q3 is turned off; the fourth resistor R4 pulls the gate of the first MOSFET Q1 to 0V, the gate voltage is less than the source voltage, and the first MOSFET Q1 is turned on.

[0078] 2. When the pulse current i > Ip, scenario one: OCP is triggered when current i > Ip and time t > Tp. The charge accumulation circuit composed of the third resistor R3 and storage capacitor C2, when the pulse current amplitude i > Ip, turns on the first transistor Q2. Vin charges the storage capacitor C2 through the path Q2→R3→D2→C2. When the potential at point b exceeds Vth (the threshold voltage of the second transistor Q3), the second transistor Q3 turns on, and the first-state latching circuit composed of the first transistor Q2 and the second transistor Q3 remains in the OCP trigger state. The capacitance of storage capacitor C2 and the resistance of the third resistor R3 must not be too small to avoid false triggering of OCP by a short-duration overcurrent pulse. Conversely, the capacitance of storage capacitor C2 and the resistance of R3 must not be too large to prevent the potential at node b from failing to rise to Vth (the threshold voltage Q3 of the second transistor Q3) as expected. At this time, the first control signal line Reset1 is at a low level, and the third MOSFET Q8 is in the off state, so the charge on the storage capacitor C2 will not be discharged. Scenario 2: When the overcurrent pulses are short but numerous, the number of pulses i > Ip exceeds Np, triggering OCP. Whenever i > Ip, the first transistor Q2 is turned on and the storage capacitor C2 is charged. In the initial stage, the potential at point b < Vth (the threshold voltage of the second transistor Q3) keeps the second transistor Q3 in the off state, and the first MOSFET Q1 continues to be turned on. Afterwards, when the current i is less than Ip, the first transistor Q2 is turned off, and the charge stored in the storage capacitor C2 is limited within the storage capacitor C2 due to the action of the first diode D1; at this time, the third MOSFET Q8 is in the off state, so the charge on the storage capacitor C2 will not be discharged. Therefore, when the number of pulses i > Ip exceeds Np, the potential at point b Vb > Vth (the threshold voltage of the second transistor Q3), and the first state latch module latches the overcurrent protection circuit into the state of triggering OCP. For details, please refer to [link / reference]. Figure 7 and Figure 8 , Figure 7 This is a waveform diagram of the load current when a pulsed overcurrent occurs. For example... Figure 7 As shown, OCP can be triggered when the current i > Ip and the time t > Tp; OCP can be triggered when the number of pulses i > Ip exceeds Np. Figure 8 for Figure 5 The flowchart of the process when the medium-pulse overcurrent triggers the OCP is as follows: Figure 8 As shown, this constitutes a state-locked loop.

[0079] 3. Restore the latch circuit to the non-OCP triggered state. After an OCP occurs, the third MOSFET Q8 can restore the first-state latch module to the non-OCP triggered state. The working mechanism is as follows: The first control signal line Reset1 is set to a high level by the external control circuit, the third MOSFET Q8 is turned on, and then the charge of the storage capacitor C2 is discharged through the path Q8→C2→GND. When Vb < Vth (the threshold voltage of the second transistor Q3), the second transistor Q3 is turned off and the first MOSFET Q1 is turned on, restoring the power supply from the input terminal Vin to the output terminal Vout.

[0080] Please see further. Figure 9 , Figure 9 This is a schematic diagram of the third embodiment of the overcurrent protection circuit provided in this application. Figure 9 As shown, the overcurrent protection circuit also includes a control module 14 connected to the current detection module 12. In this embodiment, the current detection module 12 includes a second MOSFET, the gate of which is connected to the control module 14, the source of which is connected to the power supply module 11, and the drain of which is connected to the load. By adjusting the resistance of the second MOSFET through the control module 14, the current protection threshold (i.e., the adjustable current setting threshold) in the circuit can be adjusted. See details in [reference needed]. Figure 10 , Figure 10 This application provides a graph showing the resistance of a MOSFET as a function of gate voltage and drain current. Vgs is the gate voltage of the MOSFET, and Id is the drain (source) current of the MOSFET.

[0081] Based on the first embodiment, this embodiment replaces the sampling resistor Rsense with a second MOS transistor in the P-channel, and the overcurrent protection threshold Ip can be set by software. This embodiment is more convenient than changing the hardware settings.

[0082] Please see further. Figure 11 , Figure 11 A schematic diagram of the circuit structure of the third embodiment of the overcurrent protection circuit provided in this application. Figure 11 As shown, the current detection module 12 includes a second MOSFET Q4. The gate of the second MOSFET Q4 is connected to the control signal Vgs output by the control module. By changing the resistance value of the second MOSFET Q4 through the control signal Vgs, the current protection threshold (set threshold) in the circuit is changed. The first state latch module 13 can be configured with the circuit structure described in the first embodiment, or it can be configured with the circuit structure described in the second embodiment.

[0083] The second MOSFET Q4 is a P-channel MOSFET. By setting the gate voltage of the second MOSFET Q4, the cross voltage between the source and drain of the second MOSFET Q4 can be adjusted. When the load current Id in the circuit increases and the cross voltage exceeds the threshold voltage Vth of the second MOSFET Q2, the overcurrent protection mechanism is activated.

[0084] Please see further. Figure 12 , Figure 12 This is a schematic diagram of the fourth embodiment of the overcurrent protection circuit provided in this application. Figure 12 As shown, the overcurrent protection circuit also includes a second state latch module 15 and a control module 16. The second state latch module 15 is connected to the first state latch module 13 and the power supply module 11, and is used to receive the feedback signal FB from the first state latch module 13, and control the output of the power supply module 11 according to the feedback signal FB. The control module 16 is connected to the first state latch module 13 and the second state latch module 15, and is used to receive the feedback signal FB from the first state latch module 13, and provide a reset signal to the first state latch module 13 and the second state latch module 15 according to the feedback signal FB, so that the first state latch module 13 and the second state latch module 15 return to their initial operating states.

[0085] In one specific embodiment, the current detection module 12 includes a second MOSFET Q4, and the control module 16 is also connected to the control terminal of the current detection module 12, that is, connected to the gate of the second MOSFET Q4, for regulating / adjusting the current protection threshold of the current detection module 12 to protect the circuit.

[0086] Please refer to further details. Figure 13 , Figure 13 This is a schematic diagram of the circuit structure of a specific embodiment of the first state latch module provided in this application. The first state latch module 13 can be configured with the circuit structure described in the first embodiment, the second embodiment, or the third embodiment. Figure 13As shown, in this specific embodiment, the first state latch module 13 is configured with the circuit structure described in the second embodiment, and the current detection module 12 is configured with the circuit structure described in the third embodiment. Specifically, the first state latch module 13 includes a first reset unit 134, which includes a third MOSFET Q8. The gate of the third MOSFET Q8 is connected to the first control signal line Reset1, the source is connected to the base of the second transistor Q3 and the first plate of the storage capacitor C2, and the drain is grounded through a resistor. The first control signal line Reset1 is the first output terminal of the control module 16. The third MOSFET Q8 discharges the base of the second transistor Q3 and the storage capacitor C2 to pull down the potential at point b when the system is powered on, thereby maintaining the second transistor Q3 in the off state and restoring the first MOSFET Q1 to power the load.

[0087] In this embodiment, the first state latch module 13 further includes a sixth resistor R6 disposed between the second resistor R2 and the ground line. The feedback points of the second state latch module 15 and the control module 16 are connected to the collector of the first transistor Q2 through the second resistor R2, connected to the base of the second transistor Q3 through the second resistor R2 and the third resistor R3, and grounded through the sixth resistor R6, thereby achieving connection with the first state latch module 13 for receiving the feedback signal FB from the first state latch module 13. The second resistor R2 and the sixth resistor R6 form a voltage divider circuit to generate the feedback signal FB. When the feedback signal FB is low, it indicates that OCP has not been triggered. When the feedback signal FB is high, it indicates that OCP has been triggered. The feedback signal FB is generated by the first state latch module 13 and input to the second state latch module 15 and the control module 16. 1) After the feedback signal FB is given to the second state latch module 15, the voltage source output of the power supply module 11 and multiple loads can be disconnected when an overcurrent occurs. 2) After the feedback signal FB is given to the control module 16, the control module 16 resets the first state latch module 13 and the second state latch module according to the internal logic processing unit to clear the overcurrent protection state and restore the voltage source output of the power supply module 11 to the load.

[0088] Please refer to further information. Figure 14 , Figure 14 This is a schematic diagram of the circuit structure of a specific embodiment of the second state latch module provided in this application. The second state latch module 15 includes a fourth MOSFET Q7, a third transistor Q6, and a fourth transistor Q5.

[0089] In this configuration, the gate of the fourth MOSFET Q7 is connected to the feedback point of the first state latch module 13, its source is connected to the feedback point of the first state latch module 13 via a resistor, and its drain is connected to the base of the third transistor Q6 and the collector of the fourth transistor Q5. The base of the third transistor Q6 and the collector of the third MOSFET Q7 are connected to the power supply module 11 to control the output of the power supply module 11. The base of the fourth transistor Q5 is connected to the collector of the third transistor Q6 and the power supply module 11. The emitter of the fourth transistor Q5 is connected to the DC voltage source VCC, and the collector of the fourth transistor Q5 is connected to the base of the third transistor Q6 and the drain of the third MOSFET Q7 to lock the conduction state of the third transistor Q6.

[0090] In this circuit, the fourth transistor Q5 is a PNP transistor, and the third transistor Q6 is an NPN transistor. The fourth transistor Q5 and the third transistor Q6 form a second-state latching circuit. When an overcurrent occurs, the overcurrent protection state is triggered, that is, the feedback point FB outputs a high-level pulse to trigger the fourth transistor Q5 and the third transistor Q6 to lock into the conducting state. When the initial power-on and control module 16 outputs a high-level pulse at node b1, the normal operation state is triggered, that is, the fourth transistor Q5 and the third transistor Q6 are locked into the off state, and the power control signal EN is output at a high level.

[0091] In this embodiment, the second state latch module 15 further includes a second diode D2, which is disposed between the drain of the fourth MOS transistor Q7 and the base of the third transistor Q6 and the collector of the fourth transistor Q5, in order to prevent the voltage of the junction b2 from flowing back and affecting the potential of the feedback point.

[0092] Among them, the fourth MOSFET Q7 is an N-channel MOSFET, which is controlled by the feedback signal of the feedback point FB. When the feedback signal of the feedback point FB is high, the fourth MOSFET Q7 is turned on, the second diode D2 is turned on, and the junction b2 is high.

[0093] In this embodiment, the second state latch module 15 further includes a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11. The eleventh resistor R11 is positioned between the feedback point of the first state latch module 13 and the source of the fourth MOSFET Q7. Specifically, the source of the fourth MOSFET Q7 is connected to both the feedback point of the first state latch module 13 and the gate of the fourth MOSFET Q7 via the eleventh resistor R11. This connection creates a voltage difference between the source and gate of the fourth MOSFET Q7 when the feedback signal FB is high, thereby enabling the fourth MOSFET Q7 to conduct. The seventh resistor R7 is positioned between the base and emitter of the fourth transistor Q5. The eighth resistor R8 is connected to the collector of the fourth transistor Q5. The ninth resistor R9 is connected to the base of the third transistor Q6, and the tenth resistor R10 is connected to the emitter of the third transistor Q6. Specifically, one end of the eighth resistor R8 is connected to the collector of the fourth transistor Q5, and the other end is connected to the drain of the fourth MOSFET Q7. One end of the ninth resistor R9 is connected to the base of the third transistor Q6, and the other end is connected to the drain of the fourth MOSFET Q7 and the other end of the eighth resistor R8. One end of the tenth resistor R10 is connected to the emitter of the third transistor Q6 and ground, and the other end is connected to the other ends of the eighth resistor R8 and the ninth resistor R9, as well as the drain of the fourth MOSFET Q7.

[0094] In this embodiment, the second state latch module 15 further includes a third capacitor C3 and a fourth capacitor C4. The two ends of the third capacitor C3 are connected to the base and emitter of the fourth transistor Q5, respectively. The two ends of the fourth capacitor C4 are connected to the base and emitter of the third transistor Q6, respectively. The third capacitor C3 and the fourth capacitor C4 are used for noise reduction to prevent the fourth transistors Q5 and Q6 from being mis-activated due to noise interference.

[0095] Among them, the eighth resistor R8 and the ninth resistor R9 form a voltage divider circuit to adjust the potential of node b2, ensuring that the third transistor Q6 is in the conducting state when the second state latching circuit is triggered in the overcurrent protection state.

[0096] Please refer to further information. Figure 15 , Figure 15 This is a schematic diagram of a specific embodiment of the control module provided in this application.

[0097] The control module 16 includes a first output terminal Reset1 and a second output terminal Reset2. The first output terminal Reset1 is connected to the first reset unit 134 of the first state latch module 13, specifically, to the gate of the third MOSFET Q8. The second output terminal Reset2 is also connected to the collector of the third transistor Q6 and the base of the fourth transistor Q5, used to trigger the turn-on latch state of the third transistor Q6 and the fourth transistor Q5 to close. The input terminal of the control module 16 is connected to the feedback point FB of the first state latch module 13. The control module 16 also includes an internal logic processing unit, used to determine the levels of the first output signal Rst1 and the second signal Rst2 based on the potential of the feedback signal FB and the control logic, thereby determining the output states of the first output terminal Reset1 and the second output terminal Reset2. The first output terminal Reset1 and the second output terminal Reset2 have three output states: low-level output, high-level output, and high-impedance output.

[0098] The working state of this specific embodiment is as follows:

[0099] 1. When Vin is powered on and the subsequent load current is less than the set protection threshold, if i < Ip, the first state latch module 13 is in normal working condition, and the output feedback signal FB is low. The second state latch module 15, under the pull-up action of the seventh resistor R7, triggers normal working condition, and the power control signal EN outputs a high level, indicating normal power output. Please refer to further details. Figure 16 , Figure 16 for Figure 14 The second state latching module triggers the state locking diagram of the normal operating state. The control module 16 detects the feedback signal FB and sets the first output terminal Reset1 and the second output terminal Reset2 to high impedance output through the internal logic processing unit.

[0100] 2. When the load current exceeds the set protection threshold, if i > Ip, and the first state latch module 13 triggers overcurrent protection, the circuit connection between the input terminal Vin and the output terminal Vout is disconnected, and the feedback signal FB is high. The feedback signal FB pulls node b2 high, the second state latch module 15 triggers overcurrent protection, the power control signal EN is low, and the power module 11 cuts off the output; please refer to further details. Figure 17 , Figure 17 for Figure 14 The second state latching module triggers the overcurrent protection state state locking diagram. The control module 16 detects the feedback signal FB and, through its internal logic processing unit, determines whether to change the output state of the first output terminal Reset1 and the second output terminal Reset2 according to the pre-set processing logic.

[0101] In this embodiment, the control module 16 is also used to control the reset operation of the first state latch module 13 and the second state latch module 15. Specifically, by using the first output terminal Reset1 to output a brief low-level pulse and then return to a high-impedance state, the first state latch module 13 can be reset to the normal operating state, restoring the conduction state of the first MOSFET Q1, thereby restoring the circuit connection from the input terminal Vin to the output terminal Vout. By using the second output terminal Reset2 to output a high-level pulse and then return to a high-impedance state, the second state latch module 15 can be reset to the normal operating state, restoring the power control signal EN to a high level, thereby restoring the output of the power module 11.

[0102] Furthermore, the control module 16 also includes a control signal output terminal, which is connected to the control terminal of the current detection module 12. The control signal Vgs output changes the resistance value of the second MOS transistor Q4, thereby changing the current protection threshold (set threshold) in the circuit. In one embodiment, the control module 16 also includes a regulation module 14, which can be used to output the regulation signal Vgs.

[0103] It should be noted that the DC power supply VCC is the basic voltage source of the power supply module 11, used to provide the basic voltage signal and maintain the basic operation of the circuit. The control module 16 is used to control / enable the output of the high voltage source in the power supply module 11.

[0104] This application also provides a display panel, which includes the overcurrent protection circuit described in any of the above embodiments. The overcurrent protection circuit can be fabricated within the panel, or it can be a separate component on a PCB integrated board, or integrated within a chip. The overcurrent protection circuit component within the panel is fabricated using an LTPS process.

[0105] The beneficial effect of this application is that by connecting a current detection module and a first state latch module in series between the voltage source and the load, the magnitude of the current in the path can be detected. When an overcurrent occurs, the circuit connection with the load is disconnected through the first state latch module to avoid overheating of the panel short circuit point or causing a fire. In addition, the disconnected state is locked under no special circumstances to avoid repeated on / off triggering of the circuit, which helps to promote the extremely low-cost L-Driver.

[0106] It should be noted that a transistor is an important semiconductor device, mainly used for signal amplification, switching control, and current regulation. It is one of the core components of modern electronic circuits, and is divided into two main categories: bipolar junction transistors (BJTs) and field-effect transistors (FETs), including PNP and NPN types. In this application, "MOS transistor" can refer to a field-effect transistor, and "transistor" can refer to a bipolar junction transistor; both are types of transistors.

[0107] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An overcurrent protection circuit, characterized by comprising: include: The power module is used to provide power voltage to the load; A current detection module is disposed between the power supply module and the load. One end of the current detection module is connected to the power supply module and the other end is connected to the load. It is used to sample whether the current output by the power supply module to the load exceeds a set threshold. The first state latch module includes a switching unit, a latch control unit, and a timing and pulse counting unit; The switching unit is disposed between the current detection module and the load. The switching unit includes a first MOS transistor, the gate of which is connected to the latch control unit, the source of which is connected to the power module, and the drain of which is connected to the load, for controlling the on / off state of the power module and the load. The latch control unit is connected to the current detection module and the switching unit respectively, and is used to control the switching unit to lock in the open state when the current detected by the current detection module exceeds a set threshold, thereby controlling the power module and the load to lock in the open state; wherein, the latch control unit includes a first transistor and a second transistor; the base of the first transistor is connected to the other end of the current detection module, the emitter of the first transistor is connected to one end of the current detection module and the power module, the collector of the first transistor is connected to the base of the second transistor; the base of the second transistor is connected to the collector of the first transistor, the base of the second transistor is also grounded, the emitter of the second transistor is grounded and connected to the gate of the first MOSFET, and the collector of the second transistor is connected to the power module and the source of the first MOSFET; The timing and pulse counting unit is located between the current detection module and the latching control unit of the first state latching module. It is used to control the operation of the first state latching module after the current has been continuous for a certain period of time or the number of pulses has exceeded a certain number. The timing and pulse counting module includes a storage capacitor and a first diode. The first plate of the storage capacitor is connected to the collector of the first transistor and the base of the second transistor, and the second plate of the storage capacitor is grounded. It is used to store the accumulated charge that the first transistor has charged into the base of the second transistor. The anode of the first diode is connected to the collector of the first transistor, and the cathode of the first diode is connected to the first plate of the storage capacitor and the base of the second transistor to prevent the charge on the storage capacitor from being lost.

2. The overcurrent protection circuit of claim 1, wherein, The current detection module includes a sampling resistor, one end of which is connected to the power supply module and the other end of which is connected to the load.

3. The overcurrent protection circuit of claim 1, wherein, The overcurrent protection circuit also includes a control module connected to the control terminal of the current detection module; The current detection module includes a second MOSFET, and the control module is connected to the gate of the second MOSFET. The voltage output by the control module controls the resistance of the second MOSFET, thereby adjusting the current protection threshold in the circuit.

4. The overcurrent protection circuit according to claim 1, characterized in that, The overcurrent protection circuit also includes: The second state latch module is connected to the first state latch module and the power module, and is used to receive the feedback signal from the first state latch module and control the output of the power module according to the feedback signal. The control module, connected to the first state latch module and the second state latch module, is used to receive feedback signals from the first state latch module and provide reset signals to the first state latch module and the second state latch module according to the feedback signals, so that the first state latch module and the second state latch module resume working state.

5. The overcurrent protection circuit according to claim 4, characterized in that, The first state latch module further includes a first reset unit, which is connected to the base of the second transistor and is used to reset the first state latch module. The first reset unit includes a third MOS transistor connected to the base of the second transistor. The gate of the third MOS transistor is connected to the control module, the source of the third MOS transistor is connected to the base of the second transistor, and the drain is grounded. It is used to discharge the base of the second transistor when the control module outputs a first reset signal, so as to turn off the second transistor and then turn on the switching unit. The first reset unit also includes a protection resistor, through which the drain of the third MOS transistor is grounded to protect the third MOS transistor.

6. A display panel, characterized in that, The display panel includes the overcurrent protection circuit as described in any one of claims 1 to 5.

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