Image data acquisition method and device

Abstract

The invention discloses an image data acquisition method and device. The method comprises the following steps: acquiring a characteristic value for representing alignment of a data channel and a clock channel; at least one initial delay value of a target channel is obtained, at least one initial target channel is determined according to the at least one initial delay value, and the target channel is a clock channel or a data channel; moving the data channels, and determining the initial target channel of which the characteristic value is found in the data channels as an effective target channel; determining a target delay value of the target channel according to the effective target channel, and adjusting the target channel according to the target delay value, so that the data channel is aligned with the clock channel; and sampling the image data in the data channel based on the aligned rising edge of the clock channel.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to a method and device for acquiring image data. Background Art

[0002] To ensure reliable alignment of data and clock, especially for high-speed differential signals like those used in sensors and other similar high-speed signals, alignment of the clock and data receivers is necessary to improve data reliability and stability. Misalignment of data and clock can lead to data parsing errors and misjudgments at the receiver. Skew in the transmitted data itself and link skew between different channels can also cause clock and data misalignment and misalignment. Related technologies typically add a fixed delay value to the data or clock channel and then verify alignment. Once the fixed value is verified, it is fixed in the processing method for subsequent products or batches. This method of adding a fixed delay value to the data or clock channel requires repeated trial and error to verify data and clock alignment before achieving a reliable fixed value. If the delay adjustment range is large, verifying alignment can be time-consuming and inefficient. Furthermore, after obtaining the fixed value, a certain amount of product testing or sufficient high and low temperature testing is required to adjust the fixed value, obtain the optimal intermediate value, and verify its reliability, which significantly increases time and equipment costs.

[0003] To address the above-mentioned problems, no effective solutions have been proposed so far. Summary of the Invention

[0004] The embodiments of the present application provide a method and apparatus for acquiring image data, so as to at least solve the technical problem of low efficiency in acquiring image data due to obtaining delay value alignment channels through multiple attempts.

[0005] According to one aspect of an embodiment of the present application, a method for acquiring image data is provided, including: acquiring a characteristic value for characterizing the alignment of a data channel and a clock channel; acquiring at least one initial delay value of a target channel, and determining at least one initial target channel based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; moving the data channel, and determining the initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel based on the valid target channel, and adjusting the target channel based on the target delay value so that the data channel and the clock channel are aligned; and sampling image data in the data channel based on the rising edge of the aligned clock channel.

[0006] Optionally, a target delay value of the target channel is determined according to the effective target channel, and the target channel is adjusted according to the target delay value so that the data channel and the clock channel are aligned, including: when the target channel is the clock channel, moving the data channel, and determining the initial clock channel whose characteristic value is found in the data channel as the effective clock channel; determining the target delay value of the clock channel according to multiple effective clock channels, adjusting the clock channel according to the target delay value of the clock channel, and aligning the data channel with the clock channel; when the target channel is the data channel, moving the data channel, and determining the initial data channel whose characteristic value is found in the clock channel as the effective data channel; determining the target delay value of the data channel according to multiple effective data channels, adjusting the data channel according to the target delay value of the data channel, aligning the data channel with the clock channel, and sampling the image data in the data channel based on the rising edge of the aligned clock channel.

[0007] Optionally, obtaining at least one initial delay value of the target channel includes: obtaining a preset step size; and sequentially increasing the delay value of the target channel according to the preset step size to obtain the at least one initial delay value.

[0008] Optionally, the target delay value of the clock channel is determined based on multiple valid clock channels, including: sequentially moving the data channel in the same direction by different integer bits, and determining the number of valid clock channels corresponding to different integer bits, the amplitude of the data channel movement is determined based on the spacing between adjacent rising edges and falling edges in the clock channel, and the number of different integer bits is determined based on the number of bits of the characteristic value; determining the integer bit with the largest number of valid clock channels as the first target integer bit, and determining multiple valid clock channels corresponding to the first target integer bit as target clock channels; and determining the target delay value of the clock channel based on the delay value of the target clock channel.

[0009] Optionally, determining a target delay value of a data channel based on multiple valid data channels includes: sequentially moving the data channel in the same direction by different integer bits, and determining the number of valid data channels corresponding to different integer bits; determining the integer bit with the largest number of valid data channels as the second target integer bit, and determining multiple valid data channels corresponding to the second target integer bit as target data channels; and determining the target delay value of the data channel based on the delay value of the target data channel.

[0010] Optionally, the integer bit with the largest number of valid clock channels is determined as the first target integer bit, and multiple valid clock channels corresponding to the first target integer bit are determined as target clock channels, including: shifting the data channels to the left by odd bits and even bits respectively, and determining the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits respectively; comparing the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits, and determining the largest number of valid clock channels as the target clock channels.

[0011] Optionally, the integer bit with the largest number of valid clock channels is determined as the first target integer bit, and multiple valid clock channels corresponding to the first target integer bit are determined as target clock channels, including: shifting the data channels to the right by odd bits and even bits respectively, and determining the number of valid clock channels corresponding to the right shift of odd bits and the number of valid clock channels corresponding to the right shift of even bits respectively; comparing the number of valid clock channels corresponding to the shift of odd bits and the number of valid clock channels corresponding to the shift of even bits, and determining the largest number of valid clocks as the target clock channels.

[0012] Optionally, determining the target delay value of the clock channel according to the delay value of the target clock channel includes: acquiring delay values ​​of multiple target clocks; and determining an average value of the delay values ​​of the multiple target clocks as the delay value of the clock channel.

[0013] Optionally, an initial clock channel whose characteristic value is found in the data channel is determined to be a valid clock channel, including: obtaining the number of bits of the characteristic value; and determining that the initial clock channel is a valid clock channel when there are a continuous target number of rising edges in the initial clock channel corresponding to each value in the characteristic value in sequence, wherein the target number is a multiple of the number of bits.

[0014] Optionally, the method further includes: sampling the data channel at a rising edge of the clock channel; and determining that the data channel is aligned with the clock channel when a value obtained by sampling is equal to the characteristic value.

[0015] According to another aspect of an embodiment of the present application, another image data acquisition method is provided, including: obtaining a characteristic value for characterizing the alignment of a data channel and a clock channel; obtaining at least one initial delay value of the clock channel, and determining at least one initial clock channel based on the at least one initial delay value; moving the data channel, and determining the initial clock channel in which the characteristic value is found in the data channel as a valid clock channel; determining a target delay value of the clock channel based on the valid clock channel, and adjusting the clock channel based on the target delay value so that the data channel and the clock channel are aligned; and sampling the image data in the data channel based on the rising edge of the aligned clock channel.

[0016] According to another aspect of an embodiment of the present application, an image data acquisition device is also provided, including: a first acquisition module, used to acquire a characteristic value used to characterize the alignment of a data channel and a clock channel; a second acquisition module, used to acquire at least one initial delay value of a target channel, and determine at least one initial target channel based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; a moving module, used to move the data channel, and determine the initial target channel in which the characteristic value is found in the data channel as a valid target channel; a determination module, used to determine a target delay value of the target channel based on the valid target channel, and adjust the target channel based on the target delay value so that the data channel and the clock channel are aligned; and a sampling module, used to sample image data in the data channel based on the rising edge of the aligned clock channel.

[0017] According to another aspect of the embodiment of the present application, a three-dimensional scanning system is also provided, including: a scanner and a host computer, the scanner and the host computer are connected; the scanner includes an image acquisition module, the image acquisition module is used to obtain image data of the surface of the object to be measured; the image acquisition module is also used to obtain characteristic values ​​used to characterize the alignment of the data channel and the clock channel; obtain at least one initial delay value of the target channel, and determine at least one initial target channel based on the at least one initial delay value, the target channel is: a clock channel or a data channel; move the data channel, and determine the initial target channel whose characteristic value is found in the data channel as a valid target channel; determine the target delay value of the target channel based on the valid target channel, and adjust the target channel according to the target delay value so that the data channel and the clock channel are aligned; based on the rising edge of the aligned clock channel, sample the image data in the data channel; transmit the sampled image data to the host computer; the host computer is used to complete the three-dimensional reconstruction of the object to be measured based on the image data.

[0018] According to another aspect of the embodiments of the present application, a computer device is also provided, including: a memory for storing program instructions; a processor, connected to the memory, for executing the program instructions of the following functions: obtaining a characteristic value for characterizing the alignment of a data channel and a clock channel; obtaining at least one initial delay value of a target channel, and determining at least one initial target channel based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; moving the data channel, and determining the initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel based on the valid target channel, and adjusting the target channel based on the target delay value so that the data channel and the clock channel are aligned; sampling image data in the data channel based on the rising edge of the aligned clock channel.

[0019] According to another aspect of the embodiments of the present application, a non-volatile storage medium is provided, which includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the above-mentioned image data acquisition method by running the computer program.

[0020] In an embodiment of the present application, a characteristic value for characterizing the alignment of a data channel and a clock channel is obtained; at least one initial delay value of a target channel is obtained, and at least one initial target channel is determined based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; the data channel is moved, and the initial target channel in which the characteristic value is found in the data channel is determined as a valid target channel; a target delay value of the target channel is determined based on the valid target channel, and the target channel is adjusted based on the target delay value so that the data channel and the clock channel are aligned; based on the rising edge of the aligned clock channel, image data in the data channel is sampled, at least one initial target channel is determined by at least one initial delay value, and then a valid target channel is determined based on the at least one initial target channel, and finally, a target delay value of the target channel is determined based on the valid target channel, thereby avoiding multiple attempts to verify and improving the efficiency of alignment of the data channel and the clock channel, thereby achieving the technical effect of image data acquisition efficiency, and further solving the technical problem in the related art of low image data acquisition efficiency caused by obtaining delay value alignment channels through multiple attempts. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0022] Figure 1 is a hardware structure block diagram of a computer terminal for implementing an image data acquisition method according to an embodiment of the present application;

[0023] Figure 2 is a flow chart of an image data acquisition method of the present application;

[0024] Figure 3 This is a schematic diagram of the structure of a three-dimensional scanning system according to an embodiment of the present application;

[0025] Figure 4 is a flow chart of another method for acquiring image data according to an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of an effective clock according to an embodiment of the present application;

[0027] Figure 6 is a schematic diagram of an invalid clock according to an embodiment of the present application;

[0028] Figure 7 This is a schematic diagram of an optimal delay value according to an embodiment of the present application;

[0029] Figure 8 is a flowchart of another method for acquiring image data according to an embodiment of the present application;

[0030] Figure 9 It is a structural schematic diagram of an image data acquisition device according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of this application.

[0032] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in a sequence other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0033] The image data acquisition method embodiment provided in the embodiment of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Figure 1 FIG1 shows a hardware structure block diagram of a computer terminal for implementing an image data acquisition method. Figure 1As shown, the computer terminal 10 may include one or more (illustrated by 102a, 102b, ..., 102n in the figure) processors (the processor may include but is not limited to a microprocessor MCU or a programmable logic device FPGA and other processing devices), a memory 104 for storing data, and a transmission module 106 for communication functions. In addition, it may also include: a display, a keyboard, a cursor control device, an input / output interface (I / O interface), a universal serial bus (USB) port (which may be included as one of the ports of the I / O interface), a network interface, and a BUS bus. Those skilled in the art will understand that Figure 1 The structure shown is only for illustration and does not limit the structure of the above electronic device. Figure 1 More or fewer components than shown, or with Figure 1 Different configurations shown.

[0034] It should be noted that the one or more processors and / or other data processing circuits described above may generally be referred to herein as "data processing circuitry." The data processing circuitry may be embodied in whole or in part as software, hardware, firmware, or any other combination thereof. Furthermore, the data processing circuitry may be a single, independent processing module, or may be incorporated in whole or in part into any of the other components of the computer terminal 10. As described in the embodiments of the present application, the data processing circuitry serves as a processor control (e.g., selection of a variable resistor terminal path connected to an interface).

[0035] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / data storage device corresponding to the image data acquisition method in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory 104, that is, implementing the above-mentioned image data acquisition method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor, and these remote memories may be connected to the computer terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0036] The transmission module 106 is configured to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by the communications provider of the computer terminal 10. In one embodiment, the transmission module 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission module 106 may be a radio frequency (RF) module, which is configured to communicate with the Internet wirelessly.

[0037] The display may be, for example, a touch screen liquid crystal display (LCD) that enables a user to interact with a user interface of the computer terminal 10 .

[0038] It should be noted that, in some optional embodiments, the above Figure 1 The computer device shown may include hardware elements (including circuits), software elements (including computer code stored on a computer-readable medium), or a combination of hardware elements and software elements. Figure 1 This is merely one example of a particular embodiment and is intended to illustrate the types of components that may be present in the computer device described above.

[0039] In the above-mentioned operating environment, an embodiment of the present application provides an embodiment of an image data acquisition method. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0040] Figure 2 is a flow chart of a method for acquiring image data according to an embodiment of the present application. Figure 2 As shown, the method includes the following steps:

[0041] Step S202, obtaining a characteristic value for characterizing alignment between a data channel and a clock channel;

[0042] Step S204, obtaining at least one initial delay value of a target channel, and determining at least one initial target channel according to the at least one initial delay value, where the target channel is: a clock channel or a data channel;

[0043] Step S206, moving the data channel, and determining the initial target channel whose characteristic value is found in the data channel as the valid target channel;

[0044] Step S208, determining a target delay value of the target channel according to the valid target channel, and adjusting the target channel according to the target delay value so that the data channel and the clock channel are aligned;

[0045] Step S210 : sampling the image data in the data channel based on the rising edge of the aligned clock channel.

[0046] The image data acquisition method in steps S202 to S210 described above adopts the following steps: obtaining a characteristic value for characterizing the alignment of a data channel and a clock channel; obtaining at least one initial delay value of a target channel, and determining at least one initial target channel based on the at least one initial delay value, where the target channel is a clock channel or a data channel; moving the data channel, and determining the initial target channel whose characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel based on the valid target channel, and adjusting the target channel based on the target delay value so that the data channel and the clock channel are aligned; sampling the image data in the data channel based on the rising edge of the aligned clock channel, determining at least one initial target channel based on the at least one initial delay value, then determining a valid target channel based on the at least one initial target channel, and finally determining a target delay value of the target channel based on the valid target channel, thereby avoiding multiple verification attempts and improving the efficiency of data channel and clock channel alignment, thereby achieving the technical effect of image data acquisition efficiency, and further solving the technical problem of low image data acquisition efficiency caused by obtaining delay value alignment channels through multiple attempts in the related art. Detailed description is given below.

[0047] It should be noted that when adding a fixed delay value to the data channel or clock channel, it is necessary to repeatedly try and change different values ​​before finding a verified fixed value to check whether the data and clock are aligned. If the delay adjustment range is large, it will take a lot of time to verify the alignment, which is inefficient. At the same time, after obtaining the fixed value, it is necessary to conduct a certain number of product tests to adjust the fixed value, obtain the optimal intermediate value, and verify its reliability, which will greatly increase time and equipment costs. Individual defective products or batches of defective products may have poor performance, the optimal fixed delay value may not be applicable, or the clock will coincide with the edge of the data after introduction, which will cause data errors and affect product stability.

[0048] In step S204 , the initial delay value may be obtained by sequentially increasing the delay value of the target channel itself within a preset range (the maximum value of the initial delay value of the target channel does not exceed a preset threshold).

[0049] In an optional manner, one or more initial delay values ​​can be obtained by sequentially increasing the same step length, for example: obtaining a preset step length; sequentially increasing the delay value of the target channel according to the preset step length to obtain at least one initial delay value, and the preset step length can be determined based on the minimum time accuracy value of the system reference clock.

[0050] When the target channel is a clock channel, the delay value of the clock channel is increased to obtain multiple initial clock channels, and then the data channel is shifted so that the initial clock channel searches for characteristic values ​​in the data channel to determine the valid clock channel;

[0051] When the target channel is a data channel, the delay value of the data channel is increased to obtain multiple initial data channels, and then the data channels are shifted so that the clock channel searches for characteristic values ​​in the data channels to determine valid data channels.

[0052] It can be understood that the above-mentioned initial target channel is the target channel with the delay value added, for example, the initial clock channel is the clock channel with the delay value added, and the initial data channel is the data channel with the delay value added.

[0053] It should be noted that the image data acquisition method provided in this application can be applied to the output of camera images. Furthermore, in the scenario of constructing a three-dimensional model, it can be used to output the projection image captured by the camera.

[0054] Specifically, the present application also provides a three-dimensional scanning system. Figure 3 As shown, the system comprises: a host computer 301 and a scanner 302, wherein the scanner 302 comprises: an image acquisition module 303 for acquiring image data of the surface of the object under test; the image acquisition module 303 is further configured to acquire a characteristic value for characterizing the alignment of the data channel and the clock channel; acquire at least one initial delay value of a target channel and determine at least one initial target channel based on the at least one initial delay value, where the target channel can be a clock channel or a data channel; move the data channel and determine the initial target channel for which the characteristic value is found in the data channel as the valid target channel; determine a target delay value for the target channel based on the valid target channel and adjust the target channel based on the target delay value so that the data channel and the clock channel are aligned; sample the image data in the data channel based on the rising edge of the aligned clock channel; transmit the sampled image data to the host computer 301; and the host computer 301 is configured to complete 3D reconstruction of the object under test based on the image data. The scanner 302 can be an active 3D scanner or a passive 3D scanner. The active 3D scanner can be a structured light 3D scanner or a time-of-flight 3D scanner.

[0055] In some embodiments of the present application, when the target channel is a clock channel, the data channel is moved, and the initial clock channel whose characteristic value is found in the data channel is determined as a valid clock channel; the target delay value of the clock channel is determined based on multiple valid clock channels, the clock channel is adjusted based on the target delay value of the clock channel, and the data channel and the clock channel are aligned; when the target channel is a data channel, the data channel is moved, and the initial data channel whose characteristic value is found in the clock channel is determined as a valid data channel; the target delay value of the data channel is determined based on multiple valid data channels, the data channel is adjusted based on the target delay value of the data channel, the data channel and the clock channel are aligned, and the image data in the data channel is sampled based on the rising edge of the aligned clock channel.

[0056] In the case where the target channel is a clock channel, the embodiment of the present application also provides another method for acquiring image data, such as Figure 4 As shown, including:

[0057] Step S402, obtaining a characteristic value for characterizing alignment between a data channel and a clock channel;

[0058] Step S404, obtaining at least one initial delay value of the clock channel, and determining at least one initial clock channel according to the at least one initial delay value;

[0059] Step S406: moving the data channel, and determining the initial clock channel whose characteristic value is found in the data channel as a valid clock channel;

[0060] Step S408, determining a target delay value of the clock channel according to the valid clock channel, and adjusting the clock channel according to the target delay value so that the data channel and the clock channel are aligned;

[0061] Step S410: sampling the image data in the data channel based on the rising edge of the aligned clock channel.

[0062] Taking the target channel as the clock channel as an example, the following two methods are adopted in the process of obtaining the target delay value of the clock channel in the embodiments of the present application: the first method is: first, add a delay value to the clock channel to obtain one or more initial clock channels, and then shift the data channel to find the characteristic value; the second method is: first, add a delay value to the data channel, and then shift the data channel to find the characteristic value. In some embodiments of the present application, the target delay value of the clock channel can be determined according to the effective clock channel by the following method: sequentially shift the data channel in the same direction by different integer bits, and respectively determine the number of effective clock channels corresponding to different integer bits, the amplitude of the data channel movement is determined according to the spacing between adjacent rising edges and falling edges in the clock channel, and the number of different integer bits is determined according to the number of bits of the characteristic value; the integer bit with the largest number of effective clock channels is determined as the first target integer bit, and the multiple effective clock channels corresponding to the first target integer bit are determined as the target clock channel; the target delay value of the clock channel is determined according to the delay value of the target clock channel;

[0063] It can be understood that the initial target channel is the target channel after the delay value is added.

[0064] When determining the target delay value of the data channel based on the valid data channel, the data channel is shifted in the same direction by different integer bits in sequence, and the number of valid data channels corresponding to the different integer bits is determined respectively; the integer bit with the largest number of valid data channels is determined as the second target integer bit, and the multiple valid data channels corresponding to the second target integer bit are determined as the target data channels; and the target delay value of the data channel is determined based on the delay value of the target data channel.

[0065] It should be noted that the step size of the data channel movement can be determined based on the characteristic value. For example, if the characteristic value 101010 is 6 bits, the step size of the data left and right shift is 0 to 5 steps. The left and right shifts of the data are performed after the clock delay value is increased by a step size. It is verified whether the characteristic value can be found by shifting the data after the clock delay value is increased by a step size. The amplitude of the shift is determined based on the spacing between adjacent rising and falling edges of the clock channel.

[0066] When the target channel is a data channel, the method of moving the data channel is similar to that when the target channel is a clock channel, and is not described in detail here.

[0067] In order to prevent the delay value of the clock channel from being exactly at the edge of the data after the data channel is moved, resulting in data errors, the embodiments of the present application use the following two methods to move the data channel. One optional method is: respectively shift the data channel to the left by odd and even bits, and respectively determine the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits; compare the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits, and determine the valid clock channel with the largest number as the target clock channel. Another optional method is: respectively shift the data channel to the right by odd and even bits, and respectively determine the number of valid clock channels corresponding to the right shift of odd bits and the number of valid clock channels corresponding to the right shift of even bits; compare the number of valid clock channels corresponding to the odd shift and the number of valid clock channels corresponding to the even shift, and determine the valid clock with the largest number as the target clock channel.

[0068] In summary, the target delay value can be determined based on the delay value corresponding to the maximum number of successful left shifts of even bits and the delay value corresponding to the maximum number of successful left shifts of odd bits, or right shifting can be selected and the target delay value can be determined based on the delay value corresponding to the maximum number of successful right shifts of even bits and the delay value corresponding to the maximum number of successful right shifts of odd bits.

[0069] It is understandable that the method for determining the target data channel is similar to the method for determining the target clock channel, and will not be described in detail here.

[0070] After the target clock channel is determined, delay values ​​of multiple target clock channels may be obtained; and an average value of the delay values ​​of the multiple target clock channels may be determined as the target delay value of the clock channel.

[0071] It is understandable that the method for determining the target delay value of the data channel is similar to that for the clock channel, and will not be described in detail here.

[0072] Table 1 shows the result of determining the target clock during the left shift of the data channel.

[0073] Table 1

[0074] clk delay1 clk delay2 clk delay3 clk delay4 clk delay5 Shift left 1 bit success success fail fail fail Shift left 2 bits fail fail success success success

[0075] As shown in Table 1, clk delay1 represents the initial clock corresponding to the initial delay value after the delay value of the clock channel is increased by one step. Similarly, clk delay2, clk delay3, clk delay4, and clk delay5 represent the initial clocks obtained after increasing the delay value by 2, 3, 4, and 5 steps, respectively. In Table 1, success indicates that the characteristic value is found, which is a valid clock. Failure indicates that the characteristic value is not found, which is an invalid clock.

[0076] It can be understood that when shifting left by one bit (odd bit), the effective clocks are 2, and when shifting left by two bits (even bit), the effective clocks are 3. Then clk delay3, clk delay4, and clk delay5 can be determined as the target clocks, and the delay value of the clock channel is the average of the three clock delay values ​​of clk delay3, clk delay4, and clk delay5.

[0077] In some embodiments of the present application, the effective clock can be determined by: obtaining the number of bits of the characteristic value; determining that the initial clock is a valid clock when there are a continuous target number of rising edges in the initial clock corresponding to each value in the characteristic value in sequence, wherein the target number is a multiple of the number of bits. In an optional manner, whether the data channel and the clock channel are aligned can be determined by sampling the data channel at the rising edge of the clock channel; when the sampled value is equal to the characteristic value, determining that the data channel and the clock channel are aligned.

[0078] like Figure 5 As shown, the characteristic value is 101010. It is sufficient to find 101010 in 6 consecutive rising edges, or it can be found in 6*N rising edges, which is determined according to the actual application scenario.

[0079] Figure 6 A schematic diagram of an invalid clock is shown, such as Figure 6 As shown, the rising edge of the clock cannot find the characteristic value 101010.

[0080] It should also be noted that, when odd and even digits are not distinguished, Figure 7 As shown, with clock delay 1, the data is successfully shifted left by 0 bits (even bits) (finding the characteristic value), and after clock delay 2, the data is successfully shifted left by 1 bit (odd bits). After averaging both delay 1 and delay 2, the rising edge of the clock channel coincides with the data edge. If only odd bits are shifted left, the data is successfully shifted left by 3 bits (odd bits) after delay 1 and delay 2, respectively. This ensures that both delay 1 and delay 2 coincide with the same peak or valley, avoiding crossing the edge and causing edge issues. The process for left shifting even and odd bits is similar and will not be repeated here.

[0081] Figure 8 Another clock lane alignment method is shown in Figure 8 As shown,

[0082] Step S801, the delay value of the clock clk is increased sequentially within a preset range;

[0083] Step S802: Each time the delay value of the clock clk increases by one step, each data channel is shifted left or right according to the aligned characteristic value. If the characteristic value can be found after the shift, it means that the current delay value of the clock clk is valid, otherwise it is invalid.

[0084] In step S803, in order to prevent the middle optimal value of the effective delay value from being exactly at the edge of the data after the data channel is successfully shifted left or right, it is necessary to distinguish between data shifted left by an even number of bits, data shifted left by an odd number of bits, or data shifted right by an even number of bits, data shifted right by an odd number of bits;

[0085] Step S804: After the delay value of the clock clk is increased, for example, to five steps, the number of consecutive successful left shifts of even bits is compared with the number of consecutive successful left shifts of odd bits, or the number of consecutive successful right shifts of even bits is compared with the number of consecutive successful right shifts of odd bits.

[0086] Step S805 , after the comparison is completed, the middle value of the larger number of times is taken as the optimal value of the delay value to be introduced into the clock channel delay.

[0087] Figure 9 is an image data acquisition device according to an embodiment of the present application, such as Figure 9 As shown, including:

[0088] A first acquisition module 90 is used to acquire a characteristic value used to characterize the alignment of the data channel and the clock channel;

[0089] A second acquisition module 92 is configured to acquire at least one initial delay value of a target channel and determine at least one initial target channel according to the at least one initial delay value, where the target channel is a clock channel or a data channel;

[0090] A moving module 94 is configured to move the data channel and determine an initial target channel whose characteristic value is found in the data channel as a valid target channel;

[0091] A determination module 96 is configured to determine a target delay value of a target channel according to the valid target channel, and adjust the target channel according to the target delay value so that the data channel and the clock channel are aligned;

[0092] The sampling module 98 is configured to sample the image data in the data channel based on the rising edge of the aligned clock channel.

[0093] The moving module 94 includes: a moving sub-module, which is used to move the data channel when the target channel is a clock channel, and determine the initial clock channel whose characteristic value is found in the data channel as a valid clock channel; determine the target delay value of the clock channel based on multiple valid clock channels, adjust the clock channel according to the target delay value of the clock channel, and align the data channel with the clock channel; when the target channel is a data channel, move the data channel, and determine the initial data channel whose characteristic value is found in the clock channel as a valid data channel; determine the target delay value of the data channel based on multiple valid data channels, adjust the data channel according to the target delay value of the data channel, align the data channel with the clock channel, and sample the image data in the data channel based on the rising edge of the aligned clock channel.

[0094] The second acquisition module 92 includes an acquisition submodule for acquiring at least one initial delay value of the target channel, including: acquiring a preset step size; and sequentially increasing the delay value of the target channel according to the preset step size to obtain at least one initial delay value.

[0095] The acquisition submodule includes: a first determination unit and a second determination unit. The first determination unit is used to sequentially shift the data channel in the same direction by different integer bits, and respectively determine the number of valid clock channels corresponding to different integer bits. The amplitude of the data channel shift is determined according to the spacing between adjacent rising edges and falling edges in the clock channel, and the number of different integer bits is determined according to the number of bits of the characteristic value; the integer bit with the largest number of valid clock channels is determined as the first target integer bit, and the multiple valid clock channels corresponding to the first target integer bit are determined as target clock channels; and the target delay value of the clock channel is determined according to the delay value of the target clock channel.

[0096] The second determination unit is used to sequentially move the data channels in the same direction by different integer bits, and determine the number of valid data channels corresponding to different integer bits; determine the integer bit with the largest number of valid data channels as the second target integer bit, and determine the multiple valid data channels corresponding to the second target integer bit as the target data channels; and determine the target delay value of the data channel according to the delay value of the target data channel.

[0097] The first determination unit includes: a first subunit and a second subunit, wherein the first subunit is used to shift the data channel to the left by odd bits and even bits respectively, and respectively determine the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits; compare the number of valid clock channels corresponding to the left shift of odd bits and the number of valid clock channels corresponding to the left shift of even bits, and determine the valid clock channel with the largest number as the target clock channel.

[0098] The second sub-unit is used to shift the data channel to the right by odd bits and even bits respectively, and determine the number of valid clock channels corresponding to shifting the odd bits to the right and the number of valid clock channels corresponding to shifting the even bits to the right respectively; compare the number of valid clock channels corresponding to shifting the odd bits and the number of valid clock channels corresponding to shifting the even bits, and determine the valid clock with the largest number as the target clock channel.

[0099] The device also includes: a delay unit, configured to obtain delay values ​​of a plurality of target clock channels; and determine an average value of the delay values ​​of the plurality of target clock channels as a target delay value of the clock channel.

[0100] The device also includes: an effective clock determination unit, which is used to obtain the number of bits of the characteristic value; when there are a continuous target number of rising edges in the initial clock channel corresponding to each value in the characteristic value in sequence, the initial clock channel is determined to be a valid clock channel, wherein the target number is a multiple of the number of bits.

[0101] The data channel is sampled at the rising edge of the clock channel; when the sampled value is equal to the characteristic value, it is determined that the data channel is aligned with the clock channel.

[0102] It should be noted that Figure 9 The image data acquisition device shown is used to perform Figure 2 The image data acquisition method shown is an image data acquisition method, so the relevant explanations in the image data acquisition method are also applicable to this image data acquisition device, and will not be repeated here.

[0103] An embodiment of the present application also provides a computer device, comprising: a memory for storing program instructions; obtaining a characteristic value for characterizing the alignment of a data channel and a clock channel; obtaining at least one initial delay value of a target channel, and determining at least one initial target channel based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; moving the data channel, and determining the initial target channel for which the characteristic value is found in the data channel as a valid target channel; determining a target delay value for the target channel based on the valid target channel, and adjusting the target channel based on the target delay value so that the data channel and the clock channel are aligned; and sampling image data in the data channel based on the rising edge of the aligned clock channel.

[0104] It should be noted that the above-mentioned computer equipment is used to execute Figure 2 The image data acquisition method shown in the figure, therefore the relevant explanations in the above image data acquisition method are also applicable to the computer device and will not be repeated here.

[0105] An embodiment of the present application also provides a non-volatile storage medium, which includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the following image data acquisition method by running the computer program: obtaining a characteristic value used to characterize the alignment of a data channel and a clock channel; obtaining at least one initial delay value of a target channel, and determining at least one initial target channel based on the at least one initial delay value, where the target channel is: a clock channel or a data channel; moving the data channel, and determining the initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel based on the valid target channel, and adjusting the target channel based on the target delay value so that the data channel and the clock channel are aligned; and sampling the image data in the data channel based on the rising edge of the aligned clock channel.

[0106] It should be noted that the above non-volatile storage medium is used to execute Figure 2 The image data acquisition method shown in the figure, therefore the relevant explanations in the above image data acquisition method are also applicable to the non-volatile storage medium, and will not be repeated here.

[0107] An embodiment of the present application further provides a computer program product, including a computer program, which implements the steps of the method described in each embodiment of the present application when executed by a processor.

[0108] An embodiment of the present application further provides another computer program product, comprising a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in each embodiment of the present application are implemented.

[0109] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0110] In the above embodiments of the present application, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only exemplary. For example, the division of units can be a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0112] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple units. Some or all of the units may be selected to achieve the purpose of the present embodiment according to actual needs.

[0113] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0114] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, server or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program code.

[0115] The above is only a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A method for acquiring image data, characterized in that: include: Obtaining characteristic values ​​for characterizing alignment between a data channel and a clock channel; Acquire at least one initial delay value of a target channel, and determine at least one initial target channel according to the at least one initial delay value, where the target channel is: the clock channel or the data channel; Moving the data channel, and determining an initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel according to the valid target channel, and adjusting the target channel according to the target delay value so that the data channel and the clock channel are aligned; The image data in the data channel is sampled based on the aligned rising edge of the clock channel.

2. The method according to claim 1, characterized in that Determining a target delay value of the target channel according to the valid target channel, and adjusting the target channel according to the target delay value so that the data channel and the clock channel are aligned, including: In a case where the target channel is the clock channel, moving the data channel, and determining an initial clock channel in which the characteristic value is found in the data channel as a valid clock channel; determining a target delay value of the clock channel according to the plurality of valid clock channels, adjusting the clock channel according to the target delay value of the clock channel, and aligning the data channel with the clock channel; In a case where the target channel is the data channel, moving the data channel, and determining an initial data channel in which the characteristic value is found in the clock channel as a valid data channel; Determine a target delay value of the data channel according to the multiple valid data channels, adjust the data channel according to the target delay value of the data channel, align the data channel with the clock channel, and sample the image data in the data channel based on the rising edge of the aligned clock channel.

3. The method according to claim 1, characterized in that Obtain at least one initial delay value for the target channel, including: Get the preset step size; The delay value of the target channel is sequentially increased according to a preset step size to obtain the at least one initial delay value.

4. The method according to claim 2, characterized in that Determining a target delay value of the clock channel according to the plurality of valid clock channels includes: Sequentially shifting the data channels in the same direction by different integer bits, and determining the number of valid clock channels corresponding to the different integer bits, wherein the amplitude of the data channel shift is determined according to the spacing between adjacent rising edges and falling edges in the clock channels, and the number of the different integer bits is determined according to the number of bits of the characteristic value; Determine the integer bit with the largest number of valid clock channels as a first target integer bit, and determine the multiple valid clock channels corresponding to the first target integer bit as target clock channels; A target delay value of the clock channel is determined according to the delay value of the target clock channel.

5. The method according to claim 2, characterized in that Determining a target delay value of the data channel according to the plurality of valid data channels includes: Sequentially shifting the data channels in the same direction by different integer positions, and determining the number of valid data channels corresponding to different integer positions; Determine the integer bit with the largest number of valid data channels as a second target integer bit, and determine the multiple valid data channels corresponding to the second target integer bit as target data channels; A target delay value of the data channel is determined according to the delay value of the target data channel.

6. The method according to claim 4, characterized in that Determining the integer bit with the largest number of valid clock channels as a first target integer bit, and determining the multiple valid clock channels corresponding to the first target integer bit as target clock channels, including: Shifting the data channel to the left by odd and even bits respectively, and determining the number of valid clock channels corresponding to the left shift by odd bits and the number of valid clock channels corresponding to the left shift by even bits respectively; The number of valid clock channels corresponding to the left shift of odd bits is compared with the number of valid clock channels corresponding to the left shift of even bits, and the valid clock channels with the largest number are determined as the target clock channels.

7. The method according to claim 4, characterized in that Determining the integer bit with the largest number of valid clock channels as a first target integer bit, and determining the multiple valid clock channels corresponding to the first target integer bit as target clock channels, including: Shifting the data channel to the right by odd and even bits respectively, and determining the number of valid clock channels corresponding to shifting the data channel to the right by odd bits and the number of valid clock channels corresponding to shifting the data channel to the right by even bits respectively; The number of valid clock channels corresponding to the shifted odd bits is compared with the number of valid clock channels corresponding to the shifted even bits, and the valid clock with the largest number is determined as the target clock channel.

8. The method according to claim 6 or 7, characterized in that Determining a target delay value of the clock channel according to the delay value of the target clock channel includes: Obtaining delay values ​​of a plurality of target clocks; An average value of the delay values ​​of the plurality of target clocks is determined as the delay value of the clock channel.

9. The method according to claim 1, characterized in that Determining an initial clock channel in the data channel where the characteristic value is found as a valid clock channel includes: Obtaining the number of digits of the eigenvalue; When there are a target number of consecutive rising edges in the initial clock channel corresponding to each value of the characteristic value in sequence, the initial clock channel is determined to be the valid clock channel, wherein the target number is a multiple of the number of bits.

10. The method according to claim 9, characterized in that The method further comprises: Sampling the data channel at the rising edge of the clock channel; When the sampled value is equal to the characteristic value, it is determined that the data channel is aligned with the clock channel.

11. A method for acquiring image data, characterized in that: include: Obtaining characteristic values ​​for characterizing alignment between a data channel and a clock channel; Obtaining at least one initial delay value of the clock channel, and determining at least one initial clock channel according to the at least one initial delay value; Moving the data channel, and determining an initial clock channel in which the characteristic value is found in the data channel as a valid clock channel; determining a target delay value of the clock channel according to the valid clock channel, and adjusting the clock channel according to the target delay value so that the data channel and the clock channel are aligned; The image data in the data channel is sampled based on the aligned rising edge of the clock channel.

12. An image data acquisition device, characterized in that: include: A first acquisition module is used to obtain a characteristic value used to characterize the alignment of the data channel and the clock channel; a second acquisition module, configured to acquire at least one initial delay value of a target channel, and determine at least one initial target channel according to the at least one initial delay value, wherein the target channel is: the clock channel or the data channel; A moving module, configured to move the data channel and determine an initial target channel in which the characteristic value is found in the data channel as a valid target channel; a determining module, configured to determine a target delay value of the target channel according to the valid target channel, and adjust the target channel according to the target delay value so that the data channel and the clock channel are aligned; A sampling module is used to sample the image data in the data channel based on the aligned rising edge of the clock channel.

13. A three-dimensional scanning system, characterized in that: include: A scanner and a host computer, wherein the scanner is connected to the host computer; The scanner includes an image acquisition module, which is used to obtain image data of the surface of the object being measured; The image acquisition module is further used to obtain a characteristic value for characterizing the alignment of the data channel and the clock channel; Acquire at least one initial delay value of a target channel, and determine at least one initial target channel according to the at least one initial delay value, where the target channel is: the clock channel or the data channel; Moving the data channel, and determining an initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel according to the valid target channel, and adjusting the target channel according to the target delay value so that the data channel and the clock channel are aligned; Sampling the image data in the data channel based on the aligned rising edge of the clock channel; Transmitting the sampled image data to the host computer; The host computer is used to complete the three-dimensional reconstruction of the measured object based on the image data.

14. A computer device, characterized in that: include: a memory for storing program instructions; A processor, connected to the memory, is configured to execute program instructions for the following functions: obtaining a characteristic value for characterizing alignment between a data channel and a clock channel; Acquire at least one initial delay value of a target channel, and determine at least one initial target channel according to the at least one initial delay value, where the target channel is: the clock channel or the data channel; Moving the data channel, and determining an initial target channel in which the characteristic value is found in the data channel as a valid target channel; determining a target delay value of the target channel according to the valid target channel, and adjusting the target channel according to the target delay value so that the data channel and the clock channel are aligned; The image data in the data channel is sampled based on the aligned rising edge of the clock channel.

15. A non-volatile storage medium, characterized in that: The non-volatile storage medium includes a stored computer program, wherein the device where the non-volatile storage medium is located executes the image data acquisition method according to any one of claims 1 to 11 by running the computer program.

Images