Memory cell, semiconductor device, and memory device

Abstract

The memory cell includes first and second active regions and first, second, third, and fourth gate structures. The first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to engage the first active region when forming a first transistor, a second transistor, a third transistor, and a fourth transistor of a write port of the memory cell, respectively. The second and third gate structures are configured to further engage the second active region when forming fifth and sixth transistors of a write port of the memory cell. The memory cell also includes a fifth gate structure configured to engage the second active region when forming a seventh transistor of a read port of the memory cell. The second active region has a first segment providing a channel region for the seventh transistor and a second segment providing channel regions for the fifth transistor and the sixth transistor. The first segment and the second segment have different widths. The embodiment of the invention also relates to a memory cell, a semiconductor device and a memory device.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory cell, a semiconductor device, and a memory device. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. However, such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] Semiconductor memory is an electronic data storage device implemented on a semiconductor-based integrated circuit and has a much faster access time than other types of data storage technologies. For example, static random access memory (SRAM) devices are commonly used in integrated circuits. SRAM devices are popular in high-speed communications, image processing, and system-on-chip (SOC) applications. Bits can be read from or written to an SRAM cell in a few nanoseconds, while the access time for rotating storage such as hard disks is in the millisecond range.

[0004] When entering the deep submicron era, SRAM devices have become increasingly popular due to the lithography-friendly layout shapes of their active areas, polysilicon lines, and metal layers. Among SRAM devices, multi-port SRAM devices have become popular. For example, dual-port (2P) SRAM devices allow parallel operations, such as 1R (read) 1W (write) or 2R (read) in one cycle, and therefore have a higher bandwidth than single-port SRAM devices. However, in the deep submicron era, SRAM cells are generally large, especially for multi-port SRAM cells, due to insufficient area utilization. With the advancement of process nodes, there is a need for a multi-port SRAM structure with reduced cell size while maintaining key performance indicators such as, but not limited to, voltage dynamic data retention (VDDR), maximum operating voltage (Vmax), minimum operating voltage (Vmin), alpha ratio, and beta ratio. Summary of the Invention

[0005] Some embodiments of the present application provide a memory cell, comprising: a first active region and a second active region, wherein each of the first active region and the second active region extends longitudinally in a first direction; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, which are arranged in sequence from first to fourth along the first direction, wherein each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally in a second direction perpendicular to the first direction, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to form a first transistor, a second transistor, a third transistor, and a fourth gate structure respectively forming a write port of the memory cell; The memory cell is connected to a first transistor and a fourth transistor by connecting the first active region to the first active region, and the second gate structure and the third gate structure are configured to further connect the second active region when forming a fifth transistor and a sixth transistor of the write port of the memory cell; and a fifth gate structure extending longitudinally in the second direction, wherein the fifth gate structure is configured to connect the second active region when forming a seventh transistor of the read port of the memory cell, wherein the second active region has a first segment providing a channel region for the seventh transistor and a second segment providing a channel region for the fifth transistor and the sixth transistor, the first segment having a first width, and the second segment having a second width different from the first width.

[0006] Other embodiments of the present application provide a semiconductor device, comprising: a write port of a memory cell, wherein the write port includes at least a pull-up transistor, a pull-down transistor and a transfer gate transistor; and a read port of the memory cell, wherein the read port includes a transfer gate transistor, wherein: the transfer gate transistor in the write port is an n-type transistor, the transfer gate transistor in the read port is a p-type transistor, the channel region of the pull-down transistor in the write port and the channel region of the transfer gate transistor in the write port are arranged on a first active region, the channel region of the pull-up transistor in the write port and the channel region of the transfer gate transistor in the read port are arranged on a second active region extending parallel to the first active region, and the second active region has a variable width.

[0007] Still other embodiments of the present application provide a memory device, comprising: a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor, and a second pull-down transistor, which share a first active area extending in a first direction; a first pull-up transistor, a second pull-up transistor, and a read port pass-gate transistor, which share a second active area extending in the first direction; and an isolation component, adjacent to a gate structure of the first pass-gate transistor and extending longitudinally in a second direction perpendicular to the first direction, wherein the second active area is divided into a first segment and a second segment by the isolation component, and wherein the first segment and the second segment have different widths. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The presently disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is emphasized that, in accordance with standard industry practice, various components are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1A and Figure 1B A perspective view and a top view, respectively, of a portion of a memory device according to some embodiments of the present disclosure are shown.

[0010] Figure 2 Cross-sectional views of various layers of a memory device according to some embodiments of the present disclosure are shown.

[0011] Figure 3 A circuit schematic diagram for a dual-port SRAM cell according to some embodiments of the present disclosure is shown.

[0012] Figure 4 and Figure 5 The following are some examples according to the present disclosure: Figure 3 Schematic layout of the dual-port SRAM cell in .

[0013] Figure 6 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 12 、 Figure 13 、 Figure 14 、 Figure 15 、 Figure 16 、 Figure 17 、 Figure 18 、 Figure 19 、 Figure 20 and Figure 21 Some other embodiments of the present disclosure are shown based on Figure 3 Schematic layout of the SRAM array of dual-port SRAM cells in FIG.

[0014] Figure 7A 、 Figure 7B and Figure 11 A cross-sectional view of a portion of an SRAM array according to some embodiments of the present disclosure is shown.

[0015] Figure 22 A flow chart illustrating a method for forming an integrated circuit having a plurality of SRAM cells according to some embodiments of the present disclosure is shown.

[0016] Figure 23 、 Figure 24 、 Figure 25 、 Figure 26 、 Figure 27 、 Figure 28 、 Figure 29 、 Figure 30 、 Figure 31 、 Figure 32 、 Figure 33 、 Figure 34 、 Figure 35 、 Figure 36 、 Figure 37 、 Figure 38 、 Figure 39 、 Figure 40 and Figure 41 An integrated circuit with an SRAM cell according to some embodiments of the present disclosure is shown. Figure 22 A cross-sectional view during the manufacturing process of the method.

[0017] Figure 42 A plan view of a channel member in a gate-all-around (GAA) transistor of an integrated circuit according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing different features of the embodiments of the present disclosure. Specific examples of components and arrangements are described below to simplify the embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component do not directly contact each other.

[0019] In addition, the embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, in the following embodiments of the present disclosure, a component formed on another component that is connected to and / or coupled to another component may include an embodiment in which the components are directly in contact with each other, and may also include an embodiment in which additional components are formed between the components so that the components are not in direct contact. In addition, spatially relative terms such as "lower", "upper", "horizontal", "vertical", "above", "above", "below", "under", "upward", "downward", "top", "bottom" and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.) are used to facilitate understanding of the relationship between one component and another component of the embodiments of the present disclosure. Spatially relative terms are intended to cover different orientations of devices including components. Furthermore, when "about", "approximately", etc. are used to describe a number or a range of numbers, the term is intended to cover numbers within + / -10% of the described number, unless otherwise specified. For example, the term "about 5nm" covers a size range from 4.5nm to 5.5nm.

[0020] The present disclosure generally relates to memory devices, and more particularly to multi-port static random access memory (SRAM) cells. According to various exemplary embodiments, dual-port (2P) SRAM cells and corresponding layouts are provided. Some variations of some embodiments are discussed. In addition, some embodiments may be applicable to logic circuits.

[0021] Some exemplary embodiments relate to, but are not limited to, multi-gate devices. Multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCEs). One such multi-gate device that has been introduced is the fin field-effect transistor (FinFET). FinFETs are named for the fin-shaped structure that extends from the substrate on which they are formed and is used to form the FET channel. Another multi-gate device (introduced in part to address the performance challenges associated with FinFETs) is the gate-all-around (GAA) transistor. GAA transistors are named for their gate structure that can extend around the channel region (e.g., a nanosheet stack) to provide access to the channel on four sides. GAA transistors are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their structure allows them to be scaled rapidly while maintaining gate control and mitigating SCEs. The following disclosure will continue with one or more GAA examples to illustrate various embodiments of the present disclosure. However, it should be understood that the present application should not be limited to a particular type of device unless otherwise stated. For example, aspects of the embodiments of the present disclosure may also be applicable to implementations based on FinFETs or planar FETs.

[0022] The dual-port SRAM cell includes a pull-down (PD) transistor, a pull-up (PU) transistor, and a transfer gate (PG) transistor in the write port and one or more read port transfer gate (R-PG) transistors in the read port. In some embodiments, transistors of the same conductivity type (e.g., n-type or p-type) are formed on the same active area. The active area for a transistor refers to the area where the source region, drain region, and channel region are formed below the gate structure of the transistor. In this context, the active area is also referred to as an "oxide-defined (OD) region." The active area can be a three-dimensional (3D) structure for a multi-gate transistor. The dramatic reduction in IC size has produced densely packed active areas with ever-decreasing widths. In order to optimize transistor performance, the active area is typically set to a constant width to ensure that each transistor formed thereon will have the widest available channel area, especially for p-type transistors, which are more susceptible to insufficient current drive than n-type transistors. In some embodiments of the present disclosure, during the formation of the GAA transistor, a dielectric dummy layer replaces the sacrificial layer before the gate replacement process. This approach reduces the diffusion of impurities (e.g., germanium) from the sacrificial layer into the channel layer, thereby enhancing the channel integrity of the GAA transistor (e.g., having a flat edge with less etching loss otherwise caused by impurity diffusion) and current drive capability, particularly for p-type transistors. The improved current drive capability ensures that the p-type transistor can maintain satisfactory performance even when the active area width is not maximized. Therefore, allowing the width of the active area to be variable provides an additional adjustment parameter for fine-tuning SRAM performance.

[0023] The details of the device structure of the embodiments of the present disclosure are described in the accompanying drawings. The accompanying drawings have outlined the components of several embodiments so that those skilled in the art can better understand the detailed description below. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

[0024] Figure 1A and Figure 1B A perspective view and a top view, respectively, of a portion of an integrated circuit (IC) device 10 (such as an SRAM device) implemented using GAA transistors are shown. Figure 1AIC device 10 includes a substrate 12. Substrate 12 may include: elemental (single element) semiconductors such as silicon, germanium, and / or other suitable materials; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; alloy semiconductors such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. Substrate 12 may be a single layer of material having a uniform composition. Alternatively, substrate 12 may include multiple layers of materials having similar or different compositions suitable for IC device fabrication. In one example, substrate 12 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, substrate 12 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof. Various doped regions, such as source / drain (S / D) regions, may be formed in or on substrate 12. The doped region may be doped with an n-type dopant (such as phosphorus or arsenic) and / or a p-type dopant (such as boron), depending on design requirements. The doped region may be formed directly on the substrate 12 in a P-well structure, an N-well structure, a dual-well structure, or using a raised structure. The doped region may be formed by implanting dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques.

[0025] Three-dimensional active regions 14 are formed on substrate 12. Each of active regions 14 includes elongated nanostructures 26 (e.g., nanostructures 26) vertically stacked in a channel region defined in the active region and above a fin-shaped base. Figure 2 ). The fin-shaped base protrudes upwardly out of the substrate 12. A source / drain feature 16 is formed in the source / drain region defined in the active region and above the fin-shaped base. The source / drain feature 16 abuts two opposite ends of the nanostructure 26. The source / drain feature 16 may include an epitaxial layer epitaxially grown on the fin-shaped base. It should be noted that although the source / drain feature 16 is shown as having a uniform width along the Y direction, this is for illustrative purposes only. As will be described below with at least reference to Figures 12 to 21 As discussed, there may be inflections in the active region. These inflections may produce variations in the width of segments of the active region, and thus in the width of the source / drain features 16. Generally, segments of the active region with greater widths correspond to wider source / drain features 16, and vice versa.

[0026] IC device 10 also includes an isolation structure (or isolation feature) 18 formed above substrate 12. Isolation structure 18 electrically separates the various components of IC device 10. Isolation structure 18 may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low-k dielectric material, and / or other suitable materials. In some embodiments, isolation structure 18 may include a shallow trench isolation (STI) feature. In one embodiment, isolation structure 18 is formed by etching a trench in substrate 12 during the formation of active area 14. The trench may then be filled with the isolation material described above, followed by a chemical mechanical planarization (CMP) process. Other isolation structures such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures may also be implemented as isolation structure 18. Optionally, isolation structure 18 may include a multilayer structure, for example, having one or more thermal oxide liner layers.

[0027] The IC device 10 also includes a gate structure (or gate stack, or simply gate) 20 formed above and in contact with the active region 14. The gate structure 20 can be a dummy gate structure (e.g., including an oxide gate dielectric and a polysilicon gate electrode), or it can be a high-k metal gate (HKMG) structure including a high-k gate dielectric and a metal gate electrode, wherein the HKMG structure is formed by replacing the dummy gate structure. Although not depicted herein, the gate structure 20 can include additional material layers, such as an interface layer, a capping layer, other suitable layers, or combinations thereof.

[0028] refer to Figure 1B , a plurality of active regions 14 are longitudinally oriented along the X direction, and a plurality of gate structures 20 are longitudinally oriented along the Y direction, i.e., generally perpendicular to the active regions 14. Transistors are formed at the intersections of the active regions 14 and the gate structures 20. In many embodiments, the IC device 10 includes additional components, such as gate spacers disposed along the sidewalls of the gate structures 20, and a number of other components.

[0029] Figure 2 It is along Figure 1A A partial schematic cross-sectional view of line AA, Figure 2 1 shows various layers (levels) that may be fabricated above substrate 12 according to various aspects of the disclosed embodiments. Figure 2In the embodiment, the various layers include a device layer DL and a multi-layer interconnect MLI disposed above the device layer DL. The device layer DL includes devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or device components (e.g., doped wells, gate structures, and / or source / drain features). In some embodiments, the device layer DL includes a substrate 12, a doped region 15 (e.g., an n-well and / or a p-well) disposed in the substrate 12, an isolation feature 18, and a transistor T. In the depicted embodiment, the transistor T includes a suspended nanostructure (channel member) 26 disposed between the source / drain features 16 and a gate structure 20, wherein the gate structure 20 wraps around and / or surrounds the suspended nanostructure 26. The nanostructure 26 may include a nanosheet, a nanotube, a nanowire, or some other type of nanostructure extending horizontally in the X direction. Each gate structure 20 has a metal gate structure formed by a gate electrode 22 disposed above a gate dielectric 24 and gate spacers 25 disposed along the sidewalls of the metal gate structure.

[0030] The multilayer interconnect MLI electrically couples the various devices and / or components of the device layer DL so that the various devices and / or components can operate as dictated by the design requirements for the memory. In the depicted embodiment, the multilayer interconnect MLI includes a contact layer (CO level), a via zero layer (V0 level), a metal zero (M0) level, a via one layer (V1 level), a metal one layer (M1 level), a via two layer (V2 level), a metal two layer (M2 level), a via three layer (V3 level), and a metal three layer (M3 level). The disclosed embodiments contemplate multilayer interconnects MLI having more or fewer layers and / or levels, for example, a total number of N metal layers (levels) of the multilayer interconnect MLI, where N is an integer ranging from 2 to 10. Each level of the multilayer interconnect MLI includes conductive features (e.g., metal lines, metal vias, and / or metal contacts) disposed in one or more dielectric layers (e.g., an interlayer dielectric (ILD) layer and a contact etch stop layer (CESL)). In some embodiments, conductive features at the same level (such as the M1 level) of the multilayer interconnect MLI are formed simultaneously. In some embodiments, the conductive features at the same level of the multilayer interconnect MLI have top surfaces that are substantially coplanar with each other and / or bottom surfaces that are substantially coplanar with each other. The CO level includes a source / drain contact (MD) disposed in the dielectric layer 28; the V0 level includes a gate via VG, a source / drain contact via VD, and a docking contact disposed in the dielectric layer 28; the M0 level includes an M0 metal line disposed in the dielectric layer 28, wherein the gate via VG connects the gate structure to the M0 metal line, the source / drain via V0 connects the source / drain to the M0 metal line, and the docking contact connects the gate structure and the source / drain together and to the M0. Metal lines; V1 level includes V1 vias disposed in dielectric layer 28, wherein the V1 vias connect the M0 metal line to the M1 metal line; M1 level includes M1 metal line disposed in dielectric layer 28; V2 level includes V2 vias disposed in dielectric layer 28, wherein the V2 vias connect the M1 line to the M2 line; M2 level includes M2 metal line disposed in dielectric layer 28; V3 level includes V3 vias disposed in dielectric layer 28, wherein the V3 vias connect the M2 line to the M3 line. For clarity, the diagram has been simplified. Figure 2 , to better understand the inventive concepts of the disclosed embodiments. Additional components may be added in various layers of the memory, and some of the described components may be replaced, modified, or eliminated in other embodiments of the memory. Figure 2 These are examples only and may not reflect an actual cross-sectional view of the IC device 10 and / or the SRAM cell 100 , which are discussed in further detail below.

[0031] Now refer to Figure 3, shows an exemplary circuit schematic for a dual-port SRAM cell 100. The dual-port SRAM cell 100 includes a write port 100W and a read port 100R. The write port 100W includes pull-up transistors PU-1 and PU-2, pull-down transistors PD-1 and PD-2, and pass-gate transistors PG-1 and PG-2. In the illustrated embodiment, transistors PU-1 and PU-2 are p-type transistors, and transistors PG-1, PG-2, PD-1, and PD-2 are n-type transistors.

[0032] The drains of pull-up transistor PU-1 and pull-down transistor PD-1 are coupled together, and the drains of pull-up transistor PU-2 and pull-down transistor PD-2 are coupled together. Transistors PU-1 and PD-1 are cross-coupled with transistors PU-2 and PD-2 to form a data latch. The gates of transistors PU-1 and PD-1 are coupled together and to the common drain of transistors PU-2 and PD-2 to form a storage node SN, and the gates of transistors PU-2 and PD-2 are coupled together and to the common drain of transistors PU-1 and PD-1 to form a complementary storage node SNB. The sources of pull-up transistors PU-1 and PU-2 are coupled to a power supply voltage Vdd (also referred to as Vcc), and the sources of pull-down transistors PD-1 and PD-2 are coupled to a voltage Vss, which may be electrical ground in some embodiments.

[0033] The storage node SN of the data latch is coupled to the bit line W_BL of the write port 100W through the pass-gate transistor PG-2, and the complementary storage node SNB is coupled to the complementary bit line W_BLB of the write port 100W through the pass-gate transistor PG-1. The storage node SN and the complementary storage node SNB are complementary nodes that are generally at opposite logic levels (logic high or logic low). The gates of the pass-gate transistors PG-1 and PG-2 are coupled to the word line W_WL of the write port 100W.

[0034] The read port 100R of the SRAM cell 100 includes a read port pass-gate transistor (R-PG) coupled between the bit line R_BL and the storage node SN (or coupled to the gates of transistors PU-1 and PD-1). The gate of the read port pass-gate transistor R-PG is coupled to the word line R_WL of the read port 200R. In the embodiment shown, transistor R-PG is a p-type transistor. That is, in the dual-port SRAM cell 100, the pass-gate transistor in the write port is an n-type transistor, and the pass-gate transistor in the read port is a p-type transistor.

[0035] Figure 4A simplified schematic layout 200 of a dual-port SRAM cell 100 is shown, which includes a write port 100W and a read port 100R. The write port 100W includes transistors PG-1, PG-2, PU-1, PU-2, PD-1, and PD-2. The read port 100R includes transistor R-PG. For reasons of visual clarity and simplicity, the active areas and gate structures of these transistors are shown in FIG. 1 along with some gate cut features. Figure 4 , while interconnect components such as contacts, vias, and metal lines are shown in FIG. Figure 4 Omit.

[0036] like Figure 4 As shown in FIG, the dual-port SRAM cell 100 includes active regions 202 and 204. The active regions 202, 204 are each Figure 4 In the illustrated embodiment, the active regions 202, 204 may each include (or may be implemented as) the above-discussed Figure 2 Nanostructure 26. In other embodiments, active regions 202 and 204 may also include fin structures. Active region 202 is a component of write port 100W, and active region 204 has a side portion that is a component of read port 100R and the remaining portion that is a component of write port 100W. In other words, active region 204 is shared by read port 100R and write port 100W. In the illustrated embodiment, active region 204 belongs to transistors PU-1, PU-2, and R-PG, which are p-type transistors. Therefore, active region 204 is formed above N-well 206. At the same time, active region 202 belongs to transistors PG-1, PD-1, PD-2, and PG-2, which are n-type transistors. Therefore, active region 202 is formed above P-well 208 (or P-type substrate).

[0037] The dual-port SRAM cell 100 further includes gate structures 212, 214, 216, 218, and 220. Each of the gate structures 212-220 is Figure 4 The gate structures 212-220 may each include (or may be implemented as) the above-discussed Figure 2 1. Gate structure 20. Gate structures 212, 214, 216, and 220 are components of write port 100W. Gate structure 218 is a component of read port 100R. Gate structures 214, 216 each extend through both active regions 202, 204. Thus, gate structure 214 is shared by transistors PD-1 and PU-1, and gate structure 216 is shared by transistors PD-2 and PU-2.

[0038] The dual-port SRAM cell 100 further includes a plurality of gate-cut dielectric features, including a dielectric feature 230 extending longitudinally along the X-direction and a dielectric feature 232 extending longitudinally along the Y-direction. In the illustrated embodiment, the dielectric feature 230 is disposed between the active regions 202 and 204 and abuts the gate structure 218 and the gate structure 220. Furthermore, the dielectric feature 230 is disposed above the interface between the N-well 206 and the P-well 208. The dielectric feature 230 divides the otherwise continuous gate structure into two isolated segments corresponding to the gate structure 218 and the gate structure 220. The dielectric feature 230 is formed by filling corresponding cut metal gate (CMG) trenches in the locations of the dielectric features. The dielectric feature 230 is also referred to as a CMG feature 230.

[0039] The dielectric component 232 is formed in a continuous polysilicon on diffusion edge (CPODE) process. For the purposes of the embodiments of the present disclosure, a "diffusion edge" may be equivalently referred to as an active edge, where, for example, the active edge abuts an adjacent active area. The dielectric component 232 is also referred to as a CPODE component 232. Prior to the CPODE process, the active edge may include a pseudo GAA structure having a dummy gate structure (e.g., a polysilicon gate) and a plurality of vertically stacked nanostructures as a channel layer. In addition, internal spacers may be provided between adjacent nanostructures at the lateral ends of the nanostructures. In various instances, the source / drain epitaxial component is provided on either side of the pseudo GAA structure so that adjacent source / drain epitaxial components are in contact with the internal spacers and nanostructures of the pseudo GAA structure. A subsequent CPODE etching process removes the dummy gate structure and channel layer from the pseudo GAA structure to form a CPODE trench. The dielectric material filling the CPODE trench for isolation is referred to as a CPODE component. In some embodiments, after forming the CPODE feature, the remaining dummy gate structure is replaced by a metal gate structure in a replacement gate (gate-last) process. In other words, in some embodiments, the CPODE feature replaces a portion of an otherwise continuous gate structure and is confined between opposing gate spacers of the replaced portion of the gate structure. In contrast, the CMG feature interrupts an otherwise continuous gate structure and extends into adjacent regions of the gate structure. Figure 4 In the embodiment shown in FIG. 2 , the CPODE component 232 abuts the gate structure 212 and is aligned with the gate structure 212. The CPODE component 232 extends along the Y direction and across the N-well 206 to the other P-well 208 of the adjacent SRAM cell. In other words, two adjacent SRAM cells can share the CPODE component 232. Furthermore, in some embodiments, the CPODE component 232 can extend deeper into the underlying substrate than the CMG component 230.

[0040] Still refer to Figure 4, a boundary 240 of the dual-port SRAM cell 100 is shown using a dashed line. It is worth noting that some active areas and gate structures may extend beyond this illustrated boundary 240, as these components may also form part of adjacently positioned SRAM cells. The boundary 240 is rectangular, wherein its length in the X direction exceeds its length in the Y direction. The first dimension of the boundary 240 along the X direction is denoted as the cell width W, while the second dimension along the Y direction is denoted as the cell height H. In the context of a memory array of repeating dual-port SRAM cells 100, the cell width W may be referred to as the memory cell pitch along the X direction, and the cell height H may be referred to as the memory cell pitch along the Y direction.

[0041] The cell size of the dual-port SRAM cell 100 is W×H, where the cell width W is approximately 4 times the poly pitch (e.g., the center-to-center distance between two adjacent gate structures along the X direction), and the cell height H is approximately 2 times the isolation pitch (e.g., the center-to-center distance between two adjacent STI features along the Y direction). An area of ​​one poly pitch multiplied by one isolation pitch is represented as a unit area, each unit area includes the intersection of the gate structure and the active area, and the dual-port SRAM cell 100 utilizes a cell size of approximately 8 times the unit area when accommodating seven transistors (i.e., transistors PG-1, PG-2, PU-1, PU-2, PD-1, PD-2, and R-PG). The area utilization is considered high because there is only one unit area that is not used to form a functional transistor, but rather accommodates the intersection of the CPODE feature and the active area.

[0042] The active region 202 for the n-type transistor has a W N The width of the active region 204 for the p-type transistor is denoted as W P Each of the gate structures 212-220 has a critical dimension (CD) or gate width denoted as G. In some embodiments, G is in a range from about 10 nm to about 20 nm, and W N In the range from about 11 nm to about 35 nm, and W P In the range of from about 11 nm to about 35 nm. In some embodiments, W P Equal to W N (W P =W N ) to balance the read port speed and the write port speed. In some embodiments, W P Greater than W N (W P >W N ) to better accommodate read port speed requirements. In some embodiments, W P Less than W N (W P<W N ) to better accommodate write port speed requirements. Due to limited p-type carrier mobility, p-type transistors typically have lower current driving capabilities than n-type transistors. To address this issue, the active area 204 can conventionally have a constant width W P , ensuring that each p-type transistor formed thereon has the widest available channel area. However, the disclosed embodiment implements a modified method in GAA transistor fabrication (described later on). Figures 22 to 42 Detailed discussion) which improves the etch selectivity during the gate replacement process. This enhancement significantly improves the current drive capability of the GAA transistor, especially for p-type transistors. Thus, this improvement allows some transistors formed on the active area 204 to have varying widths without compromising current drive capability. In other words, in some embodiments, the active area 204 can now be formed with variable widths. P This concept will be further elaborated later in the embodiments of the present disclosure.

[0043] Figure 5 An alternative schematic layout 200' of the dual-port SRAM cell 100 is shown. Many aspects of the alternative layout 200' are similar to those of the Figure 4 For reasons of clarity and consistency, the layout 200 shown in Figure 4 and Figure 5 Similar elements in the layout are labeled the same, and the details of these elements do not need to be repeated again below. Unlike layout 200, in optional layout 200', there is no CPODE component 232 in optional layout 200', but there is an additional CMG component 230' and an additional gate structure 212'. The CMG component 230' is arranged between the active areas 202, 204 and is adjacent to the gate structure 212 and the gate structure 212'. In addition, the dielectric component 230' is arranged above the interface between the N-well 206 and the P-well 208. The dielectric component 230' divides the originally continuous gate structure into two isolation segments corresponding to the gate structure 212 and the gate structure 212'. The gate structure 212' covers the edge of one end of the active area 204. At the same time, the end of the active area 204 does not extend beyond the other side of the gate structure 212 in the X direction. Therefore, a non-functional transistor (represented as T nf ).

[0044] Figure 6 FIG. 3 shows a layout 300 of an SRAM array according to an embodiment of the present disclosure. Figure 6 , multiple dual-port SRAM cells 100a, 100b, 100c and 100d are arranged in the X direction and the Y direction to form a 2×2 array of SRAM cells. Each SRAM cell in the array can be used as Figure 4 . In some embodiments, two adjacent SRAM cells in the X direction are line-symmetric with respect to a common boundary therebetween, and two adjacent SRAM cells in the Y direction are line-symmetric with respect to a common boundary therebetween. That is, SRAM cell 100b is a copy of SRAM cell 100a, but flipped over the Y axis; SRAM cell 100c is a copy of SRAM cell 100a, but flipped over the X axis; and SRAM cell 100d is a copy of SRAM cell 100b, but flipped over the X axis. For clarity, the diagram has been simplified. Figure 6 , in order to better understand the inventive concept of the embodiments of the present disclosure. For example, the active region, gate structure, CPODE component, N well, P well and cell boundary are shown, while some other components are omitted. Figure 6 As depicted in FIG, the layout 300 of the SRAM array includes well regions 206 and 208 arranged alternately along the Y axis. In other words, each P-well 208 is adjacent to an N-well 206, which is adjacent to another P-well 208, and this pattern repeats. Figure 6 In the embodiment shown in FIG, the gate structure in each dual-port SRAM cell does not extend beyond the corresponding cell boundary, and each CPODE component is shared by two adjacent SRAM cells arranged in the Y direction.

[0045] Figure 7A According to various aspects of the embodiments of the present disclosure Figure 6 A partial schematic cross-sectional view of line AA (line AA cuts the active region 204 along the longitudinal direction of the active region 204 ). Figure 7B According to various aspects of the embodiments of the present disclosure Figure 6 A partial schematic cross-sectional view of line BB (BB line cutting CPODE component). Figure 7A and Figure 7B , the active area 204 extends through the SRAM cells 100a, 100b, but is sandwiched between the CPODE components in the SRAM cell 100a and the CPODE components in the SRAM cell 100b. The CPODE components replace the original metal gate structure closest to the cell edge. The distance between the CPODE components in the SRAM cell 100a and the CPODE components in the SRAM cell 100b (CPODE to CPODE spacing) is 7 times the poly pitch. To better illustrate the arrangement of the CPODE components, Figure 7A Also depicted in FIG. 1 are additional CPODE features in the SRAM cell located to the left of the SRAM cell 100 a and additional CPODE features in the SRAM cell located to the right of the SRAM cell 100 b along the X direction.

[0046] Between the CPODE features in SRAM cell 100a and the CPODE features in SRAM cell 100b, active region 204 includes a channel region consisting of nanostructures 26 and source / drain features 16 adjacent to the ends of nanostructures 26. Gate structures wrap around nanostructures 26 and form transistors PU-1, PU-2, and R-PG in SRAM cell 100a and transistors R-PG, PU-2, and PU-1 in SRAM cell 100b. Active region 204 is disposed over an N-well 206, and active region 202 is disposed over a P-well 208. Source / drain features 16 formed over active region 204 are p-type epitaxial features, and source / drain features 16 formed over active region 202 are n-type epitaxial features. Isolation structure 18 may include shallow trench isolation (STI) features. In one embodiment, isolation structure 18 is formed by etching trenches in substrate 12 during the formation of active regions 202 and 204. The isolation structure 18 may include a multi-layer structure, for example, having an oxide liner 18a (e.g., a thermal SiO2 liner), a first dielectric layer 18b (e.g., SiOCN), and a second dielectric layer 18c (e.g., SiO2). It should be noted that a hard mask layer 50 is deposited on the isolation structure 18. The composition of the hard mask layer 50 is different from that of the isolation features 18 to ensure that each of them can be selectively etched without substantially damaging the other. The hard mask layer 50 may be a single layer or a multi-layer. For example, the hard mask layer 50 may include an oxide liner 50a (e.g., SiO2 or SiON) and a nitride layer 50b (e.g., SiN or SiON) disposed above the oxide liner 50a. The presence of the hard mask layer 50 stacked between the isolation feature 18 and the CPODE feature is a distinguishing feature of the modified method employed in the manufacture of GAA transistors (to be discussed later). Figures 22 to 42 (discussed in detail).

[0047] Figure 8 An alternative layout 300' for an SRAM array is shown. Many aspects of the alternative layout 300' are similar to Figure 6 For reasons of clarity and consistency, the layout 300 shown in Figure 6 and Figure 8 Unlike the layout 300, in the alternative layout 300', the end portion of the active area 204 extending beyond the CPODE component has a reduced width W. P '(W P ' <W PThe location where the width of the active area changes abruptly is called an "inflection." In the depicted embodiment, the inflection of the active area 204 is located below the CPODE feature and is located on the side of the active area 204 facing the adjacent active area 202. The opposite side of the active area 204 facing the adjacent active area 204 does not have an inflection.

[0048] Figure 9 An alternative layout 300 of an SRAM array is shown. Many aspects of the alternative layout 300 are similar to Figure 8 For reasons of clarity and consistency, the layout 300' shown in Figure 8 and Figure 9 Similar elements in the alternative layout 300 are labeled the same, and the details of these elements are not necessarily repeated again below. Unlike the layout 300 ′, in the alternative layout 300 ″, the kinks of the active area 204 are positioned on both sides of the active area 204 .

[0049] Figure 10 An alternative layout 400 of an SRAM array is shown. Figure 10 , multiple dual-port SRAM cells 100a, 100b, 100c and 100d are arranged in the X direction and the Y direction to form a 2×2 array of SRAM cells. Each SRAM cell in the array can be used as Figure 5 Many aspects of the optional layout 400 are similar to the layout 200' depicted in FIG. Figure 6 For reasons of clarity and consistency, the layout 300 shown in Figure 6 and Figure 10 Similar elements in the alternative layout 400 are labeled the same, and the details of these elements are not necessarily repeated below. Unlike the layout 300, in the alternative layout 400, there is no CPODE component, but a non-functional transistor T is formed. nf When the additional gate structure covers the edge of the end portion of the active region 204, the end portion of the active region 204 does not extend beyond the other side of the corresponding additional gate structure along the X direction.

[0050] Figure 11 According to various aspects of the embodiments of the present disclosure Figure 10 A partial schematic cross-sectional view of the CC line (CC line cuts the active region 204 along the longitudinal direction of the active region 204). Figure 7A Different from the cross-sectional view depicted in FIG, the active region 204 is sandwiched between the isolation member 18 and the non-functional transistor T disposed on the end of the active region 204. nfA hard mask layer 50 is deposited on the isolation feature 18. The gate spacers 25 and the dielectric layer 28 (which may include a contact etch stop layer (CESL) and an interlayer dielectric (ILD) layer) are disposed on the hard mask layer 50. The presence of the hard mask layer 50 stacked between the isolation feature 18 and the gate spacers 25 is a distinguishing feature of the modified method employed in GAA transistor fabrication (discussed later). Figures 22 to 42 (discussed in detail).

[0051] Figure 12 An alternative layout 500 of an SRAM array is shown, which is modified by Figure 6 Many aspects of the optional layout 500 are similar to Figure 6 For reasons of clarity and consistency, the layout 300 shown in Figure 6 and Figure 12 Like elements in FIG are labeled the same, and the details of these elements need not be repeated below. Unlike layout 300, in alternative layout 500, active area 204 does not have a constant width W. P , but the segment providing the channel region for the R-PG transistor has a smaller width W P '(W P >W P '). In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P As discussed above, the width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements. By providing pull-up transistors PU-1, PU-2 with wider channel areas and read port pass gate transistor R-PG with narrower channel areas, the VDDR of the SRAM device can be improved, such as by about 30mV to about 80mV. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 0.75 to about 1 (0.75 <W P ' / W P <1). The range is not trivial or arbitrary. If the ratio is not greater than about 0.75, the channel width for transistor R-PG may be too small to provide sufficient current drive capability; if the ratio is not less than 1, transistors PU-1 and PU-2 may not have a stronger current drive capability than transistor R-PG to achieve VDDR improvement. In some embodiments, the difference between the widths (W P -W P') can be in a range from about 2 nm to about 8 nm. In the depicted embodiment, the inflections of the active region 204 are all located on the side of the active region 204 that faces the adjacent active region 202. The opposite side of the active region 204 that faces the adjacent active region 204 does not have an inflection. Each inflection of the active region 204 is located along the X-direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG, such as at a midpoint between the two gate structures.

[0052] Figure 13 An alternative layout 600 of an SRAM array is shown, which is modified by Figure 10 Many aspects of the optional layout 600 are similar to Figure 10 For reasons of clarity and consistency, the layout 400 shown in Figure 10 and Figure 13 Like elements in FIG are labeled the same, and the details of these elements need not be repeated again below. Unlike layout 400, in alternative layout 600, active area 204 does not have a constant width W. P , but the segment providing the channel region for the R-PG transistor has a smaller width W P '(W P >W P '). In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P As discussed above, the width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements. By providing pull-up transistors PU-1, PU-2 with wider channel areas and read port pass gate transistor R-PG with narrower channel areas, the VDDR of the SRAM device can be improved, such as by about 30mV to about 80mV. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 0.75 to about 1 (0.75 <W P ' / W P <1). The range is not trivial or arbitrary. If the ratio is not greater than about 0.75, the channel width for transistor R-PG may be too small to provide sufficient current drive capability; if the ratio is not less than 1, transistors PU-1 and PU-2 may not have a stronger current drive capability than transistor R-PG to achieve VDDR improvement. In some embodiments, the difference between the widths (W P -W P') can be in a range from about 2 nm to about 8 nm. In the depicted embodiment, the inflections of the active region 204 are all located on the side of the active region 204 that faces the adjacent active region 202. The opposite side of the active region 204 that faces the adjacent active region 204 does not have an inflection. Each inflection of the active region 204 is located along the X-direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG, such as at a midpoint between the two gate structures.

[0053] Figure 14 An alternative layout 700 of an SRAM array is shown, which is modified by Figure 6 Many aspects of the optional layout 700 are similar to those of the Figure 6 For reasons of clarity and consistency, the layout 300 shown in Figure 6 and Figure 14 Like elements in the FIGURE 7 are labeled the same, and the details of these elements need not be repeated below. Unlike the layout 300, in the alternative layout 700, the active area 204 does not have a constant width W. P , but the segment providing the channel region for the pull-up transistors PU-1, PU-2 is extended to have a larger width W P '(W P '>W P In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P Width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements, but is smaller than the width W P By providing pull-up transistors PU-1 and PU-2 with wider channel regions and read port pass gate transistor R-PG with narrower channel regions, the VDDR of the SRAM device can be improved, such as by about 30 mV to about 80 mV. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 1 to about 1.25 (1 <W P ' / W P<1.25). The range is not trivial or arbitrary. If the ratio is not less than about 1.25, the channel widths for transistors PU-1, PU-2 may be too large and become too close to the adjacent active area 202; if the ratio is not greater than 1, transistors PU-1, PU-2 may not have a stronger current drive capability than transistor R-PG to achieve VDDR improvement. In some embodiments, the difference between the widths (W P '-W P ) can be in a range from about 2 nm to about 10 nm. In the depicted embodiment, the inflections of the active region 204 are positioned on both sides of the active region 204. Each inflection of the active region 204 is positioned along the X direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG (such as a midpoint between the two gate structures) or under a corresponding CPODE component.

[0054] Figure 15 An alternative layout 800 of an SRAM array is shown, which is modified by Figure 10 Many aspects of the optional layout 800 are similar to Figure 10 For reasons of clarity and consistency, the layout 400 shown in Figure 10 and Figure 15 Like elements in the FIG400 are labeled the same, and the details of these elements need not be repeated again below. Unlike the layout 400, in the alternative layout 800, the active area 204 does not have a constant width W. P , but the segment providing the channel region for the pull-up transistors PU-1, PU-2 is extended to have a larger width W P '(W P '>W P In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P Width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements, but is smaller than the width W P By providing pull-up transistors PU-1 and PU-2 with wider channel regions and read port pass gate transistor R-PG with narrower channel regions, the VDDR of the SRAM device can be improved, such as by about 30 mV to about 80 mV. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 1 to about 1.25 (1 <W P ' / WP <1.25). The range is not trivial or arbitrary. If the ratio is not less than about 1.25, the channel widths for transistors PU-1, PU-2 may be too large and become too close to the adjacent active area 202; if the ratio is not greater than 1, transistors PU-1, PU-2 may not have a stronger current drive capability than transistor R-PG to achieve VDDR improvement. In some embodiments, the difference between the widths (W P '-W P ) can be in a range from about 2 nm to about 10 nm. In the depicted embodiment, the inflections of active region 204 are positioned on both sides of active region 204. Each inflection of active region 204 is positioned along the X direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG, such as a midpoint between the two gate structures.

[0055] Figure 16 An alternative layout 800' of an SRAM array is shown. The alternative layout 800' is Figure 15 Unlike the layout 800, in the alternative layout 800', the inflections of the active area 204 are all located on the side of the active area 204 facing the adjacent active area 202. The opposite side of the active area 204 facing the adjacent active area 204 has no inflection.

[0056] Figure 17 An alternative layout 800" of an SRAM array is shown. The alternative layout 800" is Figure 15 . Unlike layout 800, in alternative layout 800", the inflections of the active area 204 are all located on the side of the active area 204 facing the adjacent active area 204. The opposite side of the active area 204 facing the adjacent active area 202 does not have an inflection. The choice of layouts 800, 800' and 800" depends mainly on the distance requirements between adjacent active areas of the same type and opposite type, especially when design rules have set restrictions on the minimum distance between adjacent active areas of the same type and / or opposite type.

[0057] Figure 18 An alternative layout 900 of an SRAM array is shown, which is modified by Figure 6 Many aspects of the optional layout 900 are similar to those of the Figure 6 For reasons of clarity and consistency, the layout 300 shown in Figure 6 and Figure 18 Like elements in FIG are labeled the same, and the details of these elements need not be repeated again below. Unlike layout 300, in alternative layout 900, active area 204 does not have a constant width W. P, but the segment providing the channel region for the pull-up transistors PU-1, PU-2 has a smaller width W P '(W P >W P '). In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P Width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements, but is greater than the width W P By providing pull-up transistors PU-1 and PU-2 with narrower channel areas and read port pass gate transistor R-PG with larger channel areas, the Vmin of the SRAM device can be improved. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 0.75 to about 1 (0.75 <W P ' / W P <1). This range is not trivial or arbitrary. If the ratio is not greater than about 0.75, the channel widths used for transistors PU-1 and PU-2 may be too small to provide sufficient current drive capability; if the ratio is greater than 1, transistor R-PG will not have a current drive capability greater than that of transistors PU-1 and PU-2 to achieve Vmin improvement. In some embodiments, the difference between the widths (W P '-W P ) can be in a range from about 2 nm to about 8 nm. In the depicted embodiment, the inflections of the active region 204 are all located on the side of the active region 204 that faces the adjacent active region 202. The opposite side of the active region 204 that faces the adjacent active region 204 does not have an inflection. Each inflection of the active region 204 is located along the X-direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG, such as at a midpoint between the two gate structures.

[0058] Figure 19 An alternative layout 1000 of an SRAM array is shown, which is modified by Figure 10 Many aspects of the optional layout 1000 are similar to Figure 10 For reasons of clarity and consistency, the layout 400 shown in Figure 10 and Figure 19Like elements in the FIGURE 10 are labeled the same, and the details of these elements need not be repeated below. Unlike the layout 400, in the alternative layout 1000, the active area 204 does not have a constant width W. P , but the segment providing the channel region for the pull-up transistors PU-1, PU-2 has a smaller width W P '(W P >W P '). In a further implementation of the embodiment, the width W of the active area 202 N Equal to width W P (W N =W P Width W N Can optionally be smaller or larger than the width W P , which depends on the device performance requirements, but is greater than the width W P By providing pull-up transistors PU-1 and PU-2 with narrower channel areas and read port pass gate transistor R-PG with larger channel areas, the Vmin of the SRAM device can be improved. In some embodiments, W P 'With W P The ratio (W P ' / W P ) can be in the range of from about 0.75 to about 1 (0.75 <W P ' / W P <1). This range is not trivial or arbitrary. If the ratio is not greater than about 0.75, the channel widths used for transistors PU-1 and PU-2 may be too small to provide sufficient current drive capability; if the ratio is greater than 1, transistor R-PG will not have a current drive capability greater than that of transistors PU-1 and PU-2 to achieve Vmin improvement. In some embodiments, the difference between the widths (W P '-W P ) can be in a range from about 2 nm to about 8 nm. In the depicted embodiment, the inflections of the active region 204 are all located on the side of the active region 204 that faces the adjacent active region 202. The opposite side of the active region 204 that faces the adjacent active region 204 does not have an inflection. Each inflection of the active region 204 is located along the X-direction between the gate structure of transistor PU-2 and the gate structure of transistor R-PG, such as at a midpoint between the two gate structures.

[0059] Figure 20 An alternative layout 1000' of an SRAM array is shown. The alternative layout 1000' is Figure 19 Unlike the layout 1000 , in the alternative layout 1000 ′, the kinks of the active area 204 are positioned on both sides of the active area 204 .

[0060] Figure 21 An alternative layout 1000" of an SRAM array is shown. The alternative layout 1000" is Figure 19 . Unlike layout 1000, in alternative layout 1000", the inflections of the active area 204 are all located on the side of the active area 204 facing the adjacent active area 204. The opposite side of the active area 204 facing the adjacent active area 202 does not have an inflection. The choice of layouts 1000, 1000' and 1000" depends mainly on the distance requirements between adjacent active areas of the same type and opposite type, especially when design rules have set restrictions on the minimum distance between adjacent active areas of the same type and / or opposite type.

[0061] In order to achieve this by introducing a variable active area width (e.g. Figures 12 to 21 W in P and W P ') to support fine tuning of SRAM device performance, the current driving capability of the transistor, especially the p-type transistor formed on the p-type active area, needs to have a performance margin (design margin). In view of this requirement, the embodiment of the present disclosure implements a modified method in the manufacture of GAA transistors, which improves the current driving capability of the GAA transistor, and therefore, such an improvement allows the active area to change width without compromising the current driving capability of the transistor. The manufacturing process will now be described in detail with reference to the following drawings. In this regard, Figure 22 2 is a flow chart illustrating a method 2000 for forming a semiconductor device from a work-in-progress (WIP) structure according to an embodiment of the present disclosure. The method 2000 is merely an example and is not intended to limit the disclosed embodiments to those explicitly shown in the method 2000. Additional steps may be provided before, during, and after the method 2000, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Figures 23 to 42 Describe Method 2000, Figures 23 to 42 is based on Figure 22 FIG20 is a partial cross-sectional view of a WIP structure 3000 at different stages of fabrication according to an embodiment of the method 2000 in FIG20. Because the WIP structure 3000 is to be fabricated into a semiconductor device or semiconductor structure, such as the IC device 10 (including a memory array including the SRAM cell 100), the WIP structure 3000 may be referred to herein as a semiconductor device 3000 or a memory device 3000, depending on the context.

[0062] refer to Figure 22 and Figure 23 , the method 2000 includes block 2002, where a stack 3004 of alternating semiconductor layers is formed above the WIP structure 3000. Figure 23 As shown in FIG, WIP structure 3000 includes substrate 3002. Substrate 3002 can be implemented as substrate 12 in IC device 10, as described above. In some embodiments, substrate 3002 can be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 3002 can include various doping configurations as known in the art depending on design requirements. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) can be formed on substrate 3002. In some embodiments, the n-type dopant used to form the n-type well can include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) can be formed on substrate 3002. In some embodiments, the p-type dopant used to form the p-type well can include boron (B) or gallium (Ga). Suitable doping can include ion implantation and / or diffusion processes of the dopant. Substrate 3002 can also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, the substrate 3002 may include a compound semiconductor and / or an alloy semiconductor. In addition, the substrate 3002 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0063] In some embodiments, the stack 3004 above the substrate 3002 includes channel layers 3008 of a first semiconductor composition interleaved with sacrificial layers 3006 of a second semiconductor composition. Alternatively, the sacrificial layers 3006 may be interleaved with the channel layers 3008. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 3006 include silicon germanium (SiGe) or germanium tin (GeSn), and the channel layers 3008 include silicon (Si). It should be noted that the three (3) layers of the sacrificial layers 3006 and the three (3) layers of the channel layers 3008 are arranged alternately, as shown in FIG. Figure 23 , which is for illustrative purposes only and is not intended to limit the scope of the claims beyond what is specifically recited. It will be appreciated that any number of epitaxial layers can be formed in stack 3004. The number of layers depends on the desired number of channel components for semiconductor device 3000. In some embodiments, the number of channel layers 3008 is between 2 and 10.

[0064] The sacrificial layer 3006 and the channel layer 3008 in the stack 3004 can be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As noted above, in at least some examples, the sacrificial layer 3006 comprises an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 3008 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 3006 and the channel layer 3008 are substantially free of dopants (i.e., have a dopant density of from about 0 atoms / cm 3 to about 1×10 17 atoms / cm 3 extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for stack 3004.

[0065] refer to Figure 22 and Figure 24 , the method 2000 includes block 2004, where a fin structure 3012 is formed from the stack 3004 and the substrate 3002. In some embodiments, as Figure 24 The two fin structures 3012 depicted in the figure can be implemented as two active regions 202 and 204 in the SRAM cell 100. In order to pattern the stack 3004, a hard mask layer can be deposited over the stack 3004 to form an etching mask. The hard mask layer can be a single layer or a multilayer. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer disposed over the pad oxide layer. The fin structure 3012 can be patterned by the stack 3004 and the substrate 3002 using a photolithography process and an etching process. The photolithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., RIE etching), wet etching and / or other etching methods. As Figure 24 As shown in FIG, the etching process in box 2004 forms a trench that extends vertically through the stack 3004 and a portion of the substrate 3002. The trench defines a fin structure 3012. In some embodiments, a double patterning or multiple patterning process can be used to define the fin structure, the fin structure having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 3012 by etching portions of the stack 3004 and the substrate 3002. As shown in FIG. Figure 24As shown in FIG, the fin structures 3012 including the sacrificial layer 3006 and the channel layer 3008 extend vertically in the Z direction and longitudinally in the X direction. Each of the fin structures 3012 includes a base fin structure 3012B patterned by the substrate 3002 and a patterned stack 3004 disposed directly above the base fin structure 3012B.

[0066] Still refer to Figure 22 and Figure 24 , the method 2000 includes block 2006, in which an isolation feature 3014 is formed around the base fin structure 3012B of the fin-shaped structure 3012. The isolation feature 3014 can be implemented as the isolation feature 18 in the IC device 10 as described above. Figure 24 In some embodiments shown in , the isolation feature 3014 is disposed on the sidewalls of the base fin structure 3012B. In some embodiments, the isolation feature 3014 can be formed in a trench to isolate the fin structure 3012 from an adjacent fin structure. The isolation feature 3014 can also be referred to as a shallow trench isolation (STI) feature 3014. For example, in some embodiments, a dielectric layer is first deposited over the substrate 3002 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer can be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back by a dry etching process, a wet etching process, and / or a combination thereof to form Figure 24 After recessing, the fin structure 3012 is raised above the STI feature 3014 , while the base fin structure 3012B is embedded or buried in the STI feature 3014 .

[0067] refer to Figure 22 and Figure 25 , the method 2000 includes block 2008, where a hard mask layer 3015 is formed over the STI features 3014 and around the top portion of the substrate fin structure 3012B. The hard mask layer 3015 may be implemented as Figure 7B and Figure 11. The composition of hard mask layer 3015 can be different from the composition of STI features 3014 to ensure that each can be selectively etched without substantially damaging the other. In some embodiments, STI features 3014 include oxide, and hard mask layer 3015 includes a nitride (e.g., silicon nitride) or an oxynitride (e.g., silicon oxynitride). For example, in some embodiments, a nitride-containing material is first deposited over STI features 3014 to fill the trenches with the nitride. In various examples, the nitride-containing material can be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, a spin-on process, and / or other suitable processes. The deposited nitride-containing material is then thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized nitride-containing material is further recessed or pulled back by a dry etch process, a wet etch process, and / or a combination thereof to form hard mask layer 3015. After recessing, the fin structure 3012 rises above the hard mask layer 3015 , while the base fin structure 3012B is embedded or buried in the combination of the STI features 3014 and the hard mask layer 3015 .

[0068] refer to Figure 22 and Figures 26 to 27 , the method 2000 includes block 2010, where a dummy gate stack 3020 is formed over the channel region 3012C of the fin structure 3012. The dummy gate stack 3020 serves as a placeholder structure to undergo various processes and will be removed and replaced by a functional gate structure. Figure 27 In some of the embodiments shown in Figure 27 It is along Figure 26 In the cross-sectional view cut along line DD in FIG, the dummy gate stack 3020 is formed above the fin structure 3012, and the fin structure 3012 can be divided into a channel region 3012C located below the dummy gate stack 3020 and a source / drain region 3012SD not located below the dummy gate stack 3020. The channel region 3012C is adjacent to the source / drain region 3012SD. Figure 27 As shown in FIG, the channel region 3012C is disposed between two source / drain regions 3012SD along the X direction.

[0069] The formation of the dummy gate stack 3020 may include depositing the layers in the dummy gate stack 3020 and patterning the layers. Figure 26, a dummy dielectric layer 3016, a dummy electrode layer 3018, and a gate top hard mask layer 3022 can be blanket deposited over the WIP structure 3000. The dummy dielectric layer 3016 can be formed on the fin structure 3012 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable process. In some instances, the dummy dielectric layer 3016 can include silicon oxide. Thereafter, the dummy electrode layer 3018 can be deposited over the dummy dielectric layer 3016 using a CVD process, an ALD process, or other suitable process. In some instances, the dummy electrode layer 3018 can include polysilicon. For patterning purposes, the gate top hard mask layer 3022 can be deposited on the dummy electrode layer 3018 using a CVD process, an ALD process, or other suitable process. Then, the gate top hard mask layer 3022, the dummy electrode layer 3018, and the dummy dielectric layer 3016 can be patterned to form a dummy gate stack 3020, as shown in FIG. Figure 26 As shown in . For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography) and an etching process. The photolithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. The photolithography process forms a patterned photoresist layer. Then, the patterned photoresist layer is applied as an etching mask in the etching process to pattern the gate top hard mask layer 3022, the dummy electrode layer 3018, and the dummy dielectric layer 3016. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 3022 may include a silicon oxide layer 3023 and a silicon nitride layer 3024 above the silicon oxide layer 3023. As Figure 27 As shown in , the dummy gate stack 3020 is patterned such that it is disposed only over the channel region 3012C and not over the source / drain regions 3012SD.

[0070] refer to Figure 22 and Figure 28, method 2000 includes block 2012, in which a gate spacer layer 3026 is deposited over the WIP structure 3000 (including over the dummy gate stack 3020). In some embodiments, the gate spacer layer 3026 is conformally deposited over the WIP structure 3000, including over the top surface and sidewalls of the dummy gate stack 3020. The term "conformally" is used herein to facilitate describing a layer having a substantially uniform thickness over various regions. The gate spacer layer 3026 can be a single layer or multiple layers. At least one layer of the gate spacer layer 3026 can include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 3026 can be deposited over the dummy gate stack 3020 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process.

[0071] refer to Figure 22 and Figure 29 , method 2000 includes box 2014, in which the source / drain region 3012SD of the fin structure 3012 is anisotropically recessed to form a source / drain trench 3028. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain region 3012SD and a portion of the substrate 3002. The resulting source / drain trench 3028 extends vertically through the depth of the stack 3004 and extends partially into the substrate 3002. An exemplary dry etching process for box 2014 may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. As Figure 29 As shown in FIG, the source / drain regions 3012SD of the fin structure 3012 are recessed to expose the sidewalls of the sacrificial layer 3006 and the channel layer 3008. Because the source / drain trenches 3028 extend into the substrate 3002 beneath the stack 3004, the source / drain trenches 3028 include a bottom surface and lower sidewalls defined in the substrate 3002.

[0072] refer to Figure 22 and Figure 30, method 2000 includes block 2016, where a plurality of channel layers 3008 in the channel region are released as channel members 3008. Channel members 3008 may correspond to nanostructures 26 in IC device 10. Depending on the design, channel members 3008 may take the form of nanowires, nanosheets, or other nanostructures. After forming source / drain trenches 3028, sacrificial layers 3006 interleaved with channel layers 3008 in channel region 3012C are selectively removed. The selective removal of sacrificial layers 3006 releases channel layers 3008 to form Figure 30 . The selective removal of sacrificial layer 3006 forms a spacer between and around adjacent channel members 3008. The selective removal of sacrificial layer 3006 can be implemented by selective dry etching, selective wet etching or other selective etching processes. Exemplary selective dry etching processes can include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Exemplary selective wet etching processes can include APM etching (e.g., ammonium hydroxide-hydrogen peroxide-water mixture).

[0073] refer to Figure 22 and Figure 31 , the method 2000 includes block 2018, in which a dielectric dummy layer 3030 is deposited around the channel members 3008 and over the source / drain trenches 3028. The dummy layer 3030 may include silicon oxide and may be deposited using plasma enhanced chemical vapor deposition (PECVD) or ALD. The dummy layer 3030 fills the spaces between the channel members 3008 and covers the end sidewalls of the channel members 3008. In addition, the dummy layer 3030 is in direct contact with the sidewalls of the gate spacer layer 3026 and the top surface of the substrate 3002.

[0074] refer to Figure 22 and Figure 32 , method 2000 includes block 2020, in which an inner spacer recess 3032 is formed. The dummy layer 3030 is selectively and partially recessed to form the inner spacer recess 3032, while the gate spacer layer 3026, the dummy gate stack 3020, the exposed portion of the substrate 3002, and the channel layer 3008 are substantially not etched. In embodiments where the channel layer 3008 is primarily composed of silicon (Si) and the dummy layer 3030 is formed of silicon oxide, the selective recessing of the dummy layer 3030 can be performed using a selective wet etching process or a selective dry etching process. Exemplary selective dry etching processes may include using carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or mixtures thereof. Exemplary selective wet etching processes may include using hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0075] refer to Figure 22 and Figure 33, method 2000 includes block 2022, where an inner spacer layer 3034 is deposited over the inner spacer recess 3032. The composition of the inner spacer layer 3034 is different from the composition of the dielectric dummy layer 3030 to ensure that each can be selectively etched without substantially damaging the other. In some embodiments, the inner spacer layer 3034 can include silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), silicon nitride (SiN), silicon oxycarbide (SiOC), or silicon oxynitride (SiON). In some embodiments, the inner spacer layer 3034 can be deposited using CVD or ALD.

[0076] refer to Figure 22 and Figure 34 , method 2000 includes block 2024, wherein the inner spacer layer 3034 is etched back to form an inner spacer 3036 above the inner spacer recess 3032. In some embodiments, the etch back in block 2024 may include using a dry etching process, such as a plasma-assisted reactive ion etching (RIE) process. Exemplary dry etching processes may include using boron trichloride (BCl3), chlorine (Cl2), hydrogen chloride (HCl), methane (CH4), nitrogen trifluoride (NF3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen (N2), or a combination thereof. In the depicted embodiment, the inner spacer 3036 extends laterally to a position directly below the dummy gate stack 3020. Alternatively, the inner spacer 3036 may remain substantially below the gate spacer layer 3026 without extending to a position directly below the dummy gate stack 3020.

[0077] refer to Figure 22 and Figure 35 , method 2000 includes block 2028, in which source / drain features 3050 are formed over source / drain regions 3012SD. Source / drain features 3050 can be implemented as source / drain features 16 in IC device 10. Although not explicitly shown, method 2000 can include a cleaning process to clean the surface of WIP structure 3000 before forming any of the epitaxial layers. The cleaning process can include dry cleaning, wet cleaning, or a combination thereof. In some instances, wet cleaning can include using deionized (DI) water, a mixture of ammonium hydroxide and hydrogen peroxide, DI water, a mixture of hydrochloric acid and hydrogen peroxide, SPM (sulfuric acid peroxide mixture), and / or hydrofluoric acid for oxide removal. The dry cleaning process can include helium (He) and hydrogen (H2) treatment. The hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be extracted for removal.

[0078] In some embodiments, source / drain features 3050 include a bottom epitaxial feature 3052 and a main epitaxial feature 3054 above bottom epitaxial feature 3052. Source / drain features 3050 can be n-type or p-type. When source / drain features 3050 are n-type, bottom epitaxial feature 3052 can include undoped silicon (Si) or undoped silicon germanium (SiGe), and main epitaxial feature 3054 can include silicon (Si) and an n-type dopant, such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. When source / drain features 3050 are p-type, bottom epitaxial feature 3052 can include undoped silicon (Si) or undoped silicon germanium (SiGe), and main epitaxial feature 3054 can include silicon germanium (SiGe) and a p-type dopant, such as boron (B), boron difluoride (BF2), or a combination thereof. As used herein, an undoped semiconductor material is considered undoped when it is not intentionally doped. In some optional embodiments, the bottom epitaxial component 3052 can include an anti-dopant to reduce leakage into the bulk substrate 3002. For example, the bottom epitaxial component 3052 in the n-type source / drain component 3050 can include a p-type dopant, such as boron (B). For another example, the bottom epitaxial component 3052 in the p-type source / drain component 3050 can include an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb). The source / drain component 3050 can be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the source / drain component 3050 can be achieved using in-situ doping.

[0079] refer to Figure 22 and Figures 36 to 41 , the method 2000 includes block 2030, wherein the dummy gate stack 3020 and the dummy layer 3030 are replaced with a gate structure 3060 (also referred to as a metal gate structure 3060). The operations in block 2030 may include depositing a contact etch stop layer (CESL) 3056 ( Figure 36 ); an interlayer dielectric layer 3058 is deposited over the CESL 3056 ( Figure 36 ); removing the dummy gate stack 3020 ( Figure 37 ); remove the dummy layer 3030 ( Figure 38 and Figure 39 ); and depositing a gate structure 3060 to wrap each of the channel members 3008 ( Figure 40 and Figure 41 ). Reference Figure 36, CESL 3056 is deposited over the WIP structure 3000, including over the source / drain features 3050. CESL 3056 may include silicon nitride or aluminum nitride. In some embodiments, CESL 3056 may be deposited using CVD or atomic layer deposition (ALD). An ILD layer 3058 is then deposited over the CESL 3056. In some embodiments, the ILD layer 3058 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 3058 may be deposited using CVD, flowable CVD (FCVD), spin coating, or a suitable deposition technique. After depositing the ILD layer 3058, the WIP structure 3000 may be planarized using a planarization process to expose the dummy gate stack 3020. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 3020 allows the dummy gate stack 3020 to be removed. The removal of the dummy gate stack 3020 may include one or more etching processes that are selective to the material of the dummy gate stack 3020. For example, the removal of the dummy gate stack 3020 may be performed using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 3020.

[0080] After removing the dummy gate stack 3020, the dummy layer 3030 in the channel region 3012C is exposed. A separate etching process can be implemented to selectively remove the dummy layer 3030 in the channel region 3012C. For example, a selective wet etching process or a selective dry etching process can be implemented to remove the dummy layer 3030. An exemplary selective wet etching process may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). An exemplary selective dry etching process may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or a combination thereof. The selective etching of the dummy layer 3030 etches the channel member 3008 at a much lower rate, thereby maintaining the integrity of the channel member 3008. The hard mask layer 3015 also protects the STI features 3014 from etching loss during the removal of the dummy layer 3030. The presence of the hard mask layer 3015 is one of the distinguishing features of the proposed modified method of forming a GAA transistor. After selectively removing the dummy layer 3030, the channel member 3008 in the channel region 3012C is exposed again, as shown in FIG. Figure 38 and Figure 39 As shown in .

[0081] After releasing the channel members 3008, a gate structure 3060 is formed to wrap around each of the channel members 3008, as shown in FIG. Figure 40 and Figure 41 The gate structure 3060 includes a gate dielectric layer 3062 interfacing with the channel member 3008 in the channel region 3012C and the substrate 3002 , and a gate electrode layer 3064 over the gate dielectric layer 3062 .

[0082] The gate dielectric layer 3062 may include an interface layer and a high-k dielectric layer above the interface layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the high-k dielectric layer may include other high-k dielectric materials such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium dioxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The high-k dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods. The gate dielectric layer 3062 also covers the sidewalls of the inner spacer 3036.

[0083] The gate electrode layer 3064 of the gate structure 3060 may include a multilayer structure, such as a metal layer having a selected work function to enhance device performance (referred to as a work function metal (WFM) layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer 3064 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials, or combinations thereof. In various embodiments, the gate electrode layer 3064 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process can be performed to remove excess metal, thereby providing a substantially flat top surface of the gate structure 3060. The gate structure 3060 includes a portion between the channel members 3008 in the channel region 3012C. In some embodiments, the gate structure 3060 can be an n-type gate structure or a p-type gate structure. The n-type gate structure includes an n-type work function metal layer disposed closer to the channel member 3008. The p-type gate structure includes a p-type work function metal layer disposed closer to the channel member 3008.

[0084] Figure 42A plan view of one of the channel members 3008 at the end of a gate replacement process in some embodiments is shown. The channel member 3008 (as a nanostructure (e.g., nanosheet, nanowire)) connects opposite source / drain components 3050 and provides a channel region for a corresponding transistor. In some implementations of the gate replacement process, a dummy gate stack is initially formed as a placeholder structure and subsequently replaced with a functional gate structure. After forming the epitaxial source / drain components, the sacrificial material between the nanostructures of the GAA transistor is removed. Ideally, due to different material compositions, a large etch selectivity between the sacrificial material (e.g., SiGe) and the nanostructure (e.g., Si) should protect the nanostructure from etch loss during removal of the sacrificial material. However, atoms other than silicon (e.g., Ge) in the sacrificial material may diffuse into the nanostructure as impurities during an annealing process, such as those used when forming the epitaxial source / drain components. This diffusion of impurities reduces the etch selectivity, potentially causing etch loss in the nanostructure during removal of the sacrificial material. For example, due to additional etch loss, the edges of the nanostructure may become uneven, having a curvature profile. Thus, the width of the channel member 3008 measured at the ends (denoted as We) and at the center (denoted as Wc) will be different. This deviation can be in the range from about 5% to about 50%, or expressed as a ratio, We / Wc can be in the range from about 1.05 to about 1.5 (1.05 < We / Wc < 1.5). Such a significant curvature profile at the edges of the nanostructure may cause variations in the gate structure profile, resulting in non-uniform device performance. In contrast, embodiments of the present disclosure replace the sacrificial material with a dielectric dummy layer 3030 prior to a subsequent annealing process, thereby preventing impurity diffusion. Thus, the channel member 3008 is released by removing the dielectric dummy layer 3030. The etch selectivity between the dielectric dummy layer 3030 and the channel member 3008 is significantly greater than the etch selectivity between the sacrificial layer 3006 and the channel member 3008. By design, the etch selectivity of the dielectric dummy layer 3030 for the channel member 3008 can exceed 10,000:1, ensuring that the channel member 3008 remains substantially intact. Thus, the width deviation between the ends and the center is limited to less than 5%, or expressed as a ratio, We / Wc can be in the range from about 1 to about 1.05 (1 < We / Wc < 1.05). Thus, in some embodiments, the current drive capability is improved by 20% to 50%. This performance improvement allows for a design margin for changing the width of the active region, as discussed above.

[0085] In one exemplary aspect, embodiments of the present disclosure relate to a memory cell. The memory cell includes a first active region and a second active region. Each of the first active region and the second active region extends longitudinally in a first direction. The memory cell also includes a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, arranged sequentially from first to fourth along the first direction. Each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally in a second direction perpendicular to the first direction. The first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to engage the first active region when forming a first transistor, a second transistor, a third transistor, and a fourth transistor, respectively, of a write port of the memory cell. The second gate structure and the third gate structure are configured to further engage the second active region when forming a fifth transistor and a sixth transistor of the write port of the memory cell. The memory cell also includes a fifth gate structure extending longitudinally in the second direction. The fifth gate structure is configured to engage the second active region when forming a seventh transistor of the read port of the memory cell. The second active region has a first section that provides a channel region for the seventh transistor and a second section that provides a channel region for the fifth transistor and the sixth transistor. The first segment has a first width, and the second segment has a second width different from the first width. In some embodiments, the first width is smaller than the second width. In some embodiments, a ratio of the first width to the second width is in a range from about 0.75 to about 1. In some embodiments, the first width is greater than the second width. In some embodiments, a ratio of the first width to the second width is in a range from about 1 to about 1.25. In some embodiments, the first active region has a third width that is equal to the first width or the second width. In some embodiments, the first, second, third, and fourth transistors are n-type transistors, and the fifth, sixth, and seventh transistors are p-type transistors. In some embodiments, the memory cell further includes: an isolation structure disposed between the first active region and the second active region; and a hard mask layer disposed on the isolation structure. The hard mask layer and the isolation structure include different material compositions. In some embodiments, the second active region includes a first edge facing the first active region and a second edge facing away from the first active region, the second active region including a kink located at a transition between the first segment and the second segment, the kink located on the first edge, and the second edge being flat. In some embodiments, the second active region includes a first edge facing the first active region and a second edge facing away from the first active region, the second active region includes a first kink and a second kink located at a transition between the first segment and the second segment, the first kink is located on the first edge, and the second kink is located on the second edge.

[0086] In another exemplary aspect, embodiments of the present disclosure relate to a semiconductor device. The semiconductor device includes: a write port of a memory cell, wherein the write port includes at least a pull-up (PU) transistor, a pull-down (PD) transistor, and a pass gate (PG) transistor; and a read port of the memory cell, wherein the read port includes a PG transistor. The PG transistor in the write port is an n-type transistor. The PG transistor in the read port is a p-type transistor. The channel region of the PD transistor in the write port and the channel region of the PG transistor in the write port are disposed on a first active region. The channel region of the PU transistor in the write port and the channel region of the PG transistor in the read port are disposed on a second active region extending parallel to the first active region. The second active region has a variable width. In some embodiments, the first active region has a constant width. In some embodiments, the second active region has a first segment corresponding to the channel region of the PG transistor in the read port and a second segment corresponding to the channel region of the PU transistor in the write port. The first segment is narrower than the second segment. In some embodiments, the ratio of the widths of the first segment to the second segment is in a range from about 0.75 to about 1. In some embodiments, the second active region has a first segment corresponding to the channel region of the PG transistor in the read port and a second segment corresponding to the channel region of the PU transistor in the write port, the first segment being wider than the second segment. In some embodiments, a ratio of the widths of the first segment to the second segment is in a range from 1 to 1.25.

[0087] In another exemplary aspect, an embodiment of the present disclosure relates to a memory device. The memory device includes: a first transfer gate (PG) transistor, a second PG transistor, a first pull-down (PD) transistor, and a second PD transistor, sharing a first active area extending in a first direction; a first pull-up (PU) transistor, a second PU transistor, and a read port transfer gate (R-PG) transistor, sharing a second active area extending in the first direction; and an isolation component adjacent to the gate structure of the first PG transistor and extending longitudinally in a second direction perpendicular to the first direction. The second active area is divided into a first segment and a second segment by the isolation component. The first segment and the second segment have different widths. In some embodiments, the second segment provides a channel region for the first PU transistor, the second PU transistor, and the R-PG transistor. In some embodiments, the second segment is wider than the first segment. In some embodiments, the edges of the first segment and the second segment facing away from the first active area are aligned, and the relative edges of the first segment and the second segment facing the first active area are not aligned.

[0088] Some embodiments of the present application provide a memory cell, comprising: a first active region and a second active region, wherein each of the first active region and the second active region extends longitudinally in a first direction; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, which are arranged in sequence from first to fourth along the first direction, wherein each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally in a second direction perpendicular to the first direction, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to form a first transistor, a second transistor, a third transistor, and a fourth gate structure respectively forming a write port of the memory cell; The memory cell is connected to a first transistor and a fourth transistor by connecting the first active region to the first active region, and the second gate structure and the third gate structure are configured to further connect the second active region when forming a fifth transistor and a sixth transistor of the write port of the memory cell; and a fifth gate structure extending longitudinally in the second direction, wherein the fifth gate structure is configured to connect the second active region when forming a seventh transistor of the read port of the memory cell, wherein the second active region has a first segment providing a channel region for the seventh transistor and a second segment providing a channel region for the fifth transistor and the sixth transistor, the first segment having a first width, and the second segment having a second width different from the first width.

[0089] In some embodiments, the first width is smaller than the second width. In some embodiments, a ratio of the first width to the second width is in a range from approximately 0.75 to approximately 1. In some embodiments, the first width is greater than the second width. In some embodiments, a ratio of the first width to the second width is in a range from approximately 1 to approximately 1.25. In some embodiments, the first active region has a third width that is equal to the first width or the second width. In some embodiments, the first, second, third, and fourth transistors are n-type transistors, and the fifth, sixth, and seventh transistors are p-type transistors. In some embodiments, the memory cell further comprises: an isolation structure disposed between the first and second active regions; and a hard mask layer disposed on the isolation structure, wherein the hard mask layer and the isolation structure comprise different material compositions. In some embodiments, the second active region comprises a first edge facing the first active region and a second edge facing away from the first active region, the second active region comprising a kink at a transition between the first segment and the second segment, the kink being located on the first edge, and the second edge being flat. In some embodiments, the second active region includes a first edge facing the first active region and a second edge facing away from the first active region, the second active region includes a first kink and a second kink located at a transition between the first segment and the second segment, the first kink is located on the first edge, and the second kink is located on the second edge.

[0090] Other embodiments of the present application provide a semiconductor device, comprising: a write port of a memory cell, wherein the write port includes at least a pull-up transistor, a pull-down transistor and a transfer gate transistor; and a read port of the memory cell, wherein the read port includes a transfer gate transistor, wherein: the transfer gate transistor in the write port is an n-type transistor, the transfer gate transistor in the read port is a p-type transistor, the channel region of the pull-down transistor in the write port and the channel region of the transfer gate transistor in the write port are arranged on a first active region, the channel region of the pull-up transistor in the write port and the channel region of the transfer gate transistor in the read port are arranged on a second active region extending parallel to the first active region, and the second active region has a variable width.

[0091] In some embodiments, the first active region has a constant width. In some embodiments, the second active region has a first segment corresponding to the channel region of the pass-gate transistor in the read port and a second segment corresponding to the channel region of the pull-up transistor in the write port, the first segment being narrower than the second segment. In some embodiments, a ratio of the widths of the first segment to the second segment is in a range from approximately 0.75 to approximately 1. In some embodiments, the second active region has a first segment corresponding to the channel region of the pass-gate transistor in the read port and a second segment corresponding to the channel region of the pull-up transistor in the write port, the first segment being wider than the second segment. In some embodiments, a ratio of the widths of the first segment to the second segment is in a range from approximately 1 to approximately 1.25.

[0092] Still other embodiments of the present application provide a memory device, comprising: a first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor, and a second pull-down transistor, which share a first active area extending in a first direction; a first pull-up transistor, a second pull-up transistor, and a read port pass-gate transistor, which share a second active area extending in the first direction; and an isolation component, adjacent to a gate structure of the first pass-gate transistor and extending longitudinally in a second direction perpendicular to the first direction, wherein the second active area is divided into a first segment and a second segment by the isolation component, and wherein the first segment and the second segment have different widths.

[0093] In some embodiments, the second segment provides a channel region for the first pull-up transistor, the second pull-up transistor, and the read port pass-gate transistor. In some embodiments, the second segment is wider than the first segment. In some embodiments, edges of the first and second segments facing away from the first active area are aligned, and opposite edges of the first and second segments facing the first active area are misaligned.

[0094] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A memory cell comprising: a first active region and a second active region, wherein each of the first active region and the second active region extends longitudinally in a first direction; a first gate structure, a second gate structure, a third gate structure, and a fourth gate structure, arranged sequentially from first to fourth along the first direction, wherein each of the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure extends longitudinally in a second direction perpendicular to the first direction, wherein the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure are configured to engage the first active region when forming a first transistor, a second transistor, a third transistor, and a fourth transistor of a write port of the memory cell, respectively, and wherein the second gate structure and the third gate structure are configured to further engage the second active region when forming a fifth transistor and a sixth transistor of the write port of the memory cell; and a fifth gate structure extending longitudinally in the second direction, wherein the fifth gate structure is configured to engage the second active region when forming a seventh transistor of a read port of the memory cell, The second active region has a first segment providing a channel region for the seventh transistor and a second segment providing channel regions for the fifth and sixth transistors, the first segment has a first width, and the second segment has a second width different from the first width.

2. The memory cell according to claim 1, wherein The first width is smaller than the second width.

3. The memory cell according to claim 2, wherein A ratio of the first width to the second width ranges from about 0.75 to about 1.

4. The memory cell according to claim 1, wherein The first width is greater than the second width.

5. The memory cell according to claim 4, wherein A ratio of the first width to the second width ranges from about 1 to about 1.

25. The memory cell according to claim 1 , wherein: The first active region has a third width equal to the first width or the second width.

7. The memory cell according to claim 1, wherein The first transistor, the second transistor, the third transistor, and the fourth transistor are n-type transistors, and the fifth transistor, the sixth transistor, and the seventh transistor are p-type transistors.

8. The memory cell according to claim 1 , further comprising: an isolation structure, disposed between the first active region and the second active region; as well as A hard mask layer is disposed on the isolation structure, wherein the hard mask layer and the isolation structure comprise different material compositions.

9. A semiconductor device comprising: a write port of a memory cell, wherein the write port comprises at least a pull-up transistor, a pull-down transistor, and a pass-gate transistor; and a read port of the memory cell, wherein the read port comprises a pass-gate transistor, in: The pass-gate transistor in the write port is an n-type transistor, The pass-gate transistor in the read port is a p-type transistor, The channel region of the pull-down transistor in the write port and the channel region of the pass-gate transistor in the write port are disposed on a first active region, The channel region of the pull-up transistor in the write port and the channel region of the pass-gate transistor in the read port are disposed on a second active region extending parallel to the first active region, and The second active region has a variable width.

10. A memory device comprising: A first pass-gate transistor, a second pass-gate transistor, a first pull-down transistor, and a second pull-down transistor share a first active region extending in a first direction; a first pull-up transistor, a second pull-up transistor, and a read port pass-gate transistor sharing a second active area extending in the first direction; as well as an isolation member adjacent to the gate structure of the first pass-gate transistor and extending longitudinally in a second direction perpendicular to the first direction, The second active region is divided into a first section and a second section by the isolation component, and the first section and the second section have different widths.

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