Performance modulation method for two-dimensional semiconductor devices based on active atmosphere annealing

Abstract

This application discloses a method for performance regulation of a two-dimensional semiconductor device based on active atmosphere annealing, comprising: S1: providing a two-dimensional semiconductor device, the two-dimensional semiconductor device including a substrate, a molybdenum disulfide layer formed on the substrate located in the active region of the two-dimensional semiconductor device, an active metal and a drain metal formed on the molybdenum disulfide layer, the two-dimensional semiconductor device further including a dielectric layer, the dielectric layer covering the source metal, the drain metal and the molybdenum disulfide layer, and a top gate electrode formed on the dielectric layer; S2: performing an active atmosphere annealing process on the two-dimensional semiconductor device at 120~180℃ to adjust the threshold voltage of the two-dimensional semiconductor device. This application, through the above scheme, can non-destructively regulate the threshold voltage of a two-dimensional semiconductor device with a top gate.

Description

Technical Field

[0001] This application relates to the technical field of microelectronic device manufacturing, specifically to a method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing. Background Technology

[0002] As semiconductor technology advances towards miniaturization and low power consumption, traditional silicon-based devices are gradually approaching their physical limits due to problems such as intensified short-channel effects and quantum tunneling, making it difficult to meet the performance requirements of next-generation electronic devices. Against this backdrop, two-dimensional semiconductor materials, with their unique structure and electrical properties, have become important candidate materials for breaking through traditional technological bottlenecks, and two-dimensional semiconductor devices built based on them have attracted widespread attention.

[0003] However, two-dimensional semiconductor devices commonly suffer from threshold voltage drift and current hysteresis induced by interface defects in wafer-level integration, which are difficult to control without damage using traditional chemical doping and contact engineering. Furthermore, existing annealing techniques are mostly designed for back-gate devices, where high temperatures or active atmospheres directly act on the surface of two-dimensional materials, leading to sulfur vacancy defects or oxidation damage. Therefore, how to control the threshold voltage of top-gate devices without damage at low temperatures (<200℃) has become a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] This application provides a method for performance control of two-dimensional semiconductor devices based on active atmosphere annealing, which can non-destructively control the threshold voltage of two-dimensional semiconductor devices with a top gate.

[0005] This application provides a method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing, including:

[0006] S1: A two-dimensional semiconductor device is provided, the two-dimensional semiconductor device including a substrate, a molybdenum disulfide layer formed on the substrate located in the active region of the two-dimensional semiconductor device, an active metal and a drain metal formed on the molybdenum disulfide layer, the two-dimensional semiconductor device further including a dielectric layer, the dielectric layer covering the source metal, the drain metal and the molybdenum disulfide layer, and a top gate electrode formed on the dielectric layer;

[0007] S2: Perform an active atmosphere annealing process on the two-dimensional semiconductor device to adjust the threshold voltage of the two-dimensional semiconductor device.

[0008] In some embodiments, the annealing process is carried out using a reducing atmosphere or an oxidizing atmosphere.

[0009] In some embodiments, in step S2, after annealing in the reducing atmosphere, the threshold voltage of the two-dimensional semiconductor device is negatively shifted.

[0010] In step S2, after annealing in the oxidizing atmosphere, the threshold voltage of the two-dimensional semiconductor device shifts positively.

[0011] In some embodiments, the annealing time during the active atmosphere annealing process is 0.5h to 2h.

[0012] In some embodiments, when performing the annealing process using the reducing atmosphere, the gas used is a hydrogen-argon mixture;

[0013] When performing the annealing process using the aforementioned oxidizing atmosphere, the gas used is oxygen.

[0014] In some embodiments, the two-dimensional semiconductor device is integrated in an E / D-NMOS inverter, the top gate electrode includes an enhancement-mode top gate electrode and a depletion-mode top gate electrode, and step S2 includes:

[0015] Differential active atmosphere annealing processes are applied to the different two-dimensional semiconductor devices in the E / D-NMOS inverter.

[0016] The above steps include:

[0017] The two-dimensional semiconductor device containing the enhancement-mode top gate electrode in the E / D-NMOS inverter is subjected to a first active atmosphere annealing process;

[0018] A second active atmosphere annealing process is performed on the two-dimensional semiconductor device containing the depletion-type top gate electrode in the E / D-NMOS inverter.

[0019] One of the first active atmosphere annealing process and the second active atmosphere annealing process uses an oxidizing atmosphere, and the other uses a reducing atmosphere.

[0020] In some embodiments, prior to S1, the following is included:

[0021] A substrate is provided on which a molybdenum disulfide layer is deposited;

[0022] A channel is defined on the molybdenum disulfide layer by photolithography and etching processes, and the molybdenum disulfide layer outside the channel is removed. The channel defines the active region of the substrate.

[0023] A metal deposition process is performed on the remaining molybdenum disulfide layer to form the source metal and drain metal;

[0024] A deposition medium layer, the medium layer covering the source metal, the drain metal and the exposed molybdenum disulfide layer;

[0025] A top gate electrode is formed on the surface of the dielectric layer, and the top gate electrode is located between the source metal and the drain metal.

[0026] In some embodiments, the material of the dielectric layer includes, but is not limited to, high-κ materials such as HfO2, ZrO2, and TiO2.

[0027] The technical solution of this application has at least the following advantages:

[0028] 1. By performing an active atmosphere annealing process on two-dimensional semiconductor devices at 120~180℃, the oxygen vacancy concentration in the dielectric layer can be adjusted, and the threshold voltage can be positively and negatively adjusted by utilizing the interfacial electric dipole effect.

[0029] 2. During the active annealing process, the protective dielectric layer prevents direct damage to the molybdenum disulfide layer during annealing. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is a flowchart of a two-dimensional semiconductor device performance regulation method based on active atmosphere annealing, provided in an exemplary embodiment of this application.

[0032] Figure 2 This is a schematic diagram of the structure of a two-dimensional semiconductor device with a gold gate as the top gate electrode, provided in an exemplary embodiment of this application.

[0033] Figure 3 This is a schematic diagram of the structure of a two-dimensional semiconductor device with an aluminum gate as the top gate electrode, provided in an exemplary embodiment of this application.

[0034] Figure 4 This is a flowchart of the steps preceding step S1 in a two-dimensional semiconductor device performance regulation method based on active atmosphere annealing provided in an exemplary embodiment of this application.

[0035] Figures 5-9 This is a schematic diagram of the structure of a two-dimensional semiconductor device during its formation process, provided in an exemplary embodiment of this application.

[0036] Figure 10a This is a comparison graph of the voltage transfer characteristic curve and the corresponding voltage gain curve of an E / D-NMOS inverter provided in an exemplary embodiment of this application before and after annealing in a reducing atmosphere.

[0037] Figure 10b This is a comparison graph of the voltage transfer characteristic curve and the corresponding voltage gain curve of an E / D-NMOS inverter provided in an exemplary embodiment of this application before and after annealing in an oxidizing atmosphere.

[0038] Figure 10c This is a comparison diagram of the noise margin of an E / D-NMOS inverter provided in an exemplary embodiment of this application before and after annealing in a reducing atmosphere.

[0039] Figure 10d This is a comparison diagram of the noise margin of an E / D-NMOS inverter provided in an exemplary embodiment of this application before and after annealing in an oxidizing atmosphere.

[0040] Figure 11a This is a comparison graph of the transfer curve and gate leakage current curve of an aluminum gate device before and after annealing in an oxidizing atmosphere, provided by an exemplary embodiment of this application.

[0041] Figure 11b This is a comparison graph of the transfer curve and gate leakage current curve of a gold gate device before and after annealing in an oxidizing atmosphere, provided by an exemplary embodiment of this application.

[0042] Figure 11c This is a comparison graph of the transfer curve and gate leakage current curve of an aluminum gate device before and after reducing atmosphere annealing, provided by an exemplary embodiment of this application.

[0043] Figure 11d This is a comparison graph of the transfer curve and gate leakage current curve of a gold gate device before and after reducing atmosphere annealing, provided by an exemplary embodiment of this application.

[0044] Figure 12a This is a statistical graph showing the threshold voltage difference of an aluminum gate device before and after annealing in an oxidizing atmosphere, provided in an exemplary embodiment of this application.

[0045] Figure 12b This is a statistical graph showing the difference in threshold voltage of a gold gate device before and after annealing in an oxidizing atmosphere, provided in an exemplary embodiment of this application.

[0046] Figure 12c This is a statistical graph showing the threshold voltage difference of an aluminum gate device before and after reducing atmosphere annealing, provided in an exemplary embodiment of this application.

[0047] Figure 12d This is a statistical graph showing the difference in threshold voltage of a gold gate device before and after reducing atmosphere annealing, provided in an exemplary embodiment of this application.

[0048] Explanation of reference numerals in the attached figures:

[0049] 1. Substrate; 11. Active region; 2. Molybdenum disulfide layer; 3. Source metal; 4. Drain metal; 5. Dielectric layer; 51. Lower dielectric layer; 52. Upper dielectric layer; 6. Top gate electrode; 61. Bottom aluminum layer; 62. Top gold layer. Detailed Implementation

[0050] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0051] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0052] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0053] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0054] This application provides a method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing, referring to... Figure 1 The method includes the following steps:

[0055] S1: Provides a two-dimensional semiconductor device, the two-dimensional semiconductor device includes a substrate, a molybdenum disulfide layer is formed on the substrate located in the active region of the two-dimensional semiconductor device, an active metal and a drain metal are formed on the molybdenum disulfide layer, the two-dimensional semiconductor device also includes a dielectric layer, the dielectric layer covers the source metal, the drain metal and the molybdenum disulfide layer, and a top gate electrode is formed on the dielectric layer.

[0056] For example, refer to Figure 2 and Figure 3 A two-dimensional semiconductor device is provided, comprising a substrate 1, on which a molybdenum disulfide layer 2 is formed, located within an active region 11 of the two-dimensional semiconductor device, the molybdenum disulfide layer 2 constituting a channel of the two-dimensional semiconductor device. An active metal 3 and a drain metal 4 are formed at opposite ends of the surface of the molybdenum disulfide layer 2, respectively, with the molybdenum disulfide layer 2 exposed between the source metal 3 and the drain metal 4. The two-dimensional semiconductor device further includes a dielectric layer 5, which covers the source metal 3, the drain metal 4, and the exposed molybdenum disulfide layer 2, and a top gate electrode 6 is formed on the dielectric layer 5.

[0057] Among them, the top gate electrode 6 can be made of gold, such as Figure 2 As shown, an aluminum gate can also be used, meaning the top gate electrode 6 can include a stacked structure of a bottom aluminum layer 61 and a top gold layer 62, such as... Figure 3 As shown. In other embodiments, the material of the top gate electrode 6 can also be platinum, nickel, etc., with work function matching.

[0058] Furthermore, the source metal 3 and drain metal 4 can be made of gold.

[0059] Furthermore, refer to Figure 2 and Figure 3 The dielectric layer 5 may include a lower dielectric layer 51 and an upper dielectric layer 52, with the lower dielectric layer 51 located between the molybdenum disulfide layer 2 and the upper dielectric layer 52. The upper dielectric layer 52 may be made of high-k materials such as HfO2, ZrO2, and TiO2, while the lower dielectric layer 51 may be made of Al2O3.

[0060] S2: The two-dimensional semiconductor device is subjected to an active atmosphere annealing process at 120~180℃ to adjust the threshold voltage of the two-dimensional semiconductor device.

[0061] For example, a two-dimensional semiconductor device is subjected to an active atmosphere annealing process at an annealing temperature of 120~180°C. During this process, the molybdenum disulfide layer 2 is protected from direct damage during annealing due to the protection of the dielectric layer 5. At the same time, the oxygen vacancy concentration in the dielectric layer 5 can be adjusted through this low-temperature active atmosphere annealing process, and the threshold voltage can be positively or negatively adjusted by utilizing the interfacial electric dipole effect.

[0062] Furthermore, in this step, either a reducing atmosphere or an oxidizing atmosphere can be used for the annealing process, depending on the threshold voltage adjustment requirements. When using a reducing atmosphere for annealing, oxygen vacancies are introduced into the dielectric layer 5, causing a negative shift in the threshold voltage of the two-dimensional semiconductor device. When using an oxidizing atmosphere for annealing, oxygen vacancies in the dielectric layer 5 are repaired, causing a positive shift in the threshold voltage of the two-dimensional semiconductor device. The amount of threshold voltage shift varies with the annealing temperature and duration; therefore, by specifically setting and adjusting the annealing temperature and duration, the threshold voltage shift can be adjusted within a certain range.

[0063] Furthermore, when using a reducing atmosphere for annealing, the gas used can be a hydrogen-argon mixture, for example, a hydrogen-argon mixture with 5% hydrogen and 95% argon. When using an oxidizing atmosphere for annealing, the gas used is oxygen.

[0064] Furthermore, during the active atmosphere annealing process, the annealing time is 0.5h to 2h, which can be set according to the threshold voltage adjustment requirements.

[0065] Furthermore, in some embodiments, in order to form the two-dimensional semiconductor device in step S1, prior to step S1 described above, reference is made to... Figure 4 It also includes the following steps:

[0066] S01: Provide a substrate on which a molybdenum disulfide layer is deposited.

[0067] For example, refer to Figure 5 A substrate 1 is provided, which may be a sapphire substrate. A monolayer of molybdenum disulfide 2 can be grown on the substrate 1 by chemical vapor deposition.

[0068] S02: Through photolithography and etching processes, a channel is defined on the molybdenum disulfide layer, and the molybdenum disulfide layer outside the channel is removed. The channel defines the active region of the substrate.

[0069] For example, a patterned photoresist layer can be first formed on the molybdenum disulfide layer 2 to define the channel formation region on the molybdenum disulfide layer 2. For instance, the width of the channel formation region can be 30 μm and the length can be 10 μm. Then, using the photoresist layer as a mask, excess molybdenum disulfide layer 2 can be removed by reactive ion etching. The remaining molybdenum disulfide layer 2 forms the channel and defines the active region 11 of the substrate 1, such as... Figure 6 As shown.

[0070] S03: A metal deposition process is performed on the remaining molybdenum disulfide layer to form source and drain metals.

[0071] For example, refer to Figure 7 Source metal 3 and drain metal 4 can be deposited on the remaining molybdenum disulfide layer 2, i.e., the channel, using an electron beam evaporation (EBE) process. The source metal 3 and drain metal 4 are located at opposite ends of the channel, with a gap between them.

[0072] S04: Deposited dielectric layer, which covers the source metal, drain metal, and exposed molybdenum disulfide layer.

[0073] For example, refer to Figure 8 and Figure 9 The dielectric layer 5 includes a lower dielectric layer 51 and an upper dielectric layer 52. In this embodiment, before depositing the dielectric layer 5, the channel surface can be lightly etched using a CF4 plasma etching process to remove any possible contaminants and native oxide layers. Then, referring to... Figure 8 First, an Al2O3 layer can be deposited on the molybdenum disulfide layer 2 exposed between the source metal 3 and the drain metal 4 using atomic layer deposition (ALD) technology, serving as the lower dielectric layer 51. The lower dielectric layer 51 acts as a seed layer, facilitating the subsequent growth of the upper dielectric layer 52. Then, refer to... Figure 9 HfO2 is then deposited using atomic layer deposition (ALD) to form the upper dielectric layer 52. The surfaces of the lower dielectric layer 51, the source metal 3, and the drain metal 4 are all covered by the upper dielectric layer 52. The upper dielectric layer 52 can also be made of high-κ materials such as ZrO2 or TiO2.

[0074] S05: A top gate electrode is formed on the surface of the dielectric layer, and the top gate electrode is located between the source metal and the drain metal.

[0075] For example, refer to Figure 2 and Figure 3 A top gate electrode 6 is formed on the surface of the dielectric layer 5, and the top gate electrode 6 is located between the source metal 3 and the drain metal 4. The top gate electrode 6 can be a gold gate, or it can be configured as a stacked structure including a bottom aluminum layer 61 and a top gold layer 62.

[0076] Furthermore, in some embodiments, the two-dimensional semiconductor devices described above may include multiple devices, and these two-dimensional semiconductor devices are integrated in an E / D-NMOS inverter. The two-dimensional semiconductor devices may include two-dimensional semiconductor devices with an enhancement-mode top gate electrode 6 (e.g., a gold gate) and two-dimensional semiconductor devices with a depletion-mode top gate electrode 6 (e.g., an aluminum gate). In this case, step S2 described above may include the following processing:

[0077] Differentiated active atmosphere annealing processes are applied to different two-dimensional semiconductor devices in E / D-NMOS inverters.

[0078] For example, this step includes the following processing procedures:

[0079] A first active atmosphere annealing process is performed on the two-dimensional semiconductor device containing the enhancement-mode top gate electrode in the E / D-NMOS inverter, and a second active atmosphere annealing process is performed on the two-dimensional semiconductor device containing the depletion-mode top gate electrode in the E / D-NMOS inverter. In this process, one of the first and second active atmosphere annealing processes uses an oxidizing atmosphere, while the other uses a reducing atmosphere. By using this differentiated active atmosphere annealing process to control the threshold voltage of the enhancement-mode (E-mode) and depletion-mode (D-mode) top gate electrodes respectively, the noise margin of the E / D-NMOS inverter can be improved.

[0080] Reference Figure 10a and Figure 10b , Figure 10a A comparison graph of the voltage transfer characteristic curve and the corresponding voltage gain curve of an E / D-NMOS inverter before and after annealing in a reducing atmosphere is provided. Figure 10b A comparison graph of the voltage transfer characteristic curve and corresponding voltage gain curve of an E / D-NMOS inverter before and after annealing in an oxidizing atmosphere is provided. The curve corresponding to W / O NDA is the curve before annealing, and the curve corresponding to W NDA is the curve after annealing. Figure 10a and Figure 10b In the diagram, the horizontal axis represents the input voltage, the left vertical axis represents the output voltage, and the right vertical axis represents the voltage gain. The solid line represents the voltage transfer characteristic curve, and the dashed line represents the voltage gain curve. It can be observed that after annealing in a reducing atmosphere, the threshold voltage shifts negatively, and after annealing in an oxidizing atmosphere, the threshold voltage shifts positively.

[0081] Reference Figure 10c and Figure 10d , Figure 10c A comparison graph of the noise margin of an E / D-NMOS inverter before and after annealing in a reducing atmosphere is provided. Figure 10d A comparison graph is provided showing the noise margin of an E / D-NMOS inverter before and after annealing in an oxidizing atmosphere. It can be observed that the noise margin of the E / D-NMOS inverter is improved.

[0082] Furthermore, to facilitate the demonstration of the technical effects, this application also provides the following embodiments:

[0083] This embodiment provides a gold-gate device, namely a two-dimensional semiconductor device with a gold gate as the top gate electrode, and an aluminum-gate device, namely a two-dimensional semiconductor device with a stacked structure of a bottom aluminum layer and a top gold layer as the top gate electrode. In the above-mentioned gold-gate device and aluminum-gate device, the lower dielectric layer is made of 4 nm thick Al2O3, and the upper dielectric layer is made of 16 nm thick HfO2; both the source metal and the drain metal are made of 35 nm thick gold, and their contact resistance is < 200 Ω·μm. The top gate electrode of the gold-gate device is made of 35 nm gold, while the aluminum-gate device is made of a stacked structure of a 5 nm thick bottom aluminum layer and a 30 nm thick top gold layer.

[0084] Reference Figures 11a-11d The diagram shows a comparison of the transfer curves and gate leakage curves of a two-dimensional semiconductor device before and after annealing. The left vertical axis corresponds to the transfer curve, and the right vertical axis corresponds to the gate leakage curve. The curve corresponding to W / O NDA is the curve before annealing, and the curve corresponding to W NDA is the curve after annealing. Figure 11a This is a comparison of the transfer curves and gate leakage current curves of the aluminum gate device before and after annealing in an oxidizing atmosphere. Figure 11b This is a comparison chart of the transfer curves and gate leakage current curves of the gold gate device before and after annealing in an oxidizing atmosphere. Figure 11c To compare the transfer curves and gate leakage current curves of the aluminum gate device before and after reducing atmosphere annealing, a comparative graph is provided. Figure 11d This is a comparison of the transfer curves and gate leakage current curves of the gold-gate device before and after reducing atmosphere annealing. Actual testing revealed that after annealing the aluminum-gate device in an oxidizing atmosphere using oxygen, the threshold voltage shifted positively by approximately 1.4V. Conversely, after annealing the aluminum-gate device in a reducing atmosphere using a hydrogen-argon mixture, the threshold voltage shifted negatively by 1.3V. Furthermore, the hysteresis window decreased by 60% (from 0.7V to 0.3V), and the subthreshold swing (SS) decreased by 20%.

[0085] Reference Figures 12a-12d This shows the statistical results of the threshold voltage difference before and after annealing at different annealing temperatures. Figure 12a This is a statistical graph showing the difference in threshold voltage of aluminum gate devices before and after annealing in an oxidizing atmosphere. Figure 12b This is a statistical graph showing the difference in threshold voltage of gold gate devices before and after annealing in an oxidizing atmosphere. Figure 12c This is a statistical graph showing the difference in threshold voltage of aluminum gate devices before and after reducing atmosphere annealing. Figure 12d This is a statistical graph showing the difference in threshold voltage of gold gate devices before and after annealing in a reducing atmosphere. It is evident that changes in annealing temperature have a significant impact on the threshold voltage adjustment. Therefore, the required threshold voltage adjustment can be met by specifically setting the annealing temperature.

[0086] This application provides a method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing. By performing an active atmosphere annealing process on the two-dimensional semiconductor device at 120~180℃, the oxygen vacancy concentration in the dielectric layer can be adjusted. The threshold voltage can be positively and negatively adjusted using the interfacial electric dipole effect. When using a reducing atmosphere for annealing, oxygen vacancies are introduced into the dielectric layer, causing a negative shift in the threshold voltage of the two-dimensional semiconductor device. When using an oxidizing atmosphere for annealing, oxygen vacancies in the dielectric layer are repaired, causing a positive shift in the threshold voltage of the two-dimensional semiconductor device. Simultaneously, during the active annealing process, the protection of the dielectric layer prevents direct damage to the molybdenum disulfide layer. Furthermore, the ability to finely adjust the threshold voltage of the two-dimensional semiconductor device helps improve the noise margin of logic circuits constructed using the two-dimensional semiconductor device.

[0087] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing, characterized in that, include: S1: A two-dimensional semiconductor device is provided, the two-dimensional semiconductor device including a substrate, a molybdenum disulfide layer formed on the substrate located in the active region of the two-dimensional semiconductor device, an active metal and a drain metal formed on the molybdenum disulfide layer, the two-dimensional semiconductor device further including a dielectric layer, the dielectric layer covering the source metal, the drain metal and the molybdenum disulfide layer, and a top gate electrode formed on the dielectric layer; S2: The two-dimensional semiconductor device is subjected to an active atmosphere annealing process at 120~180℃ to adjust the oxygen vacancy concentration of the dielectric layer and adjust the threshold voltage of the two-dimensional semiconductor device. In the active atmosphere annealing process, a reducing atmosphere or an oxidizing atmosphere is used for the annealing process.

2. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that: In step S2, after the annealing process using the reducing atmosphere, the threshold voltage of the two-dimensional semiconductor device shifts negatively. In step S2, after annealing in the oxidizing atmosphere, the threshold voltage of the two-dimensional semiconductor device shifts positively.

3. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that, When performing the active atmosphere annealing process, the annealing time is 0.5h to 2h.

4. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that: When using the reducing atmosphere for the annealing process, the gas used is a hydrogen-argon mixture; When performing the annealing process using the aforementioned oxidizing atmosphere, the gas used is oxygen.

5. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that, The two-dimensional semiconductor device is integrated in an E / D-NMOS inverter, the top gate electrode includes an enhancement-mode top gate electrode and a depletion-mode top gate electrode, and step S2 includes: Differential active atmosphere annealing processes are applied to the different two-dimensional semiconductor devices in the E / D-NMOS inverter. The above steps include: The two-dimensional semiconductor device containing the enhancement-mode top gate electrode in the E / D-NMOS inverter is subjected to a first active atmosphere annealing process; A second active atmosphere annealing process is performed on the two-dimensional semiconductor device containing the depletion-type top gate electrode in the E / D-NMOS inverter. One of the first active atmosphere annealing process and the second active atmosphere annealing process uses an oxidizing atmosphere, and the other uses a reducing atmosphere.

6. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that, Prior to S1, the following are included: A substrate is provided on which a molybdenum disulfide layer is deposited; A channel is defined on the molybdenum disulfide layer by photolithography and etching processes, and the molybdenum disulfide layer outside the channel is removed. The channel defines the active region of the substrate. A metal deposition process is performed on the remaining molybdenum disulfide layer to form the source metal and drain metal; A deposition medium layer, the medium layer covering the source metal, the drain metal and the exposed molybdenum disulfide layer; A top gate electrode is formed on the surface of the dielectric layer, and the top gate electrode is located between the source metal and the drain metal.

7. The method for performance regulation of two-dimensional semiconductor devices based on active atmosphere annealing according to claim 1, characterized in that, The dielectric layer is made of a high-κ material.

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