Semiconductor device and method for forming semiconductor device structure

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner. The method further includes partially removing the semiconductor layer and the sacrificial layer to expose side edges of the semiconductor layer and the sacrificial layer, and partially removing the sacrificial layer from their side edges to form a plurality of second recesses. The method further includes introducing a modifying element to convert a surface portion of the sacrificial layer and the semiconductor layer into a modified layer. The modifying element includes nitrogen, carbon, boron or a combination thereof. Further, the method includes forming an inner spacer layer over the modification layer, and removing the inner spacer layer and the modification layer outside the second recess. Remaining portions of the inner spacer layer and the modified layer form inner spacers and modified elements, respectively. The embodiment of the invention also relates to a semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods for forming semiconductor device structures. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation features smaller and more complex circuits than the previous one. However, these advances have increased the complexity of processing and manufacturing ICs.

[0003] During the evolution of integrated circuits, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be produced using a manufacturing process) has decreased. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs.

[0004] However, as feature sizes continue to decrease, manufacturing processes continue to become more difficult to perform. Therefore, forming reliable semiconductor devices at increasingly smaller sizes is a challenge. Summary of the Invention

[0005] An embodiment of the present disclosure provides a method for forming a semiconductor device structure, comprising: forming a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner on a substrate; partially removing the semiconductor layers and the sacrificial layers to form a first groove, wherein the first groove exposes the side edges of the semiconductor layers and the sacrificial layers; partially removing the sacrificial layers from the side edges of the sacrificial layers to form a plurality of second grooves; introducing modifying elements into the sacrificial layers and the semiconductor layers to convert the surface portions of the sacrificial layers and the semiconductor layers into modified layers, wherein the modifying elements include nitrogen, carbon, boron or a combination thereof; forming an internal spacer layer above the modified layer; and removing the internal spacer layer and the modified layer outside the second grooves, wherein the remaining portions of the internal spacer layer and the modified layer form an internal spacer and a modifying element, respectively.

[0006] Another embodiment of the present disclosure provides a method for forming a semiconductor device structure, comprising: forming a fin structure on a substrate, the fin structure having a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner; forming a dummy gate stack extending across the fin structure; partially removing the semiconductor layer and the sacrificial layer to form a first groove, the first groove exposing the side edges of the semiconductor layer and the sacrificial layer; replacing the sacrificial layer with a dielectric sacrificial layer; partially removing the dielectric sacrificial layer from the side edges of the dielectric sacrificial layer to form a plurality of second grooves; modifying a surface portion of the dielectric sacrificial layer with a modifying element to convert the surface portion into a modified element, wherein the modifying element includes nitrogen, carbon, boron or a combination thereof; forming an internal spacer covering the modified element in the second groove; removing the dummy gate stack and the dielectric sacrificial layer to release a plurality of semiconductor nanostructures composed of the remaining portion of the semiconductor layer; and forming a metal gate stack encapsulating the semiconductor nanostructure.

[0007] Another embodiment of the present disclosure provides a semiconductor device, comprising: a plurality of semiconductor nanostructures; a gate stack wrapping the semiconductor nanostructures; an epitaxial structure connecting the semiconductor nanostructures; a plurality of internal spacers located between the epitaxial structures and the gate stacks; and a plurality of protection elements, wherein each of the protection elements is located between the gate stack and a corresponding internal spacer of the internal spacers, and the protection elements contain nitrogen, carbon, boron, or a combination thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be increased or reduced as desired for clarity of discussion.

[0009] Figures 1A to 1J are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0010] Figure 1A-1 is a top view of an intermediate stage in a process for forming a portion of a semiconductor device structure in accordance with some embodiments.

[0011] Figure 1A-2 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0012] Figure 1A-3 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0013] Figure 1J-1is a top view of an intermediate stage in a process for forming a portion of a semiconductor device structure in accordance with some embodiments.

[0014] Figure 1J-2 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0015] Figure 1J-3 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0016] Figures 2A to 2J are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0017] Figure 2J-1 is a top view of an intermediate stage in a process for forming a portion of a semiconductor device structure in accordance with some embodiments.

[0018] Figure 2J-2 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0019] Figure 2J-3 is a cross-sectional view of an intermediate stage in a process for forming a portion of a semiconductor device structure, according to some embodiments. DETAILED DESCRIPTION

[0020] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the embodiments and / or configurations discussed.

[0021] Furthermore, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," and "upper," may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0022] Those skilled in the art will understand the term "substantially" in the description, such as "substantially flat" or "substantially coplanar", etc. In some embodiments, the adjective "substantially" can be removed. Where applicable, the term "substantially" can also include embodiments with "complete", "complete", "all", etc. The term "substantially" can vary in different technologies and is within the range of deviations understood by those skilled in the art. For example, the term "substantially" can also relate to a specified 90% or higher, such as a specified 95% or higher, in particular a specified 99% or higher, including a specified 100%, but the present disclosure is not limited to this. In addition, terms such as "substantially parallel" or "substantially perpendicular" can be interpreted as not excluding minor deviations from the specified arrangement, and can include, for example, deviations of up to 10°. The word "substantially" does not exclude "completely", for example, a component that is "substantially free of" Y can be completely free of Y.

[0023] The term "about" may vary across different technologies and is within the range of deviations understood by those skilled in the art. The term "about" in conjunction with a specific distance or dimension should be interpreted as not excluding minor deviations from the specified distance or dimension. For example, the term "about" may include deviations of up to 10% of the specified distance or dimension, but the present disclosure is not limited thereto. The term "about" in relation to a value x may mean the specified x ± 5 or 10%, but the present disclosure is not limited thereto.

[0024] Embodiments of the present disclosure may relate to FinFET structures having fins. The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns having a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in some embodiments, a sacrificial layer is formed above a substrate and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. However, the fins may be formed using one or more other applicable processes.

[0025] Embodiments of the present disclosure may relate to a gate-all-around (GAA) transistor structure. Any suitable method may be used to pattern the GAA structure. For example, the structure may be patterned using one or more photolithography processes (including double patterning or multiple patterning processes). In some embodiments, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having a pitch smaller than that obtainable using a single direct photolithography process, for example. For example, in some embodiments, a sacrificial layer is formed above a substrate, and the sacrificial layer is patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0026] Some embodiments of the present disclosure have been described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. Some of the described stages may be replaced or eliminated for different embodiments. Additional components may be added to the semiconductor device structure. Some of the components described below may be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a specific order, these operations may be performed in another logical order.

[0027] Figures 1A to 1J are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments. Figure 1A-1 is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1A It is along Figure 1A-1 A cross-sectional view of the structure taken along line II' in FIG. Figure 1A-2 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1A-2 It is along Figure 1A-1 A cross-sectional view of the structure taken along line II-II'. Figure 1A-3 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1A-3 It is along Figure 1A-1 A cross-sectional view of the structure taken along line III-III'.

[0028] In some embodiments, a semiconductor substrate 100 is received or provided. In some embodiments, semiconductor substrate 100 is a bulk semiconductor substrate, such as a semiconductor wafer. Semiconductor substrate 100 may include silicon or other elemental semiconductor materials, such as germanium. Semiconductor substrate 100 may be undoped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, semiconductor substrate 100 includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

[0029] In some other embodiments, the semiconductor substrate 100 includes a compound semiconductor. For example, the compound semiconductor includes a X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4 One or more III-V compound semiconductors of defined composition, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and they add up to 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrates including II-VI compound semiconductors may also be used.

[0030] In some embodiments, semiconductor substrate 100 is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate can be manufactured using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, semiconductor substrate 100 includes a multilayer structure. For example, semiconductor substrate 100 includes a silicon germanium layer formed on a bulk silicon layer.

[0031] Then, in some embodiments, a semiconductor stack having multiple semiconductor layers is formed over the semiconductor substrate 100. In some embodiments, the semiconductor stack includes multiple semiconductor layers 102a, 102b, and 102c. The semiconductor stack also includes multiple semiconductor layers 104a, 104b, and 104c. In some embodiments, the semiconductor layers 102a-102c and the semiconductor layers 104a-104c are arranged in an alternating manner.

[0032] In some embodiments, semiconductor layers 102a-102c serve as sacrificial layers that are removed in subsequent processes to release semiconductor layers 104a-104c. The released semiconductor layers 104a-104c form a plurality of semiconductor nanostructures. The released semiconductor nanostructures formed from semiconductor layers 104a-104c can serve as channel structures for one or more transistors.

[0033] In some embodiments, the semiconductor layers 104a-104c used to form the channel structure are made of a material different from that of the semiconductor layers 102a-102c. In some embodiments, the semiconductor layers 104a-104c are made of or include silicon, germanium, another suitable material, or a combination thereof. In some embodiments, the semiconductor layers 102a-102c are made of or include silicon germanium. In some other embodiments, the semiconductor layers 104a-104c are made of silicon germanium, and the semiconductor layers 102a-102c are made of silicon germanium having a different germanium atomic concentration than the semiconductor layers 104a-104c. Due to the different compositions, different etch selectivities and / or different oxidation rates can be achieved between the semiconductor layers 102a-102c and the semiconductor layers 104a-104c during subsequent processing.

[0034] The present disclosure contemplates that semiconductor layers 102a-102c and semiconductor layers 104a-104c include any combination of semiconductor materials that can provide a desired etch selectivity, a desired oxidation rate difference, and / or a desired performance characteristic (eg, a material that maximizes current flow).

[0035] In some embodiments, the semiconductor layers 102a-102c and 104a-104c are formed using multiple epitaxial growth operations. Each of the semiconductor layers 102a-102c and 104a-104c can be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other suitable processes, or a combination thereof.

[0036] In some embodiments, semiconductor layers 102a-102c and 104a-104c are grown in situ in the same process chamber. In some embodiments, the growth of semiconductor layers 102a-102c and 104a-104c is performed alternately and sequentially in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken until the epitaxial growth of the semiconductor stack is completed.

[0037] Afterwards, a hard mask element is formed over the semiconductor stack to assist in subsequent patterning of the semiconductor stack. One or more photolithography processes and one or more etching processes are used to pattern the semiconductor stack into a plurality of fin structures 106. Figure 1A 、 Figure 1A-1 、 Figure 1A-2 and Figure 1A-3 As shown, one of the fin structures 106 is shown. The fin structure 106 can be patterned by any suitable method. For example, the fin structure 106 can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Double patterning or multiple patterning processes can combine photolithography and self-aligned processes, allowing for the creation of patterns having, for example, a smaller pitch than can be achieved using a single direct photolithography process.

[0038] The semiconductor stack is partially removed to form a plurality of fin structures 106 (including Figure 1A 、 Figure 1A-1 、 Figure 1A-2 and Figure 1A-3 The fin structure 106 shown in FIG. Figure 1A 、 Figure 1A-2 and Figure 1A-3 As shown, the fin structure 106 may include portions of the semiconductor layers 102a-102c and 104a-104c and a plurality of semiconductor fins (including Figure 1A 、 Figure 1A-2 and Figure 1A-3 The semiconductor fin 101 is shown. The semiconductor substrate 100 may also be partially removed during the etching process for forming the fin structure 106. The remaining protruding portion of the semiconductor substrate 100 forms the semiconductor fin 101.

[0039] Afterwards, if Figure 1A-2 and Figure 1A-3 As shown, in accordance with some embodiments, isolation structure 115 is formed to surround a lower portion of fin structure 106. In some embodiments, isolation structure 115 includes a plurality of sub-layers adjacent to semiconductor fin 101.

[0040] In some embodiments, one or more dielectric layers are deposited over the fin structure 106 and the semiconductor substrate 100 to overfill the trench. The dielectric layer may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, one or more other suitable materials, or a combination thereof. The dielectric layer may be deposited using a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, a chemical vapor deposition (CVD) process, one or more other suitable processes, or a combination thereof.

[0041] Afterwards, a planarization process is used to partially remove the dielectric layer. The hard mask element above the fin structure 106 can also serve as a stop layer for the planarization process. The planarization process can include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other suitable processes, or a combination thereof.

[0042] Thereafter, one or more etch-back processes are used to partially remove the dielectric layer. As a result, the remaining portion of the dielectric layer forms the isolation structure 115. Figure 1A-2 and Figure 1A-3 As shown, an upper portion of the fin structure 106 protrudes from the top surface of the isolation structure 115 .

[0043] In some embodiments, as Figure 1A-2 and Figure 1A-3 As shown, the etch-back process for forming the isolation structure 115 is carefully controlled to ensure that the topmost surface of the isolation structure 115 is at an appropriate height level. In some embodiments, the topmost surface of the isolation structure 115 is lower than the bottommost surface of the semiconductor layer 102a used as a sacrificial layer.

[0044] Thereafter, the hard mask element is removed over the fin structure 106. Alternatively, in some other embodiments, the hard mask element is removed or consumed during the planarization process and / or the etch-back process for forming the isolation structure 115.

[0045] Then, according to some embodiments, as Figure 1A 、 Figure 1A-1 、 Figure 1A-2 and Figure 1A-3As shown, dummy gate stacks 120A and 120B are formed to extend across the fin structure 106. The dummy gate stacks 120A and 120B partially cover the fin structure 106 and extend across the fin structure 106. In some embodiments, the dummy gate stacks 120A and 120B partially cover the fin structure 106. Figure 1A-2 and Figure 1A-3 As shown, the dummy gate stacks 120A and 120B extend across and wrap around the fin structure 106 .

[0046] like Figure 1A 、 Figure 1A-2 and Figure 1A-3 As shown, each of the dummy gate stacks 120A and 120B includes a dummy gate dielectric layer 116 and a dummy gate electrode 118. The dummy gate dielectric layer 116 may be made of or include silicon oxide or another suitable material. The dummy gate electrode 118 may be made of or include polysilicon or another suitable material.

[0047] In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure 115 and the fin structure 106. The dummy gate dielectric material layer can be deposited using an ALD process, a CVD process, one or more other suitable processes, or a combination thereof. The dummy gate electrode layer can be deposited using a CVD process. Thereafter, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form dummy gate stacks 120A and 120B.

[0048] In some embodiments, hard mask element 119 is used to assist in the patterning process used to form dummy gate stacks 120A and 120B. With hard mask element 119 acting as an etch mask, one or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. As a result, the remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form dummy gate stacks 120A and 120B.

[0049] like Figure 1A and Figure 1A-1 As shown, according to some embodiments, gate spacers 128' are then formed over the sidewalls of the dummy gate stacks 120A and 120B. In some embodiments, one or more spacer layers are deposited over the dummy gate stacks 120A and 120B and the fin structure 106. The spacer layers extend along the top and sidewalls of the dummy gate stacks 120A and 120B.

[0050] The spacer layer may be made of or include silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, silicon oxide, carbon-containing silicon oxide, aluminum oxide, hafnium oxide, one or more other suitable materials, or combinations thereof. In some embodiments, one or more spacer layers are made of a high-k material. The spacer layer may be deposited using a CVD process, an ALD process, a physical vapor deposition (PVD) process, another suitable process, or a combination thereof.

[0051] Thereafter, according to some embodiments, the spacer layer is partially removed. One or more anisotropic etching processes may be used to partially remove the spacer layer. As a result, the remaining portion of the spacer layer forms the gate spacer 128'. Figure 1A and Figure 1A-1 As shown, gate spacers 128 ′ extend along sidewalls of the dummy gate stacks 120A and 120B.

[0052] like Figure 1B As shown, according to some embodiments, the fin structure 106 is partially removed. As a result, a plurality of grooves 130 are formed. The grooves 130 expose the side edges of the semiconductor layers 102a-102c and 104a-104c. The grooves 130 can be used to accommodate epitaxial structures (such as source / drain structures) to be formed later. Depending on the context, the source / drain structure (or region) can be referred to as a source or a drain, either individually or collectively. In some embodiments, the grooves 130 formed in the fin structure 106 are used to accommodate a p-type doped epitaxial structure to be formed later. In some embodiments, the grooves 130 formed in the fin structure 106 are used to accommodate an n-type doped epitaxial structure to be formed later.

[0053] One or more etching processes may be used to form the recess 130. In some embodiments, a dry etching process is used to form the recess 130. Alternatively, a wet etching process may be used to form the recess 130. The recess 130 penetrates the fin structure 106. In some embodiments, as shown in FIG. Figure 1B As shown, the recess 130 extends further into the semiconductor fin 101 .

[0054] In some embodiments, recess 130 has substantially vertical sidewalls. In these cases, due to the profile of recess 130, the upper semiconductor layer (such as semiconductor layer 104c) is substantially as wide as the lower semiconductor layer (such as semiconductor layer 104b).

[0055] However, the embodiments of the present disclosure have many variations. In some other embodiments, each groove 130 has a sloped sidewall. The upper portion of the groove 130 is larger (or wider) than the lower portion of the groove 130. In these cases, due to the profile of the groove 130, the upper semiconductor layer (such as semiconductor layer 104c) is shorter than the lower semiconductor layer (such as semiconductor layer 104b).

[0056] Afterwards, if Figure 1C As shown, according to some embodiments, the semiconductor layers 102a-102c are laterally etched. As a result, the side edges of the semiconductor layers 102a-102c retreat from the side edges of the semiconductor layers 104a-104c. The side edges of the semiconductor layers 102a-102c are pulled back. Figure 1C As shown, due to the lateral etching of semiconductor layers 102a-102c, recesses 132 are formed. Recesses 132 can be used to accommodate protection elements and internal spacers that will be formed later. Semiconductor layers 102a-102c can be laterally etched using a wet etching process, a dry etching process, or a combination thereof. In some other embodiments, semiconductor layers 102a-102c are partially oxidized before the lateral etching.

[0057] like Figure 1C As shown, according to some embodiments, surface portions of semiconductor layers 102a-102c and 104a-104c and semiconductor fin 101 are oxidized and become native oxide layers 133. Native oxide layers 133 naturally grow on surface portions of semiconductor layers 102a-102c and 104a-104c. Each native oxide layer 133 has a plurality of portions, including a first portion P1 of semiconductor layers 102a-102c and a second portion P2 of semiconductor layers 104a-104c.

[0058] In some embodiments, the first portion P1 and the second portion P2 have different compositions. In some embodiments, the semiconductor layers 102a-102c are made of silicon germanium. Exposed surface portions of the semiconductor layers 102a-102c are oxidized to form the first portion P1. The first portion P1 can be made of silicon germanium oxide. In some embodiments, the semiconductor layers 104a-104c are made of silicon. Exposed surface portions of the semiconductor layers 104a-104c are oxidized to form the second portion P2. The second portion P2 can be made of silicon oxide.

[0059] Thereafter, according to some embodiments, a modification process is used to modify surface portions of the semiconductor layers 102a-102c and 104a-104c. As a result, according to some embodiments, as Figure 1DAs shown, the surface portions of semiconductor layers 102a-102c and 104a-104c are converted into modified layers 133'. During the modification process, modifying elements are introduced into native oxide layer 133 to form modified layers 133'. As a result, the density of modified layers 133' increases to be higher than that of native oxide layer 133. Modifying elements may include nitrogen, carbon, boron, another suitable material, or a combination thereof.

[0060] According to some embodiments, modified layer 133' has opposing sidewalls S11 and S22. According to some embodiments, sidewall S11 faces semiconductor layers 102a-102c and 104a-104c. According to some embodiments, sidewall S22 faces away from semiconductor layers 102a-102c and 104a-104c. The atomic concentration of the modifying element (e.g., nitrogen, carbon, or boron) in modified layer 133' increases continuously from sidewall S11 to sidewall S22.

[0061] The modification process enhances the etch resistance of the modified layers 133', making them more resistant to etchants used to remove semiconductor material and / or oxide material.The modified layers 133' may have a thickness in a range from about 3 angstroms to about 15 angstroms.

[0062] In some embodiments, the modifying element includes nitrogen. Figure 1C The structure shown is placed in a nitrogen-containing atmosphere to introduce nitrogen into the native oxide layer 133. In some embodiments, a nitrogen-containing gas (such as NH3 gas) is introduced into the reaction chamber. Figure 1C The structure shown is set in the reaction chamber. As a result, nitrogen from the NH3 gas can be introduced into the native oxide layer 133. As a result, Figure 1D In some embodiments, the nitrogen atomic concentration of the modified layer 133' gradually decreases from the outer surface of the modified layer 133' (adjacent to the groove 130) toward the inner surface of the modified layer 133' (adjacent to the semiconductor layers 102a-102c or 104a-104c).

[0063] In some embodiments, the surface portions of the semiconductor layers 102a-102c and 104a-104c (or the native oxide layer 133) are exposed to a nitrogen-containing gas (such as NH3 gas) at a high temperature. In some embodiments, the native oxide layer 133 is exposed to the NH3 gas at a temperature ranging from about 550° C. to about 600° C. for about 10 minutes to about 2 hours.

[0064] Each modified layer 133' has multiple portions, including a first portion P1' near the semiconductor layers 102a-102c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the semiconductor layers 102a-102c are made of silicon germanium. The first portion P1' can be made of nitrogen-containing silicon germanium oxide. The nitrogen atomic concentration of the first portion P1' can range from approximately 5% to approximately 25%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of nitrogen-containing silicon oxide.

[0065] In some embodiments, the modifying element includes carbon. Figure 1C The structure shown is placed in a carbon-containing atmosphere to introduce carbon into the native oxide layer 133. In some embodiments, a carbon-containing gas (such as C3H6 gas) is introduced into the reaction chamber. Figure 1C The structure shown is set in the reaction chamber. As a result, carbon from the C3H6 gas can be introduced into the native oxide layer 133. As a result, Figure 1D In some embodiments, the carbon atomic concentration of the modified layer 133' gradually decreases from the outer surface of the modified layer 133' (adjacent to the groove 130) toward the inner surface of the modified layer 133' (adjacent to the semiconductor layers 102a-102c or 104a-104c).

[0066] In some embodiments, the surface portions of the semiconductor layers 102a-102c and 104a-104c (or the native oxide layer 133) are exposed to a carbon-containing gas (such as C3H6 gas) at a high temperature. In some embodiments, the native oxide layer 133 is exposed to the C3H6 gas at a temperature ranging from about 550° C. to about 650° C. for about 10 minutes to about 2 hours.

[0067] Each modified layer 133' has multiple portions, including a first portion P1' near the semiconductor layers 102a-102c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the semiconductor layers 102a-102c are made of silicon germanium. The first portion P1' can be made of carbon-containing silicon germanium oxide. The carbon atomic concentration of the first portion P1' can range from approximately 1% to approximately 15%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of carbon-containing silicon oxide.

[0068] In some embodiments, the modifying element includes boron. Figure 1CThe structure shown is placed in a boron-containing atmosphere to introduce boron into the native oxide layer 133. In some embodiments, a boron-containing plasma is introduced into the reaction chamber. Figure 1C The structure shown is set in a reaction chamber. As a result, boron from the boron-containing plasma can be introduced into the native oxide layer 133. In some embodiments, an ion implantation process is used to introduce boron into the native oxide layer 133. As a result, Figure 1D In some embodiments, the boron atomic concentration of the modified layer 133' gradually decreases from the outer surface of the modified layer 133' (adjacent to the groove 130) toward the inner surface of the modified layer 133' (adjacent to the semiconductor layers 102a-102c or 104a-104c).

[0069] Each modified layer 133' has multiple portions, including a first portion P1' near the semiconductor layers 102a-102c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the semiconductor layers 102a-102c are made of silicon germanium. The first portion P1' can be made of boron-containing silicon germanium oxide. The boron atomic concentration of the first portion P1' can range from approximately 0.5% to approximately 1%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of boron-containing silicon oxide.

[0070] Many variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, two or more modifying elements are introduced into the surface portions of semiconductor layers 102a-102c and 104a-104c. As a result, the resulting modified layer may contain two or more modifying elements. This may improve the etching resistance of the modified layer.

[0071] like Figure 1E As shown, according to some embodiments, Figure 1DAn insulating layer 134 is deposited over the structure shown. The insulating layer 134 covers the dummy gate stacks 120A and 120B and the modified layer 133' and fills the recess 132. The insulating layer 134 can be made of or include silicon nitride containing carbon (SiCN), silicon oxynitride containing carbon (SiOCN), silicon oxide containing carbon (SiOC), silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, one or more other suitable materials, or combinations thereof. In some embodiments, the insulating layer 134 has a higher nitrogen atomic concentration than the modified layer 133'. In some embodiments, the insulating layer 134 has a higher carbon atomic concentration than the modified layer 133'. In some embodiments, the insulating layer 134 has a lower boron atomic concentration than the modified layer 133'.

[0072] In some embodiments, the insulating layer is a single layer. In some other embodiments, the insulating layer includes multiple sublayers. Some sublayers may be made of different materials and / or contain different compositions. The insulating layer may be deposited using a CVD process, an ALD process, one or more other suitable processes, or a combination thereof.

[0073] Thereafter, according to some embodiments, one or more etching processes are used to partially remove the insulating layer 134 and the modified layer 133'. Portions of the insulating layer 134 and the modified layer 133' outside the groove 132 may be removed. As a result, as shown in FIG. Figure 1F As shown, according to some embodiments, the remaining portion of the insulating layer 134 forms a plurality of internal spacers 136. Figure 1F As shown, the remaining portions of the modified layer 133' form a plurality of protective elements (or modified elements) 133". The etching process may include a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the inner spacers 136 and the gate spacers 128' have different compositions to provide etching selectivity between the inner spacers 136 and the gate spacers 128'.

[0074] like Figure 1F As shown, the internal spacer 136 is separated from the side edges of the semiconductor layers 102a-102c by the protection element 133". The protection element 133" and the internal spacer 136 can work together to prevent subsequently formed epitaxial structures (such as source / drain structures) from being damaged during subsequent processes for removing the semiconductor layers 102a-102c. In some embodiments, the internal spacer 136 is made of a low-k material having a lower dielectric constant than silicon oxide. In these cases, the internal spacer 136 can also be used to reduce parasitic capacitance between the subsequently formed source / drain structures and the gate stack. As a result, the operating speed of the semiconductor device structure can be increased.

[0075] like Figure 1F As shown, in some embodiments, after the etching process for forming the inner spacer 136 and the protection element 133 ″, the portion of the semiconductor fin 101 initially covered by the insulating layer is exposed by the recess 130 . Figure 1F As shown, side edges of the semiconductor layers 104 a - 104 c are exposed by the grooves 130 .

[0076] like Figure 1F As shown, each protection element 133" has a first portion P1" and a second portion P2". The first portion P1" is adjacent to one of the semiconductor layers 102a-102c, and the second portion P2" is adjacent to the nearby semiconductor layers 104a-104c. The first portion P1" of the protection element 133" can be made of or include nitrogen-containing silicon germanium oxide, carbon-containing silicon germanium oxide, boron-containing silicon germanium oxide, another suitable material, or a combination thereof. The second portion P2" of the protection element 133" can be made of or include nitrogen-containing silicon oxide, carbon-containing silicon oxide, boron-containing silicon oxide, another suitable material, or a combination thereof. In some embodiments, the second portion P2" of the protection element 133" has a higher nitrogen atomic concentration than the first portion P1". In some embodiments, the second portion P2 ″ of the protection element 133 ″ has a higher carbon atomic concentration than the first portion P1 ″. In some embodiments, the second portion P2 ″ of the protection element 133 ″ has a higher boron atomic concentration than the first portion P1 ″.

[0077] like Figure 1G As shown, according to some embodiments, an epitaxial structure 138 is formed on the side edges of the semiconductor layers 104a-104c and the semiconductor fin 101. The epitaxial structure 138 can be used as a source / drain structure (or region). Depending on the context, the source / drain structure (or region) can refer to a source or a drain, either individually or collectively. In some embodiments, the epitaxial structure 138 fills the groove 130. In some embodiments, the epitaxial structure 138 overfills the groove 130 to ensure full contact between the epitaxial structure 138 and the side edges of the nearby semiconductor layer 104c. In some other embodiments, the epitaxial structure 138 partially fills the groove 130. Figure 1G As shown, in some embodiments, the epitaxial structure 138 is in direct contact with the inner spacer 136 and the protection element 133 ″.

[0078] In some embodiments, epitaxial structure 138 is connected to some of semiconductor layers 104a-104c. Some of semiconductor layers 104a-104c are sandwiched between epitaxial structure 138. In some embodiments, epitaxial structure 138 is an n-type doped epitaxial structure. Epitaxial structure 138 may include epitaxially grown silicon, epitaxially grown silicon germanium (SiGe), or another suitable epitaxially grown semiconductor material. In some other embodiments, epitaxial structure 138 is a p-type doped epitaxial structure. Epitaxial structure 138 may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or another suitable epitaxially grown semiconductor material.

[0079] In some embodiments, epitaxial structure 138 is formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and / or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other suitable processes, or a combination thereof. In some embodiments, the formation of epitaxial structure 138 involves one or more etching processes for fine-tuning the shape of epitaxial structure 138.

[0080] In some embodiments, epitaxial structures 138 are doped with one or more suitable n-type dopants. For example, epitaxial structures 138 are Si source / drain components doped with phosphorus (P), antimony (Sb), arsenic (As), or another suitable dopant. In some other embodiments, epitaxial structures 138 are doped with one or more suitable p-type dopants. For example, epitaxial structures 138 are SiGe source / drain components doped with boron (B), gallium (Ga), indium (In), or another suitable dopant. In some embodiments, each epitaxial structure 138 has a first region and a second region located above the first region. The second region can have a greater dopant concentration than the first region.

[0081] In some embodiments, epitaxial structures 138 are doped in situ during their epitaxial growth. The initial reaction gas mixture used to form epitaxial structures 138 contains a dopant. In some other embodiments, epitaxial structures 138 are not doped during their growth. Instead, epitaxial structures 138 are doped in a subsequent process after epitaxial structures 138 are formed. In some embodiments, doping is achieved using an ion implantation process, a plasma immersion ion implantation process, a gas and / or solid source diffusion process, one or more other suitable processes, or a combination thereof. In some embodiments, epitaxial structures 138 are also exposed to one or more annealing processes to activate the dopant. For example, a rapid thermal annealing process is used.

[0082] Then, according to some embodiments, as Figure 1GAs shown, a dielectric layer 140 is formed over the epitaxial structure 138 to laterally surround the dummy gate stacks 120A and 120B. In some embodiments, a contact etch stop layer is formed over the epitaxial structure 138 before the dielectric layer 140 is formed. The contact etch stop layer may further extend along the sidewalls of the dummy gate stacks 120A and 120B. The contact etch stop layer may be made of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, another suitable material, or a combination thereof. The dielectric layer 140 may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), a low-k material, a porous dielectric material, another suitable material, or a combination thereof.

[0083] In some embodiments, the etch stop material layer and the dielectric material layer are sequentially deposited. The etch stop material layer can be deposited using a CVD process, an ALD process, a PVD process, one or more other applicable processes, or a combination thereof. The dielectric material layer can be deposited using an FCVD process, a CVD process, an ALD process, another applicable process, or a combination thereof.

[0084] Afterwards, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. Figure 1G As shown, the remaining portions of the etch stop material layer and the dielectric material layer respectively form a contact etch stop layer and a dielectric layer 140. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, one or more other suitable processes, or a combination thereof.

[0085] Afterwards, if Figure 1H As shown, in accordance with some embodiments, one or more etching processes are used to remove the dummy gate electrode 118 to form a trench 142. The trench 142 is surrounded by a dielectric layer 140.

[0086] like Figure 1H As shown, according to some embodiments, the dummy gate dielectric layer 116 and the semiconductor layers 102a-102c (used as sacrificial layers) are also removed. In some embodiments, one or more etching processes are used to remove the dummy gate dielectric layer 116 and the semiconductor layers 102a-102c. As a result, as shown in FIG. Figure 1H As shown, a groove 144 is formed.

[0087] In some embodiments, the native oxide layer 133 has been modified and converted into a protective element 133″, which has high etching resistance to the etchant used to remove the semiconductor layers 102a-102c (for example, a wet etchant including diluted HF, HF, H2SO4, H3PO4 or NH4F and a dry etchant including O2 ash, O2 plasma or CF4 radicals). Therefore, the epitaxial structure 138 is protected by the protective element 133″ and prevented from being damaged. The reliability and performance of the semiconductor device structure are thereby improved.

[0088] Due to the high etching selectivity, semiconductor layers 104a-104c are barely (or substantially not) etched. The remaining portions of semiconductor layers 104a-104c form a plurality of semiconductor nanostructures 104a'-104c'. Semiconductor nanostructures 104a'-104c' are formed or comprised of the remaining portions of semiconductor layers 104a-104c. Semiconductor nanostructures 104a'-104c' suspended above semiconductor fins 101 can serve as channel structures for transistors.

[0089] In some other embodiments, the etchant used to remove semiconductor layers 102a-102c also slightly removes semiconductor layers 104a-104c forming semiconductor nanostructures 104a'-104c. As a result, after removing semiconductor layers 102a-102c, the resulting semiconductor nanostructures 104a'-104c' are thinner. In some embodiments, each of semiconductor nanostructures 104a'-104c' is thinner than its edge portion because the edge portion is surrounded by other elements, thus preventing the etchant from reaching and etching the edge portion.

[0090] After removing the semiconductor layers 102a-102c (serving as sacrificial layers), a recess 144 is formed. The recess 144 is connected to the trench 142 and surrounds each of the semiconductor nanostructures 104a'-104c'. Figure 1H As shown, even though the grooves 144 are formed between the semiconductor nanostructures 104a'-104c', the semiconductor nanostructures 104a'-104c' are still held by the adjacent elements, including the epitaxial structure 138, the protective element 133", and the inner spacer 136. Therefore, after the dummy gate stacks 120A and 120B and the semiconductor layers 102a-102c (serving as sacrificial layers) are removed, the released semiconductor nanostructures 104a'-104c' are prevented from falling.

[0091] During the removal of semiconductor layers 102a-102c (serving as sacrificial layers), protection element 133" and inner spacer 136 prevent epitaxial structure 138 from being etched or damaged. This improves the quality and reliability of the semiconductor device structure.

[0092] like Figure 1I As shown, according to some embodiments, a metal gate stack is formed to fill the trench 142 and the recess 144. The metal gate stack may include a gate dielectric layer 150, a work function layer 152, and a conductive filling layer 154. The metal gate stack extends into the recess 144 to wrap each of the semiconductor nanostructures 104a'-104c'.

[0093] In some embodiments, the gate dielectric layer 150 is made of or includes a dielectric material having a high dielectric constant (high-K). The gate dielectric layer 150 may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, a hafnium dioxide-aluminum oxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-K materials, or a combination thereof. The gate dielectric layer 150 may be deposited using an ALD process, a CVD process, one or more other suitable processes, or a combination thereof.

[0094] In some embodiments, an interfacial layer is formed on the surfaces of the semiconductor nanostructures 104a'-104c' before forming the gate dielectric layer 150. The interfacial layer is very thin and made of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by applying an oxidizing agent to the surfaces of the semiconductor nanostructures 104a'-104c'. For example, a liquid containing hydrogen peroxide can be applied or provided to the surfaces of the semiconductor nanostructures 104a'-104c' to form the interfacial layer.

[0095] The work function layer 152 can be used to provide a desired work function for the transistor to enhance device performance, including improved threshold voltage. In some embodiments, the work function layer surrounding the semiconductor nanostructures 104a'-104c' is used to form a PMOS device. In these cases, the work function layer 152 is a p-type work function layer. The p-type work function layer can provide a work function value suitable for the device, such as equal to or greater than approximately 4.8 eV.

[0096] The p-type work function layer may include metal, metal carbide, metal nitride, other suitable materials, or combinations thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, one or more other suitable materials, or combinations thereof.

[0097] In some embodiments, the work function layer surrounding the semiconductor nanostructures 104a'-104c' is used to form an NMOS device. The work function layer 152 is an n-type work function layer. The n-type work function layer can provide a work function value suitable for the device, such as equal to or less than about 4.5 eV.

[0098] The n-type work function layer may include a metal, a metal carbide, a metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function layer is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

[0099] The work function layer can also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or combinations thereof. The thickness and / or composition of the work function layer can be fine-tuned to adjust the work function level.

[0100] The work function layer can be deposited over the gate dielectric layer 150 using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof. In some embodiments, the formation of the work function layer involves one or more patterning processes. As a result, an n-type work function layer and a p-type work function layer are selectively formed over different regions.

[0101] In some embodiments, a barrier layer is formed before the work function layer 152 to interface with the gate dielectric layer 150 and the subsequently formed work function layer. The barrier layer can also be used to prevent diffusion between the gate dielectric layer 150 and the subsequently formed work function layer 152. The barrier layer can be made of or include a metal-containing material. The metal-containing material can include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer can be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0102] In some embodiments, the conductive fill layer 154 is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. The conductive fill layer 154 may be deposited over the work function layer 152 using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin coating process, one or more other suitable processes, or a combination thereof.

[0103] In some embodiments, a blocking layer is formed over the work function layer 152 before forming the conductive fill layer 154. The blocking layer can be used to prevent the subsequently formed conductive fill layer 154 from diffusing or penetrating into the work function layer 152. The blocking layer can be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The blocking layer can be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other suitable processes, or a combination thereof.

[0104] Figure 1J-1 is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1J It is along Figure 1J-1 A cross-sectional view of the structure taken along line II' in FIG. Figure 1J-2 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1J-2 It is along Figure 1J-1 A cross-sectional view of the structure taken along line II-II'. Figure 1J-3 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 1J-3 It is along Figure 1J-1 A cross-sectional view of the structure taken along line III-III'.

[0105] Thereafter, according to some embodiments, a planarization process is performed to remove portions of the metal gate stack outside the trench 142 and the recess 144. As a result, according to some embodiments, as shown in FIG. Figure 1J 、 Figure 1J-1 、 Figure 1J-2 and Figure 1J-3 As shown, the remaining portions of the metal gate stack layer form metal gate stacks 156A and 156B. The planarization process may include a CMP process or another suitable process.

[0106] In some other embodiments, the conductive filling layer 154 does not extend into the groove 144 because the groove 144 is smaller and has already been filled with other elements, such as the gate dielectric layer 150 and the work function layer 152. However, the embodiments of the present disclosure are not limited thereto.

[0107] like Figure 1JAs shown, each protection element 133″ has a first surface S1 close to the metal gate stack 156A or 156B and a second surface S2 close to the corresponding inner spacer 136. In some embodiments, the atomic concentration of the modifying element (such as nitrogen, carbon, and / or boron) at the second surface S2 is higher than the atomic concentration at the first surface S1. In some embodiments, the atomic concentration of the modifying element (such as nitrogen, carbon, and / or boron) gradually increases along the direction from the first surface S1 toward the second surface S2.

[0108] Many variations and / or modifications may be made to the embodiments of the present disclosure. Figures 2A to 2J are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, according to some embodiments.

[0109] In some embodiments, forming Figure 1B The structure shown is the same as or similar to the structure shown in FIG. Thereafter, the semiconductor layers 102a-102c used as sacrificial layers are removed. As a result, according to some embodiments, Figure 2A One or more etching processes may be used to remove the semiconductor layers 102a-102c. Figure 2A As shown, after the semiconductor layers 102a-102c are removed, a plurality of recesses 202 are formed. The semiconductor layers 104a-104c are released from the semiconductor layers 102a-102c. The semiconductor layers 104a-104c are firmly held in place with the support of the dummy gate stacks 120A and 120B.

[0110] like Figure 2B As shown, according to some embodiments, a dielectric layer 204 is deposited to overfill the recess 202 and surround the semiconductor layers 104a-104c. The dielectric layer 204 may serve as a sacrificial layer and will be removed later. The dielectric layer 204 may be made of an oxide material. The dielectric layer 204 may be made of or include silicon oxide, silicon oxynitride, another suitable material, or a combination thereof. The dielectric layer 204 may be deposited using a CVD process, an ALD process, another suitable process, or a combination thereof.

[0111] like Figure 2C As shown, according to some embodiments, the dielectric layer 204 is partially removed. The portion of the dielectric layer 204 outside the groove 202 is removed. Thereafter, the dielectric layer 204 is further laterally etched to form a plurality of grooves 202'. As a result, as shown in FIG. Figure 2C As shown, the remaining portion of the dielectric layer 204 forms a plurality of dielectric sacrificial layers 206a, 206b, and 206c. The side edges of the dielectric sacrificial layers 206a, 206b, and 206c are set back from the side edges of the semiconductor layers 104a-104c.

[0112] In some embodiments, similar to Figure 1C In the illustrated embodiment, a plurality of native oxide layers 208 are formed at surface portions of the semiconductor layers 104a-104c and the semiconductor fins 101. In some embodiments, the semiconductor layers 104a-104c are made of silicon, and the native oxide layers 208 are made of silicon oxide.

[0113] like Figure 2D As shown, similar to Figure 1D In the embodiment shown, the modification process is used to convert the surface portion of the dielectric sacrificial layers 206a-206c and the surface portion of the semiconductor layers 104a-104c (ie, the native oxide layer 208) into a modified layer 233'. The formation method of the modified layer 233' can be the same as that of the Figure 1D The modified layer 133' is formed by the same or similar method. The modification process enhances the etching resistance of the modified layer 233', making it more resistant to the etchants used to remove the semiconductor material and / or oxide material. The modified layer 233' can have a thickness ranging from about 3 angstroms to about 15 angstroms.

[0114] In some embodiments, the modifying element includes nitrogen. Figure 2C The structure shown is placed in a nitrogen-containing atmosphere to introduce nitrogen into the surface portions of the semiconductor layers 104a-104c (i.e., the native oxide layer 208) and the surface portions of the dielectric sacrificial layers 206a-206c. In some embodiments, a nitrogen-containing gas (such as NH3 gas) is introduced into the reaction chamber. Figure 2C The structure shown is set in the reaction chamber. As a result, nitrogen can be introduced from NH3 gas. As a result, Figure 2D In some embodiments, the nitrogen atomic concentration of the modified layer 233' gradually decreases from the outer surface of the modified layer 233' (adjacent to the groove 130) toward the inner surface of the modified layer 233' (adjacent to the semiconductor layers 104a-104c or the dielectric sacrificial layers 206a-206c).

[0115] Each modified layer 233' has multiple portions, including a first portion P1' near the dielectric sacrificial layers 206a-206c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the dielectric sacrificial layers 206a-206c are made of silicon oxide. The first portion P1' can be made of nitrogen-containing silicon oxide. The nitrogen atomic concentration of the first portion P1' can range from about 5% to about 25%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of nitrogen-containing silicon oxide. In some embodiments, the silicon atomic concentration of the second portion P2' is higher than that of the first portion P1'.

[0116] In some embodiments, the modifying element includes carbon. Figure 2C The structure shown is placed in a carbon-containing atmosphere to introduce carbon into the surface portion of the semiconductor layers 104a-104c (i.e., the native oxide layer 208). In some embodiments, a carbon-containing gas (such as C3H6 gas) is introduced into the reaction chamber. Figure 2C The structure shown is set in the reaction chamber. As a result, carbon from the C3H6 gas can be introduced into the native oxide layer 208. As a result, Figure 2D In some embodiments, the carbon atomic concentration of the modified layer 233' gradually decreases from the outer surface of the modified layer 233' (adjacent to the groove 130) toward the inner surface of the modified layer 233' (adjacent to the dielectric sacrificial layers 206a-206c or the semiconductor layers 104a-104c).

[0117] In some embodiments, the surface portions of the dielectric sacrificial layers 206a-206c and the semiconductor layers 104a-104c (or the native oxide layer 208) are exposed to a carbon-containing gas (such as C3H6 gas) at a high temperature. In some embodiments, the native oxide layer 208 is exposed to the C3H6 gas at a temperature ranging from about 550° C. to about 650° C. for about 10 minutes to about 2 hours.

[0118] Each modified layer 233' has multiple portions, including a first portion P1' near the dielectric sacrificial layers 206a-206c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the dielectric sacrificial layers 206a-206c are made of silicon oxide. The first portion P1' can be made of carbon-containing silicon oxide. The carbon atomic concentration of the first portion P1' can range from about 1% to about 15%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of carbon-containing silicon oxide. In some embodiments, the silicon atomic concentration of the second portion P2' is higher than that of the first portion P1'.

[0119] In some embodiments, the modifying element includes boron. Figure 2C The structure shown is placed in a boron-containing atmosphere to introduce boron into the native oxide layer 208. In some embodiments, a boron-containing plasma is introduced into the reaction chamber. Figure 2C The structure shown is arranged in a reaction chamber. As a result, boron from the boron-containing plasma can be introduced into the native oxide layer 208 and the dielectric sacrificial layers 206a-206c. In some embodiments, an ion implantation process is used to introduce boron. As a result, Figure 2DIn some embodiments, the boron atomic concentration of the modified layer 233' gradually decreases from the outer surface of the modified layer 233' (adjacent to the groove 130) toward the inner surface of the modified layer 233' (adjacent to the dielectric sacrificial layers 206a-206c or the semiconductor layers 104a-104c).

[0120] Each modified layer 233' has multiple portions, including a first portion P1' near the dielectric sacrificial layers 206a-206c and a second portion P2' near the semiconductor layers 104a-104c. In some embodiments, the first portion P1' and the second portion P2' have different compositions. In some embodiments, the dielectric sacrificial layers 206a-206c are made of silicon oxide. The first portion P1' can be made of boron-containing silicon oxide. The boron atomic concentration of the first portion P1' can range from approximately 0.5% to approximately 1%. In some embodiments, the semiconductor layers 104a-104c are made of silicon. The second portion P2' can be made of boron-containing silicon oxide. In some embodiments, the silicon atomic concentration of the second portion P2' is higher than that of the first portion P1'.

[0121] Numerous variations and / or modifications may be made to the embodiments of the present disclosure. In some other embodiments, two or more modifying elements are introduced into the surface portions of the dielectric sacrificial layers 206a-206c and the semiconductor layers 104a-104c. As a result, the resulting modified layer may contain two or more modifying elements, which may improve the etching resistance of the modified layer.

[0122] like Figure 2E As shown, according to some embodiments, an insulating layer 134 is deposited. The material and formation method of the insulating layer 134 may be the same as Figure 1E The material and formation method of the insulating layer 134 shown are the same or similar.

[0123] like Figure 2F As shown, according to some embodiments, similar to Figure 1F In the illustrated embodiment, the insulating layer 134 and the modified layer 233 ′ are partially removed. As a result, the remaining portion of the modified layer 233 ′ forms a plurality of protective elements (or modified elements) 233 ″, and the remaining portion of the insulating layer 134 forms a plurality of internal spacers 136 .

[0124] like Figure 2FAs shown, each protection element 233″ has a first portion P1″ and a second portion P2″. ​​The first portion P1″ is adjacent to one of the dielectric sacrificial layers 206a-206c, and the second portion P2″ is adjacent to the nearby semiconductor layers 104a-104c. The first portion P1″ of the protection element 233″ can be made of or include nitride-containing silicon oxide, carbon-containing silicon oxide, boron-containing silicon oxide, another suitable material, or a combination thereof. The second portion P2″ of the protection element 233″ can be made of or include nitride-containing silicon oxide, carbon-containing silicon oxide, boron-containing silicon oxide, another suitable material, or a combination thereof. In some embodiments, the second portion P2″ of the protection element 233″ has a higher silicon atomic concentration than the first portion P1″.

[0125] like Figure 2G As shown, according to some embodiments, epitaxial structure 138 and dielectric layer 140 are sequentially formed. The material and formation method of epitaxial structure 138 can be the same as Figure 1G The material and forming method of the epitaxial structure 138 shown are the same or similar. The material and forming method of the dielectric layer 140 can be the same or similar. Figure 1G The dielectric layer 140 shown is made of the same or similar materials and is formed using the same or similar methods.

[0126] like Figure 2H As shown, according to some embodiments, similar to Figure 1H In the embodiment shown, the dummy gate stacks 120A and 120B are removed to form a plurality of trenches 142. Similar to the removal of the semiconductor layers 102a-102c, the dielectric sacrificial layers 206a-206c are also removed to form a plurality of recesses 144. Thus, the semiconductor layers 104a-104c are released. Figure 2H As shown, the remaining portions of the semiconductor layers 104a-104c form a plurality of semiconductor nanostructures 104a'-104c'. The protection element 233" and the internal spacer 136 work together to prevent damage to the epitaxial structure 138 during the removal of the dielectric sacrificial layers 206a-206c.

[0127] like Figure 2I As shown, according to some embodiments, similar to Figure 1I In the embodiment shown, multiple metal gate stacks are formed to fill the trenches 142 and recesses 144. As a result, the semiconductor nanostructures 104a'-104c' are surrounded by the metal gate stacks. Figure 1I In the embodiment shown, the metal gate stack layer includes a gate dielectric layer 150, a work function layer 152 and a conductive filling layer 154. The material and formation method of the gate dielectric layer 150 can be the same as Figure 1IThe material and forming method of the gate dielectric layer 150 shown in FIG. 1 are the same or similar. The material and forming method of the work function layer 152 can be the same or similar. Figure 1I The material and forming method of the work function layer 152 shown in FIG. 1 are the same or similar. The material and forming method of the conductive filling layer 154 can be the same or similar. Figure 1I The conductive filling layer 154 shown is made of the same or similar materials and is formed using the same or similar methods.

[0128] Figure 2J-1 is a top view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 2J It is along Figure 2J-1 A cross-sectional view of the structure taken along line II' in FIG. Figure 2J-2 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 2J-2 It is along Figure 2J-1 A cross-sectional view of the structure taken along line II-II'. Figure 2J-3 is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure according to some embodiments. Figure 2J-3 It is along Figure 2J-1 A cross-sectional view of the structure taken along line III-III'.

[0129] like Figure 2J 、 Figure 2J-1 、 Figure 2J-2 and Figure 2J-3 As shown, according to some embodiments, similar to Figure 1J 、 Figure 1J-1 、 Figure 1J-2 and Figure 1J-3 In the illustrated embodiment, the metal gate stack is partially removed, and the remaining portion of the metal gate stack forms a plurality of metal gate stacks 156A and 156B.

[0130] like Figure 2J As shown, each protection element 233″ has a first surface S1 close to the metal gate stack 156A or 156B and a second surface S2 close to the corresponding inner spacer 136. In some embodiments, the atomic concentration of the modifying element (such as nitrogen, carbon, and / or boron) at the second surface S2 is higher than the atomic concentration at the first surface S1. In some embodiments, the atomic concentration of the modifying element (such as nitrogen, carbon, and / or boron) gradually increases along a direction from the first surface S1 toward the second surface S2.

[0131] In some embodiments, prior to the formation of epitaxial structures, which may involve high-temperature operations, semiconductor layers 102a-102c are replaced with dielectric sacrificial layers 206a-206c. Thus, during the formation of epitaxial structure 138, atoms, such as germanium, from semiconductor layers 102a-102c are prevented from diffusing into semiconductor layers 104a-104c. Consequently, the resulting semiconductor nanostructures 104a'-104c' can have a desired profile and better surface conditions, ensuring the quality and reliability of semiconductor layers 104a-104c.

[0132] Embodiments of the present disclosure modify surface portions of the semiconductor layer and sacrificial layer to convert the native oxide portion into a protective element with improved etch resistance before forming the internal spacer. Thus, the protective element and the internal spacer can work together to protect the epitaxial structure during sacrificial layer removal. Short circuits between the metal gate stack and the epitaxial structure are significantly reduced or prevented. The performance and reliability of the semiconductor device structure are greatly improved.

[0133] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner on a substrate. The method also includes partially removing the semiconductor layer and the sacrificial layer to form a first groove, the first groove exposing the side edges of the semiconductor layer and the sacrificial layer, and partially removing the sacrificial layer from the side edges of the sacrificial layer to form a plurality of second grooves. The method also includes introducing a modifying element into the sacrificial layer and the semiconductor layer to convert the surface portion of the sacrificial layer and the semiconductor layer into a modified layer. The modifying element includes nitrogen, carbon, boron, or a combination thereof. In addition, the method includes forming an internal spacer layer above the modified layer, and removing the internal spacer layer and the modified layer outside the second groove. The remaining portions of the internal spacer layer and the modified layer form an internal spacer and a modifying element, respectively.

[0134] In some embodiments, the sacrificial layer includes silicon germanium.

[0135] In some embodiments, the surface portion of the sacrificial layer includes silicon germanium oxide, and the surface portion of the semiconductor layer includes silicon oxide.

[0136] In some embodiments, the sacrificial layer is made of an oxide material.

[0137] In some embodiments, the method further includes: forming an epitaxial structure in the first groove to cover the side edge of the semiconductor layer, the internal spacer and the modifying element; after forming the epitaxial structure, removing the sacrificial layer to release a plurality of semiconductor nanostructures composed of the remaining portion of the semiconductor layer; and forming a metal gate stack encapsulating the semiconductor nanostructure.

[0138] In some embodiments, the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to a nitrogen-containing atmosphere, a carbon-containing atmosphere, a boron-containing atmosphere, or a combination thereof.

[0139] In some embodiments, the modifying element includes nitrogen, and the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to NH3 gas at a temperature ranging from about 550°C to about 600°C for about 10 minutes to about 2 hours.

[0140] In some embodiments, the modifying element includes carbon, and the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to C3H6 gas at a temperature in a range from about 550°C to about 650°C for about 10 minutes to about 2 hours.

[0141] In some embodiments, the modifying element includes boron, and the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to a boron-containing plasma.

[0142] In some embodiments, each of the modifying elements is formed to have a thickness ranging from about 3 angstroms to about 15 angstroms.

[0143] According to some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a fin structure on a substrate, the fin structure having a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner, and forming a dummy gate stack extending across the fin structure. The method also includes partially removing the semiconductor layer and the sacrificial layer to form a first groove, the first groove exposing the side edges of the semiconductor layer and the sacrificial layer, and replacing the sacrificial layer with a dielectric sacrificial layer. The method also includes partially removing the dielectric sacrificial layer from the side edges of the dielectric sacrificial layer to form a plurality of second grooves, and modifying the surface portion of the dielectric sacrificial layer with a modifying element to convert the surface portion into a modified element. The modifying element includes nitrogen, carbon, boron, or a combination thereof. In addition, the method includes forming an internal spacer covering the modified element in the second groove, and removing the dummy gate stack and the dielectric sacrificial layer after forming the epitaxial structure to release a plurality of semiconductor nanostructures composed of the remaining portions of the semiconductor layer. The method also includes forming a metal gate stack that encapsulates the semiconductor nanostructure.

[0144] According to some embodiments, a method for forming a semiconductor device structure is provided, comprising: forming a fin structure on a substrate, the fin structure having a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner; forming a dummy gate stack extending across the fin structure; partially removing the semiconductor layer and the sacrificial layer to form a first groove, the first groove exposing the side edges of the semiconductor layer and the sacrificial layer; replacing the sacrificial layer with a dielectric sacrificial layer; partially removing the dielectric sacrificial layer from the side edges of the dielectric sacrificial layer to form a plurality of second grooves; modifying a surface portion of the dielectric sacrificial layer with a modifying element to convert the surface portion into a modified element, wherein the modifying element includes nitrogen, carbon, boron or a combination thereof; forming an internal spacer covering the modified element in the second groove; removing the dummy gate stack and the dielectric sacrificial layer to release a plurality of semiconductor nanostructures consisting of the remaining portion of the semiconductor layer; and forming a metal gate stack encapsulating the semiconductor nanostructure.

[0145] In some embodiments, the modifying element includes nitrogen, and the modifying element is introduced into the dielectric sacrificial layer and the semiconductor layer by exposing the surface portions of the dielectric sacrificial layer and the semiconductor layer to NH3 gas at a temperature in a range from about 550°C to about 600°C for about 10 minutes to about 2 hours.

[0146] In some embodiments, the modifying element includes carbon, and the modifying element is introduced into the dielectric sacrificial layer and the semiconductor layer by exposing the surface portions of the dielectric sacrificial layer and the semiconductor layer to C3H6 gas at a temperature in a range from about 550°C to about 650°C for about 10 minutes to about 2 hours.

[0147] In some embodiments, the modifying element includes boron, and the modifying element is introduced into the dielectric sacrificial layer and the semiconductor layer by using an ion implantation process.

[0148] In some embodiments, the method further includes forming a source / drain epitaxial structure in the first groove, wherein the source / drain epitaxial structure is formed to directly contact the inner spacer and the modifying element.

[0149] According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a plurality of semiconductor nanostructures and a gate stack encapsulating the semiconductor nanostructures. The semiconductor device structure also includes an epitaxial structure connecting the semiconductor nanostructures and a plurality of internal spacers located between the epitaxial structure and the gate stack. The semiconductor device structure also includes a plurality of protection elements, each of which is located between the gate stack and a corresponding internal spacer of the internal spacers. The protection elements contain nitrogen, carbon, boron, or a combination thereof.

[0150] In some embodiments, the protection element includes nitride-containing silicon oxide, nitride-containing silicon germanium oxide, carbon-containing silicon oxide, carbon-containing silicon germanium oxide, boron-containing silicon oxide, boron-containing silicon germanium oxide, or combinations thereof.

[0151] In some embodiments, the internal spacer has an atomic concentration of an element that is higher than an atomic concentration of an element of the protection element, and the element includes nitrogen, carbon, boron, or a combination thereof.

[0152] In some embodiments, the epitaxial structure is in direct contact with the inner spacer and the protection element.

[0153] In some embodiments, an internal spacer is separated from the semiconductor nanostructure by the protection element.

[0154] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use this disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner on a substrate; Partially removing the semiconductor layer and the sacrificial layer to form a first groove, wherein the first groove exposes side edges of the semiconductor layer and the sacrificial layer; partially removing the sacrificial layer from the side edges of the sacrificial layer to form a plurality of second grooves; introducing a modifying element into the sacrificial layer and the semiconductor layer to convert surface portions of the sacrificial layer and the semiconductor layer into a modified layer, wherein the modifying element comprises nitrogen, carbon, boron, or a combination thereof; forming an inner spacer layer over the modified layer; and The inner spacer layer and the modified layer are removed outside the second groove, wherein the remaining portions of the inner spacer layer and the modified layer form an inner spacer and a modifying element, respectively.

2. The method according to claim 1, wherein The sacrificial layer includes silicon germanium.

3. The method according to claim 2, wherein: The surface portion of the sacrificial layer includes silicon germanium oxide, and the surface portion of the semiconductor layer includes silicon oxide.

4. The method according to claim 1, wherein The sacrificial layer is made of oxide material.

5. The method according to claim 1, further comprising: forming an epitaxial structure in the first groove to cover the side edge of the semiconductor layer, the inner spacer, and the modifying element; After forming the epitaxial structure, removing the sacrificial layer to release a plurality of semiconductor nanostructures formed by a remaining portion of the semiconductor layer; as well as A metal gate stack is formed to wrap around the semiconductor nanostructure.

6. The method according to claim 1, wherein The modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to a nitrogen-containing atmosphere, a carbon-containing atmosphere, a boron-containing atmosphere, or a combination thereof.

7. The method according to claim 6, wherein: The modifying element includes nitrogen, and the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to NH3 gas at a temperature ranging from about 550°C to about 600°C for about 10 minutes to about 2 hours.

8. The method according to claim 1, wherein The modifying element includes carbon, and the modifying element is introduced into the sacrificial layer and the semiconductor layer by exposing the surface portions of the sacrificial layer and the semiconductor layer to C3H6 gas at a temperature ranging from about 550°C to about 650°C for about 10 minutes to about 2 hours.

9. A method for forming a semiconductor device structure, comprising: forming a fin structure on a substrate, the fin structure having a plurality of sacrificial layers and a plurality of semiconductor layers arranged in an alternating manner; forming a dummy gate stack extending across the fin structure; Partially removing the semiconductor layer and the sacrificial layer to form a first groove, wherein the first groove exposes side edges of the semiconductor layer and the sacrificial layer; replacing the sacrificial layer with a dielectric sacrificial layer; partially removing the dielectric sacrificial layer from side edges of the dielectric sacrificial layer to form a plurality of second grooves; modifying a surface portion of the dielectric sacrificial layer with a modifying element to convert the surface portion into a modified element, wherein the modifying element comprises nitrogen, carbon, boron, or a combination thereof; forming an inner spacer in the second groove to cover the modifying element; removing the dummy gate stack and the dielectric sacrificial layer to release a plurality of semiconductor nanostructures comprised of a remaining portion of the semiconductor layer; and A metal gate stack is formed to wrap around the semiconductor nanostructure.

10. A semiconductor device comprising: multiple semiconductor nanostructures; a gate stack wrapping the semiconductor nanostructure; an epitaxial structure connecting the semiconductor nanostructures; a plurality of internal spacers located between the epitaxial structure and the gate stack; as well as A plurality of protection elements are provided, wherein each of the protection elements is located between the gate stack and a corresponding one of the inner spacers, and the protection elements comprise nitrogen, carbon, boron, or a combination thereof.

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