Semiconductor device and manufacturing method thereof

Abstract

Memory devices and methods of making the same are disclosed. In some embodiments, a disclosed memory device includes a capacitor stack structure and an array of transistors. The capacitor stack structure includes: first electrode plates and second electrode plates alternately stacked in a vertical direction; a common electrode extending vertically through the capacitor stack structure and in contact with the first electrode plate; and selection electrodes each extending through the capacitor stack structure and in contact with a corresponding one of the second electrode plates. Each transistor in the array of transistors is coupled with a corresponding one of the select electrodes.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor technology, and more particularly to semiconductor devices and methods of fabricating the same. Background Art

[0002] Planar memory cells have been shrunk to ever-smaller sizes through improvements in process technology, circuit design, programming algorithms, and fabrication techniques. However, as the feature size of memory cells approaches its lower limit, planar processing and fabrication techniques become increasingly difficult and expensive. Consequently, the memory density of planar memory cells approaches its upper limit.

[0003] Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. 3D memory architectures include a memory array and peripheral circuitry for facilitating operation of the memory array. Summary of the Invention

[0004] One aspect of the present disclosure provides a semiconductor device, comprising: a stacked structure, the stacked structure including a first conductive layer and a second conductive layer alternately stacked in a vertical direction; a conductive wall, the conductive wall extending vertically through the stacked structure and contacting the first conductive layer but isolated from the second conductive layer; and conductive vias, each conductive via extending vertically through the stacked structure and electrically connected to a corresponding one of the second conductive layers, but electrically isolated from the first conductive layer and other second conductive layers in the stacked structure.

[0005] In some embodiments, the semiconductor device further includes: an isolation structure, wherein the isolation structure is located between the conductive via and the other second conductive layer to isolate the conductive via from the other second conductive layer.

[0006] In some embodiments, the semiconductor device further includes: a conductive connection structure, each conductive connection structure being located between one of the conductive vias and the corresponding one of the second conductive layers to connect the one of the conductive vias to the corresponding one of the second conductive layers.

[0007] In some embodiments, the isolation structure includes silicon oxide; and the conductive connection structure includes a metal silicide material.

[0008] In some embodiments, each of the isolation structure and the conductive connection structure has a ring structure laterally surrounding a corresponding one of the conductive vias.

[0009] In some embodiments, the second conductive layer and the first conductive layer include the same conductive material.

[0010] In some embodiments, the first conductive layer and the conductive walls include a first conductive material; and the second conductive layer and the conductive vias include a second conductive material different from the first conductive material.

[0011] In some embodiments, the semiconductor device further includes a dielectric layer, the dielectric layer including: a horizontal portion located between adjacent first and second conductive layers; a first vertical portion located between the conductive wall and the second conductive layer; and a second vertical portion located between the conductive via and the first conductive layer.

[0012] In some embodiments, the dielectric layer includes a high-K material.

[0013] In some embodiments, the dielectric layer contacts side surfaces of the conductive walls and the conductive vias and horizontal surfaces of the first conductive layer and the second conductive layer.

[0014] In some embodiments, the semiconductor device further includes: an array of transistors respectively coupled to the conductive vias.

[0015] In some embodiments, the transistors are vertical gate transistors, each of which includes a channel structure extending in a vertical direction and a gate structure located at a lateral side of the channel structure.

[0016] In some embodiments, the semiconductor device further includes: an insulating layer located between the stacked structure and the array of transistors, wherein each conductive via extends through the insulating layer to couple to a corresponding one of the transistors in the array of transistors.

[0017] In some embodiments, a first thickness of the first conductive layer is different from a second thickness of the second conductive layer.

[0018] In some embodiments, the semiconductor device further includes: a gap structure, which extends vertically through the stacked structure and extends laterally along a first direction between adjacent rows of conductive vias, wherein the conductive wall extends laterally along a second direction to cut off the gap structure.

[0019] Another aspect of the present disclosure provides a memory device, comprising: a capacitor stack structure, the capacitor stack structure comprising: first electrode plates and second electrode plates alternately stacked in a vertical direction; a common electrode extending vertically through the capacitor stack structure and in contact with the first electrode plates; and selection electrodes, each selection electrode extending through the capacitor stack structure and in contact with a corresponding one of the second electrode plates; and an array of transistors, each transistor coupled to a corresponding one of the selection electrodes.

[0020] In some embodiments, the memory device further includes a high-K layer located between adjacent first and second electrode plates, between the first electrode plate and the common electrode, and between the second electrode plate and the select electrode.

[0021] In some embodiments, the memory device further includes: a conductive connection structure, each conductive connection structure being located between one of the selection electrodes and a corresponding one of the second electrode plates to electrically connect the one of the selection electrodes and the corresponding one of the second electrode plates; and an isolation structure, the isolation structure being located between the one of the selection electrodes and other second electrode plates different from the corresponding one of the second electrode plates.

[0022] In some embodiments, the isolation structure includes silicon oxide, and the conductive connection structure includes a metal silicide material.

[0023] In some embodiments, each of the isolation structure and the conductive connection structure has a ring-shaped structure laterally surrounding a corresponding one of the select electrodes.

[0024] In some embodiments, the first electrode plate and the second electrode plate include the same conductive material.

[0025] In some embodiments, the first electrode plate and the common electrode include a first conductive material; and the second electrode plate and the select electrode include a second conductive material different from the first conductive material.

[0026] In some embodiments, the memory device further includes an insulating layer between the capacitor stack structure and the array of transistors, wherein the select electrode extends through the insulating layer.

[0027] In some embodiments, the transistor is a two-dimensional transistor or a vertical gate transistor.

[0028] In some embodiments, the memory device further includes: a gap structure extending vertically through the capacitor stack structure and extending laterally along a first direction between adjacent rows of selection electrodes, wherein the common electrode extends laterally along a second direction to cut through the gap structure.

[0029] Another aspect of the present disclosure provides a method for forming a semiconductor device, comprising: forming a stacked structure on an array of transistors, the stacked structure comprising semiconductor layers and sacrificial layers alternately stacked in a vertical direction; forming through holes, each of which extends vertically through the stacked structure and forming an isolation structure and a conductive connection structure on the exposed side walls of the semiconductor layer in the through holes, so that each through hole has a conductive connection structure in contact with a corresponding one of the semiconductor layers, and the side walls of the other semiconductor layers are covered by the isolation structure; forming conductive vias in the through holes to connect the array of transistors; replacing the semiconductor layer with a second conductive layer; and replacing the sacrificial layer with a first conductive layer.

[0030] In some embodiments, the method further includes forming an insulating layer on the array of transistors, wherein the stacked structure is formed on the insulating layer.

[0031] In some embodiments, forming the through holes, isolation structures and conductive connection structures includes: forming via holes with different depths in the stacked structure, each via hole stopping at a corresponding one of the sacrificial layers; and oxidizing the surface of the semiconductor layer exposed by the via holes to form an isolation structure.

[0032] In some embodiments, forming the through holes, isolation structures and conductive connection structures further includes: performing a first expansion on the depth of the via holes so that each via hole exposes an underlying semiconductor layer without an isolation structure; and forming a conductive connection structure on the exposed side walls of the semiconductor layer without an isolation structure through the first expanded via holes.

[0033] In some embodiments, forming the through holes, isolation structures and conductive connection structures further includes: performing a second expansion of the depth of the via holes so that each via hole stops at the insulating layer; and oxidizing the surface of the semiconductor layer exposed by the second expanded via holes to form an additional isolation structure.

[0034] In some embodiments, forming the through holes, the isolation structure, and the conductive connection structure further includes: performing a third expansion on the depth of the via hole to form the through holes, so that each through hole extends through the insulating layer and exposes a corresponding one of the transistors.

[0035] In some embodiments, replacing the semiconductor layer with a second conductive layer includes: forming a vertical trench extending vertically through the stacked structure and stopping at the insulating layer; removing the semiconductor layer through the vertical trench to form a first horizontal trench; and forming a second conductive layer in the first horizontal trench.

[0036] In some embodiments, replacing the sacrificial layer with the first conductive layer includes: removing the portion of the second conductive layer exposed by the vertical groove; removing the sacrificial layer through the vertical groove to form a second horizontal groove; forming a dielectric layer in the second horizontal groove and on the sidewalls of the vertical groove to cover the exposed surface of the second conductive layer; and forming the first conductive layer in the second horizontal groove.

[0037] In some embodiments, the method further includes forming a slit structure extending vertically through the stacked structure and extending laterally along a first direction, wherein a row of through holes is formed between adjacent first slit structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and enable one skilled in the relevant art to make and use the present disclosure.

[0039] Figure 1 A schematic circuit diagram of a memory device including vertical transistors according to some embodiments of the present disclosure is shown.

[0040] Figure 2 A schematic side cross-sectional view of a 3D memory device according to some embodiments of the present disclosure is shown.

[0041] Figure 3 Schematic planar cross-sectional views of memory devices according to some embodiments of the present disclosure are shown.

[0042] Figure 4 A block diagram of a system having a memory device according to some embodiments of the present disclosure is shown.

[0043] Figure 5 A flow chart of a fabrication method for forming a 3D memory device according to some embodiments of the present disclosure is shown.

[0044] Figure 6A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0045] Figure 6B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0046] Figure 7A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0047] Figure 7B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0048] Figure 8A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0049] Figure 8B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0050] Figure 9A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0051] Figure 9B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0052] Figure 10 A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0053] Figure 11 A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0054] Figure 12A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0055] Figure 12B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0056] Figure 13A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0057] Figure 13B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0058] Figure 14 A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0059] Figure 15A A schematic side cross-sectional view of a 3D memory device at a stage in a fabrication method according to some embodiments of the present disclosure is shown.

[0060] Figure 15B A schematic planar cross-sectional view of a 3D memory device at a certain stage of a fabrication method according to some embodiments of the present disclosure is shown.

[0061] The present disclosure will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0062] Although specific configurations and arrangements are discussed, it should be understood that this discussion is for illustrative purposes only. Therefore, other configurations and arrangements may be used without departing from the scope of this disclosure. Furthermore, this disclosure may be employed in a variety of other applications. The functions and structural features described in this disclosure may be combined, adjusted, and modified in ways not specifically shown in the accompanying drawings, and such combinations, adjustments, and modifications are within the scope of this disclosure.

[0063] In general, terms should be understood, at least in part, by their usage in the context. For example, depending, at least in part, on the context, the words "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular, or may be used to describe a combination of features, structures, or characteristics in the plural. Similarly, words such as "a," "an," or "the" may also be understood to express singular usage or plural usage, depending, at least in part, on the context. Furthermore, the word "based on" may be understood to not necessarily be intended to express an exclusive set of factors, but rather may allow for the presence of other factors that may not be explicitly stated, again depending, at least in part, on the context.

[0064] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” means not only directly on something, but also encompasses being on something with intervening features or layers therebetween, and “over” or “over” means not only being above or over something, but also encompasses being above or over something with no intervening features or layers therebetween (i.e., directly on something).

[0065] Furthermore, spatially relative terms, such as "below," "beneath," "below," "above," and "upper," may be used herein for ease of description to describe an element or feature in relation to one or more other elements or features as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0066] As used herein, the term "substrate" refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned, or it can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, for example, silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be composed of non-conductive materials such as glass, plastic, or sapphire wafers.

[0067] As used herein, the term "layer" refers to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying structure or the upper structure, or may have a range smaller than the range of the underlying structure or the upper structure. In addition, a layer may be a region of a homogeneous or heterogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between any paired horizontal planes between the top surface and the bottom surface of the continuous structure, or located at the top surface and the bottom surface. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may contain one or more layers therein, and / or may have one or more layers located thereon, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (forming interconnect lines and / or vertical interconnect channel (VIA) contacts therein) and one or more dielectric layers.

[0068] In the memory cells of some memory devices (e.g., dynamic random access memory (DRAM)), transistors are used as switches or selection devices. In a one-transistor-one-capacitor (1T1C) DRAM structure, data is stored in a capacitor. Vertical transistors can have different gate structure architecture designs, such as single metal gate (SMG), dual metal gate (DMG), triple metal gate (TMG), gate all around (GAA), etc. Vertical capacitors are generally formed by a drilling process to form a vertical tube with a limited aperture size. Due to the limitations of the drilling process, it is difficult to increase the capacitance of the existing manufacturing process, and the process window is very small.

[0069] In order to solve one or more of the aforementioned problems, the present disclosure introduces a novel design of a capacitor architecture. The existing vertically placed tubular capacitor is changed into a planar stacked plate capacitor. Vertical conductive vias are used to connect the transistor and the capacitor. Polysilicon oxidation is used to form an isolation structure between the vertical conductive via and the planar stacked plate. In addition, a silicide structure (e.g., Ti / Co / Ni) can be used to select the capacitor plate layer that needs to be connected to the vertical conductive via, thereby avoiding the use of any recessed process. Therefore, the challenge of reducing the existing capacitor due to the limited aperture size caused by the use of the recessed process and the size requirements and uniformity requirements for the vertical holes can be avoided, thereby achieving the goal of selecting the layer. Therefore, the disclosed capacitor stack structure can achieve large capacitance and size reduction, thereby coordinating with the size reduction of the transistor.

[0070] Figure 1 Schematic diagram of a memory device 100 having an array of memory cells (each having a vertical transistor) according to some embodiments of the present disclosure is shown. The memory device 100 may include an array of memory cells, wherein each memory cell 110 includes a vertical transistor 120 and a storage unit coupled to the vertical transistor 120. Figure 1 In some embodiments shown, the memory cell array is a DRAM cell array, and the storage cells are capacitors 130 for storing charge as binary information stored by the corresponding DRAM cells. In some other embodiments not shown, the memory cell array is a PCM cell array, and the storage cells may be PCM elements (e.g., including a chalcogenide alloy) for storing binary information of the corresponding PCM cells based on the different resistivity of the PCM elements in the amorphous phase and the crystalline phase.

[0071] like Figure 1 As shown in , the memory cells 110 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 100 may include word lines 150 that couple the memory cell array to peripheral circuitry to control the switching of vertical transistors 120 in the memory cells 110 located in a row, and bit lines 160 that couple the memory cell array to peripheral circuitry to transmit and / or receive data to and from the memory cells 110 located in a column. That is, each word line 150 is coupled to the memory cells 110 of a corresponding row, and each bit line 160 is coupled to the memory cells 110 of one or more corresponding logical columns.

[0072] In some embodiments of the present disclosure, vertical transistor 120 may be a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). The gate of vertical transistor 120 is coupled to word line 150, one of the source and drain of vertical transistor 120 is coupled to bit line 160, the other of the source and drain of vertical transistor 120 is coupled to one electrode of capacitor 130, and the other electrode of capacitor 130 is coupled to ground. In some embodiments, capacitor 130 may have a stacked structure as described in detail below.

[0073] Figure 2 A schematic side cross-sectional view of a 3D memory device according to some embodiments of the present disclosure is shown. Figure 3 Schematic planar cross-sectional view of a memory device according to some embodiments of the present disclosure is shown. It should be noted that Figure 3 Shown Figure 2 The memory device shown in FIG300 is a planar cross-sectional view taken along line AA′, and Figure 2 It shows Figure 3 FIG2 is a cross-sectional view 200 of a 3D memory device along line BB′ shown in FIG2 .

[0074] like Figure 2 As shown in , the disclosed memory device may include a transistor layer 220 located on a substrate 210. The substrate 210 may be a semiconductor substrate that may include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some other embodiments, the substrate 210 may be a carrier substrate that may include any suitable semiconductor material or non-conductive material, such as glass, plastic, or a sapphire wafer.

[0075] The transistor layer 220 may include an array of vertical transistors, for example, an array of gate all around (GAA) type vertical transistors or an array of single metal gate (SMG) type vertical transistors, an array of dual metal gate (DMG) type vertical transistors, an array of triple metal gate (TMG) type vertical transistors, etc. Specifically, the transistor layer 220 may include an array of channel structures 222 and a gate structure layer 225 along a lateral direction, each channel structure 222 extending along a vertical direction (e.g., Figure 2 and Figure 3 As shown). The gate structure layer 225 may include a plurality of gate structures, each of which is located at one or more sides of the corresponding channel structure 222. Each gate structure includes a gate electrode and a gate dielectric. In some embodiments, the gate structures of a row of vertical transistors along the first lateral direction may form a word line. Thus, the first lateral direction (x direction) may also be referred to as a word line direction. Although Figure 2Although not shown in the figure, the disclosed memory device may further include a plurality of bit lines, each bit line extending along a second lateral direction (y-direction, referred to as a bit line direction) perpendicular to the first lateral direction. Each bit line may be connected to a vertical transistor of a corresponding column along the second lateral direction (y-direction).

[0076] like Figure 2 As shown in , the disclosed memory device may further include a capacitor stack structure 240, which includes a first conductive layer 269 (also referred to as a first electrode plate 269) and a second conductive layer 259 (also referred to as a second electrode plate 259) alternately stacked along a vertical direction (z direction). In some embodiments, the first thickness of the first conductive layer 269 is different from the second thickness of the second conductive layer 259. Figure 2 and Figure 3 As shown in FIG, one or more conductive walls 260 (also referred to as common electrodes 260) may extend vertically through the capacitor stack structure 240 and contact the first conductive layer 269 but be isolated from the second conductive layer 259. A plurality of conductive vias 250 (also referred to as select electrodes 250) may each extend vertically through the capacitor stack structure 240 and be electrically connected to a corresponding one of the second conductive layers 259 but be electrically isolated from the first conductive layer 269 and the other second conductive layers 259 in the capacitor stack structure 240.

[0077] The first conductive layer 269, the second conductive layer 259, the conductive wall 260 and / or the conductive via 250 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. In some embodiments, the first conductive layer 269, the second conductive layer 259, the conductive wall 260 and / or the conductive via 250 may include multiple conductive layers, such as a W layer located above a TiN layer. In some embodiments, the second conductive layer 259 and the first conductive layer 269 may include the same conductive material. In some other embodiments, the first conductive layer 269 and the conductive wall 260 may include a first conductive material, and the second conductive layer 259 and the conductive via 250 may include a second conductive material different from the first conductive material.

[0078] In some embodiments, the conductive connection structures 256 may be located between one of the conductive vias 250 and a corresponding one of the second conductive layers 259, thereby connecting the one of the conductive vias 250 to the corresponding one of the second conductive layers 259. For example, Figure 2As shown in FIG, conductive via 250-1 is electrically coupled to a corresponding conductive layer 259-1 via a conductive connection structure 256-1, conductive via 250-2 is electrically coupled to a corresponding conductive layer 259-2 via a conductive connection structure 256-2, and conductive via 250-3 is electrically coupled to a corresponding conductive layer 259-3 via a conductive connection structure 256-3. In some embodiments, the conductive connection structure 256 may include a metal silicide material. In some embodiments, each conductive connection structure 256 has a ring-shaped structure that laterally surrounds a corresponding one of the conductive vias 250.

[0079] In some embodiments, a plurality of isolation structures 280 can be located between the conductive via 250 and a second conductive layer 259 other than the corresponding conductive layer 259 connected to the conductive via 250. Thus, the conductive via 250 can be isolated from the unrelated second conductive layer 259. For example, the conductive via 250-1 is isolated from the second conductive layer 259 other than the corresponding conductive layer 259-1, and the conductive via 250-2 is isolated from the second conductive layer 259 other than the corresponding conductive layer 259-2, and the conductive via 250-3 is isolated from the second conductive layer 259 other than the corresponding conductive layer 259-3, as shown in FIG. Figure 2 In some embodiments, the isolation structures 280 can include any suitable insulating material, such as silicon oxide. In some embodiments, each isolation structure 280 has a ring-shaped structure that laterally surrounds a corresponding one of the conductive vias 250 .

[0080] In some embodiments, as Figure 2 and Figure 3 As shown in , the capacitor stack structure 240 may further include a dielectric layer 270. Dielectric layer 270 may include a horizontal portion located between adjacent first and second conductive layers 269 and 259, a first vertical portion located between conductive walls 260 and second conductive layers 259, and a second vertical portion located between conductive vias 250 and first conductive layer 269. In some embodiments, the dielectric layer includes any suitable high-K material. In some embodiments, dielectric layer 270 contacts the side surfaces of conductive walls 260 and conductive vias 250, as well as the horizontal surfaces of first and second conductive layers 269 and 259.

[0081] like Figure 3 As shown in , the disclosed memory device may further include a plurality of slit structures 380, each of which extends vertically through the capacitor stack structure 240 and extends laterally along a first direction (x-direction) between adjacent rows of conductive vias 250. The conductive walls 260 may each extend laterally along a second direction (y-direction) to cut through the slit structures 380.

[0082] In summary, the first conductive layer 269 and the connected conductive wall 260 together form a common first electrode (or upper electrode) of the capacitor of the capacitor stack structure 240, and the second conductive layer 259 and the connected conductive via 250 together form a plurality of individual second electrodes (or lower electrodes), each second electrode being coupled to a corresponding one of the transistors in the array of transistors in the transistor layer 220 through a corresponding storage node contact (SNC) structure.

[0083] In some embodiments, one or more peripheral circuits (not shown) can be coupled to the capacitor through bit lines, word lines, common electrodes of capacitors, select electrodes of capacitors, and any other suitable metal wiring. Figure 2 and Figure 3 . It is noted that the one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the disclosed memory device by applying and sensing voltage signals and / or current signals to and from each memory cell via word lines and bit lines. The one or more peripheral circuits may include various types of peripheral circuits formed using CMOS technology.

[0084] Figure 4 FIG2 shows a block diagram of a system 400 having a memory device according to some embodiments of the present disclosure. The system 400 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory component located therein. Figure 4 As shown in FIG, system 400 may include a host 408 and a memory system 402 having one or more memory devices 404 and a memory controller 406. Host 408 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). Host 408 may be configured to send or receive data to and from memory device 404. Memory device 404 may be any memory device disclosed herein, such as, Figure 2 and Figure 3 The memory device shown in .

[0085] According to some embodiments, the memory controller 406 is coupled to the memory device 404 and the host 408 and is configured to control the memory device 404. The memory controller 406 can manage the data stored in the memory device 404 and communicate with the host 408. The memory controller 406 can be configured to control the operations of the memory device 404, such as read, write, and refresh operations. The memory controller 406 can also be configured to manage various functions related to the data stored in or to be stored in the memory device 404, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 406 is further configured to determine the maximum memory capacity that the computer system can use, the number of memory banks, the memory type and speed, the memory particle data depth and data width, and other important parameters. Any other appropriate functions can also be performed by the memory controller 406. The memory controller 406 can communicate with an external device (e.g., the host 408) according to a specific communication protocol. For example, the memory controller 406 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer mini-interface (SCSI) protocol, an enhanced minidisk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0086] Figure 5 A flow chart of a fabrication method 500 for forming a 3D memory device according to some embodiments of the present disclosure is shown. Figures 6A-6B 、 Figures 7A-7B 、 Figures 8A-8B 、 Figures 9A-9B 、 Figure 10-11 、 Figures 12A-12B 、 Figures 13A-13B 、 Figure 14 and Figures 15A-15B Shown are various embodiments according to the present disclosure. Figure 5 Schematic side cross-sectional views and / or plan cross-sectional views of a 3D memory device at certain stages of fabrication of method 500 are shown in FIG. It should be understood that the operations shown in method 500 are not exclusive and that other operations may be performed before, after, or between any of the operations shown. Furthermore, some of the operations may be performed simultaneously or in different order. Figure 5 Executed in the order shown.

[0087] like Figure 5As shown in FIG5 , method 500 begins with operation 510 , in which a stacked structure may be formed on an array of transistors. The stacked structure may include semiconductor layers and sacrificial layers alternately stacked in a vertical direction. Figure 6A A schematic side cross-sectional view of a 3D memory device is shown after operation 510 of method 500 . Figure 6B 5. A schematic plan cross-sectional view of a 3D memory device after operation 510 of method 500 is shown. Figure 6A Shown Figure 6B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line BB′ in the yz plane, and Figure 6B Shown Figure 6A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0088] In such Figure 6A In some embodiments shown in , a transistor layer can be formed on a substrate 610. The substrate 610 can be a semiconductor substrate that can include silicon (e.g., single crystal silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), or any other suitable material. In some other embodiments, the substrate 610 can be a carrier substrate that can include any suitable semiconductor material or non-conductive material, such as glass, plastic, or a sapphire wafer.

[0089] In such Figure 6A In some embodiments shown, the transistor layer 620 formed can include an array of vertical transistors. Specifically, forming the transistor layer 220 can include forming an array of channel structures 622, each channel structure extending in a vertical direction (z-direction) on the substrate 610. The array of channel structures 622 can be formed by any suitable process. For example, a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc.) can be performed to form a semiconductor layer on the substrate 610. A photolithography process can then be applied to pattern the semiconductor layer using an etch mask (e.g., a photoresist mask and / or a hard mask), and one or more dry etching and / or wet etching processes (e.g., RIE) can be performed on the semiconductor layer to etch portions of the semiconductor layer to form the array of channel structures 622.

[0090] In some embodiments, the material of the channel structure 622 can include any suitable semiconductor material. For example, the material of the channel structure 622 can be polysilicon. As another example, the material of the channel structure 622 can be a metal oxide semiconductor material, such as IGZO. It should be understood that the cross-section of each channel structure 622 can have any suitable shape, such as a square shape, a rectangular shape (or a trapezoidal shape), a circular shape, a partially circular shape, an elliptical shape, a partially elliptical shape, or any other suitable shape.

[0091] In some embodiments, forming the transistor layer 620 may further include forming a gate structure layer 625 in a lateral direction. The gate structure layer 625 may be formed to include a plurality of gate structures, each gate structure being located at one or more sides of the corresponding channel structure 622. Thus, the array of vertical transistors formed may be a gate all around (GAA) type vertical transistor, a single metal gate (SMG) type vertical transistor, a dual metal gate (DMG) type vertical transistor, or a triple metal gate (TMG) type vertical transistor, etc. Although Figure 6A Not shown, but each gate structure may include a gate electrode and a gate dielectric. The gate electrode may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.) or a silicide. For example, the gate electrode may include doped polysilicon, i.e., gate polysilicon. In some other embodiments, the gate electrode may include multiple conductive layers, such as a W layer located above the TiN layer. The gate dielectric may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the gate structures of a row of vertical transistors along a first lateral direction may be formed to be interconnected to form a word line extending along the first lateral direction (x direction).

[0092] In some embodiments, although Figure 6AAlthough not shown, forming the transistor layer 620 may further include forming a plurality of storage node contact (SNC) structures (not shown), each of which contacts an end (e.g., an upper end) of a corresponding one of the channel structures in the array of channel structures 622. The SNC structures may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), a silicide, and / or a combination thereof. In addition, forming the transistor layer 620 may further include forming a plurality of bit lines (not shown), each bit line extending along the second lateral direction (y-direction) and connected to an end (e.g., a lower end) of a corresponding column of vertical transistors along the second lateral direction (y-direction). For example, the substrate 610 may be thinned, and a conductive layer may be formed and patterned to form the bit lines. The bit lines may include any suitable conductive material, such as polysilicon, a metal (e.g., W, Cu, Al, etc.), a metal compound (e.g., TiN, TaN, etc.), or a silicide. For example, the bit lines may include multiple conductive layers, such as a W layer located above a TiN layer.

[0093] like Figure 6A As shown in FIG, an etch stop layer 630 can be formed on the transistor layer 620, and a stacked structure 640 can be formed on the etch stop layer 630. In some embodiments, the etch stop layer 630 can be formed by a thin film deposition process such as CVD, PVD, ALD, etc. The etch stop layer 630 can include any suitable dielectric material, such as silicon nitride, silicon oxynitride, or a high-k dielectric. The stacked structure 640 can include semiconductor layers 644 and sacrificial layers 642 alternately stacked in a vertical direction (z-direction). In some embodiments, the alternating semiconductor layers 644 and sacrificial layers 642 can be formed by a variety of thin film deposition processes such as CVD, PVD, ALD, etc. The semiconductor layers 644 can include any suitable semiconductor material, such as Si (e.g., c-Si, poly-Si), SiGe, GaAs, Ge, etc. The sacrificial layer 642 can be an insulating layer comprising any suitable insulating material having an etching ratio different from the etching ratio of the material of the semiconductor layer 644 during one or more selective etching processes. In some embodiments, the sacrificial layer 642 comprises silicon nitride.

[0094] Re-reference Figure 5 The method 500 may proceed to operation 520 where a slit structure may be formed in the stacked structure. Each slit structure may extend vertically through the stacked structure and laterally along a first direction. Figure 7A A schematic side cross-sectional view of a 3D memory device is shown after operation 520 of method 500 . Figure 7B5 shows a schematic planar cross-sectional view of a 3D memory device after operation 520 of method 500. It is noted that Figure 7A Shown Figure 7B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line BB′ in the yz plane, and Figure 7B Shown Figure 7A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0095] like Figure 6A and Figure 6B As shown in , the stacked structure 640 can be patterned to form a plurality of first slits 650 arranged in parallel in the second lateral direction (y-direction), each of which extends along the first lateral direction (x-direction). The plurality of first slits 650 can extend vertically through the stacked structure 640 and stop at the etch stop layer 630, and extend laterally along the first lateral direction (x-direction). The plurality of first slits 650 can be formed by any suitable etching process (e.g., optical etching, dry etching, wet etching, cleaning, etc.).

[0096] like Figure 7A and Figure 7B As shown, a plurality of slit structures 750 may be formed in the first slit 650. The slit structures 750 may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, or a high-k dielectric. In some embodiments, the slit structures 750 may be formed by any suitable deposition process, such as CVD, PVD, ALD, etc., followed by a chemical mechanical polishing (CMP) process. The formed slit structures 750 may extend laterally parallel along a first lateral direction (x-direction).

[0097] Re-reference Figure 5 The method 500 may proceed to operation 530 where a plurality of via holes having different depths may be formed in the stacked structure. Each via hole may stop at a corresponding one of the sacrificial layers. Figure 8A A schematic side cross-sectional view of a 3D memory device is shown after operation 530 of method 500 . Figure 8B 5 shows a schematic planar cross-sectional view of a 3D memory device after operation 530 of method 500. It is noted that Figure 8A Shown Figure 8B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line CC′ in the xz plane, and Figure 8B Shown Figure 8A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0098] like Figure 8A and Figure 8B As shown, an array of via holes 850 can be formed in the stacked structure 640. Each of the via holes 850 can stop at a corresponding one of the sacrificial layers 642. Therefore, each individual via hole (e.g., via hole 850-1, via hole 850-2, via hole 850-3, etc.) can have a different depth along the vertical direction (z direction). Figure 8B In the plan view shown, the array of via holes 850 can be arranged in rows extending parallel along a first lateral direction (x-direction) and in columns extending parallel along a second lateral direction (y-direction). In some embodiments, one or more rows of via holes 850 can be located between adjacent slot structures 750. In some embodiments, the array of via holes 850 can be formed by any suitable etching process.

[0099] Re-reference Figure 5 The method 500 may proceed to operation 540 where the surface of the semiconductor layer exposed by the via hole may be oxidized to form an isolation structure. Figure 9A A schematic side cross-sectional view of a 3D memory device is shown after operation 540 of method 500 . Figure 9B 5 shows a schematic planar cross-sectional view of a 3D memory device after operation 540 of method 500. It is noted that Figure 9A Shown Figure 9B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line CC′ in the xz plane, and Figure 9B Shown Figure 9A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0100] like Figure 9A and Figure 9B As shown in FIG, the surface of the sidewall of the semiconductor layer 644 exposed by the via hole 850 may be oxidized to form an isolation structure 960. Figure 9B As shown in , each of the isolation structures 960 has a ring-shaped structure that laterally surrounds a corresponding via hole 850. Since the via holes 850 have different depths in the vertical direction (z direction) and expose different numbers of semiconductor layers 644 in the stacked structure 640, the number of isolation structures 960 formed in different via holes 850 corresponds to the number of semiconductor layers 644 passed through by each of the via holes 850. For example, Figure 9AAs shown in , the via hole 850-1, the via hole 850-2, and the via hole 850-3 each expose a different number of semiconductor layers 644 in the stacked structure 640, and thus the number of isolation structures 960 formed in the via hole 850-1, the via hole 850-2, and the via hole 850-3 is also different.

[0101] Re-reference Figure 5 , method 500 can proceed to operation 550, in which the via hole can be further etched to perform a first expansion on the depth of the via hole, so that each of the first expanded via holes exposes an underlying semiconductor layer without an isolation structure, and a conductive connection structure can be formed on the exposed sidewall of the semiconductor layer without an isolation structure through the first expanded via hole. Figure 10 A schematic side cross-sectional view of a 3D memory device is shown after operation 550 of method 500 .

[0102] like Figure 10 As shown in , the via holes 850 can be further etched to perform a first depth expansion, so that each first-expanded via hole 1050 (e.g., first-expanded via holes 1050-1, 1050-2, and 1050-3) can expose an underlying semiconductor layer 644 without the isolation structure 960. Conductive connection structures 1070 (e.g., conductive connection structures 1070-1, 1070-2, and 1070-3) can be formed on the exposed sidewalls of the semiconductor layer 644 without the isolation structure 960 through the first-expanded via holes 1050, respectively. In some embodiments, the conductive connection structures 1070 can include a metal silicide material, such as titanium silicide, nickel silicide, or cobalt silicide. Metal ion implantation and / or thermal diffusion can be performed through the first-expanded via holes 1050 to transform the exposed surface of the exposed sidewalls of the semiconductor layer 644 without the isolation structure 960, thereby forming the conductive connection structures 1070. In some embodiments, each of the conductive connection structures 1070 may have a ring structure that laterally surrounds a corresponding one of the first expanded via holes 1050 .

[0103] Re-reference Figure 5 , method 500 can proceed to operation 560, in which the first expanded via hole can be further etched, thereby performing a second expansion on the depth of the first expanded via hole, so that the formed second expanded via hole stops at the etch stop layer, and the surface of the semiconductor layer exposed by the second expanded via hole can be oxidized to form an additional isolation structure. Figure 11 A schematic side cross-sectional view of a 3D memory device is shown after operation 560 of method 500 .

[0104] like Figure 11 As shown in , the first-expanded via holes 1050 can be further etched to perform a second depth expansion, so that each second-expanded via hole 1150 (e.g., second-expanded via holes 1150-1, 1150-2, and 1150-3) can expose an underlying semiconductor layer 644 without isolation structure 960. The second-expanded via holes 1150 can stop at the etch stop layer 630 and thus have the same depth. The second-expanded via holes 1150 can expose the sidewalls of the semiconductor layer 644 located below the conductive connection structure 1070 in each of the second-expanded via holes 1150. The exposed surface of the sidewalls of the semiconductor layer 644 located below the conductive connection structure 1070 in the second-expanded via holes 1150 can be oxidized to form an additional isolation structure 1160. Each of the additional isolation structures 1160 has a ring structure that laterally surrounds a corresponding one of the second-expanded via holes 1150 .

[0105] Re-reference Figure 5 , method 500 can proceed to operation 570, in which the second expanded via hole can be further etched, thereby performing a third expansion on the depth of the second expanded via hole, so that the formed third expanded via hole extends through the etch stop layer, thereby exposing the transistor layer, and a plurality of conductive vias can be formed in the third expanded via hole to couple with the transistor layer. Figure 12A A schematic side cross-sectional view of a 3D memory device is shown after operation 570 of method 500 . Figure 12B 5 shows a schematic planar cross-sectional view of a 3D memory device after operation 570 of method 500. It is noted that Figure 12A Shown Figure 12B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line CC′ in the xz plane, and Figure 12B Shown Figure 12A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0106] like Figure 12A and Figure 12BAs shown in , the second-extended via hole 1150 can be further etched to perform a third depth extension, such that the formed third-extended via hole extends through the etch stop layer 630 to expose the transistor layer 620. In some embodiments, any suitable etching process, such as a punching operation, can be performed to remove a portion of the etch stop layer 630 to expose the SNC structure of the array of vertical transistors in the transistor layer 620. Thereafter, a deposition process such as CVD, PVD, ALD, etc. can be performed to fill the third-extended via hole, thereby forming a plurality of conductive vias 1250 (e.g., conductive vias 1250-1, 1250-2, and 1250-3) in the third-extended via hole. Each conductive via 1250 can extend vertically through the stacked structure 640 and the etch stop layer 630 and contact the SNC structure of the array of vertical transistors in the transistor layer 620.

[0107] Re-reference Figure 5 , method 500 may proceed to operation 580, where the semiconductor layer may be replaced with a plurality of second conductive layers. In some embodiments, replacing the semiconductor layer with the second conductive layer includes: forming one or more slits extending vertically through the stacked structure and stopping at the insulating layer; removing the semiconductor layer through the slits to form a first horizontal trench; and forming the second conductive layer in the first horizontal trench. Figure 13A A schematic side cross-sectional view of a 3D memory device is shown after operation 580 of method 500 . Figure 13B 5 shows a schematic planar cross-sectional view of a 3D memory device after operation 580 of method 500. It is noted that Figure 13A Shown Figure 13B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line CC′ in the xz plane, and Figure 13B Shown Figure 13A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0108] like Figure 13A and Figure 13BAs shown in , the stacked structure 640 can be patterned to form a plurality of second slits 1360 arranged in parallel in a first lateral direction (x-direction), each second slit extending along a second lateral direction (y-direction). The plurality of second slits 1360 can extend vertically through the stacked structure 640 and stop at the etch stop layer 630, and extend laterally along the second lateral direction (y-direction). The plurality of second slits 1360 can be formed by any suitable etching process (e.g., optical etching, dry etching, wet etching, cleaning, etc.). The semiconductor layer 644 of the stacked structure 640 can be removed through the second slits 1360 to form a first horizontal trench (not shown), and a second conductive layer 1344 can be formed in the first horizontal trench by any suitable deposition process such as CVD, PVD, ALD, etc. In some embodiments, the second conductive layer 1344 can include any suitable conductive material, such as a metal (e.g., W, Cu, Al, etc.) or a metal compound (e.g., TiN, TaN, etc.).

[0109] Re-reference Figure 5 Method 500 may proceed to operation 590, where the sacrificial layer may be replaced with a plurality of first conductive layers, and one or more conductive walls may be formed. In some embodiments, replacing the sacrificial layer with the first conductive layer includes: removing a portion of the second conductive layer exposed by the second slit; removing the sacrificial layer through the second slit to form a second horizontal trench; forming a dielectric layer in the second horizontal trench and on sidewalls of the slit to cover the exposed surface of the second conductive layer; and forming the first conductive layer in the second horizontal trench. One or more conductive walls may be formed in the second slit. Figure 14 A schematic side cross-sectional view of a 3D memory device during operation 590 of method 500 is shown. Figure 15A A schematic side cross-sectional view of a 3D memory device is shown after operation 590 of method 500 . Figure 15B 5 shows a schematic planar cross-sectional view of a 3D memory device after operation 590 of method 500. It is noted that Figure 15A Shown Figure 15B A schematic side cross-sectional view of the 3D memory device shown in FIG. 1 along line CC′ in the xz plane, and Figure 15B Shown Figure 15A Schematic planar cross-sectional view of the 3D memory device shown in , taken along line AA′ in the xy plane.

[0110] like Figure 14As shown in , the portion of the deposited conductive material in the second slit 1360 and the portion of the second conductive layer 1344 adjacent to the second slit 1360 can first be removed by any appropriate etching / cleaning process, and the sacrificial layer 642 can be removed through the second slit 1360 to form a plurality of second horizontal trenches 1442. The sacrificial layer 642 can be removed by any appropriate selective etching process. The plurality of second horizontal trenches 1442 formed can expose the top and bottom surfaces of the second conductive layer 1344 and portions of the sidewalls of the plurality of conductive vias 1250.

[0111] like Figure 15A and Figure 15B As shown in FIG, a dielectric layer 1548 can be formed in the second horizontal trench 1442 and on the sidewalls of the second slit 1360 to cover the exposed surface of the second conductive layer 1344 and the exposed sidewalls of the plurality of conductive vias 1250. In some embodiments, the dielectric layer 1548 can include any suitable high-k dielectric material, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof, and can be formed by any suitable thin film deposition process (e.g., CVD, PVD, ALD, etc.). In some embodiments, a conductive material is then deposited in the second horizontal trench 1442 and the second slit 1360 to form the first conductive layer 1542 and the conductive wall 1560, respectively. The first conductive layer 1542 and the conductive wall 1560 can be formed by any suitable deposition process such as CVD, PVD, ALD, etc., and the first conductive layer 1542 and the conductive wall 1560 can include any suitable conductive material, for example, a metal (e.g., W, Cu, Al, etc.) or a metal compound (e.g., TiN, TaN, etc.).

[0112] The specific embodiments described above can be easily modified and / or adapted for various applications. Therefore, based on the teaching and guidance provided herein, it is intended that such adaptations and modifications fall within the meaning and range of equivalents of the disclosed embodiments.

[0113] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: A stacked structure comprising first conductive layers and second conductive layers alternately stacked in a vertical direction; a conductive wall extending vertically through the stack structure and contacting the first conductive layer but isolated from the second conductive layer; as well as Conductive vias, each conductive via vertically extending through the stacked structure and electrically connected to a corresponding one of the second conductive layers, but electrically isolated from the first conductive layer and other second conductive layers in the stacked structure.

2. The semiconductor device according to claim 1, further comprising: An isolation structure is located between the conductive via and the other second conductive layer to isolate the conductive via from the other second conductive layer.

3. The semiconductor device according to claim 2, further comprising: Conductive connection structures, each conductive connection structure is located between one of the conductive vias and the corresponding one of the second conductive layers to connect the one of the conductive vias to the corresponding one of the second conductive layers.

4. The semiconductor device according to claim 3, wherein: The isolation structure comprises silicon oxide; and The conductive connection structure includes a metal silicide material.

5. The semiconductor device according to claim 3, wherein: Each of the isolation structure and the conductive connection structure has a ring structure laterally surrounding a corresponding one of the conductive vias.

6. The semiconductor device according to claim 1, wherein: The second conductive layer and the first conductive layer include the same conductive material.

7. The semiconductor device according to claim 1, wherein: The first conductive layer and the conductive wall comprise a first conductive material; and The second conductive layer and the conductive via include a second conductive material different from the first conductive material.

8. The semiconductor device according to claim 1, further comprising: A dielectric layer comprising: a horizontal portion located between adjacent first and second conductive layers; a first vertical portion located between the conductive wall and the second conductive layer; and A second vertical portion is located between the conductive via and the first conductive layer.

9. The semiconductor device according to claim 8, wherein: The dielectric layer includes a high-K material.

10. The semiconductor device according to claim 8, wherein: The dielectric layer contacts side surfaces of the conductive wall and the conductive via, and horizontal surfaces of the first conductive layer and the second conductive layer.

11. The semiconductor device according to claim 1 , further comprising: An array of transistors are respectively coupled to the conductive vias.

12. The semiconductor device according to claim 11, wherein: The transistors are vertical gate transistors, each of which includes a channel structure extending in a vertical direction and a gate structure located at a lateral side of the channel structure.

13. The semiconductor device according to claim 11, further comprising: an insulating layer between the stacked structure and the array of transistors, Each conductive via extends through the insulating layer to couple to a corresponding transistor in the array of transistors.

14. The semiconductor device according to claim 1, wherein: A first thickness of the first conductive layer is different from a second thickness of the second conductive layer.

15. The semiconductor device according to claim 1, further comprising: a slot structure extending vertically through the stacked structure and extending laterally in a first direction between adjacent rows of conductive vias, The conductive wall extends transversely along the second direction to cut off the gap structure.

16. A memory device comprising: A capacitor stack structure comprising: The first electrode plates and the second electrode plates are alternately stacked in a vertical direction, a common electrode extending vertically through the capacitor stack structure and contacting the first electrode plate, and select electrodes, each select electrode extending through the capacitor stack structure and contacting a corresponding one of the second electrode plates; and An array of transistors, each transistor coupled to a corresponding one of the select electrodes.

17. The memory device of claim 16, further comprising: A high-K layer is located between the adjacent first and second electrode plates, between the first electrode plate and the common electrode, and between the second electrode plate and the selection electrode.

18. The memory device of claim 16, further comprising: a conductive connecting structure, each conductive connecting structure being located between one of the selective electrodes and a corresponding one of the second electrode plates to electrically connect the one of the selective electrodes and the corresponding one of the second electrode plates; as well as An isolation structure is located between the one of the selection electrodes and another second electrode plate different from the corresponding one of the second electrode plates.

19. The memory device of claim 18, wherein: The isolation structure comprises silicon oxide; and The conductive connection structure includes a metal silicide material.

20. The memory device of claim 18, wherein: Each of the isolation structure and the conductive connection structure has a ring-shaped structure laterally surrounding a corresponding one of the select electrodes.

21. The memory device of claim 16, wherein: The first electrode plate and the second electrode plate include the same conductive material.

22. The memory device of claim 16, wherein: The first electrode plate and the common electrode include a first conductive material; and The second electrode plate and the select electrode include a second conductive material different from the first conductive material.

23. The memory device of claim 16, further comprising: an insulating layer between the capacitor stack structure and the array of transistors, Wherein, the selection electrode extends through the insulating layer.

24. The memory device of claim 16, wherein: The transistor is a two-dimensional transistor or a vertical gate transistor.

25. The memory device of claim 16, further comprising: a slit structure extending vertically through the capacitor stack structure and extending laterally in a first direction between adjacent rows of select electrodes, The common electrode extends transversely along the second direction to cut off the gap structure.

26. A method for forming a semiconductor device, comprising: forming a stacked structure on the array of transistors, the stacked structure comprising semiconductor layers and sacrificial layers alternately stacked in a vertical direction; forming through holes each extending vertically through the stacked structure and forming an isolation structure and a conductive connection structure on exposed sidewalls of the semiconductor layer in the through holes, such that each through hole has a conductive connection structure in contact with a corresponding one of the semiconductor layers, and sidewalls of the other semiconductor layers are covered by the isolation structure; forming a conductive via in the through hole to connect the array of transistors; replacing the semiconductor layer with a second conductive layer; as well as The sacrificial layer is replaced with a first conductive layer.

27. The method of claim 26, further comprising: forming an insulating layer on the array of transistors, Wherein, the stacked structure is formed on the insulating layer.

28. The method according to claim 27, wherein Forming the through hole, the isolation structure, and the conductive connection structure includes: forming via holes having different depths in the stacked structure, each via hole stopping at a corresponding one of the sacrificial layers; and The surface of the semiconductor layer exposed by the via hole is oxidized to form an isolation structure.

29. The method according to claim 28, wherein Forming the through hole, the isolation structure and the conductive connection structure further includes: Performing a first expansion on the depth of the via holes so that each via hole exposes an underlying semiconductor layer without the isolation structure; and A conductive connection structure is formed on the exposed sidewall of the semiconductor layer without the isolation structure through the first expanded via hole.

30. The method according to claim 29, wherein Forming the through hole, the isolation structure and the conductive connection structure further includes: Performing a second expansion on the depth of the via holes so that each via hole stops at the insulating layer; and The surface of the semiconductor layer exposed by the second expanded via hole is oxidized to form an additional isolation structure.

31. The method according to claim 30, wherein Forming the through hole, the isolation structure and the conductive connection structure further includes: The depth of the via hole is thirdly expanded to form the through holes, so that each through hole extends through the insulating layer and exposes a corresponding one of the transistors.

32. The method according to claim 31, wherein Replacing the semiconductor layer with the second conductive layer includes: forming a vertical trench extending vertically through the stacked structure and stopping at the insulating layer; removing the semiconductor layer through the vertical trench to form a first horizontal trench; and The second conductive layer is formed in the first horizontal trench.

33. The method according to claim 32, wherein Replacing the sacrificial layer with the first conductive layer includes: removing a portion of the second conductive layer exposed by the vertical trench; removing the sacrificial layer through the vertical trench to form a second horizontal trench; forming a dielectric layer in the second horizontal trench and on sidewalls of the vertical trench to cover exposed surfaces of the second conductive layer; and The first conductive layer is formed in the second horizontal trench.

34. The method of claim 26, further comprising: forming a gap structure extending vertically through the stacked structure and extending laterally along a first direction, Wherein, a row of through holes is formed between adjacent first gap structures.

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