Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device includes a memory device, a sense amplifier, and a processing unit. The sense amplifier and the processing unit are disposed on a first layer, and the memory device is disposed on a second layer stacked on the first layer. The memory device includes a first transistor, a second transistor, and a capacitor, both of which are disposed overlapping on the first transistor. Source electrodes and drain electrodes of the first and second transistors are provided at different heights with respect to the substrate surface. A gate electrode of the first transistor is used as one of a source electrode and a drain electrode of the second transistor and one electrode of the capacitor. A dielectric layer of the capacitor is disposed on a gate electrode of the first transistor. The other electrode of the capacitor is provided on the dielectric layer of the capacitor so as to be spaced apart from the gate electrode of the second transistor.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device. Another embodiment of the present invention relates to a memory device and a method for manufacturing a memory device. Another embodiment of the present invention relates to a transistor and a method for manufacturing a transistor. Another embodiment of the present invention relates to a capacitor and a method for manufacturing a capacitor. Another embodiment of the present invention relates to an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the aforementioned technical field. Examples of the technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices incorporating these devices, and methods for driving or manufacturing these devices.

[0003] Note that in this specification and other documents, a semiconductor device refers to a device that utilizes semiconductor characteristics and refers to circuits that include semiconductor elements (transistors, diodes, photodiodes, etc.) and devices that include such circuits. Furthermore, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. For example, examples of semiconductor devices include integrated circuits, chips that include integrated circuits, and electronic components that contain chips in packages. Furthermore, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices themselves are semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, such as the use of large-scale integrated circuits (LSIs) in semiconductor devices. For example, central processing units (CPUs) and memories are used in semiconductor devices. A CPU is an assembly of semiconductor elements that includes a semiconductor integrated circuit (including at least transistors and memory) processed from a semiconductor wafer into a chip, and electrodes that serve as connection terminals.

[0005] Semiconductor circuits (IC chips) such as CPUs and memories are mounted on circuit boards such as printed wiring boards and used as components of various electronic devices.

[0006] In addition, the technology of forming transistors using a semiconductor thin film formed on a substrate with an insulating surface has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and display devices. Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, and oxide semiconductors are attracting attention as other materials.

[0007] Furthermore, it is known that transistors using oxide semiconductors have extremely low leakage current in the non-conducting state. For example, Patent Document 1 discloses a low-power CPU that utilizes the low leakage current characteristic of transistors using oxide semiconductors. Furthermore, Patent Document 2 discloses a memory device that utilizes the low leakage current characteristic of transistors using oxide semiconductors to achieve long-term retention of stored data.

[0008] In recent years, with the miniaturization and lightweighting of electronic devices, the demand for further high-density integrated circuits has increased. In addition, there is a need to improve the productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology in which a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film are stacked to provide multiple memory cells in an overlapping manner, thereby increasing the density of the integrated circuit.

[0009] Furthermore, the use of vertical transistors can achieve higher density of integrated circuits. For example, Patent Document 4 discloses a vertical transistor in which the side surfaces of an oxide semiconductor are covered by a gate electrode via a gate insulating layer. [Prior technical literature] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187 [Patent Document 2] Japanese Patent Application Publication No. 2011-151383 [Patent Document 3] International Patent Application Publication No. 2021 / 053473 [Patent Document 4] Japanese Patent Application Publication No. 2013-211537 [Non-patent literature]

[0011] [Non-Patent Literature 1] M. Oota et al., “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm,” IEDM Tech. Dig., 2019, pp. 50-53 Summary of the Invention Technical problem to be solved by the invention

[0012] One of the purposes of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a transistor that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device, a memory device, or a transistor with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor with large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a transistor, a memory device, or a semiconductor device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide an inexpensive semiconductor device or a memory device. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or a memory device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device or a memory device with high operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, a memory device, or a transistor.

[0013] Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, a memory device, or a transistor that can achieve miniaturization or high integration. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device, a memory device, or a transistor that is highly reliable. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a transistor with a large on-state current. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a transistor, a memory device, or a semiconductor device that has good electrical characteristics. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device that has a high yield. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device that has low power consumption. Furthermore, one of the objects of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device or a memory device that has a high operating speed. Furthermore, one of the objects of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device, a memory device, or a transistor.

[0014] Note that the inclusion of these objectives does not preclude the existence of other objectives. One embodiment of the present invention does not necessarily achieve all of the above objectives. Objectives other than the above objectives may be extracted from the description of the specification, drawings, and claims. Means of solving technical problems

[0015] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer. The second transistor and the capacitor are both arranged to overlap on the first transistor. The source electrode and the drain electrode of each of the first transistor and the second transistor are located at different heights relative to a substrate surface. The first insulating layer is arranged between the source electrode and the drain electrode of the first transistor and includes a first opening that reaches one of the source electrode and the drain electrode of the first transistor. The other of the source electrode and the drain electrode of the first transistor is arranged on the first insulating layer. The semiconductor layer of the first transistor has a region in contact with a top surface of one of the source electrode and the drain electrode of the first transistor within the first opening, a side surface of the first insulating layer within the first opening, a side surface of the other of the source electrode and the drain electrode of the first transistor within the first opening, and a top surface of the other of the source electrode and the drain electrode of the first transistor. The gate insulating layer of the first transistor is arranged on the semiconductor layer of the first transistor so as to contact the semiconductor layer. The gate electrode of the first transistor is arranged on the first transistor so as to have a region overlapping with the semiconductor layer of the first transistor. The semiconductor layer of the second transistor has a region in contact with a top surface of the gate electrode of the first transistor within the second opening, a side surface of the second insulating layer within the second opening, a side surface of the other of the source electrode and the drain electrode of the second transistor within the second opening, and a top surface of the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer of the second transistor is provided on the semiconductor layer of the second transistor in a manner contacting the semiconductor layer of the second transistor. The gate electrode of the second transistor is provided on the gate insulating layer of the second transistor in a manner having a region overlapping with the semiconductor layer of the second transistor. The dielectric layer of the capacitor is provided on the gate electrode of the first transistor. The other electrode of the capacitor is provided on the dielectric layer of the capacitor in a manner having a region overlapping with the gate electrode of the first transistor and being spaced apart from the second opening when viewed from a plan view.

[0016] In the above description, at least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is preferably a transistor including a metal oxide.

[0017] In addition, in the above, it is preferred to have a region where the side of the semiconductor layer of the first transistor is roughly aligned with the side of the other of the source electrode and the drain electrode of the first transistor, and a region where the side of the semiconductor layer of the second transistor is roughly aligned with the side of the other of the source electrode and the drain electrode of the second transistor.

[0018] In the above description, it is preferable that the end portion of the other electrode of the capacitor that does not face the first opening is located outside the end portion of the gate electrode of the first transistor.

[0019] In the above description, the other electrode of the capacitor is preferably provided at both a first end portion of the gate electrode of the first transistor and a second end portion opposite to the first end portion.

[0020] In the above description, the other electrode of the capacitor preferably has a region overlapping with a top surface of the gate electrode of the first transistor so as to surround the second opening.

[0021] In addition, in the above, the dielectric layer of the capacitor preferably includes any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0022] In the above, the dielectric layer of the capacitor preferably contains any one of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium bismuth tantalate, bismuth ferrite, and barium titanate.

[0023] In the above, the first insulating layer and the second insulating layer preferably include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate, and acrylic resin.

[0024] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer and a first conductive film on the first conductive layer; processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, and forming a first opening reaching the first conductive layer in the first conductive film and the first insulating layer; processing the second conductive layer to form a third conductive layer; forming a first metal oxide film in contact with the top surface of the first conductive layer in the first opening, the side surface of the first insulating layer in the first opening, the side surface of the third conductive layer in the first opening, and the top surface of the third conductive layer; processing the first metal oxide film to form a first semiconductor layer in a manner having an overlapping area with the first opening; forming a second insulating layer in contact with the top surface of the first semiconductor layer; forming a second conductive film on the second insulating layer; processing the second conductive film to form a fourth conductive layer in a manner having an overlapping area with the first semiconductor layer; forming a third insulating layer on the fourth conductive layer and the second insulating layer. ; forming a third conductive film on the third insulating layer; processing the third conductive film to form a fifth conductive layer in a manner having an overlapping area with the fourth conductive layer; forming a fourth insulating layer and a fourth conductive film on the fifth conductive layer and the third insulating layer; processing the fourth insulating layer and the fourth conductive film to form a sixth conductive layer from the fourth conductive film, and forming a second opening reaching the fourth conductive layer in the fourth conductive film and the fourth insulating layer; processing the sixth conductive layer to form a seventh conductive layer; forming a second metal oxide film in contact with the top surface of the fourth conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the seventh conductive layer in the second opening, and the top surface of the seventh conductive layer; processing the second metal oxide film to form a second semiconductor layer in a manner having an overlapping area with the second opening; forming a fifth insulating layer in contact with the top surface of the second semiconductor layer; forming a fifth conductive film on the fifth insulating layer; and processing the fifth conductive film to form an eighth conductive layer in a manner having an overlapping area with the second semiconductor layer.

[0025] In addition, one embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer and a first conductive film on the first conductive layer; processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, and forming a first opening reaching the first conductive layer in the first conductive film and the first insulating layer; forming a first metal oxide film in contact with the top surface of the first conductive layer in the first opening, the side surface of the first insulating layer in the first opening, the side surface of the second conductive layer in the first opening, and the top surface of the second conductive layer; processing the first metal oxide film to form a first semiconductor layer in a manner having an overlapping region with the first opening; processing the second conductive layer to form a third conductive layer in a manner having an overlapping region with the first semiconductor layer; forming a second insulating layer in contact with the top surface of the first semiconductor layer; forming a second conductive film on the second insulating layer; processing the second conductive film to form a fourth conductive layer in a manner having an overlapping region with the first semiconductor layer; forming a third insulating layer on the fourth conductive layer and the second insulating layer; forming a third insulating layer on the third insulating layer a third conductive film is formed on the substrate; the third conductive film is processed to form a fifth conductive layer having an overlapping area with the fourth conductive layer; a fourth insulating layer and a fourth conductive film are formed on the fifth conductive layer and the third insulating layer; the fourth insulating layer and the fourth conductive film are processed to form a sixth conductive layer from the fourth conductive film, and a second opening reaching the fourth conductive layer is formed in the fourth conductive film and the fourth insulating layer; a second metal oxide film is formed in contact with the top surface of the fourth conductive layer in the second opening, the side surface of the third insulating layer in the second opening, the side surface of the fourth insulating layer in the second opening, the side surface of the sixth conductive layer in the second opening, and the top surface of the sixth conductive layer; the second metal oxide film is processed to form a second semiconductor layer having an overlapping area with the second opening; the sixth conductive layer is processed to form a seventh conductive layer having an overlapping area with the second semiconductor layer; a fifth insulating layer is formed in contact with the top surface of the second semiconductor layer; a fifth conductive film is formed on the fifth insulating layer; and the fifth conductive film is processed to form an eighth conductive layer having an overlapping area with the second semiconductor layer.

[0026] In addition, one embodiment of the present invention is a semiconductor device including a storage unit and a processing unit, the storage unit including a storage device and a sense amplifier, the processing unit including a CPU, an MPU, or a GPU, the sense amplifier and the processing unit being arranged on a first layer, the storage device being arranged on a second layer and including a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer, the second layer being stacked on the first layer, the second transistor and the capacitor being stacked on the first transistor, the source electrode and the drain electrode of each of the first transistor being located at different heights relative to a substrate surface, the first insulating layer being arranged between the source electrode and the drain electrode of the first transistor and including a first opening reaching one of the source electrode and the drain electrode of the first transistor, the other of the source electrode and the drain electrode of the first transistor being arranged on the first insulating layer, the semiconductor layer of the first transistor having a region in contact with a top surface of one of the source electrode and the drain electrode of the first transistor within the first opening, a side surface of the first insulating layer within the first opening, a side surface of the other of the source electrode and the drain electrode of the first transistor within the first opening, and a top surface of the other of the source electrode and the drain electrode of the first transistor, and the gate insulating layer of the first transistor being in contact with the semiconductor layer of the first transistor. A first transistor is disposed on the gate insulating layer of the first transistor in a manner that has a region overlapping with the semiconductor layer of the first transistor and is used as one of the source electrode and the drain electrode of the second transistor and one electrode of the capacitor. The second insulating layer is disposed between the source electrode and the drain electrode of the second transistor and includes a second opening that reaches the gate electrode of the first transistor. The other of the source electrode and the drain electrode of the second transistor is disposed on the second insulating layer. The semiconductor layer of the second transistor has a region in contact with a top surface of the gate electrode of the first transistor within the second opening, a side surface of the second insulating layer within the second opening, a side surface of the other of the source electrode and the drain electrode of the second transistor within the second opening, and a top surface of the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer of the second transistor is disposed on the gate insulating layer of the second transistor in a manner that is in contact with the semiconductor layer of the second transistor. The gate electrode of the second transistor is disposed on the gate insulating layer of the second transistor in a manner that has a region overlapping with the semiconductor layer of the second transistor. A dielectric layer of the capacitor is disposed on the gate electrode of the first transistor. The other electrode of the capacitor is disposed on the dielectric layer of the capacitor in a manner that has a region overlapping with the gate electrode of the first transistor and is spaced apart from the second opening when viewed from a plan view.

[0027] In the above description, at least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is preferably a transistor including a metal oxide.

[0028] In addition, in the above, it is preferred to have a region where the side of the semiconductor layer of the first transistor is roughly aligned with the side of the other of the source electrode and the drain electrode of the first transistor, and a region where the side of the semiconductor layer of the second transistor is roughly aligned with the side of the other of the source electrode and the drain electrode of the second transistor.

[0029] In the above description, it is preferable that the end portion of the other electrode of the capacitor that does not face the first opening is located outside the end portion of the gate electrode of the first transistor.

[0030] In the above description, the other electrode of the capacitor is preferably provided at both a first end portion of the gate electrode of the first transistor and a second end portion opposite to the first end portion.

[0031] In the above description, the other electrode of the capacitor preferably has a region overlapping with a top surface of the gate electrode of the first transistor so as to surround the second opening.

[0032] In addition, in the above, the dielectric layer of the capacitor preferably includes any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

[0033] In the above, the dielectric layer of the capacitor preferably contains any one of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium bismuth tantalate, bismuth ferrite, and barium titanate.

[0034] In the above, the first insulating layer and the second insulating layer preferably include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate, and acrylic resin. Effects of the Invention

[0035] According to one embodiment of the present invention, a semiconductor device, a memory device, or a transistor capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device, a memory device, or a transistor with high reliability can be provided. In addition, according to one embodiment of the present invention, a transistor with large on-state current can be provided. In addition, according to one embodiment of the present invention, a transistor, a memory device, or a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, an inexpensive semiconductor device or memory device can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or memory device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device or memory device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device, memory device, or transistor can be provided.

[0036] In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device, a memory device, or a transistor that can achieve miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device, a memory device, or a transistor that has high reliability can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a transistor with large on-state current can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a transistor, a memory device, or a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with high yield can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device or a memory device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device, a memory device, or a transistor can be provided.

[0037] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above effects can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1A This is a block diagram illustrating an example of the structure of an electronic computer. Figure 1B and Figure 1C This is a schematic diagram illustrating an example of the structure of an electronic computer. Figure 2 This is a schematic diagram illustrating an example of the structure of an electronic computer. Figure 3 This is a circuit diagram illustrating a structural example of a semiconductor device. Figures 4A to 4D This is a circuit diagram illustrating a structural example of a semiconductor device. Figure 5A is a plan view showing a structural example of a storage device. Figure 5B and Figure 5C is a cross-sectional view showing a structural example of a storage device. Figure 6 is a cross-sectional view showing a structural example of a storage device. Figure 7A is a cross-sectional view showing a structural example of a transistor. Figure 7B is a plan view showing a structural example of a transistor. Figure 8A is a plan view showing a structural example of a storage device. Figure 8B and Figure 8C is a cross-sectional view showing a structural example of a storage device. Figure 9A is a plan view showing a structural example of a storage device. Figure 9B and Figure 9C is a cross-sectional view showing a structural example of a storage device. Figure 10A is a plan view showing a structural example of a storage device. Figure 10B and Figure 10C is a cross-sectional view showing a structural example of a storage device. Figure 11 This is a circuit diagram illustrating a structural example of a semiconductor device. Figure 12 This is a timing chart illustrating an example of the operation of a semiconductor device. Figure 13 This is a block diagram illustrating a structural example of a storage device. Figure 14A and Figure 14B This is a circuit diagram illustrating a structural example of a storage device. Figure 15 It is a schematic diagram illustrating a structural example of a storage device. Figure 16 This is a circuit diagram illustrating a structural example of a semiconductor device. Figure 17 This is a timing chart illustrating an example of the operation of a semiconductor device. 18A to 18D It is a schematic diagram illustrating an example of operation of a semiconductor device. Figure 19 This is a timing chart illustrating an example of the operation of a semiconductor device. Figures 20A to 20G It is a schematic diagram illustrating an example of operation of a semiconductor device. Figure 21 is a block diagram illustrating a CPU. Figure 22A and Figure 22B It is a perspective view of a semiconductor device. Figure 23A and Figure 23B It is a perspective view of a semiconductor device. Figure 24A and Figure 24B This diagram shows various storage devices in a hierarchical manner. Figure 25A It is a plan view showing an example of a method for manufacturing a storage device. Figure 25B and Figure 25C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 26 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 27A It is a plan view showing an example of a method for manufacturing a storage device. Figure 27B and Figure 27C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 28 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 29A It is a plan view showing an example of a method for manufacturing a storage device. Figure 29B and Figure 29C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 30 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 31A It is a plan view showing an example of a method for manufacturing a storage device. Figure 31B and Figure 31C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 32 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 33A It is a plan view showing an example of a method for manufacturing a storage device. Figure 33B and Figure 33C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 34 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 35A It is a plan view showing an example of a method for manufacturing a storage device. Figure 35B and Figure 35C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 36 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 37A It is a plan view showing an example of a method for manufacturing a storage device. Figure 37B and Figure 37C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 38 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 39A It is a plan view showing an example of a method for manufacturing a storage device. Figure 39B and Figure 39C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 40 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 41A It is a plan view showing an example of a method for manufacturing a storage device. Figure 41B and Figure 41C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 42 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 43A It is a plan view showing an example of a method for manufacturing a storage device. Figure 43B and Figure 43C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 44 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 45A It is a plan view showing an example of a method for manufacturing a storage device. Figure 45B and Figure 45C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 46 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 47A It is a plan view showing an example of a method for manufacturing a storage device. Figure 47B and Figure 47C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 48 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 49A It is a plan view showing an example of a method for manufacturing a storage device. Figure 49B and Figure 49C is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 50 is a cross-sectional view illustrating an example of a method for manufacturing a storage device. Figure 51 is a cross-sectional view showing a structural example of a storage device. Figure 52A and Figure 52B This is a diagram showing an example of an electronic component. Figure 53A and Figure 53B is a diagram illustrating an example of an electronic device. Figures 53C to 53E This is a diagram showing an example of a mainframe computer. Figure 54 This is a diagram showing an example of space equipment. Figure 55 FIG. 1 is a diagram illustrating an example of a storage system that can be used in a data center. Modes for Carrying Out the Invention

[0039] The embodiments will be described in detail with reference to the accompanying drawings. However, those skilled in the art will readily understand that the present invention is not limited to the following description and can be modified in various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the embodiments described below.

[0040] Note that in the structures of the invention described below, the same reference numerals are used in common across different drawings to represent the same parts or parts having the same function, and their repeated descriptions are omitted. In addition, when parts having the same function are represented, the same hatching is sometimes used without a special reference numeral.

[0041] Furthermore, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not necessarily represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges shown in the drawings. For example, in actual manufacturing processes, layers or resist masks may be unintentionally thinned due to etching or other processes, but this is sometimes omitted from the drawings to facilitate understanding.

[0042] Note that in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience. However, such ordinal numbers do not limit the number of components or the order of components (for example, the order of steps or the order of stacking). In addition, the ordinal numbers assigned to components in one part of this specification may not be consistent with the ordinal numbers assigned to the same components in another part of this specification or in the claims.

[0043] A transistor is a type of semiconductor element that can amplify current or voltage, control conduction or non-conduction, etc. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).

[0044] In this specification, etc., a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (also called a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) where a channel is formed. Current can flow between the source and drain through the channel formation region. Note that in this specification, etc., the channel formation region refers to the region where current primarily flows.

[0045] In addition, when using transistors with different polarities or when the direction of current changes during circuit operation, the functions of "source" and "drain" may be interchanged. Therefore, in this specification, "source" and "drain" may be used interchangeably.

[0046] Note that the impurities of a semiconductor refer to, for example, elements other than the main components that constitute the semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be said to be an impurity. When impurities are contained, for example, an increase in the defect state density of the semiconductor or a decrease in the crystallinity may occur. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, for example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In addition, water sometimes acts as an impurity. In addition, for example, the mixing of impurities sometimes leads to oxygen vacancies (also recorded as V O ) formation.

[0047] Note that in this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen in its composition, and an oxynitride refers to a material containing more nitrogen than oxygen in its composition.

[0048] For example, the content of elements such as hydrogen, oxygen, carbon, and nitrogen in the film can be analyzed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS). When the content of the target element is high (e.g., 0.5 atomic% or more or 1 atomic% or more), XPS analysis is preferred. On the other hand, when the content of the target element is low (e.g., 0.5 atomic% or less or 1 atomic% or less), SIMS analysis is preferred. When comparing elemental contents, a combined analysis using both SIMS and XPS is more preferred.

[0049] In this specification, the terms "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be replaced with "conductive film" or "conductive film" may be replaced with "conductive layer." Furthermore, for example, "insulating film" may be replaced with "insulating layer" or "insulating layer" may be replaced with "insulating film." Furthermore, for example, "semiconductor film" may be replaced with "semiconductor layer" or "semiconductor layer" may be replaced with "semiconductor film."

[0050] In this specification, etc., "parallel" refers to a state in which two straight lines are arranged at an angle of greater than -10 degrees and less than 10 degrees. Therefore, a state in which the angle is greater than -5 degrees and less than 5 degrees is also included. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of greater than -30 degrees and less than 30 degrees. In addition, "perpendicular" refers to a state in which two straight lines are arranged at an angle of greater than 80 degrees and less than 100 degrees. Therefore, a state in which the angle is greater than 85 degrees and less than 95 degrees is also included. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of greater than 60 degrees and less than 120 degrees.

[0051] In addition, in this specification and the like, "connection" includes "electrical connection".

[0052] "A and B are electrically connected" means that, when A and B are not connected via an insulator (when A and B are connected via a conductor or semiconductor, or when A and B are in contact), there is a time sequence during which electric signals are transferred or received, or electric potentials interact with each other, between A and B during circuit operation. In other words, during circuit operation, even if there are times when electric signals are not transferred or received, or electric potentials interact with each other, as long as there is a time sequence during which electric signals are transferred or received, or electric potentials interact with each other, it can be said that "A and B are electrically connected."

[0053] “Electrically connected” includes connection without passing through a circuit element (eg, a transistor, but excluding wiring) (direct connection) and connection through one or more circuit elements (indirect connection).

[0054] "A and B are electrically connected" includes, for example, cases where A and B are not connected via a circuit element, or where A and B are connected via the source and drain of one or more transistors. Note that this assumes that there is a timing for the exchange of electrical signals or the interaction of potentials between A and B.

[0055] The case where it cannot be said that “A and B are electrically connected” because A and B are connected through an insulator refers to the case where, for example, a dielectric of a capacitor, a gate insulating film of a transistor, etc. is interposed between A and B.

[0056] Since A and B are not connected through an insulator, there is no timing for the transfer of electric signals or interaction of electric potentials between A and B, and therefore it cannot be said that "A and B are electrically connected". For example, the following situations refer to the following situations: a potential V from a power supply or signal source is supplied on the path from A to B (note that this does not include the case where the potential V is supplied through a circuit element); when A and C are connected through the source and drain of transistor TrP and B and C are connected through the source and drain of transistor TrQ, there is no timing for both transistor TrP and transistor TrQ to be turned on at the same time.

[0057] In this specification, etc., a "resistance element" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistance element" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistance element" may sometimes be referred to as a "resistance", "load", or "region having a resistance value". In contrast, "resistance", "load", or "region having a resistance value" may sometimes be referred to as a "resistance element". As for the resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0058] In this specification, etc., a "capacitive element" may be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, a "capacitive element", "parasitic capacitance" or "gate capacitance" may sometimes be referred to as a "capacitor". In contrast, a "capacitor" may sometimes be referred to as a "capacitive element", "parasitic capacitance" or "gate capacitance". In addition, a "capacitor" (a "capacitor" having three or more terminals) includes an insulator and a pair of conductors that clamp the insulator. Thus, the "pair of conductors" of the "capacitor" may be referred to as a "pair of electrodes", "a pair of conductive regions", "a pair of regions" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as a first terminal and a second terminal, respectively. In addition, the electrostatic capacitance value may be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it may also be greater than 1pF and less than 10μF.

[0059] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel or p-channel) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other is used as the drain. Therefore, in this specification, etc., the source and drain can sometimes be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0060] For example, in this specification, a multi-gate structure transistor having two or more gates can be used as an example of a transistor. When a multi-gate structure is adopted, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0061] In addition, a circuit diagram showing a circuit element sometimes includes a case where the circuit element includes multiple circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are electrically connected in series. For example, a circuit diagram showing a capacitor includes a case where two or more capacitors are electrically connected in parallel. In addition, for example, a circuit diagram showing a transistor includes a case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch includes two or more transistors, the two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.

[0062] In this specification, a node may also be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit structure or device structure. Terminals, wiring, etc. may also be referred to as nodes.

[0063] In this specification, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is ground potential (earth potential), "voltage" may also be referred to as "potential." Note that ground potential does not necessarily mean 0V. Furthermore, potential is relative; changes in the reference potential also cause changes in the potential supplied to wiring, applied to circuits, and output from circuits.

[0064] In this specification and other documents, the terms "high-level potential" and "low-level potential" do not necessarily refer to specific potentials. For example, even if two wirings are described as "wirings for supplying a high-level potential," the high-level potentials supplied by the two wirings may be different. Similarly, even if two wirings are described as "wirings for supplying a low-level potential," the low-level potentials supplied by the two wirings may be different.

[0065] In addition, "current" refers to the migration phenomenon of charge (conduction). For example, the description of "conduction occurs in a positively charged body" can be replaced by the description of "conduction occurs in a negatively charged body in the opposite direction". Therefore, in this specification, etc., unless otherwise stated, "current" refers to the migration phenomenon of charge (conduction) when carriers migrate. Here, as carriers, for example, electrons, holes, anions, cations, complex ions, etc. can be cited. The carriers are different depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers migrate, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers migrate is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, etc., unless otherwise specified, with respect to the positive and negative signs of current (or the direction of current), the description of "current flows from element A to element B" can be replaced by the description of "current flows from element B to element A". In addition, the description of "current is input to element A" can be replaced by the description of "current is output from element A".

[0066] In this specification, unless otherwise specified, the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or the blocking state). In an n-channel transistor, the off-state refers to the voltage V between the gate and the source. gs Below the threshold voltage V th (In a p-channel transistor, V gs Higher than Vth ) status.

[0067] Note that in this specification and other documents, a tapered shape refers to a shape in which at least a portion of a component's side surface is inclined relative to the substrate surface or the surface being formed. For example, this refers to a region where the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface being formed is less than 90 degrees. Furthermore, the side surface, substrate surface, or surface being formed of a component does not necessarily have to be completely flat; it may be a nearly planar shape with a slight curvature or a nearly planar shape with fine irregularities.

[0068] In this specification, when it is described that A is in contact with B, at least a portion of A is in contact with B. Therefore, for example, it can be alternatively described that A has a region in contact with B.

[0069] In this specification and the like, when it is described that A is located on B, at least a portion of A is located on B. Therefore, for example, it can be alternatively described that A has a region located on B.

[0070] In this specification and the like, when it is described that A covers B, at least a portion of A covers B. Therefore, for example, it can be alternatively described that A has a region covering B.

[0071] In this specification and the like, when it is described that A and B overlap, at least a portion of A overlaps with B. Therefore, for example, it can be alternatively described that A has a region that overlaps with B.

[0072] In this specification and other documents, for convenience, terms such as "upper," "lower," "left," and "right" are used to describe the positional relationships of components with reference to the accompanying drawings. Furthermore, the positional relationships of the components may be appropriately modified depending on the orientation in which the components are described. Therefore, the terms are not limited to those described in this specification and may be appropriately modified depending on the circumstances.

[0073] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, or also referred to as OS). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor may refer to a transistor containing a metal oxide or an oxide semiconductor. Note that metal oxides containing nitrogen are sometimes collectively referred to as metal oxides. In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0074] (Implementation Method 1) A semiconductor device according to one embodiment of the present invention can be used as an electronic computer (also referred to as a computer). At least a portion of an electronic computer according to one embodiment of the present invention can be used in, for example, a microcomputer, a personal computer, a workstation, a mainframe, or a supercomputer.

[0075] In the components of a semiconductor device according to one embodiment of the present invention, a processing unit such as a CPU and a portion of a memory unit (e.g., a sense amplifier) ​​can be formed on the same layer (the first layer). Therefore, the semiconductor device can be manufactured using fewer steps than when the processing unit and the memory unit are formed on separate layers. Furthermore, by forming the processing unit and a portion of the memory unit on the same layer (the first layer), the physical distance between them can be reduced, thereby reducing the effects of signal delays and other effects of wiring between them. Consequently, the operating speed of the semiconductor device can be increased and power consumption can be reduced.

[0076] In addition, in a semiconductor device according to one embodiment of the present invention, a memory cell (sometimes also referred to as a memory device) constituting a memory portion is provided on a layer (second layer) different from the first layer. Here, the second layer is stacked on the first layer. In a semiconductor device according to one embodiment of the present invention, the memory cell can be formed using micro transistors and capacitors. In addition, the transistors and capacitors constituting the memory cell are arranged in an overlapping manner, and each component is formed in a manner that shares a portion thereof. Therefore, a micro semiconductor device with high integration can be realized. In addition, a semiconductor device with fewer processes and low cost can be realized. Below, an electronic computer that can be used for a semiconductor device according to one embodiment of the present invention is described with reference to the accompanying drawings.

[0077] <Structure Example of Electronic Computer> Figure 1A 1 is a block diagram illustrating a configuration example of an electronic computer 900 that can be used in a semiconductor device according to one embodiment of the present invention.

[0078] like Figure 1A As shown, the electronic computer 900 includes a processing unit 910 (sometimes also called a processor), a storage unit 920 (sometimes also called a memory), and a control unit 930. The processing unit 910, the storage unit 920, and the control unit 930 are electrically connected to each other via a bus 971.

[0079] Note that, although not shown, the electronic computer 900 may also include, for example, an input / output unit (sometimes also referred to as an interface). This input / output unit has the function of transmitting and receiving data with functional devices external to the electronic computer 900 (e.g., input devices, output devices, and storage devices).

[0080] The processing unit 910 has, for example, a function of executing a series of processes (tasks) by sequentially executing processes corresponding to a program. Alternatively, it has, for example, a function of executing multiple tasks. At least a portion of the processing unit 910 may be, for example, a CPU, an MPU (Micro Processing Unit), a GPU (Graphics Processing Unit), or the like.

[0081] The processing unit 910 includes a computing unit 911 (sometimes also referred to as a core), a control unit 912 , and a register unit 913 . The register unit 913 includes one or more register units 914 .

[0082] The register unit 914 includes a scan flip-flop 915 and a backup memory 916. At least a portion of the register unit 914 can be used, for example, as general registers and special registers (e.g., a program counter (PC), an instruction register (IR), and a status register (SR)).

[0083] The calculation unit 911 may include, for example, an arithmetic logic unit (ALU) and a floating point unit (FPU).

[0084] The control unit 912 has a function of controlling the operation of the processing unit 910. For example, it has a function of controlling the processing to be executed while switching between multiple tasks. In addition, for example, it may include an instruction decoder (ID) and the like.

[0085] A specific configuration example of the register unit 914 will be described later.

[0086] The storage unit 920 has a function of storing programs and data, for example. At least a portion of the storage unit 920 can be used as a main memory or a cache memory, for example.

[0087] The storage unit 920 includes a memory array unit 921 and a control unit 922 .

[0088] The memory array section 921 includes one or more memory blocks 923. The memory block 923 includes one or more memory cells 924 and a sense amplifier 926. The memory cell 924 includes one or more storage units 925.

[0089] Here, sometimes Figure 1A A collection of multiple memory cells 925 surrounded by dotted lines is called a memory cell array.

[0090] The control unit 922 has a function of controlling the operation of the storage unit 920 . For example, it has a function of controlling writing and reading of data to and from the memory array unit 921 .

[0091] A specific configuration example of the memory block 923 and a specific configuration example of the storage unit 920 will be described later.

[0092] The control unit 930 has the function of controlling the operation of the electronic computer 900. Furthermore, it may include, for example, a power management unit (PMU). The PMU, for example, has the function of controlling the operation of power gating. For example, it has the function of controlling the power supply to each component included in the electronic computer 900 by switching a power switch (not shown) into a conductive or non-conductive state.

[0093] Figure 1B It is a schematic diagram illustrating an example of the layer structure of the electronic computer 900.

[0094] like Figure 1B As shown, electronic computer 900 includes layer 985 and layer 982. Layer 982 includes layer 983 and multiple layers 984 (layer 984[1] to layer 984[K] (K is an integer greater than or equal to 2)). Alternatively, a structure including only one layer 984 may be employed.

[0095] Layer 983 is stacked on layer 985. Layers 984[1] to 984[K] are stacked on layer 983.

[0096] In addition, in order to facilitate the description of the positional relationship of each component, the X direction, Y direction, and Z direction are specified in the following description. The X direction, Y direction, and Z direction are perpendicular or approximately perpendicular to each other. Note that approximately perpendicular refers to a state in which the angle formed by two components of an object is greater than 85 degrees and less than 95 degrees. The Z direction is the direction in which layer 983 and layers 984[1] to 984[K] are stacked on layer 985. Therefore, the X direction and the Y direction are directions along the surfaces of layer 985, layer 983, and layers 984[1] to 984[K].

[0097] Layer 985 can be provided on an insulating substrate or a semiconductor substrate including a variety of materials.

[0098] In the structure of one embodiment of the present invention, for example, layer 985 can be provided on a substrate containing silicon. That is, layer 985 can also be provided with a Si transistor (a transistor whose channel formation region contains silicon). In addition, in one embodiment of the present invention, for example, by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor in layer 985, a CMOS circuit (for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit) can be formed.

[0099] Each of layer 983 and layers 984[1] to 984[K] may include various materials such as conductors, semiconductors, and insulators. Furthermore, each of layer 983 and layers 984[1] to 984[K] may include various elements such as capacitors and transistors.

[0100] Furthermore, the semiconductor layer including the channel formation region of the transistor provided in layer 983 and the semiconductor layer including the channel formation region of the transistor provided in layers 984[1] to 984[K] may include the same material or different materials. Furthermore, the transistor provided in layer 983 and the transistor provided in layers 984[1] to 984[K] may have the same structure or different structures.

[0101] One embodiment of the present invention may have a structure in which an OS transistor (a transistor including an oxide semiconductor in a channel formation region) is provided in the layer 983 and the layers 984 [ 1 ] to 984 [K].

[0102] OS transistors have extremely low off-state current. Furthermore, even in high-temperature environments, the off-state current hardly increases, and the on-state current is not easily reduced. Consequently, for example, when a wiring electrically connected to one of the source and drain of an OS transistor is in a floating state (sometimes referred to as "floating"), the charge stored in that wiring can be retained for a long period of time. Therefore, in one embodiment of the present invention, for example, by forming a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.

[0103] In one embodiment of the present invention, the OS transistor may have a structure in which a planar transistor is provided in layer 983 and a vertical transistor (a transistor in which at least a portion of a semiconductor layer including a channel formation region is provided within an opening formed in an insulating layer) is provided in layers 984[1] to 984[K]. Note that the detailed structure of the vertical transistor will be described in detail in Figure 7A and Figure 7B etc.

[0104] Compared to planar transistors, vertical transistors can easily reduce the area they occupy (footprint). Furthermore, vertical transistors have a structure that makes it easy to reduce the channel length and increase the channel width, making it easy to reduce on-state resistance (increase on-state current). Therefore, in one embodiment of the present invention, for example, by forming a memory cell using a vertical transistor, the cell area (cell size) of the memory cell can be reduced.

[0105] Planar transistors can easily increase their channel length compared to vertical transistors, thus easily reducing short-channel effects such as drain-induced barrier lowering (DIBL). In other words, they can easily achieve transistors with high saturation (small changes in drain current with respect to drain voltage in the transistor's saturation region). Therefore, in one embodiment of the present invention, for example, by configuring a sense amplifier using planar transistors, the characteristics of the sense amplifier can be improved.

[0106] Alternatively, for example, vertical transistors may be provided in layer 983. Alternatively, for example, planar transistors may be provided in layers 984[1] to 984[K].

[0107] Although not shown, the electronic computer 900 may also include wiring layers between the layers 985, 983, and 984[1] to 984[K] as appropriate. For example, the wiring layers may include wiring for electrically connecting various elements to each other.

[0108] In addition, if Figure 2 As shown, the electronic computer 900 may include a plurality of layers 983 (layers 983[1] to 983[H] (H is an integer greater than or equal to 2)) and have a structure in which the layers 983[1] to 983[H] are stacked. Furthermore, the electronic computer 900 may include a plurality of layers 982 (layers 982[1] to 982[L] (L is an integer greater than or equal to 2)) and have a structure in which the layers 982[1] to 982[L] are stacked.

[0109] Figure 1C Schematic diagram illustrating an example of the configuration of the components included in the electronic computer 900. Figure 1A The components shown can be Figure 1B The layers shown are appropriately configured. Figure 1C 9, a calculation unit 911, a control unit 912, a scan flip-flop 915, and a backup memory 916 included in a processing unit 910 are shown as part of the components included in the electronic computer 900. In addition, a storage cell 925 and a sense amplifier 926 included in a storage unit 920 are also shown.

[0110] Figure 1C The electronic computer 900 shown includes layers 985, 983, and 984[1] to 984[K]. Figure 1C As shown, the operation unit 911, the control unit 912, the scan flip-flop 915, and the sense amplifier 926 are arranged in layer 985. Furthermore, although not shown, the control unit 930 and the control unit 922 included in the storage unit 920 are also arranged in layer 985. Alternatively, the sense amplifier 926 may be arranged, for example, between the operation unit 911 and the control unit 912. The backup memory 916 is arranged in layer 983, overlapping the scan flip-flop 915. The storage cell 925 is arranged in layers 984[1] to 984[K], overlapping the sense amplifier 926. Alternatively, the storage cell 925 may be provided, for example, in an overlapping manner on the operation unit 911 and the control unit 912. Alternatively, the storage cell 925 may be arranged, for example, in an overlapping manner on the backup memory 916.

[0111] In other words, we can also say Figure 1C The electronic computer 900 shown has a configuration in which a memory array unit 921 included in a storage unit 920 is disposed inside a processing unit 910. Alternatively, a control unit 922 may be disposed inside the processing unit 910.

[0112] By configuring in the above manner, for example, the ineffective space of layer 983 and layer 984[1] to layer 984[K] can be reduced to improve area efficiency. As a result, the surface density (recording density) of the memory array unit 921 can be increased. As a result, the storage capacity of the storage unit 920 included in the electronic computer 900 can be increased and the electronic computer 900 can be miniaturized. In addition, for example, the bus 971 between the processing unit 910 and the storage unit 920 can be shortened. As a result, the access time (the time required to write and read data) and the access energy (the energy consumed by writing and reading data) can be reduced. Therefore, the operating speed of the electronic computer 900 can be increased and the power consumption can be reduced.

[0113] Next, specific configuration examples of each of a semiconductor device that can be used for the register unit 914 , a semiconductor device that can be used for the memory block 923 , and a storage device that can be used for the storage unit 920 will be described.

[0114] Note that in the following description, the potential corresponding to binary data is defined as the high power supply potential VDD for binary data "1," and the low power supply potential VSS for binary data "0." Compared to potential VSS, potential VDD is at least higher than the threshold voltage of the transistor. Alternatively, potential VSS may be, for example, ground potential. Furthermore, the signal potential is either H or L. When potential H is applied to the gate of an n-channel transistor, the transistor turns on, while when applied to the gate of a p-channel transistor, the transistor turns off. When potential L is applied to the gate of an n-channel transistor, the transistor turns off, while when applied to the gate of a p-channel transistor, the transistor turns on. Potential H may be, for example, the same as potential VDD or a higher potential than potential VDD. Potential L may be, for example, the same as potential VSS or a lower potential than potential VSS.

[0115] Note that the potential H and the potential L do not need to be the same for each of the multiple signals. Each of the multiple signals may have a different potential H and potential L depending on the threshold voltage of the transistor to which the signal is supplied. For example, the signal supplied to the gate of the Si transistor in layer 985 and the signal supplied to the gate of the OS transistor in layers 983 and layers 984[1] to 984[K] may have different potentials H and L.

[0116] <Semiconductor Device Usable for Memory Section 920> A semiconductor device 710 according to one embodiment of the present invention will be described. For example, at least a portion of the semiconductor device 710 can be used in the above-mentioned Figure 1A The electronic computer 900 shown in FIG. For example, the memory block 923 included in the storage unit 920 can be used.

[0117] [Structure example] Figure 3 7 is a circuit diagram illustrating a structural example of the semiconductor device 710 .

[0118] Figure 3 The semiconductor device 710 shown includes a plurality of memory cells 741 and a sensing circuit 751 .

[0119] In one embodiment of the present invention, when the semiconductor device 710 is used in the memory block 923 included in the electronic computer 900, for example, the memory cell 741 corresponds to the memory cell 925, and the sensor circuit 751 corresponds to the sense amplifier 926. That is, for example, the memory cell 741 is arranged in layers 984[1] to 984[K], and the sensor circuit 751 is arranged in layer 985. Therefore, for example, a vertical OS transistor can be used for the memory cell 741, and a Si transistor can be used for the sensor circuit 751.

[0120] Note that in Figure 3 , eight memory cells 741 arranged in layer 984[1], eight memory cells 741 arranged in layer 984[2], and eight memory cells 741 arranged in layer 984[K] are typically shown.

[0121] Some of the memory cells 741 are electrically connected to the sensing circuit 751 via wiring RBL serving as a read bit line, and the remaining memory cells 741 are electrically connected to the sensing circuit 751 via wiring RBLB serving as a read bit line.

[0122] The sensor circuit 751 has the function of supplying a potential corresponding to the data to each of the wirings RBL and RBLB when writing data, and has the function of outputting a potential corresponding to the data based on the potential difference between the wirings RBL and RBLB when reading data.

[0123] Figure 11 It is an explanation Figure 3 FIG. 7 is a circuit diagram of a specific structural example of a semiconductor device 710. Figure 11 1 and 2. The figure typically shows two memory cells (memory cell 741[1,1] and memory cell 741[1,2]) arranged in layer 984[1] and electrically connected to wiring RBL, and two memory cells (memory cell 741[1,3] and memory cell 741[1,4]) electrically connected to wiring RBLB. Furthermore, two memory cells (memory cell 741[2,1] and memory cell 741[2,2]) arranged in layer 984[2] and electrically connected to wiring RBL, and two memory cells (memory cell 741[2,3] and memory cell 741[2,4]) electrically connected to wiring RBLB are also shown.

[0124] The sensing circuit 751 includes a switch circuit 752, a precharge circuit 753, a precharge circuit 754, an amplifier circuit 755, and a precharge circuit 756. Each of the switch circuit 752, the precharge circuit 753, the precharge circuit 754, the amplifier circuit 755, and the precharge circuit 756 is electrically connected to the wiring RBL and the wiring RBLB. The switch circuit 752 is electrically connected to the wiring DBL and the wiring DBLB. The sensing circuit 751 controls the writing and reading of data in the memory cell 741.

[0125] Switch circuit 752 has the function of establishing a conductive state or a non-conductive state between the wiring pair of wirings RBL and RBLB and the wiring pair of wirings DBL and DBLB, based on a signal supplied to wiring CSEL. Specifically, switch circuit 752 includes transistor M721 and transistor M722. One of the source and drain of transistor M721 is electrically connected to wiring RBL. The other of the source and drain of transistor M721 is electrically connected to wiring DBL. One of the source and drain of transistor M722 is electrically connected to wiring RBLB. The other of the source and drain of transistor M722 is electrically connected to wiring DBLB. The gate of transistor M721 and the gate of transistor M722 are electrically connected to wiring CSEL. Transistors M721 and M722 are n-channel transistors.

[0126] The precharge circuit 753 has the function of precharging the wirings RBL and RBLB to the potential supplied to the wiring VPRE based on the signal supplied to the wiring EQ. Specifically, the precharge circuit 753 includes a transistor M731, a transistor M732, and a transistor M733. One of the source and drain of transistor M731 is electrically connected to the wiring RBL. The other of the source and drain of transistor M731 is electrically connected to the wiring RBLB. One of the source and drain of transistor M732 is electrically connected to the wiring RBL. One of the source and drain of transistor M733 is electrically connected to the wiring RBLB. The other of the source and drain of transistor M732 and the other of the source and drain of transistor M733 are electrically connected to the wiring VPRE. The gates of transistor M731, transistor M732, and transistor M733 are electrically connected to the wiring EQ. Transistors M731, M732, and M733 are n-channel transistors.

[0127] The precharge circuit 754 has the function of precharging the wirings RBL and RBLB to the potential supplied to the wiring VPRE based on a signal supplied to the wiring EQB. Specifically, the precharge circuit 754 includes a transistor M741, a transistor M742, and a transistor M743. One of the source and drain of transistor M741 is electrically connected to the wiring RBL. The other of the source and drain of transistor M741 is electrically connected to the wiring RBLB. One of the source and drain of transistor M742 is electrically connected to the wiring RBL. One of the source and drain of transistor M743 is electrically connected to the wiring RBLB. The other of the source and drain of transistor M742 and the other of the source and drain of transistor M743 are electrically connected to the wiring VPRE. The gates of transistor M741, transistor M742, and transistor M743 are electrically connected to the wiring EQB. Transistors M741, M742, and M743 are p-channel transistors.

[0128] Amplifier circuit 755 has the function of supplying a predetermined potential to wiring SAP and wiring SAN, thereby outputting a potential corresponding to one of the binary data values ​​to wiring RBL and a potential corresponding to the other of the binary data values ​​to wiring RBLB. Specifically, amplifier circuit 755 includes transistor M751, transistor M752, transistor M753, and transistor M754. One of the source and drain of transistor M751 is electrically connected to wiring RBL. One of the source and drain of transistor M752 is electrically connected to wiring RBLB. One of the source and drain of transistor M753 is electrically connected to wiring RBL. One of the source and drain of transistor M754 is electrically connected to wiring RBLB. The other of the source and drain of transistor M751 and the other of the source and drain of transistor M752 are electrically connected to wiring SAP. The other of the source and drain of transistor M753 and the other of the source and drain of transistor M754 are electrically connected to wiring SAN. The gates of transistor M751 and transistor M753 are electrically connected to wiring RBLB. The gates of transistor M752 and transistor M754 are electrically connected to wiring RBL. Transistors M751 and M752 are p-channel transistors. Transistors M753 and M754 are n-channel transistors.

[0129] Precharge circuit 756 is electrically connected to wiring RBL and wiring RBLB. Precharge circuit 756 precharges wiring RBL to the potential supplied to wiring VPRE2 based on a signal supplied to wiring SW4. Furthermore, precharge circuit 756 precharges wiring RBLB to the potential supplied to wiring VPRE2 based on a signal supplied to wiring SW5. Specifically, precharge circuit 756 includes transistor M771 and transistor M772. One of the source and drain of transistor M771 is electrically connected to wiring RBL. One of the source and drain of transistor M772 is electrically connected to wiring RBLB. The other of the source and drain of transistor M771 and the other of the source and drain of transistor M772 are electrically connected to wiring VPRE2. The gate of transistor M771 is electrically connected to wiring SW4. The gate of transistor M772 is electrically connected to wiring SW5. Transistors M771 and M772 are p-channel transistors.

[0130] Here, when any one of the plurality of memory cells 741 is selected in the semiconductor device 710 and data is written to the memory cell 741, a signal may be supplied to the wiring WWL electrically connected to the memory cell 741. Figure 11 When writing data to the memory cell 741[1,1] arranged in the layer 984[1], it is sufficient to supply a potential H to the wiring WWL electrically connected to the memory cell 741[1,1] and to supply a potential L to the wiring WWL electrically connected to the other memory cells 741.

[0131] In addition, when any one of the plurality of memory cells 741 is selected in the semiconductor device 710 and data is read from the memory cell 741, a signal may be supplied to the wiring RWL electrically connected to the memory cell 741. Figure 11 When reading data from the memory cell 741[1, 1] configured in the layer 984[1], it is sufficient to supply a potential H to the wiring RWL electrically connected to the memory cell 741[1, 1] and to supply a potential L to the wiring RWL electrically connected to the other memory cells 741.

[0132] <Storage Unit Usable for Storage Section 920> A memory cell according to one embodiment of the present invention is described. Figure 1A The electronic computer 900 shown in FIG. 10 can be used as the storage unit 925 included in the storage unit 920, for example.

[0133] Figures 4A to 4D Each of these is a circuit diagram illustrating a structural example of a memory cell according to one embodiment of the present invention.

[0134] Figure 4A The illustrated memory cell 741a includes transistor 42, transistor 41, and capacitor 51. One of the source and drain of transistor 42 is electrically connected to the gate of transistor 41 and one terminal of capacitor 51. The other of the source and drain of transistor 42 is electrically connected to wiring WBL serving as a write bit line. The gate of transistor 42 is electrically connected to wiring WWL serving as a write word line. One of the source and drain of transistor 41 is electrically connected to wiring RBL serving as a read bit line. The other of the source and drain of transistor 41 is electrically connected to wiring RWL serving as a read word line. The other terminal of capacitor 51 is electrically connected to wiring CL. In some cases, the wiring electrically connected to one of the source and drain of transistor 42, the gate of transistor 41, and one terminal of capacitor 51 is referred to as wiring MN in the following descriptions.

[0135] The memory cell 741a can store binary data by making the potential corresponding to the amount of charge held in the wiring MN high or low correspond to "1" or "0." Furthermore, when writing data, the memory cell 741a can turn on the transistor 42 to supply the potential corresponding to the data from the wiring WBL to the wiring MN. Furthermore, when reading data, the memory cell 741a can turn on or off the transistor 41 according to the potential of the wiring MN to extract the potential corresponding to the data to the wiring RBL.

[0136] As the transistor 42 of one embodiment of the present invention, for example, an n-channel OS transistor can be used. Also, as the transistor 41, for example, an n-channel transistor can be used.

[0137] in addition, Figure 4A The structure shown in memory cell 741a that uses an OS transistor as transistor 42 is sometimes referred to as NOSRAM (registered trademark). NOSRAM stands for Nonvolatile Oxide Semiconductor RAM. NOSRAM uses OS transistors with extremely low off-state current, allowing for long-term data storage. Furthermore, since the write transistor (transistor 42) is different from the read transistor (transistor 41), data can be read non-destructively. Therefore, it can be used, for example, as a nonvolatile memory.

[0138] Figure 4B The storage unit 741b is shown as Figure 4A The memory cell 741b, a modification of the memory cell 741a shown, differs from the memory cell 741a in that the other of the source and drain of the transistor 42 is electrically connected to the wiring BL and one of the source and drain of the transistor 41 is electrically connected to the wiring BL.

[0139] Figure 4C The storage unit 741c shown is Figure 4A The modified example of the memory cell 741a shown is different from the memory cell 741a in that the other of the source and the drain of the transistor 41 is electrically connected to the wiring PL and the other terminal of the capacitor 51 is electrically connected to the wiring RWL.

[0140] Figure 4D The memory cell 741d is shown as Figure 4C The modified example of the memory cell 741c shown is different from the memory cell 741c in that a p-channel transistor is used as the transistor 41 in the memory cell 741d.

[0141] <Storage Device Usable for Storage Unit 741> Next, a specific structural example of a memory device that can be used for the memory cell 741 included in the semiconductor device according to one embodiment of the present invention will be described with reference to the drawings.

[0142] A memory device according to one embodiment of the present invention includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer.

[0143] In a memory device according to one embodiment of the present invention, a first transistor, a capacitor, and a second transistor are arranged overlapping one another. This reduces the area occupied by the memory device when viewed from a planar perspective. For example, when a memory device according to one embodiment of the present invention is used in a memory cell 741, the area occupied by the memory cell when viewed from a planar perspective can be reduced. Consequently, the memory cell can be miniaturized, thereby realizing a highly integrated semiconductor device.

[0144] In addition, in a memory device according to one embodiment of the present invention, a second transistor is stacked on a first transistor. Both the first transistor and the second transistor have a structure in which the source electrode and the drain electrode are overlapped and arranged at different heights relative to the substrate surface, and the drain current flows in the height direction (vertical direction) (the above-mentioned "vertical transistor"). As a result, compared with a transistor having a structure in which the source electrode and the drain electrode are arranged on the same plane (planar transistor), further miniaturization can be achieved. By including the transistor of the above-mentioned structure, the memory device according to one embodiment of the present invention can further achieve miniaturization and high integration of semiconductor devices.

[0145] Note that in the memory device according to one embodiment of the present invention, the first insulating layer is located between the source electrode and the drain electrode of the first transistor, and the second insulating layer is located between the source electrode and the drain electrode of the second transistor.

[0146] Furthermore, in the memory device according to one embodiment of the present invention, a partial component (gate electrode) of the first transistor is also used as a partial component (one of the source electrode and the drain electrode) of the second transistor.

[0147] That is, in the memory device according to one embodiment of the present invention, some components of the first transistor are also used as some components of the second transistor.

[0148] In addition, in a storage device according to one embodiment of the present invention, an insulating layer (third insulating layer) and a conductive layer constituting a portion of the capacitor are sequentially overlapped on the first transistor in a manner that includes a region overlapping with the gate electrode of the first transistor. In a capacitor included in a storage device according to one embodiment of the present invention, the gate electrode of the first transistor is used as one electrode, the insulating layer (third insulating layer) is used as a dielectric layer, and the conductive layer is used as the other electrode. In other words, in a storage device according to one embodiment of the present invention, an insulating layer (third insulating layer) and a conductive layer constituting a portion of the capacitor are provided in a manner that includes a region overlapping with the first transistor, and the gate electrode of the first transistor is also used as one electrode of the capacitor.

[0149] In addition, in a storage device according to one embodiment of the present invention, the side surface of the conductive layer (the conductive layer constituting a portion of the capacitor) and the side surface of a portion of the gate electrode of the second transistor (the portion embedded in the second insulating layer) are arranged opposite to each other via a portion of the second insulating layer, a portion of the semiconductor layer of the second transistor, and a portion of the gate insulating layer of the second transistor. Thus, in a storage device according to one embodiment of the present invention, the region between the conductive layer and a portion of the gate electrode of the second transistor (the portion embedded in the second insulating layer) can also be used as a capacitor. In other words, it can also be said that in a storage device according to one embodiment of the present invention, the gate electrode of the second transistor can also be used as an electrode of a capacitor. In addition, it can be said that the second insulating layer, the semiconductor layer of the second transistor, and the gate insulating layer of the second transistor in the region sandwiched by the conductive layer and a portion of the gate electrode of the second transistor (the portion embedded in the second insulating layer) can also be used as the dielectric layer of the capacitor.

[0150] That is, in the memory device according to one embodiment of the present invention, some components of the first transistor also serve as some components of the capacitor. Furthermore, some components of the second transistor also serve as some components of the capacitor.

[0151] As described above, a memory device according to one embodiment of the present invention can significantly reduce the number of steps compared to manufacturing the first transistor and the second transistor separately. Furthermore, compared to manufacturing the capacitor and the first transistor separately, the number of steps can be significantly reduced. Furthermore, compared to manufacturing the capacitor and the second transistor separately, the number of steps can be significantly reduced. Therefore, an inexpensive memory device can be realized. Furthermore, a method for manufacturing a memory device with a high yield can be provided.

[0152] Next, a specific configuration example of a storage device according to one embodiment of the present invention will be described.

[0153] <Storage Device Configuration Example 1> Figure 5A 1 is a plan view showing an example of the structure of a storage device according to one embodiment of the present invention. Figure 5A Some components such as the insulating layer are omitted. Some components are also omitted in the plan views shown later. Figure 5B It is along Figure 5A A cross-sectional view along the dashed line A1-A2 is shown. Figure 5C It is along Figure 5A A cross-sectional view along the dashed line A3-A4 is shown. Figure 6 It is along Figure 5A A cross-sectional view along the dashed line A5-A6 is shown.

[0154] The memory device according to one embodiment of the present invention includes a transistor 41 , a transistor 42 , a capacitor 51 , an insulating layer 103 a , and an insulating layer 103 b .

[0155] Insulating layer 103a is provided on insulating layer 101. Transistor 41 is provided on insulating layer 101 with a portion thereof embedded in insulating layer 103a. Part of the components of capacitor 51 are provided on transistor 41 with a region overlapping with transistor 41. Insulating layer 103b is provided to cover transistor 41 and capacitor 51. Transistor 42 is provided to overlap transistor 41 and capacitor 51 with a portion thereof embedded in insulating layer 103b.

[0156] Here, it is preferable that the insulating layer 101, the insulating layer 103a, and the insulating layer 103b all serve as interlayer insulating layers and are planarized. Note that the insulating layers serving as interlayer insulating layers do not necessarily need to be planarized.

[0157] The transistor 41 includes a conductive layer 111 a , a conductive layer 112 a , a semiconductor layer 113 a , an insulating layer 105 a , and a conductive layer 115 a .

[0158] The conductive layer 111a serves as one of a source electrode and a drain electrode of the transistor 41. The conductive layer 112a serves as the other of the source electrode and the drain electrode of the transistor 41. The insulating layer 105a serves as a gate insulating layer of the transistor 41. The conductive layer 115a serves as a gate electrode of the transistor 41.

[0159] Conductive layer 111a is provided on insulating layer 101, insulating layer 103a is provided on insulating layer 101 and conductive layer 111a, and conductive layer 112a is provided on insulating layer 103a. Conductive layer 111a and conductive layer 112a have a region overlapping each other with insulating layer 103a interposed therebetween. Figure 5A and Figure 5B In the example shown, the side end of conductive layer 111a is located inside the side end of conductive layer 112a that does not face opening 121a in the X direction. That is, the side end of conductive layer 112a that does not face opening 121a does not overlap with conductive layer 111a, but the side end of conductive layer 111a overlaps with conductive layer 112a. However, one embodiment of the present invention is not limited to this. For example, the side end of conductive layer 111a may be located outside the side end of conductive layer 112a that does not face opening 121a.

[0160] The insulating layer 103 a and the conductive layer 112 a include an opening 121 a that reaches the conductive layer 111 a . Figure 5A The example in which the shape of the opening 121a is circular when viewed from above is shown. By making the top surface shape (the outline shape when viewed from above) of the opening 121a circular, the processing accuracy when forming the opening 121a can be improved, allowing the formation of a fine opening 121a. Alternatively, the top surface shape of the opening 121a may be a polygon such as an ellipse or a quadrilateral, or a polygon with rounded corners.

[0161] Semiconductor layer 113a is provided to cover opening 121a, including a region located within opening 121a. Semiconductor layer 113a includes a region in contact with the top surface of conductive layer 112a, a region in contact with the side surfaces of conductive layer 112a within opening 121a, a region in contact with the side surfaces of insulating layer 103a within opening 121a, and a region in contact with the top surface of conductive layer 111a within opening 121a. Semiconductor layer 113a has a shape that follows the top surface of conductive layer 112a, the side surfaces of conductive layer 112a within opening 121a, the side surfaces of insulating layer 103a within opening 121a, and the top surface of conductive layer 111a within opening 121a. Consequently, semiconductor layer 113a has a recessed portion at a position overlapping opening 121a.

[0162] Note that in Figure 5BIn the embodiment, the side surface of the semiconductor layer 113a is substantially aligned with the side surface of the conductive layer 112a that does not face the opening 121a in the X direction. However, one embodiment of the present invention is not limited to this. For example, the side surface of the semiconductor layer 113a may be located outside or inside the side surface of the conductive layer 112a that does not face the opening 121a in the X direction.

[0163] However, the semiconductor layer 113a preferably covers the side end portion of the conductive layer 112a on the side of the opening 121a. Figure 5A and Figure 5B In the example shown in FIG, the side end of the semiconductor layer 113a extends to the outside of the opening 121a in the X direction and is roughly aligned with the side end of the conductive layer 112a that does not face the opening 121a. In other words, in the X direction, the lower end of the semiconductor layer 113a is roughly aligned with the upper end of the conductive layer 112a. In other words, this example shows that the entire semiconductor layer 113a overlaps with the conductive layer 112a or the opening 121a. In addition, in Figure 5A and Figure 5B In the example shown in FIG, the side edge of the semiconductor layer 113a is located outside the side edge of the conductive layer 111a in the X direction. In other words, this example shows an example in which a portion of the semiconductor layer 113a overlaps with the conductive layer 111a.

[0164] In this specification, the upper end portion refers to the uppermost portion of the side end portion, and the lower end portion refers to the lowermost portion of the side end portion. In other words, both the upper end portion and the lower end portion are part of the side end portion.

[0165] Note that although Figure 5B 、 Figure 5C and Figure 6 The semiconductor layer 113a has a single-layer structure, but one embodiment of the present invention is not limited thereto and the semiconductor layer 113a may have a stacked-layer structure of two or more layers.

[0166] The insulating layer 105a, serving as the gate insulating layer of the transistor 41, covers the opening 121a and is provided so as to have a region located within the opening 121a. The insulating layer 105a is provided on the semiconductor layer 113a, the conductive layer 112a, and the insulating layer 103a. The insulating layer 105a has a region in contact with the top surface of the semiconductor layer 113a, a region in contact with the side surfaces of the semiconductor layer 113a, a region in contact with the top surface of the conductive layer 112a, a region in contact with the side surfaces of the conductive layer 112a, and a region in contact with the top surface of the insulating layer 103a. The insulating layer 105a has a shape that extends along the top surface of the semiconductor layer 113a, the side surfaces of the semiconductor layer 113a, the top surface of the conductive layer 112a, the side surfaces of the conductive layer 112a, and the top surface of the insulating layer 103a. As a result, the insulating layer 105a has a recessed portion at a position overlapping the opening 121a.

[0167] The conductive layer 115a serving as the gate electrode of the transistor 41 is provided on the insulating layer 105a and has a region in contact with the top surface of the insulating layer 105a. The conductive layer 115a has a region overlapping with the semiconductor layer 113a via the insulating layer 105a. Here, the semiconductor layer 113a may have a structure in which the side surfaces and bottom surface of the conductive layer 115a are covered via the insulating layer 105a within the opening 121a. For example, within the opening 121a, the insulating layer 105a has a region in contact with the side surfaces of the semiconductor layer 113a, a region in contact with the top surface of the recess of the semiconductor layer 113a, a region in contact with the side surfaces of the conductive layer 115a, and a region in contact with the bottom surface of the conductive layer 115a.

[0168] As mentioned above, Figure 5B and Figure 5C The transistor 41 shown is a transistor in which a semiconductor layer (semiconductor layer 113a), a gate insulating layer (insulating layer 105a) and a gate electrode (conductive layer 115a) are arranged inside an opening (opening 121a) formed in an interlayer insulating layer (insulating layer 103a). In other words, in this transistor, the semiconductor layer is arranged so as to surround the gate electrode via the gate insulating layer when viewed from a plane. Thus, the channel length direction of the transistor 41 can be a direction along the side of the insulating layer 103a in the opening 121a when viewed from a cross section. Therefore, the channel length is not affected by the performance of the exposure device used when manufacturing the transistor 41, so the channel length can be made smaller than the limiting resolution of the exposure device. Thus, the transistor 41 can be miniaturized. In addition, for example, although Figure 5A Although the example shows that the entire opening 121a has a region overlapping with the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a, a portion of the opening 121a may not overlap with at least one of the conductive layer 111a, the semiconductor layer 113a, and the conductive layer 115a.

[0169] Transistor 41 is a so-called top-gate transistor having a gate electrode above semiconductor layer 113a. Furthermore, because the bottom surface of semiconductor layer 113a (the surface facing insulating layer 101) is in contact with the source and drain electrodes, it is also referred to as a TGBC (Top Gate Bottom Contact) transistor.

[0170] like Figure 5B and Figure 5CAs shown in FIG. 1 , a portion of the insulating layer 105a is located outside the opening 121a, that is, located on the conductive layer 112a and the insulating layer 103a. In this case, the insulating layer 105a preferably covers the side edges of the semiconductor layer 113a. This prevents short circuits between the conductive layer 115a and the semiconductor layer 113a. Furthermore, the insulating layer 105a preferably covers the side edges of the conductive layer 112a. This prevents short circuits between the conductive layer 115a and the conductive layer 112a.

[0171] In addition, if Figure 5B and Figure 5C As shown in FIG. 1 , a portion of the conductive layer 115a is located outside the opening 121a, that is, located on the conductive layer 112a and the insulating layer 103a. Figure 5B and Figure 5C The example in which the side edge of the conductive layer 115a is located inside the side edge of the semiconductor layer 113a is shown, but the present invention is not limited thereto and the side edge of the conductive layer 115a may be located outside the side edge of the semiconductor layer 113a.

[0172] Insulating layer 107a is provided in contact with the top surface of insulating layer 105a, the side surfaces of conductive layer 115a, and the top surface of conductive layer 115a. Insulating layer 135 is provided on insulating layer 107a. Conductive layer 141 is provided on insulating layer 135 so as to have a region overlapping with conductive layer 115a. Furthermore, conductive layer 141 is spaced apart from openings 121a provided in insulating layer 103a and conductive layer 112a when viewed from above.

[0173] Capacitor 51 includes conductive layer 115 a, conductive layer 141, a portion of insulating layer 107 a (a portion sandwiched between conductive layer 115 a and conductive layer 141), and a portion of insulating layer 135 (a portion sandwiched between conductive layer 115 a and conductive layer 141). In addition to the above, capacitor 51 includes a portion of conductive layer 115 b (a portion located within opening 121 b) serving as the gate electrode of transistor 42, the insulating layer 103 b on transistor 41 in a region sandwiched between the portion of conductive layer 115 b and conductive layer 141, the semiconductor layer 113 b serving as the semiconductor layer of transistor 42, and the insulating layer 105 b serving as the gate insulating layer of transistor 42.

[0174] Conductive layer 115 a serves as one electrode of capacitor 51. Conductive layer 141 serves as the other electrode of capacitor 51. A portion of insulating layer 107 a (a portion sandwiched between conductive layer 115 a and conductive layer 141) and a portion of insulating layer 135 (a portion sandwiched between conductive layer 115 a and conductive layer 141) serve as dielectric layers of capacitor 51.

[0175] In addition to the above, a portion of the conductive layer 115b (the portion located within the opening 121b) is also used as an electrode of the capacitor 51. The insulating layer 103b, the semiconductor layer 113b, and the insulating layer 105b in the region sandwiched between the conductive layer 141 and the portion of the conductive layer 115b can also be used as a dielectric layer of the capacitor 51.

[0176] That is, in the memory device of one embodiment of the present invention, the two portions between conductive layer 141 and conductive layer 115a and between conductive layer 141 and a portion of conductive layer 115b (the portion located within opening 121b) have regions that can function as capacitors, and these two portions can be considered as capacitors 51. When capacitor 51 has such a structure, even when conductive layer 141 has a fine top surface shape, the capacitance value required for the operation of the memory device of one embodiment of the present invention can be ensured by adjusting the thickness of conductive layer 141.

[0177] An insulating layer 103 b is provided over the transistor 41 and the capacitor 51 .

[0178] The insulating layer 107a serves as a dielectric layer of the capacitor 51 and has a function of suppressing diffusion of impurities into the transistor 41. For example, it has a function of suppressing diffusion of impurities into the semiconductor layer 113a.

[0179] As described above, the insulating layer 135 is used as a dielectric layer of the capacitor 51. For example, the insulating layer 135 preferably uses a material with a high dielectric constant, such as the so-called high-k material described in [Insulator] described later. By using a material with a high relative dielectric constant for the insulating layer 135, the capacitance value of the capacitor 51 can be increased. As a result, a storage device with a long data retention time can be realized. In addition, the data retention time becomes longer, and the frequency of the timed data rewriting (refresh operation) can be reduced, thereby realizing a storage device with low power consumption.

[0180] Furthermore, the insulating layer 135 may also be made of, for example, a ferroelectric material described in the "Insulator" section below. Using a ferroelectric material for the insulating layer 135 allows for a nonvolatile memory device. This eliminates the need for the aforementioned refresh operation, allowing for a memory device with lower power consumption.

[0181] Note that a portion of insulating layer 103b can also serve as the dielectric layer of container 51. As described above, insulating layer 103b can also serve as an interlayer insulating layer. Therefore, a material with a low relative dielectric constant, as described in [Insulator], is preferably used for insulating layer 103b. Using a material with a low relative dielectric constant for insulating layer 103b can reduce parasitic capacitance generated between wirings in the memory device. For the same reason, a material with a low relative dielectric constant is also preferably used for insulating layer 103a.

[0182] The transistor 42 includes a conductive layer 115 a , a conductive layer 112 b , a semiconductor layer 113 b , an insulating layer 105 b , and a conductive layer 115 b .

[0183] The conductive layer 115a serves as one of a source electrode and a drain electrode of the transistor 42. The conductive layer 112b serves as the other of the source electrode and the drain electrode of the transistor 42. The insulating layer 105b serves as a gate insulating layer of the transistor 42. The conductive layer 115b serves as a gate electrode of the transistor 42.

[0184] In addition, as described above, the conductive layer 115a also serves as the other of the source electrode and the drain electrode of the transistor 41. Figures 5A to 6 In the illustrated memory device, the conductive layer 115 a functions as both a gate electrode of the transistor 41 and a source electrode and a drain electrode of the transistor 42 .

[0185] The insulating layer 103b is provided on the conductive layer 115a. The conductive layer 112b is provided on the insulating layer 103b. The conductive layer 115a and the conductive layer 112b have a region overlapping with each other via the insulating layer 103b.

[0186] The conductive layer 112b, the insulating layer 103b, the insulating layer 135, and the insulating layer 107a have an opening 121b that reaches the conductive layer 115a. Figure 5A An example is shown in which the shape of the opening 121b is circular when viewed from a plane. In addition, the opening 121b may have the same shape as the opening 121a.

[0187] The structure of transistor 42 can be the same as that of transistor 41 except for the structure of one of the source electrode and the drain electrode. By replacing transistor 41, insulating layer 103a, insulating layer 105a, conductive layer 112a, semiconductor layer 113a, and conductive layer 115a with transistor 42, insulating layer 103b, insulating layer 105b, conductive layer 112b, semiconductor layer 113b, and conductive layer 115b, and replacing the names as needed, the structure of transistor 42 can be described with reference to the structure of transistor 41 except for the structure of one of the source electrode and the drain electrode.

[0188] In this specification and other documents, the insulating layer 103a and the insulating layer 103b are sometimes collectively referred to as the insulating layer 103. Furthermore, the insulating layer 105a and the insulating layer 105b are sometimes collectively referred to as the insulating layer 105. Furthermore, the insulating layer 107a and the insulating layer 107b are sometimes collectively referred to as the insulating layer 107. Furthermore, the conductive layer 112a and the conductive layer 112b are sometimes collectively referred to as the conductive layer 112. Furthermore, the semiconductor layer 113a and the semiconductor layer 113b are sometimes collectively referred to as the semiconductor layer 113. Furthermore, the conductive layer 115a and the conductive layer 115b are sometimes collectively referred to as the conductive layer 115. Furthermore, the opening 121a and the opening 121b are sometimes collectively referred to as the opening 121.

[0189] An insulating layer 107b is provided over the conductive layer 115b and the insulating layer 105b. The insulating layer 107b can be provided to cover the top and side surfaces of the conductive layer 115b. The insulating layer 107b has the function of suppressing the diffusion of impurities into the transistor 42. For example, it has the function of suppressing the diffusion of impurities into the semiconductor layer 113b.

[0190] As described above, in a memory device according to one embodiment of the present invention, transistor 41, capacitor 51, and transistor 42 are stacked one on top of the other. Furthermore, in each of transistors 41 and 42, a semiconductor layer, a gate insulating layer, and a gate electrode are provided within an opening formed in an interlayer insulating layer. One of a source electrode and a drain electrode is provided below the opening, and the other of the source electrode and drain electrode is provided on the interlayer insulating layer. This reduces the footprint of the memory device when viewed from above. Consequently, miniaturization of the memory device is possible. Therefore, according to one embodiment of the present invention, a memory device capable of achieving high integration can be provided.

[0191] In the memory device according to one embodiment of the present invention, some components of transistor 41 are also used as some components of transistor 42. Furthermore, some components of transistor 41 are also used as some components of capacitor 51. Furthermore, some components of transistor 42 are also used as some components of capacitor 51.

[0192] Thus, compared to the case where transistor 41 and transistor 42 are manufactured separately, the memory device of one embodiment of the present invention can significantly reduce the number of steps. Furthermore, compared to the case where capacitor 51 and transistor 41 are manufactured separately, the number of steps can be significantly reduced. Furthermore, compared to the case where capacitor 51 and transistor 42 are manufactured separately, the number of steps can be significantly reduced. Therefore, an inexpensive memory device can be realized. Furthermore, a method for manufacturing a memory device with a high yield can be provided.

[0193] Note that in Figures 5B to 6In the cross-sectional views shown, the boundaries between layers may not be clearly identified. For example, the boundary between two insulating layers in contact with each other may not be clearly identified. Furthermore, the boundary between two conductive layers in contact with each other may not be clearly identified. Furthermore, the boundary between two semiconductor layers in contact with each other may not be clearly identified.

[0194] Figure 7A yes Figure 5C The transistor 41 and its vicinity are shown in an enlarged view. Figure 7B Show Figure 7A The XY plane of the transistor is shown. Note that Figure 7B The conductive layer 111a is not shown in the figure. By replacing the conductive layer 111a with the conductive layer 115a, the conductive layer 111a can be replaced with the conductive layer 115a. Figure 7A The structure shown is applied to transistor 42 . Figure 7B The structure shown can be applied to both the transistor 41 and the transistor 42 .

[0195] like Figure 7A As shown, the semiconductor layer 113 includes a region 113 i and regions 113 na and 113 nb provided so as to sandwich the region 113 i .

[0196] The region 113na is a region of the semiconductor layer 113 in contact with the conductive layer 111a. At least a portion of the region 113na is used as one of the source region and the drain region of the transistor. The region 113nb is a region of the semiconductor layer 113 in contact with the conductive layer 112. At least a portion of the region 113nb is used as the other of the source region and the drain region of the transistor. Figure 7B As shown, the conductive layer 112 is in contact with the entire periphery of the semiconductor layer 113. Therefore, the other of the source region and the drain region of the transistor can be formed over the entire periphery of the portion of the semiconductor layer 113 formed at the same height as the conductive layer 112.

[0197] Region 113i is a region between region 113na and region 113nb of the semiconductor layer 113. At least a portion of region 113i serves as a channel formation region of the transistor. In other words, the channel formation region of the transistor is located in the region between conductive layer 111a and conductive layer 112 in the semiconductor layer 113. Alternatively, the channel formation region of the transistor can be considered to be located in the region of the semiconductor layer 113 that is in contact with the insulating layer 103 or in the vicinity thereof.

[0198] The channel length of the transistor is the distance between the source region and the drain region. In other words, the channel length of the transistor can be determined by the thickness of the insulating layer 103 on the conductive layer 111a. Figure 7A, the solid double arrow in FIG. The channel length L of the transistor is indicated. When viewed in cross section, the channel length L is the distance between the end of the region where the semiconductor layer 113 contacts the conductive layer 111a and the end of the region where the semiconductor layer 113 contacts the conductive layer 112. In other words, the channel length L corresponds to the length of the side surface of the insulating layer 103 on the side of the opening 121 when viewed in cross section.

[0199] In a planar transistor, the channel length is set, for example, according to the exposure limit of the photolithography method, but in the present invention, the channel length is set according to the thickness of the insulating layer 103. Therefore, the channel length of the transistor can be set to be very fine, that is, below the exposure limit of the photolithography (for example, 1 nm or more and 60 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 40 nm or less, 5 nm or more and 30 nm or less, 5 nm or more and 20 nm or less, or 5 nm or more and 10 nm or less). As a result, the on-state current of the transistor increases, and the frequency characteristics can be improved. Therefore, a semiconductor device with a fast operating speed can be provided. For example, the read speed and write speed of the memory cell can be improved.

[0200] Here, the transistor using metal oxide for the semiconductor layer has a higher resistance to the short channel effect than the transistor using silicon for the semiconductor layer, and the details will be described later. Figure 7A and Figure 7B The channel length of the transistor having the structure shown is shorter than that of the planar transistor. Figure 7A and Figure 7B In the structure shown, a metal oxide is preferably used for the semiconductor layer 113. However, a material other than a metal oxide, such as silicon, may be used for the semiconductor layer 113.

[0201] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 121. Therefore, compared to a planar transistor in which the channel formation region, source region, and drain region are separately provided on the XY plane, the area occupied by the transistor can be reduced. This allows for a highly integrated memory device, thereby increasing the memory capacity per unit area.

[0202] like Figure 7BAs shown, the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged in a concentric circle shape on the XY plane including the channel formation region of the semiconductor layer 113. Therefore, the side surface of the conductive layer 115 arranged in the center is opposite to the side surface of the semiconductor layer 113 via the insulating layer 105. In other words, when viewed from a plane, the entire inner periphery of the semiconductor layer 113 is the channel formation region. In this case, for example, the channel width of the transistor is determined by the outer periphery of the semiconductor layer 113. In other words, it can be said that the channel width of the transistor is determined by the maximum width of the opening 121 (the diameter when the opening 121 is circular when viewed from a plane). Figure 7A and Figure 7B The maximum width D of the opening 121 is shown by a double-dashed arrow. Figure 7B The double-arrow dot-dash line indicates the channel width W of the transistor. By increasing the maximum width D of the opening 121 , the channel width is increased, and the on-state current can be increased.

[0203] The maximum width D of opening 121 is preferably, for example, 5 nm to 100 nm, 10 nm to 60 nm, 20 nm to 50 nm, 20 nm to 40 nm, or 20 nm to 30 nm. This allows for a highly integrated memory device. As described above, when opening 121 is circular when viewed from above, the maximum width D of opening 121 corresponds to the diameter of opening 121, and the channel width W can be calculated as "D × π."

[0204] In addition, in a memory device according to one embodiment of the present invention, the channel length L of the transistor is preferably at least smaller than the channel width W of the transistor. The channel length L of the transistor according to one embodiment of the present invention is not less than 0.1 times and not more than 0.99 times, and preferably not less than 0.5 times and not more than 0.8 times, the channel width W of the transistor. By adopting this structure, a transistor with excellent electrical characteristics and high reliability can be realized.

[0205] Since the semiconductor layer 113, the insulating layer 105, and the conductive layer 115 are arranged concentrically, the distance between the conductive layer 115 and the semiconductor layer 113 is substantially uniform. Therefore, a gate electric field can be applied substantially uniformly from the conductive layer 115 to the semiconductor layer 113.

[0206] The sidewalls of the opening 121 are preferably perpendicular to the top surface of the conductive layer 111a. By adopting this structure, miniaturization or high integration of the storage device can be achieved. In addition, the sidewalls of the opening 121 can also be tapered.

[0207] <Storage Device Configuration Example 2> Figures 8A to 8C Shows different from Figures 5A to 5C FIG. 1 shows an example of a structure of a storage device according to one embodiment of the present invention. Figure 8A It is a plan view showing a structural example of a part of a storage device. Figure 8B It is along Figure 8A The cross-sectional view along the dotted line A1-A2 is shown, Figure 8C It is along Figure 8A The cross-sectional view of the dotted line A3-A4 shown in FIG. Figure 8A The cross-sectional view along the dotted line A5-A6 shown in FIG. Figure 6 .

[0208] Figures 8A to 8C The storage device shown is Figures 5A to 5C The storage device shown differs in the structure of capacitor 51 .

[0209] Specifically, in Figures 8A to 8C In the storage device shown, the end portion of the capacitor 51 that does not face the opening 121b is located Figures 5A to 5C The storage device is shown outside of this end.

[0210] exist Figures 8A to 8C In capacitor 51 included in the illustrated memory device, the end of conductive layer 141 that does not face opening 121b extends beyond the end of conductive layer 115a. Conductive layer 141 has a region that overlaps not only with conductive layer 115a but also with conductive layer 112a and insulating layer 103a. Therefore, conductive layer 141 has regions that overlap with the top surface of conductive layer 115a, the side surfaces of conductive layer 115a, the top surface of conductive layer 112a, the side surfaces of conductive layer 112a, and the top surface of insulating layer 103a, via insulating layer 107a and insulating layer 135.

[0211] In this case, in addition to Figures 5A to 5C In addition to the structure of capacitor 51 shown, the region sandwiched between conductive layer 141 and the side surface of conductive layer 115a is also used as part of capacitor 51. In addition, the region sandwiched between conductive layer 141 and the top surface of conductive layer 112a located outside conductive layer 115a is also used as part of capacitor 51. In addition, the region sandwiched between conductive layer 141 and the side surface of conductive layer 112a is also used as part of capacitor 51.

[0212] therefore, Figures 8A to 8C The capacitor 51 shown may have a Figures 5A to 5C The capacitor 51 shown has a larger capacitance value. Figures 8A to 8C The storage device case shown can be implemented with the use of Figures 5A to 5C The case of the memory device shown has a longer data retention time and lower power consumption than the memory device.

[0213] in addition, Figures 8A to 8CThe capacitor 51 is shown with Figures 5A to 5C The capacitor 51 shown is larger than that when viewed from the plane, so it is Figures 5A to 5C The capacitor 51 shown does not require high processing accuracy for the conductive layer 141. This can improve the yield of the memory device.

[0214] exist Figures 8A to 8C The storage device shown above can refer to Figures 5A to 5C Description of the storage device shown.

[0215] <Storage Device Configuration Example 3> Figures 9A to 9C An example of a structure of a storage device according to one embodiment of the present invention that is different from the structure described above is shown. Figure 9A It is a plan view showing a structural example of a part of a storage device. Figure 9B It is shown along Figure 9A The cross-sectional view along the dotted line A1-A2 is shown, Figure 9C It is shown along Figure 9A The cross-sectional view of the dotted line A3-A4 shown in FIG. Figure 9A The cross-sectional view along the dotted line A5-A6 shown in FIG. Figure 6 .

[0216] Figures 9A to 9C The structure of the capacitor 51 of the illustrated memory device is different from that of the memory device described above.

[0217] Specifically, in Figures 5A to 5C In the memory device shown in FIG. 1 , the conductive layer 141 is formed only on the top surface of one side end portion (A1 side) of the conductive layer 115a. Figures 9A to 9C In the illustrated memory device, the conductive layer 141 is also formed on the top surface of the other end portion (A2 side) of the conductive layer 115a.

[0218] exist Figures 9A to 9C In the memory device shown, the two conductive layers 141 are arranged symmetrically with the dot-dash line A3-A4 as an axis when viewed from a plane. Figures 9A to 9C The storage device shown includes two Figures 5A to 5C The storage device shown comprises a capacitor 51 .

[0219] Through this structure, Figures 9A to 9C The capacitor 51 shown may have Figures 5A to 5C The capacitance value is twice that of capacitor 51 shown. Figures 5A to 5C The storage device shown is compared to Figures 9A to 9C The memory device shown can realize a memory device with longer data retention time and lower power consumption.

[0220] exist Figures 9A to 9C The storage device shown above can refer to Figures 5A to 5C Description of the storage device shown.

[0221] <Storage Device Configuration Example 4> Figures 10A to 10C An example of a structure of a storage device according to one embodiment of the present invention that is different from the structure described above is shown. Figure 10A It is a plan view showing a structural example of a part of a storage device. Figure 10B It is shown along Figure 10A The cross-sectional view along the dotted line A1-A2 is shown, Figure 10C It is shown along Figure 10A The cross-sectional view of the dotted line A3-A4 shown in FIG. Figure 10A The cross-sectional view along the dotted line A5-A6 shown in FIG. Figure 6 .

[0222] Figures 10A to 10C The structure of the capacitor 51 of the illustrated memory device is different from that of the memory device described above.

[0223] Specifically, the memory device described above has a structure in which the conductive layer 141 overlaps a portion of the conductive layer 115a when viewed from a planar perspective. Figures 10A to 10C The illustrated memory device has a structure in which the conductive layer 141 overlaps the entire top surface of the conductive layer 115a in a manner surrounding the opening 121b when viewed from a planar perspective.

[0224] exist Figures 10A to 10C In the memory device shown in FIG. 1 , the conductive layer 141 includes an opening 127 in a region overlapping the opening 121 b when viewed from a plane. The opening 127 is arranged so as to include the opening 121 b. In other words, Figures 10A to 10C In the memory device shown, the conductive layer 141 overlaps the entire top surface of the conductive layer 115 a except for the region overlapping the opening 127 when viewed from above.

[0225] Note that in Figure 10A In the example shown, the shape of the opening 127 is circular when viewed from a plane, but is not limited thereto. For example, the top surface of the opening 127 may also be an ellipse, a quadrilateral, or a polygon with rounded corners. Figure 10A In the example shown, the top surface shape of the opening 127 and the top surface shapes of the openings 121a and 121b are all circular, but the present invention is not limited thereto and the top surface shape of the opening 127 may be different from the top surface shapes of the openings 121a and 121b.

[0226] Through this structure, Figures 10A to 10CThe capacitor 51 shown may have a larger capacitance value than the capacitor 51 included in the storage device shown above. Figures 10A to 10C The memory device shown may be a memory device that retains data for a longer time and consumes less power than the memory device shown above.

[0227] exist Figures 10A to 10C The storage device shown above can refer to Figures 5A to 5C Description of the storage device shown.

[0228] Next, components of transistors (transistor 41 and transistor 42 ) included in the memory device according to one embodiment of the present invention will be described.

[0229] [Components of a transistor] As the semiconductor layer 113 (semiconductor layer 113a, semiconductor layer 113b), a single layer or a stack of metal oxides described in [Metal Oxide] below can be used. Alternatively, as the semiconductor layer 113, a single layer or a stack of materials such as silicon described in [Other Semiconductor Materials] below can be used.

[0230] When a metal oxide is used for the semiconductor layer 113, specifically, a metal oxide having a composition of In:M:Zn = 1:3:2 [atomic ratio] or approximately thereabouts, In:M:Zn = 1:3:4 [atomic ratio] or approximately thereabouts, In:M:Zn = 1:1:0.5 [atomic ratio] or approximately thereabouts, In:M:Zn = 1:1:1 [atomic ratio] or approximately thereabouts, In:M:Zn = 1:1:1.2 [atomic ratio] or approximately thereabouts, In:M:Zn = 1:1:2 [atomic ratio] or approximately thereabouts, or In:M:Zn = 4:2:3 [atomic ratio] or approximately thereabouts can be used as the semiconductor layer 113. The composition range of the metal oxide is preferably within ±30% of the desired atomic ratio. Gallium is preferably used as the element M.

[0231] Furthermore, when the metal oxide is deposited by sputtering, the above-mentioned atomic ratio is not limited to the atomic ratio of the deposited metal oxide, but may also be the atomic ratio of the sputtering target used for the deposition of the metal oxide.

[0232] The composition of the metal oxide used for the semiconductor layer 113 can be analyzed using, for example, energy dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma atomic emission spectrometry (ICP-AES). Alternatively, a combination of the above methods can be used for analysis. Note that the actual content of an element with a low content may be different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0233] The metal oxide can be appropriately formed by atomic layer deposition (ALD: Atomic Layer Deposition) method.

[0234] Alternatively, the metal oxide may be formed by sputtering or chemical vapor deposition (CVD: Chemical Vapor Deposition) method.

[0235] Note that when forming a metal oxide by sputtering, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content of the formed metal oxide may be reduced to approximately 50% of that of the sputtering target.

[0236] The metal oxide used for the semiconductor layer 113 is preferably crystalline. Examples of crystalline oxide semiconductors include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used for the semiconductor layer 113, with CAAC-OS being particularly preferred.

[0237] Preferably, the CAAC-OS layer has multiple layered crystal regions with their c-axes oriented in the normal direction of the surface on which they are formed. For example, the semiconductor layer 113 preferably has layered crystals that are roughly parallel to the sidewalls of the openings 121 (openings 121a and 121b), and in particular, layered crystals that are roughly parallel to the side surfaces of the insulating layer 103 (insulating layers 103a and 103b). By adopting this structure, the layered crystals of the semiconductor layer 113 are roughly parallel to the channel length direction of the transistor, thereby increasing the on-state current of the transistor.

[0238] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after formation at a temperature where the metal oxide does not undergo polycrystallization (e.g., 400°C to 600°C), CAAC-OS can be given a dense structure with even higher crystallinity. By further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0239] Furthermore, CAAC-OS rarely has clear grain boundaries, making it less likely to cause a drop in electron mobility due to these boundaries. Consequently, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS exhibit heat resistance and high reliability.

[0240] Furthermore, when a crystalline oxide such as CAAC-OS is used as the semiconductor layer 113, oxygen extraction from the semiconductor layer 113 by the source electrode or the drain electrode can be suppressed. Therefore, even during heat treatment, oxygen extraction from the semiconductor layer 113 can be suppressed, and the transistor is stable even to the high temperatures (so-called thermal budget) encountered during the manufacturing process.

[0241] The crystallinity of the semiconductor layer 113 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED), or a combination of a plurality of these methods.

[0242] The thickness of the semiconductor layer 113 is preferably, for example, from 1 nm to 20 nm, from 3 nm to 15 nm, from 5 nm to 12 nm, or from 5 nm to 10 nm. Thus, even in an opening 121 having a small diameter, the semiconductor layer 113 can be formed with high coverage on the sidewalls of the opening 121, thereby improving the manufacturing yield of the transistor.

[0243] Note that in Figure 5B 、 Figure 5C and Figure 7A Although the semiconductor layer 113 is shown as a single layer in the figures, the present invention is not limited thereto. The semiconductor layer 113 may also have a stacked structure of multiple oxide layers having different chemical compositions. For example, a structure in which multiple types of the above-mentioned metal oxides are appropriately stacked may be employed.

[0244] The insulating layer 105 (insulating layer 105a, insulating layer 105b) serving as a gate insulating layer can be a single layer or a stack of insulators described in "Insulator" below. For example, silicon oxide or silicon oxynitride can be used as the insulating layer 105. Silicon oxide and silicon oxynitride are preferred because of their thermal stability.

[0245] Alternatively, a material having a high relative dielectric constant, so-called high-k material, as described in "Insulator" below, may be used as the insulating layer 105. For example, hafnium oxide or aluminum oxide may be used.

[0246] For example, the thickness of the insulating layer 105 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. At least a portion of the insulating layer 105 preferably includes a region having the aforementioned thickness. Thus, even when the opening 121 has a fine diameter, the insulating layer 105 can be formed with high coverage on the sidewalls of the opening 121, thereby improving the manufacturing yield of the transistor.

[0247] The concentration of impurities such as water and hydrogen in the insulating layer 105 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0248] exist Figure 5B 、 Figure 5C and Figure 7A In the figures, the insulating layer 105 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 105 may also have a stacked structure.

[0249] The conductive layer 115 (conductive layer 115a, conductive layer 115b) serving as a gate electrode can be a single layer or a stack of any of the conductive materials described in "Conductor" below. For example, a highly conductive material such as tungsten, aluminum, or copper can be used as the conductive layer 115.

[0250] As the conductive layer 115, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of suppressing the diffusion of oxygen. Examples of such conductive materials include conductive materials containing nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials containing oxygen (e.g., ruthenium oxide). This can suppress the reduction in the conductivity of the conductive layer 115. Alternatively, as the conductive layer 115, a semiconductor with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide can be used.

[0251] Note that in Figure 5B 、 Figure 5C and Figure 7A In the figures, the conductive layer 115 is shown as a single layer, but the present invention is not limited thereto. The conductive layer 115 may also have a stacked structure.

[0252] As the conductive layer 111a, a single layer or a stack of conductive materials described in [Conductor] described later can be used. As the conductive layer 111a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has the function of suppressing the diffusion of oxygen. For example, titanium nitride or tantalum nitride can be used. In addition, for example, a structure in which tantalum nitride is stacked on titanium nitride can also be used. In this case, titanium nitride is in contact with the insulating layer 101 and the insulating layer 103a, and tantalum nitride is in contact with the semiconductor layer 113a. By adopting this structure, excessive oxidation of the conductive layer 111a due to the semiconductor layer 113a can be suppressed. In addition, when oxide insulators are used as the insulating layer 101 and the insulating layer 103a, excessive oxidation of the conductive layer 111a due to the above-mentioned insulating layer can be suppressed. Alternatively, the conductive layer 111a can also have a structure in which tungsten is stacked on titanium nitride, for example.

[0253] Since the conductive layer 111a has a region in contact with the semiconductor layer 113a, it is preferably formed using an oxygen-containing conductive material as described in the "Conductor" section below. Using an oxygen-containing conductive material as the conductive layer 111a allows the conductive layer 111a to maintain conductivity even when it absorbs oxygen. For example, a single layer or a stack of indium tin oxide (ITO), silicon-doped indium tin oxide (ITSO), or indium zinc oxide (IZO (registered trademark)) can be used as the conductive layer 111a.

[0254] exist Figure 5B 、 Figure 5C and Figure 7A , etc., illustrate a structure in which the top surface of the conductive layer 111a is flat, but the present invention is not limited thereto. For example, a recessed portion overlapping the opening 121a may be formed on the top surface of the conductive layer 111a. By forming at least a portion of the semiconductor layer 113a, the insulating layer 105a, and the conductive layer 115a so as to fill this recessed portion, the gate electric field of the conductive layer 115a can be easily applied to the conductive layer 111a near the semiconductor layer 113a.

[0255] Similarly, the top surface of the conductive layer 115a does not need to be flat. For example, a recessed portion overlapping the opening 121b may be formed on the top surface of the conductive layer 115a. By forming at least a portion of the semiconductor layer 113b, the insulating layer 105b, and the conductive layer 115b so as to fill the recessed portion, the gate electric field of the conductive layer 115b can be easily applied to the conductive layer 115a near the semiconductor layer 113b.

[0256] The conductive layer 112 (conductive layer 112a, conductive layer 112b) can be a single layer or a stack of conductive materials described in "Conductor" below. For example, a highly conductive material such as tungsten, aluminum, or copper can be used as the conductive layer 112.

[0257] As with the conductive layers 111a and 115, the conductive layer 112 is preferably made of a conductive material that is not easily oxidized or a conductive material that inhibits oxygen diffusion. For example, titanium nitride or tantalum nitride can be used. This structure can prevent excessive oxidation of the conductive layer 112 by the semiconductor layer 113. Furthermore, as with the conductive layer 115, a highly conductive semiconductor, such as polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide can be used for the conductive layer 112.

[0258] For example, a structure in which tungsten is stacked on titanium nitride may be employed. By stacking tungsten in this manner, the conductivity of the conductive layer 112 can be improved.

[0259] When the conductive layer 112 has a stacked structure of a first conductive layer and a second conductive layer, for example, the first conductive layer may be formed using a highly conductive material, and the second conductive layer may be formed using a conductive material containing oxygen. By using a conductive material containing oxygen for the second conductive layer, where the area of ​​the region in contact with the insulating layer 105 is larger than that of the first conductive layer, diffusion of oxygen from the insulating layer 105 into the first conductive layer of the conductive layer 112 can be suppressed. For example, it is preferable to use tungsten for the first conductive layer of the conductive layer 112, and to use silicon-added indium tin oxide for the second conductive layer of the conductive layer 112.

[0260] When semiconductor layer 113a is in contact with conductive layer 111a (or semiconductor layer 113b is in contact with conductive layer 115a), a metal compound or oxygen vacancies are formed in semiconductor layer 113 (semiconductor layer 113a, semiconductor layer 113b), thereby reducing the resistance of region 113na of semiconductor layer 113. By reducing the resistance of semiconductor layer 113a in contact with conductive layer 111a (or semiconductor layer 113b in contact with conductive layer 115a), the contact resistance between semiconductor layer 113a and conductive layer 111a (or the contact resistance between semiconductor layer 113b and conductive layer 115a) can be reduced. Similarly, when semiconductor layer 113 is in contact with conductive layer 112, the resistance of region 113nb of semiconductor layer 113 is reduced. Therefore, the contact resistance between semiconductor layer 113 and conductive layer 112 can be reduced.

[0261] The insulating layer 101 and the insulating layer 103 (insulating layer 103a, insulating layer 103b) used as the interlayer insulating layer preferably have a low relative dielectric constant. By using a material with a low relative dielectric constant as the interlayer insulating layer, parasitic capacitance generated between wirings can be reduced. As the insulating layer 101 and the insulating layer 103, a single layer or a stack of insulators containing a material with a low relative dielectric constant, as described in the "Insulator" section below, can be used. In particular, silicon oxide and silicon oxynitride are preferred due to their thermal stability.

[0262] The concentration of impurities such as water and hydrogen in the insulating layer 101 and the insulating layer 103 is preferably reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the semiconductor layer 113.

[0263] The insulating layer 103 disposed near the channel formation region of the semiconductor layer 113 preferably contains oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen). By heat-treating the insulating layer 103 containing excess oxygen, oxygen is supplied from the insulating layer 103 to the channel formation region of the semiconductor layer 113, thereby reducing oxygen vacancies in the semiconductor layer 113 and defects (hereinafter sometimes referred to as V O H). As a result, the electrical characteristics of the transistor can be stabilized and the reliability can be improved.

[0264] An insulator having the function of capturing or fixing hydrogen, as described in the "Insulator" section below, can be used as the insulating layer 103. By adopting such a structure, hydrogen in the semiconductor layer 113 can be captured or fixed, thereby reducing the hydrogen concentration in the semiconductor layer 113. For example, magnesium oxide or aluminum oxide can be used as the insulating layer 103.

[0265] exist Figure 5B 、 Figure 5C and Figure 7A In the figures, the insulating layer 103 is shown as a single layer, but the present invention is not limited thereto. The insulating layer 103 may also have a stacked-layer structure.

[0266] As the insulating layer 107 (insulating layer 107a, insulating layer 107b), an insulator having a hydrogen barrier property, as described in "Insulator" below, is preferably used. This prevents hydrogen from diffusing from outside the transistor through the insulating layer 105 into the semiconductor layer 113. Silicon nitride films and silicon oxynitride films are suitable for the insulating layer 107 because they rarely release impurities (e.g., water and hydrogen) and are not easily permeable to oxygen and hydrogen.

[0267] As the insulating layer 107, an insulator having the function of capturing or fixing hydrogen, as described in the "Insulator" section below, is preferably used. This structure suppresses the diffusion of hydrogen from above the insulating layer 107 into the semiconductor layer 113, and hydrogen in the semiconductor layer 113 is captured or fixed, thereby reducing the hydrogen concentration in the semiconductor layer 113. As the insulating layer 107, magnesium oxide, aluminum oxide, hafnium oxide, or the like can be used. Alternatively, for example, a stacked film of aluminum oxide and silicon nitride on the aluminum oxide can be used as the insulating layer 107.

[0268] Note that although Figure 5B 、 Figure 5C and Figure 7A , etc., shows a structure in which the insulating layer 107 is formed on the top surface of the transistor, but the present invention is not limited to this. For example, the insulating layer 107 or an insulating layer having the same function or material as the insulating layer 107 may be formed on the side and bottom surfaces of the transistor, so that the transistor is surrounded by the insulating layer 107. Alternatively, the insulating layer 107 may be formed on the top, side, and bottom surfaces of the transistor 41 and the transistor 42, so that the insulating layer 107 surrounds the transistor 41 and the transistor 42. By adopting this structure, impurities (for example, water and hydrogen) can be suppressed from entering the interior of the transistor 41 and the transistor 42.

[0269] Next, components of a capacitor (capacitor 51 ) included in a storage device according to one embodiment of the present invention will be described.

[0270] [Components of a capacitor] The conductive layer 115a and the conductive layer 141 can be formed using a single layer or a stack of conductive materials described in the "Conductor" section below. For example, a highly conductive material such as tungsten, aluminum, or copper can be used for the conductive layer 115a and the conductive layer 141. Using such a highly conductive material can improve the conductivity of the conductive layer 115a and the conductive layer 141.

[0271] The conductive layer 115a and the conductive layer 141 are preferably made of a single layer or a stack of conductive materials that are not easily oxidized or have the function of suppressing the diffusion of oxygen. For example, indium tin oxide with added titanium nitride or silicon may be used. Alternatively, for example, a structure in which titanium nitride is stacked on tungsten may be used. Alternatively, for example, a structure in which tungsten is stacked on a first titanium nitride and a second titanium nitride is stacked on the tungsten may be used. By adopting such a structure, when an oxide insulator is used as the insulating layer 135, oxidation of the conductive layer 115a due to the insulating layer 135 can be suppressed. Furthermore, when an oxide insulator is used as the insulating layer 103b, oxidation of the conductive layer 141 due to the insulating layer 103b can be suppressed. Furthermore, a semiconductor with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or a silicide such as nickel silicide may be used as the conductive layer 115a and the conductive layer 141.

[0272] The insulating layer 107a is preferably made of the above-mentioned insulator having a barrier property against hydrogen. In addition, an insulator having a function of capturing or fixing hydrogen is preferably used.

[0273] A material with a high relative dielectric constant, so-called high-k material, as described below in the section "Insulators," is preferably used as insulating layer 135. Using a high-k material as insulating layer 135 allows insulating layer 135 to be thickened to a level sufficient to suppress leakage current and ensure sufficient capacitance for capacitor 51.

[0274] The insulating layer 135 preferably uses an insulator composed of a high-k material in a stacked manner, preferably using a stacked structure of a material with a high relative dielectric constant (high-k) and a material whose dielectric strength is greater than that of the high-k material. For example, as the insulating layer 135, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking insulators with greater dielectric strength, such as aluminum oxide, the dielectric strength is improved, thereby suppressing electrostatic damage to the capacitor 51.

[0275] A material having ferroelectricity can also be used as the insulating layer 135. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X(X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, there can be mentioned a material in which an element J1 is added to hafnium oxide (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum and strontium). Here, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, there can be mentioned a material in which an element J2 is added to zirconium oxide (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum and strontium). In addition, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO) or barium titanate with a perovskite structure.

[0276] In addition, examples of materials that can exhibit ferroelectricity include metal nitrides containing element M1, element M2, and nitrogen. Here, element M1 is one or more selected from aluminum, gallium, and indium. Furthermore, element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, and chromium. Furthermore, the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be appropriately set. Furthermore, metal oxides containing element M1 and nitrogen sometimes exhibit ferroelectricity even if they do not contain element M2. Furthermore, examples of materials that can exhibit ferroelectricity include materials obtained by adding element M3 to the above-mentioned metal nitrides. Furthermore, element M3 is one or more selected from magnesium, calcium, strontium, zinc, and cadmium. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set.

[0277] In addition, as materials that can have ferroelectricity, there can be mentioned perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 of κ-type alumina.

[0278] Note that although metal oxides and metal nitrides are described above, the present invention is not limited thereto. For example, metal oxynitrides obtained by adding nitrogen to the metal oxides or metal oxynitrides obtained by adding oxygen to the metal nitrides may also be used.

[0279] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of multiple materials selected from the above materials can be used. Alternatively, the insulating layer 135 can have a stacked structure composed of multiple materials selected from the above materials. For example, the crystal structure (properties) of the materials listed above may change not only depending on the deposition conditions but also depending on various processes. Therefore, in this specification, etc., a material that exhibits ferroelectricity is not only referred to as a ferroelectric, but also referred to as a material that can have ferroelectricity or a material that imparts ferroelectricity.

[0280] It is preferred to use a metal oxide containing one or both of hafnium and zirconium because they can have ferroelectricity even if they are processed into a thin film of a few nm. Here, the thickness of the insulating layer 135 can be, for example, less than 100 nm, preferably less than 50 nm, more preferably less than 20 nm, and further preferably less than 10 nm (typically, more than 2 nm and less than 9 nm). For example, the thickness is preferably more than 8 nm and less than 12 nm. By using a ferroelectric layer that can be thin-filmed, the capacitor 51 can be combined with a semiconductor element such as a miniaturized transistor to form a storage device. Note that in this specification, etc., a material that can have ferroelectricity and is formed into a layer is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is sometimes referred to as a ferroelectric device.

[0281] In addition, it is preferable to use metal oxides containing one or both of hafnium and zirconium because they can have ferroelectricity even with a small area. For example, even if the area (occupied area) of the ferroelectric layer when viewed from above is 100 μm, 2 Below 10μm 2 Below 1μm 2 Below or 0.1μm 2 The following can also have ferroelectricity. In addition, sometimes even if the area is 10000nm 2 Below or 1000nm 2 The area occupied by the capacitor 51 can be reduced by forming a ferroelectric layer with a small area.

[0282] Note that in a metal oxide containing one or both of hafnium and zirconium, oxygen vacancies (V O) concentration is higher, the easier it is to produce crystals with orthorhombic crystal structure. Thus, it is preferred to add an element to the metal oxide comprising one or both of hafnium and zirconium to increase the oxygen vacancy concentration in the metal oxide. As such, the 3rd Group elements of the periodic table (also referred to as IIIa Group elements) can be cited. The 3rd Group elements of the periodic table added to the above-mentioned metal oxide are more preferably one or more selected from scandium, lanthanum and yttrium, and are further preferably one or both of lanthanum and yttrium. Note that in this specification, the 3rd Group elements of the periodic table are sometimes referred to as Group 3 elements.

[0283] Ferroelectrics are insulators that have the property of being polarized internally when an electric field is applied from the outside and maintaining polarization even when the electric field becomes 0. Therefore, by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) using this material as a dielectric, a non-volatile memory element can be formed. Non-volatile memory elements using ferroelectric capacitors are sometimes referred to as FeRAM (Ferroelectric Random Access Memory), ferroelectric memories, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Thus, when a ferroelectric capacitor is used as the capacitor 51, the storage device shown in this embodiment can be used as a ferroelectric memory.

[0284] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen in the crystals contained in the ferroelectric layer is displaced by an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystals contained in the ferroelectric layer. Therefore, in order for the insulating layer 135 to exhibit ferroelectricity, the insulating layer 135 needs to have crystals. In particular, the insulating layer 135 preferably has crystals with an orthorhombic crystal structure, thereby exhibiting ferroelectricity. The crystal structure of the crystals contained in the insulating layer 135 may also be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, monoclinic and hexagonal systems. In addition, the insulating layer 135 may also have an amorphous structure. In this case, the insulating layer 135 may also have a composite structure of an amorphous structure and a crystal structure.

[0285] As described above, the insulating layer 103b preferably has a low relative dielectric constant. This can reduce parasitic capacitance generated between wiring lines. As the insulating layer 103b, a single layer or a stack of insulating layers comprising a material with a low relative dielectric constant, as described in the "Insulator" section below, can be used. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability.

[0286] <Constituent Materials of Storage Device> Next, constituent materials that can be used in a storage device according to one embodiment of the present invention will be described.

[0287] [Substrate] As substrates for forming transistors 41, 42, and capacitor 51, for example, insulating substrates, semiconductor substrates, or conductive substrates can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of materials such as silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include insulating substrates provided with conductors or semiconductors, semiconductor substrates provided with conductors or insulators, and conductive substrates provided with semiconductors or insulators. Alternatively, a substrate in which elements are provided over these substrates may be used.

[0288] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0289] For example, when carrying out miniaturization and high integration of transistor, due to the thin film of gate insulating layer, problems such as leakage current sometimes occur. By using high-k material as the insulator used as gate insulating layer, it is possible to realize low voltage when transistor is working while maintaining physical thickness. In addition, the equivalent oxide thickness (EOT) of the insulator used as gate insulating layer can be reduced. On the other hand, by using the material with low relative dielectric constant for the insulator used as interlayer insulating layer, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferred to select material according to the function of insulator. In addition, the material with low relative dielectric constant is also the material with large dielectric strength.

[0290] Examples of materials with a high relative dielectric constant (high-k) include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0291] As materials with low relative dielectric constants, for example, inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, resins such as polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic resin can be cited. In addition, as other inorganic insulating materials with low relative dielectric constants, for example, silicon oxide added with fluorine, silicon oxide added with carbon, and silicon oxide added with carbon and nitrogen can be cited. In addition, for example, porous silicon oxide can be cited. Note that these silicon oxides can also contain nitrogen. In addition, silicon oxide can also be formed using organic silanes such as tetraethoxysilane (TEOS), for example.

[0292] Furthermore, by surrounding a transistor using a metal oxide with an insulator that suppresses the permeation of impurities and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that suppresses the permeation of impurities and oxygen, for example, a single layer or stack of insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. Specifically, as an insulator that suppresses the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be used.

[0293] Furthermore, an insulator in contact with a semiconductor, such as a gate insulating layer, or an insulator disposed near a semiconductor layer preferably has a region containing excess oxygen. For example, by contacting a semiconductor layer or disposing an insulator having a region containing excess oxygen near the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced. Examples of insulators in which regions containing excess oxygen are easily formed include silicon oxide, silicon oxynitride, and porous silicon oxide.

[0294] Insulators having oxygen barrier properties include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0295] Insulators having hydrogen barrier properties include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride.

[0296] The insulator having oxygen barrier properties and the insulator having hydrogen barrier properties can be said to be insulators having barrier properties against one or both of oxygen and hydrogen.

[0297] Insulators capable of capturing or fixing hydrogen include oxides containing magnesium or oxides containing one or both of aluminum and hafnium. Furthermore, these oxides more preferably have an amorphous structure. In oxides with an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds sometimes have the property of capturing or fixing hydrogen. Note that while these metal oxides preferably have an amorphous structure, they may also partially have crystalline regions.

[0298] Note that in this specification, etc., a blocking insulating film refers to an insulating film having a barrier property. In addition, the barrier property refers to the property that the corresponding substance does not diffuse easily (also referred to as the property that the corresponding substance does not easily penetrate, the property that the corresponding substance has low permeability, or the function of inhibiting the diffusion of the corresponding substance). In addition, the function of capturing or fixing (also referred to as doping) the corresponding substance can also be referred to as a barrier property. Note that hydrogen recorded as the corresponding substance refers to, for example, hydrogen atoms, hydrogen molecules, water molecules, and OH. - At least one of substances that bond with hydrogen, etc. In addition, unless otherwise specified, the impurity recorded as the corresponding substance refers to an impurity in the channel formation region or the semiconductor layer, for example, at least one of hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. In addition, oxygen recorded as the corresponding substance refers to, for example, at least one of oxygen atoms and oxygen molecules, etc. Specifically, oxygen barrier properties refer to the property that at least one of oxygen atoms and oxygen molecules, etc., does not diffuse easily.

[0299] [Conductor] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements, etc. As the alloy with the above metal elements as a component, a nitride of the alloy or an oxide of the alloy can also be used. For example, tantalum nitride, titanium nitride, tungsten, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, an oxide comprising lanthanum and nickel, etc. can be preferably used. In addition, a semiconductor with high conductivity represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used.

[0300] In addition, nitrogen-containing conductive materials such as tantalum nitride, titanium nitride, molybdenum nitride, tungsten nitride, ruthenium nitride, tantalum and aluminum nitride, or titanium and aluminum nitride, oxygen-containing conductive materials such as ruthenium oxide, strontium and ruthenium oxide, or lanthanum and nickel oxide, and materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are not easily oxidized, have the function of suppressing oxygen diffusion, or maintain conductivity even when absorbing oxygen. Note that examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, silicon-added indium tin oxide, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In this specification, conductive materials containing oxygen are sometimes referred to as oxide conductors.

[0301] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferred because of its high conductivity.

[0302] Furthermore, multiple conductors formed from the above materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above metal element with a conductive material containing oxygen. Furthermore, a laminated structure may be formed by combining a material containing the above metal element with a conductive material containing nitrogen. Furthermore, a laminated structure may be formed by combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0303] Furthermore, when a metal oxide is used in the channel formation region of a transistor, a gate electrode conductor preferably employs a stacked structure comprising a material containing the aforementioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. Positioning the conductive material containing oxygen on the channel formation region side facilitates the supply of oxygen released from the conductive material to the channel formation region.

[0304] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal elements and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0305] [Metal oxides] Metal oxides sometimes have lattice defects. Lattice defects include point defects such as atomic vacancies and strange atoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids. Lattice defects can also be caused by a mismatch in the atomic ratio of the constituent elements (an excess or deficiency of constituent atoms) and impurities.

[0306] When metal oxides are used in the semiconductor layers of transistors, lattice defects in the metal oxides can lead to carrier generation and trapping. Therefore, when metal oxides with a high number of lattice defects are used in the semiconductor layers of transistors, the electrical characteristics of the transistor may be unstable. Therefore, metal oxides used in the semiconductor layers of transistors preferably have fewer lattice defects.

[0307] In a transistor using a metal oxide, in particular, if oxygen vacancies (V O ) and impurities, the electrical characteristics are easily changed, sometimes reducing reliability. In addition, hydrogen near the oxygen vacancy forms V O H and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the metal oxide, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Thus, in the channel formation region of the metal oxide, it is preferred to minimize oxygen vacancies and impurities. In other words, it is preferred that the carrier concentration in the channel formation region of the metal oxide is reduced and is i-typed (intrinsic) or substantially i-typed.

[0308] The type of lattice defects that are likely to exist in a metal oxide and the amount of the lattice defects that exist vary depending on the structure of the metal oxide, the method of depositing the metal oxide, and the like.

[0309] The structures of metal oxides are classified into single crystal structures and other structures (non-single crystal structures). Examples of non-single crystal structures include CAAC structures, polycrystalline structures, NC structures, amorphous-like (a-like) structures, and amorphous structures. The a-like structure has a structure intermediate between the NC structures and the amorphous structures.

[0310] In addition, metal oxides with an a-like structure and metal oxides with an amorphous structure contain voids or low-density regions. In other words, the crystallinity of metal oxides with an a-like structure and metal oxides with an amorphous structure is lower than that of metal oxides with an nc structure and metal oxides with a CAAC structure. In addition, the hydrogen concentration in metal oxides with an a-like structure is higher than that of metal oxides with an nc structure and metal oxides with a CAAC structure. Therefore, lattice defects are easily generated in metal oxides with an a-like structure and metal oxides with an amorphous structure.

[0311] Therefore, it is preferable to use a highly crystalline metal oxide for the semiconductor layer of a transistor. For example, a metal oxide having a CAAC structure or a single-crystalline metal oxide is preferably used. By using such a metal oxide in a transistor, a transistor with excellent electrical characteristics can be realized. In addition, a transistor with high reliability can be realized.

[0312] In addition, the channel formation region of the transistor preferably uses a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is sufficient to increase the mobility of the metal oxide used for the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of n-channel transistors) or reduce the scattering factors that affect the transmission of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region through which carriers can easily flow in the channel length direction, the on-state current of the transistor can be increased.

[0313] Here, it is preferred to use a metal oxide with high crystallinity as the metal oxide having a channel formation region. Furthermore, the crystal preferably has a crystal structure having multiple layers (e.g., a first layer, a second layer, and a third layer). In other words, the crystal has a layered crystal structure (also referred to as a layered crystal or a layered structure). In this case, the c-axis direction of the crystal is the direction in which multiple layers are stacked. Metal oxides having this crystal include, for example, single crystal oxide semiconductors and CAAC-OS.

[0314] Furthermore, the c-axis of the crystals is preferably oriented in the normal direction to the metal oxide's formed surface or film surface. Thus, the multiple layers are arranged parallel or substantially parallel to the metal oxide's formed surface or film surface. In other words, the multiple layers extend in the channel length direction.

[0315] For example, the three-layered crystal structure has the following structure: The first layer has an atomic coordination structure of an oxygen octahedron with the metal contained in the first layer at the center. The second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the second layer at the center. The third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal contained in the third layer at the center.

[0316] Examples of the crystal structure of the above-mentioned crystal include a YbFe2O4 type structure, a Yb2Fe3O7 type structure, and modified structures thereof.

[0317] Furthermore, it is preferred that the first to third layers are each composed of a single metal element or multiple metal elements having the same valence, and oxygen. It is preferred that the valence of the one or more metal elements constituting the first layer be the same as the valence of the one or more metal elements constituting the second layer. Alternatively, the first and second layers may contain the same metal element. Furthermore, it is preferred that the valence of the one or more metal elements constituting the first layer be different from the valence of the one or more metal elements constituting the third layer.

[0318] By adopting the above structure, the crystallinity of the metal oxide can be improved, thereby increasing the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of the transistor, the on-state current of the transistor is increased, thereby improving the electrical characteristics of the transistor.

[0319] As a metal oxide of one embodiment of the present invention, for example, indium oxide, gallium oxide and zinc oxide can be mentioned. The metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M and zinc. Element M is a metal element or semi-metal element with a high bond energy with oxygen, for example, a metal element or semi-metal element with a higher bond energy with oxygen than indium. As element M, specifically aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be mentioned. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. When the element M contained in the metal oxide is gallium, the metal oxide of one embodiment of the present invention preferably contains one or more selected from indium, gallium and zinc. Note that in this specification and the like, metal elements and semi-metal elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include semi-metal elements.

[0320] As a metal oxide in one embodiment of the present invention, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), and the like containing silicon can be cited.

[0321] By increasing the ratio of the number of atoms of indium to the total number of atoms of all metal elements contained in the metal oxide, the field-effect mobility of the transistor can be increased.

[0322] In addition, the metal oxide may also replace indium and contain one or more metal elements with a large periodic number in the periodic table. Alternatively, the metal oxide may also contain one or more metal elements with a large periodic number in the periodic table in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large periodic number in the periodic table, the field effect mobility of the transistor can sometimes be improved. As the metal element with a large periodic number in the periodic table, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0323] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field-effect mobility of the transistor. Examples of non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0324] Furthermore, by increasing the ratio of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. This suppresses fluctuations in the electrical characteristics of the transistor and improves reliability.

[0325] Furthermore, by increasing the ratio of the number of atoms of the element M relative to the total number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Consequently, carrier generation due to oxygen vacancies is suppressed, thereby enabling the realization of a transistor with a low off-state current. Furthermore, variations in the electrical characteristics of the transistor are suppressed, thereby improving reliability.

[0326] Furthermore, by increasing the ratio of the number of In atoms to the total number of atoms of all metal elements contained in the metal oxide, a transistor having a large on-state current and high frequency characteristics can be obtained.

[0327] In this embodiment, In—Ga—Zn oxide is sometimes described as an example of a metal oxide.

[0328] In order to form the metal oxide having the layered crystal structure, it is preferable to deposit atoms layer by layer. The metal oxide having the layered crystal structure can be easily formed by using the ALD method.

[0329] Examples of the ALD method include a thermal ALD method in which a precursor and a reactant react using only thermal energy, and a plasma ALD method (PEALD: Plasma Enhanced ALD) method using a reactant excited by plasma.

[0330] The ALD method can deposit atoms layer by layer, thereby having the effects of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. In addition, because plasma is used in the PEALD method, deposition can be performed at lower temperatures, so it is sometimes preferred. Note that the precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or SIMS.

[0331] When the ALD method is used as a deposition method for metal oxides, by adopting one or both of high substrate temperature conditions during deposition and performing impurity removal treatment, the amount of carbon and chlorine in the film can be reduced compared to the case where the ALD method is used without adopting the above two conditions.

[0332] For example, when depositing a metal oxide, it is preferred to intermittently perform an impurity removal process under an oxygen-containing atmosphere. In addition, after depositing the metal oxide, it is preferred to perform an impurity removal process under an oxygen-containing atmosphere. By performing an impurity removal process on one or both sides during and after the deposition of the metal oxide, impurities in the film can be removed. Thus, it is possible to suppress impurities (hydrogen, carbon, nitrogen, etc.) contained in raw materials such as precursors from remaining in the metal oxide. Therefore, the impurity concentration in the metal oxide can be reduced. In addition, the crystallinity of the metal oxide can be improved.

[0333] Examples of the impurity removal treatment include plasma treatment, microwave treatment, and heat treatment.

[0334] When performing plasma treatment or microwave treatment, the substrate temperature is preferably, for example, room temperature (e.g., 25° C.) or higher and 500° C. or lower, 100° C. or higher and 450° C. or lower, 200° C. or higher and 450° C. or lower, 300° C. or higher and 450° C. or lower, or 400° C. or higher and 450° C. or lower. Furthermore, the temperature of heat treatment is preferably, for example, 100° C. or higher and 500° C. or lower, 200° C. or higher and 450° C. or lower, 300° C. or higher and 450° C. or higher, or 400° C. or higher and 450° C. or lower.

[0335] In particular, setting the temperature during the impurity removal process to a temperature below the maximum temperature during the transistor or memory device manufacturing process is preferred because the impurity content of the metal oxide can be reduced without reducing productivity. For example, by setting the maximum temperature during the manufacturing of a memory device according to one embodiment of the present invention to 500°C or below, preferably 450°C or below, the productivity of the transistor or memory device can be improved.

[0336] Here, microwave treatment refers to treatment using, for example, a device including a power source for generating high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0337] For example, microwave treatment preferably uses a microwave processing device that includes a power supply that generates high-density plasma using microwaves. Here, for example, the frequency of the microwave processing device can be set to 300 MHz or more and 300 GHz or less, more preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz. By using high-density plasma, a high density of oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably 1000 W or more and 10000 W or less, for example, 2000 W or more and 5000 W or less. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the film.

[0338] The microwave treatment is preferably performed under reduced pressure, and the pressure is preferably, for example, 10 Pa to 1000 Pa, more preferably 300 Pa to 700 Pa. The treatment temperature is preferably, for example, room temperature (25° C.) to 750° C., more preferably 300° C. to 500° C., and even more preferably 400° C. to 450° C.

[0339] Alternatively, a heat treatment may be performed continuously after the microwave treatment or plasma treatment without exposure to the outside air. The heat treatment temperature is preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and even more preferably 400° C. to 450° C.

[0340] For example, microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Even more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%.

[0341] In addition, the heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under a reduced pressure state. Alternatively, the heat treatment can be carried out in a nitrogen gas or inert gas atmosphere, and then heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated. The heat treatment can be carried out in an atmosphere of ultra-dry air (air with a water content of less than 20ppm, preferably less than 1ppm, preferably less than 10ppb).

[0342] This heat treatment can remove impurities such as hydrogen and carbon contained in the metal oxide. For example, carbon in the metal oxide can be released as CO2 and CO, and hydrogen in the metal oxide can be released as H2O. Furthermore, while removing these impurities, the metal atoms and oxygen atoms are rearranged, thereby improving crystallinity. This can form a metal oxide with a highly crystalline layered crystal structure, particularly a metal oxide with the aforementioned CAAC structure.

[0343] For example, unlike a deposition method in which particles released from a target material or the like are deposited, the ALD method is a deposition method in which a film is formed due to a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so the ALD method is suitable for forming a surface covering an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferably used in combination with other deposition methods such as a sputtering method or a CVD method having a fast deposition rate. For example, a method in which a first metal oxide is deposited by sputtering and a second metal oxide is deposited on the first metal oxide by the ALD method can be cited. For example, when the first metal oxide has a crystalline portion, crystal growth sometimes occurs in the second metal oxide with the crystalline portion as the core.

[0344] The ALD method can control the composition of the resulting film according to the amount of source gas introduced. For example, in the ALD method, by adjusting the amount of source gas introduced, the number of introductions (also called the number of pulses), and the time required for one pulse (also called the pulse time), a film of any composition can be deposited. In addition, for example, when the ALD method is used, a film whose composition continuously changes can be deposited by changing the source gas while deposition is performed. When deposition is performed while changing the source gas, since the time required for conveying and adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the storage device can sometimes be improved.

[0345] [Transistor including metal oxide] Next, a case where a metal oxide (oxide semiconductor) is used for a transistor will be described. Hereinafter, a transistor using an oxide semiconductor for a semiconductor layer is referred to as an OS transistor, and a transistor using silicon for a semiconductor layer is referred to as a Si transistor.

[0346] By using a metal oxide (oxide semiconductor) of one embodiment of the present invention in a transistor, a transistor with high field-effect mobility can be realized. In addition, a transistor with high reliability can be realized. In addition, miniaturized or highly integrated transistors can be realized. For example, a transistor with a channel length of 2 nm or more and 30 nm or less can be manufactured.

[0347] It is preferable to use an oxide semiconductor with a low carrier concentration for the channel formation region of the transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably 1×10 17 cm -3 Below, more preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, preferably 1×10 11 cm -3 Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration of the oxide semiconductor film is to be reduced, it is preferable to reduce the impurity concentration of the oxide semiconductor film to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0348] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, the trap state density may also be low.

[0349] Furthermore, charges trapped in trap states of an oxide semiconductor take a long time to disappear, and may behave like fixed charges. Consequently, the electrical characteristics of a transistor whose channel formation region is formed in an oxide semiconductor with a high trap state density may be unstable.

[0350] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen, carbon, and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic% can be considered an impurity.

[0351] Furthermore, the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), preferably 2 eV or greater, more preferably 2.5 eV or greater, and even more preferably 3.0 eV or greater. Using an oxide semiconductor with a larger band gap than silicon can reduce the off-state current (also known as Ioff) of the transistor.

[0352] For example, in Si transistors, as the miniaturization of transistors progresses, the short channel effect (also known as SCE: Short Channel Effect) occurs. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that silicon has a small band gap. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with a large band gap, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0353] The short channel effect refers to the degradation of electrical characteristics that occurs with transistor miniaturization (reduction in channel length). Specific examples of the short channel effect include a decrease in threshold voltage, an increase in the subthreshold swing value (sometimes referred to as the S value), and an increase in leakage current. The S value refers to the change in gate voltage in the subthreshold region that causes a single-digit change in drain current at a fixed drain voltage.

[0354] Characteristic length is widely used as an indicator of resistance to short channel effects. Characteristic length refers to the curvature of the potential in the channel formation region. The smaller the characteristic length, the more steeply the potential rises, and therefore it can be said that the resistance to short channel effects is high.

[0355] OS transistors are accumulation-mode transistors, while Si transistors are inversion-mode transistors. Therefore, compared to Si transistors, the characteristic lengths between the source region and the channel formation region, and the characteristic lengths between the drain region and the channel formation region, in OS transistors are smaller. Consequently, OS transistors are more resistant to short-channel effects than Si transistors. In other words, when manufacturing transistors with short channel lengths, OS transistors are more suitable than Si transistors.

[0356] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction band lowering (CBL) effect in the short channel transistor. Therefore, the energy difference of the conduction band bottom between the source region or drain region and the channel formation region may be reduced to 0.1eV or more and 0.2eV or less. Therefore, the OS transistor can be regarded as having n + / n - / n +The accumulation type junction-less transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel forming region is n - Type region and the source and drain regions are n + Type area.

[0357] When the above structure is adopted as an OS transistor, good electrical characteristics can be achieved even if the storage device is miniaturized or highly integrated. For example, even if the channel length or gate length of the OS transistor is greater than 1nm and less than 20nm, greater than 3nm and less than 15nm, greater than 5nm and less than 10nm, greater than 5nm and less than 7nm, or greater than 5nm and less than 6nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors are more suitable as transistors with a small channel length. Note that the gate length refers to the length of the gate electrode in the direction in which carriers migrate in the channel formation region when the transistor is operating.

[0358] Furthermore, miniaturizing the OS transistor can improve the high-frequency characteristics of the transistor. Specifically, the transistor's cutoff frequency can be increased. When the gate length of the OS transistor is within the above range, the transistor's cutoff frequency can be, for example, above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz at room temperature.

[0359] As described above, OS transistors have advantages superior to Si transistors, such as small off-state current and the ability to manufacture transistors with small channel lengths.

[0360] [Impurities in metal oxides] Here, the influence of various impurities in metal oxides (oxide semiconductors) will be described.

[0361] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0362] When an oxide semiconductor contains nitrogen, electrons are generated as carriers, which increases the carrier concentration and makes it easy to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0363] The hydrogen contained in the oxide semiconductor reacts with the oxygen bonded to the metal atom to form water, and thus oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, sometimes electrons as carriers are generated because part of the hydrogen is bonded to the oxygen bonded to the metal atom. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferable to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, in the channel formation region of the oxide semiconductor, the hydrogen concentration measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 5×10 19 atoms / cm 3 , more preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 .

[0364] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may sometimes be formed to generate carriers. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0365] By using an oxide semiconductor with sufficiently reduced impurity content in a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0366] [Other semiconductor materials] The semiconductor layer 113 may be alternatively referred to as a semiconductor layer including a channel formation region of the transistor. Semiconductor materials that can be used for the semiconductor layer are not limited to the aforementioned metal oxides. As the semiconductor, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) may also be used. For example, a single element semiconductor, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) is preferably used as the semiconductor material.

[0367] Here, in this specification, etc., layered materials are a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked together through bonds weaker than covalent and ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per layer, that is, high two-dimensional conductivity. By using a material that functions as a semiconductor and has high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0368] Examples of single-element semiconductors that can be used as semiconductor materials include silicon and germanium. Examples of silicon that can be used in semiconductor layers include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. Examples of polycrystalline silicon include low-temperature polycrystalline silicon (LTPS).

[0369] Compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. Boron nitride that can be used in the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used in the semiconductor layer preferably includes crystals with a cubic structure.

[0370] Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In boron carbonitride, a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged on a plane in a hexagonal lattice structure. Chalcogenides are compounds containing elements from the chalcogen group. Chalcogenides are a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and lead. Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0371] As the semiconductor layer, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specifically, transition metal chalcogenides that can be used for the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By using the above-mentioned transition metal chalcogenides for the semiconductor layer, a transistor with a large on-state current can be provided.

[0372] <Operation Example of Semiconductor Device 710> Figure 12 It is an explanation Figure 11 A timing chart showing an operation example of the semiconductor device 710 is shown.

[0373] In the following description of the operation, the wiring VPRE is supplied with (potential VDD - potential VSS) / 2. Furthermore, the wiring VPRE2 is supplied with a potential (e.g., potential VDD) that is higher than (potential VDD - potential VSS) / 2 and lower than potential VDD. Furthermore, the wiring CL is supplied with an arbitrary fixed potential (e.g., potential VSS).

[0374] Figure 12 The timing diagram shows the states (potential H or potential L) of signals supplied to wiring WWL, wiring RWL, wiring SW4, wiring SW5, wiring EQ, wiring EQB, and wiring CSEL during each operating period (period T721 to period T725). The timing diagram also shows the potentials supplied to wiring SAP and wiring SAN. Furthermore, the diagram shows the changes in the potentials of wiring MN, wiring RBL, wiring RBLB, and wiring WBL when reading and writing data "1" (data 1) and when reading and writing data "0" (data 0), respectively.

[0375] Periods T721 to T724 are periods for reading data, and period T725 is a period for writing data.

[0376] Before period T721, the wiring WWL is supplied with a potential of L, and the wiring RWL is supplied with a potential of H. In addition, the wiring SW4 and the wiring SW5 are each supplied with a potential of H. In addition, the wiring EQ is supplied with a potential of H, and the wiring EQB is supplied with a potential of L. In addition, the wiring CSEL is supplied with a potential of L. In addition, the wiring SAP and the wiring SAN are each supplied with (potential VDD-potential VSS) / 2. At this time, the wiring RBL and the wiring RBLB are each precharged to (potential VDD-potential VSS) / 2. In addition, the wiring MN of the memory cell 741 maintains the potential VDD (the potential corresponding to data "1") or the potential VSS (the potential corresponding to data "0"). Note that in the following description, unless otherwise stated, the previous state is maintained.

[0377] In period T721, the potential L is supplied to the wiring EQ, and the potential H is supplied to the wiring EQB. This stops precharging of the wiring RBL and the wiring RBLB, and the wiring RBL and the wiring RBLB enter a floating state.

[0378] During period T722, the potential L is supplied to the wiring SW4. This precharges the wiring RBL to the potential supplied to the wiring VPRE2. That is, the potential of the wiring RBL becomes higher than the potential of the wiring RBLB.

[0379] During period T723, the potential H is supplied to the wiring SW4. This stops precharging the wiring RBL. At this time, the potential L is supplied to the wiring RWL. Consequently, the potential of the wiring RBL changes according to the potential of the wiring MN. Therefore, the wiring MN can be converted to a potential difference between the wiring RBL and the wiring RBLB.

[0380] Specifically, for example, when the data stored in the memory cell 741 is "1" (i.e., the wiring MN maintains the potential VDD), the transistor M702 included in the memory cell 741 is in the on state, and current flows from the wiring RBL to the wiring RWL. Therefore, the potential of the wiring RBL becomes lower than the potential of the wiring RBLB. Alternatively, for example, when the data stored in the memory cell 741 is "0" (i.e., the wiring MN maintains the potential VSS), the transistor M702 included in the memory cell 741 is in the non-conductive state. No current flows between the wiring RBL and the wiring RWL. Therefore, the potential of the wiring RBL becomes higher than the potential of the wiring RBLB.

[0381] During period T724, the potential H is applied to wiring RWL. Then, the potential VSS is applied to wiring SAN, and the potential VDD is applied to wiring SAP. The potential difference between wiring RBL and wiring RBLB, which occurred during the operation during period T723, is amplified by the operation of amplifier circuit 755. Consequently, the potentials of wiring RBL and wiring RBLB are determined to be either VDD or VSS, respectively. In other words, reading of the data stored in memory cell 741 is completed.

[0382] Specifically, for example, when the data stored in the memory cell 741 is "1," the potential of the wiring RBL becomes the potential VSS, and the potential of the wiring RBLB becomes the potential VDD. Alternatively, for example, when the data stored in the memory cell 741 is "0," the potential of the wiring RBL becomes the potential VDD, and the potential of the wiring RBLB becomes the potential VSS.

[0383] During period T725, the wiring WWL is supplied with a potential of H. At this time, the potential VDD or the potential VSS of the wiring WBL is supplied to the wiring MN. Then, the wiring WWL is supplied with a potential of L, thereby completing the writing of data to the memory cell 741.

[0384] in addition, Figure 11The semiconductor device 710 shown may also employ a structure in which the wiring WBL and the wiring RBL are electrically connected via a switch. Alternatively, for example, the wiring WBL and the wiring RBLB may be electrically connected via a switch. With this structure, for example, when writing data to the memory cell 741, the potential VDD or the potential VSS can be supplied from the sensing circuit 751 to the wiring WBL via the switch. For example, a transistor provided in the layer 983 or a transistor provided in the layer 985 can be used as the switch.

[0385] <Storage Device Usable for Storage Unit 920> A memory device 720 according to one embodiment of the present invention will be described. The memory device 720 may use at least a portion of the semiconductor device 710 described above. For example, at least a portion of the memory device 720 may be used in the above-described Figure 1A The electronic computer 900 shown in FIG. 10 can be used in the storage unit 920, for example.

[0386] Figure 13 7 is a block diagram illustrating a configuration example of the storage device 720 .

[0387] Figure 13 The memory device 720 shown includes a memory array 721 and a driving circuit 722 .

[0388] In one embodiment of the present invention, when the storage device 720 is used for the storage unit 920 included in the electronic computer 900 , for example, the memory array 721 corresponds to the memory array unit 921 and the drive circuit 722 corresponds to the control unit 922 .

[0389] The memory array 721 includes a plurality of sensing circuits 751 and a plurality of memory cells 741 .

[0390] In one embodiment of the present invention, as described above, the sensing circuit 751 is arranged in the layer 985 , and the plurality of memory cells 741 are arranged in the layers 984 [ 1 ] to 984 [K].

[0391] The plurality of memory cells 741 are arranged in a three-dimensional matrix of K layers×M rows×N columns (K, M, and N are each an integer greater than or equal to 1).

[0392] In addition, Figure 13, the storage cell 741[1, 1, 1] of the 1st layer, 1st row, 1st column, the storage cell 741[1, 1, N] of the 1st layer, 1st row, Nth column, the storage cell 741[1, M, 1] of the 1st layer, 1st row, 1st column, the storage cell 741[K, 1, 1] of the Kth layer, 1st row, 1st column, the storage cell 741[K, 1, N] of the Kth layer, 1st row, 1st column, the storage cell 741[K, M, 1] of the Kth layer, 1st row, 1st column, and the storage cell 741[K, M, N] of the Kth layer, Mth row, Nth column are typically shown.

[0393] In addition, the wiring WL[1, 1] electrically connected to the N memory cells 741 in the 1st row of the 1st layer, the wiring WL[1, M] electrically connected to the N memory cells 741 in the Mth row of the 1st layer, the wiring WL[K, 1] electrically connected to the N memory cells 741 in the 1st row of the Kth layer, and the wiring WL[K, M] electrically connected to the N memory cells 741 in the Mth row of the Kth layer are also shown.

[0394] The driving circuit 722 includes a power switch 761 , a power switch 762 , and a peripheral circuit 771 . The peripheral circuit 771 includes a peripheral circuit 781 , a control circuit 772 , and a voltage generating circuit 773 .

[0395] In one embodiment of the present invention, for example, the driver circuit 722 is disposed in layer 985. Therefore, for example, Si transistors can be used for the driver circuit 722. Furthermore, at least a portion of the driver circuit 722 can be disposed in layer 983 and layers 984[1] to 984[K]. Therefore, at least a portion of the driver circuit 722 can be configured using planar OS transistors and vertical OS transistors.

[0396] Terminals BW, CE, GW, MCK, WAKE, ADDR, WDA, PON1, and PON2 all supply signals from outside the memory device 720. For example, terminal RDA outputs a signal to the outside of the memory device 720.

[0397] For example, a clock signal is supplied to terminal MCK. Furthermore, control signals are supplied to terminals BW, CE, and GW. A chip enable signal is supplied to terminal CE. A global write enable signal is supplied to terminal GW. A byte write enable signal is supplied to terminal BW. An address signal is supplied to terminal ADDR. Write data is supplied to terminal WDA. Read data is supplied to terminal RDA. Power gating control signals are supplied to terminals PON1 and PON2. Furthermore, the signals supplied to terminals PON1 and PON2 may also be generated, for example, in control circuit 772.

[0398] The control circuit 772 has a function of controlling the operation of the memory device 720. For example, the control circuit 772 has a function of performing a logical operation on the signals supplied to each of the terminals CE, GW, and BW to determine the operation mode (e.g., write operation or read operation) of the memory device 720. Furthermore, the control circuit 772 has a function of generating a signal to control the peripheral circuit 781 so as to execute the operation mode.

[0399] The voltage generating circuit 773 has a function of generating an arbitrary potential for operating the driver circuit 722. For example, the voltage generating circuit 773 has a function of generating an arbitrary potential based on a signal supplied to a terminal WAKE and a clock signal supplied to a terminal MCK. For example, a signal is supplied to the terminal WAKE that controls whether the clock signal supplied to the terminal MCK is input to the voltage generating circuit 773.

[0400] The peripheral circuit 781 has the function of writing and reading data from the memory cell 741. For example, the peripheral circuit 781 has the function of generating various signals for controlling the operation of the memory cell 741 and the sensing circuit 751. The peripheral circuit 781 includes a row decoder 782, a column decoder 784, a row driver 783, a column driver 785, a data driver 786, an input circuit 787, and an output circuit 788.

[0401] The row decoder 782 and column decoder 784 decode the address signal supplied to the ADDR terminal. The row decoder 782 specifies the row to be accessed. Furthermore, it specifies the layer to be accessed. The column decoder 784 specifies the column to be accessed. The row driver 783 selects the row and layer specified by the row decoder 782 and supplies desired signals, for example, to the corresponding memory cell 741 and sensor circuit 751. The column driver 785 selects the column specified by the column decoder 784 and supplies desired signals, for example, to the corresponding sensor circuit 751.

[0402] The data driver 786 has the function of writing and reading data to and from the memory cell 741 selected by the row driver and column driver. The input circuit 787 has the function of holding data supplied to the terminal WDA from outside the memory device 720. The data (data Din) held in the input circuit 787 is written to the memory cell 741 via the data driver 786. The data stored in the memory cell 741 is read out to the output circuit 788 via the data driver 786. The output circuit 788 has the function of holding the read data (data Dout). In addition, it has the function of outputting the held data to the outside of the memory device 720 via the terminal RDA.

[0403] The power switch 761 controls whether the potential supplied to terminal VMD is supplied to the peripheral circuit 771. The power switch 762 controls whether the potential supplied to terminal VMH is supplied to the row driver 783. For example, a high power supply potential (e.g., potential VDD) for operating the driver circuit 722 is supplied to terminal VMD, and a low power supply potential (e.g., potential VSS) is supplied to terminal VMS. Furthermore, for example, a high power supply potential (e.g., potential H) for operating the memory cell 741 and the sensor circuit 751 is supplied to terminal VMH. The conductive and non-conductive states of the power switch 761 are controlled by a signal supplied to terminal PON1. The conductive and non-conductive states of the power switch 762 are controlled by a signal supplied to terminal PON2.

[0404] In the driving circuit 722, the above-mentioned circuits and terminals can be selected or omitted as appropriate. In addition, other circuits and other terminals can be added as appropriate.

[0405] Figure 14A 7 is a circuit diagram of a memory cell 717 including one sub-sensing circuit 736, a plurality of storage cells 741, and a wiring LBL.

[0406] In the memory unit 717 , each of the K layers, layers 984 [ 1 ] to 984 [ K ], is provided with P (P is an integer greater than or equal to 1) memory cells 741 . That is, the memory unit 717 includes K×P memory cells 741 .

[0407] Figure 14A Typically, storage cells 741[1,1] and 741[1,P] configured in the 1st layer (layer 984[1]) and storage cells 741[K,1] and 741[K,P] configured in the Kth layer (layer 984[K]) are shown.

[0408] Figure 14B 1 is a circuit diagram of a memory block 718 including one sensor circuit 751, one switch circuit 737, a plurality of memory cells 717, wiring GBL, wiring GBLB, wiring SA_GBL, and wiring SA_GBLB. Here, the memory block 718 corresponds to the semiconductor device 710 described above.

[0409] The memory block 718 includes Q (Q is an even number greater than or equal to 2) memory cells 717. That is, the memory block 718 includes K×P×Q memory cells 741.

[0410] Figure 14BTypically, a memory cell 717 [ 1 ] and a memory cell 717 [Q / 2] electrically connected to the wiring GBL, and a memory cell 717 [Q / 2+1] and a memory cell 717 [Q] electrically connected to the wiring GBLB are shown.

[0411] Figure 15 It is a schematic diagram illustrating an example of the arrangement of components included in the storage device 720 .

[0412] exist Figure 15 In the illustrated memory device 720, a memory array 721 includes R (R is an integer greater than or equal to 1) memory sub-arrays 723 arranged in the column direction (X direction). Each memory sub-array 723 includes N memory blocks 718 arranged in the row direction (Y direction). In other words, the memory array 721 includes R×N memory blocks 718.

[0413] in addition, Figure 15 Three memory sub-arrays 723 are typically shown, with two of them (memory sub-array 723[1] and memory sub-array 723[R]) being enclosed by dotted lines. Furthermore, two memory blocks 718 (memory block 718[1] and memory block 718[N]) are typically enclosed by dotted lines.

[0414] As described above, the memory array 721 includes R×N (R rows×N columns) memory blocks 718. Furthermore, each memory block 718 includes K×P×Q (K layers×(P×Q rows)) memory cells 741. In other words, the memory device 720 includes K×P×Q×R×N memory cells 741 arranged in a three-dimensional matrix of K layers×M rows (P×Q×R rows)×N columns within the memory array 721. Furthermore, the memory device 720 includes R×N sensor circuits 751, enabling simultaneous access to multiple sensor circuits 751 for massively parallel reading of data stored in the memory array 721.

[0415] In the memory device 720 , a word line driver 724 , a column driver 725 , a sense amplifier driver 726 , a data driver 727 , and a memory controller 728 are arranged in a layer 985 surrounding the memory array 721 .

[0416] Here, for example, the word line driver 724 and the read amplifier driver 726 are equivalent to the row driver 783, the column driver 725 is equivalent to the column driver 785, the data driver 727 is equivalent to the data driver 786, the input circuit 787 and the output circuit 788, and the memory controller 728 is equivalent to the control circuit 772 and the voltage generating circuit 773.

[0417] Although not shown, the memory device 720 may include layer selection drivers for layer 983 and layers 984[1] to 984[K] disposed above the word line driver 724. The layer selection driver may have a function of supplying a signal generated by the word line driver 724 to any layer.

[0418] In a semiconductor device according to one embodiment of the present invention, in the above description, the OS transistor is a semiconductor element including three terminals: a gate (first gate), a source, and a drain, but it can also be a semiconductor element having four terminals including a back gate (second gate). When the OS transistor includes a back gate, for example, the same potential as the gate can be supplied to the back gate to reduce the on-state resistance (increase the on-state current). For example, by supplying the same potential as the source to the back gate, the electric field generated outside the transistor is not easily affected by the channel formation region, so the electrical characteristics become stable, thereby improving reliability. For example, by supplying an arbitrary potential to the back gate, the threshold voltage can be changed. In addition, for example, the current flowing between the source and the drain can be independently controlled according to the potential supplied to the gate or the back gate respectively.

[0419] In addition, in the description of the working example of the above-mentioned semiconductor device, when the potential changes, for example, due to the load (parasitic capacitance and parasitic resistance) of the wiring, etc., a rise time and a fall time are generated. This time is, for example, greater than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond. In addition, for example, even if the timing of two different operations is shown to be the same, it does not necessarily mean that the timing is exactly the same. For example, even if a slight time lag caused by a signal delay in the wiring is included, it can sometimes be regarded as the same timing. This time lag is, for example, greater than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond.

[0420] Furthermore, the potential H or potential L supplied to each of the plurality of wirings does not need to be the same for each wiring. For example, different potentials may be set for each wiring, taking into account the threshold voltage of the transistor to which the potential is supplied. Furthermore, the potential H or potential L supplied to each wiring may include a potential drop due to the threshold voltage of the transistor, for example.

[0421] In addition, in the timing diagrams, each period may be shown with the same length, but the length of each period may be different. In other words, the length of each period may be appropriately set according to the actual operation of the semiconductor device.

[0422] The electronic computer, semiconductor device, and storage device according to one embodiment of the present invention are not limited to the above description. At least a portion of the structural examples, operating examples, and drawings corresponding to these examples illustrated in this embodiment may be appropriately combined with other structural examples, operating examples, other drawings, and other embodiments described in this specification.

[0423] <Semiconductor Device Usable for Processing Unit 910> A semiconductor device 810 according to one embodiment of the present invention will be described. For example, at least a portion of the semiconductor device 810 can be used in the above-mentioned Figure 1A The electronic computer 900 shown in FIG. For example, the electronic computer 900 can be used in the register unit 914 included in the processing unit 910 .

[0424] [Structure example] Figure 16 810 is a circuit diagram illustrating a structural example of a semiconductor device 810 .

[0425] Figure 16 The semiconductor device 810 shown includes a scan flip-flop circuit 850 and a backup circuit 830 .

[0426] In one embodiment of the present invention, when the semiconductor device 810 is used for the register unit 914 included in the electronic computer 900, for example, the scan flip-flop circuit 850 corresponds to the scan flip-flop 915, and the backup circuit 830 corresponds to the backup memory 916. Specifically, for example, the scan flip-flop circuit 850 is arranged in the layer 985, and the backup circuit 830 is arranged in the layer 983. Therefore, for example, the scan flip-flop circuit 850 can use Si transistors, and the backup circuit 830 can use OS transistors.

[0427] The scan flip-flop circuit 850 includes a selector circuit 851 and a flip-flop circuit 852. The backup circuit 830 includes a holding circuit 831[1] to a holding circuit 831[G] (G is an integer greater than or equal to 2) and a transistor M801. Each of the holding circuits 831[1] to 831[G] includes a transistor M802, a transistor M803, and a capacitor C801.

[0428] Various signals for controlling the operation of the semiconductor device 810 are supplied to the wiring BK[1] to the wiring BK[G], the wiring RV[1] to the wiring RV[G], the wiring SE, the wiring PCK, and the wiring GBK.

[0429] The semiconductor device 810 can store and hold data input from wiring D or wiring SD in the flip-flop circuit 852 within the scan flip-flop circuit 850 in synchronization with a clock signal supplied to wiring PCK, and output the data to wiring Q. The data held in the flip-flop circuit 852 is written to any one of the holding circuits 831[1] to 831[G] within the backup circuit 830 via wiring Q in response to a signal supplied to wirings BK[1] to BK[G], and is then held. This operation is sometimes referred to as saving, retaining, storing, or backing up. The data held in any one of the holding circuits 831[1] to 831[G] is written back to the flip-flop circuit 852 via wiring SD in response to a signal supplied to wirings RV[1] to RV[G], and is then held. This operation is sometimes referred to as loading, restoring, regenerating, or rebuilding.

[0430] The flip-flop circuit 852 has a function of storing and holding data supplied to the input terminal Df in synchronization with the clock signal supplied to the wiring PCK and outputting the data from the output terminal Qf. The flip-flop circuit 852 can use a flip-flop circuit prepared in a standard circuit library. For example, the flip-flop circuit 852 can use a positive-edge-triggered D flip-flop.

[0431] The selector circuit 851 has a function of transmitting data supplied to the wiring D or the wiring SD to the flip-flop circuit 852 in response to a signal supplied to the wiring SE. Data input from outside the semiconductor device 810 is supplied to the wiring D. Data held in any of the holding circuits 831[1] to 831[G] within the backup circuit 830, or data input from the wiring SD_IN, is supplied to the wiring SD. Scan test data is supplied to the terminal SD_IN.

[0432] The backup circuit 830 can hold the state of the scan flip-flop circuit 850 in any one of the holding circuits 831[1] to 831[G] when performing power gating. Furthermore, when performing processing while switching between multiple tasks, the backup circuit 830 can hold the state of the scan flip-flop circuit 850 in each task in a one-to-one correspondence in each of the holding circuits 831[1] to 831[G].

[0433] When saving data, the backup circuit 830 selects one of the holding circuits 831[1] to 831[G] based on a signal supplied to the wirings BK[1] to BK[G]. Furthermore, when loading data, the backup circuit 830 selects one of the holding circuits 831[1] to 831[G] based on a signal supplied to the wirings RV[1] to RV[G]. Signals are supplied to each of the wirings BK[1] to BK[G] and each of the wirings RV[1] to RV[G] in a one-to-one correspondence with each of the holding circuits 831[1] to 831[G].

[0434] Note that the common contents between holding circuits 831[1] to 831[G] may be described as holding circuit 831. In this case, wirings BK[1] to BK[G] may be described as wirings BK, and wirings RV[1] to RV[G] may be described as wirings RV.

[0435] like Figure 16 As shown, the holding circuit 831 is electrically connected to the wiring Q and the wiring SD. In the holding circuit 831, the terminal (wiring) electrically connected to the wiring Q is an input terminal, and the terminal (wiring) electrically connected to the wiring SD is an output terminal. That is, in the semiconductor device 810, the output terminal Qf of the flip-flop circuit 852 is electrically connected to the input terminal of the holding circuit 831, and the input terminal Df of the flip-flop circuit 852 is electrically connected to the output terminal of the holding circuit 831 through the selector circuit 851.

[0436] In the holding circuit 831, one of the source and drain of transistor M802 is electrically connected to one terminal of capacitor C801. One of the source and drain of transistor M803 is electrically connected to one terminal of capacitor C801. The other terminal of capacitor C801 is electrically connected to wiring CM. The other of the source and drain of transistor M802 is electrically connected to the input terminal of the holding circuit 831 (i.e., wiring Q). The other of the source and drain of transistor M803 is electrically connected to the output terminal of the holding circuit 831 (i.e., wiring SD). The gate of transistor M802 is electrically connected to wiring BK. The gate of transistor M803 is electrically connected to wiring RV.

[0437] Note that in the holding circuits 831[1] to 831[G], the wiring electrically connecting one of the source and drain of the transistor M802, one of the source and drain of the transistor M803, and one terminal of the capacitor C801 may be referred to as wiring SN[1] to wiring SN[G] in some cases. Furthermore, when describing common features among the holding circuits 831[1] to 831[G], wiring SN[1] to wiring SN[G] may be referred to as wiring SN.

[0438] In the backup circuit 830 , one of the source and the drain of the transistor M801 is electrically connected to the wiring SD, and the other of the source and the drain of the transistor M801 is electrically connected to the wiring SD_IN.

[0439] The gate of the transistor M801 is electrically connected to a wiring GBK to which a signal for controlling whether or not to perform a scan test is supplied.

[0440] In one embodiment of the present invention, OS transistors, for example, can be used as transistors M801, M802, and M803. OS transistors have extremely low off-state current. Furthermore, even in high-temperature environments, their off-state current hardly increases, and their on-state current hardly decreases.

[0441] Thus, the retention circuit 831 holds the data written to the wiring SN for a long period of time by placing the transistors M802 and M803 in a non-conductive state. For example, even when power is not supplied to the scan flip-flop circuit 850 due to power gating, the data can be held. In other words, the retention circuit 831 can be used as a nonvolatile memory.

[0442] Here, when data stored in wiring SN is written back to flip-flop circuit 852 in semiconductor device 810, the potential of the data may change due to parasitic capacitance of wiring SD. Therefore, it is preferable that the capacitance of capacitor C801 is larger than the parasitic capacitance of wiring SD so that the change in the potential of the data is smaller than the logic threshold of flip-flop circuit 852 and the like.

[0443] As another example of the structure of the semiconductor device 810, for example, a structure in which a transistor M801 is provided for each of the plurality of holding circuits 831 may be employed. Furthermore, for example, a structure in which a Si transistor is used as the transistor M801 may be employed.

[0444] Furthermore, in the semiconductor device 810 , in order to increase the number of holding circuits 831 without increasing the area cost, a structure in which a plurality of layers 983 are stacked and the backup circuit 830 is provided in each layer 983 may be employed.

[0445] In the semiconductor device 810 according to one embodiment of the present invention, the backup circuit 830 can be provided without changing the circuit structure and layout of the scan flip-flop circuit 850. In other words, the backup circuit 830 is a circuit with extremely high versatility.

[0446] Furthermore, by stacking the backup circuit 830 on the scan flip-flop circuit 850 in the semiconductor device 810, the distance of the wiring used for electrical connection can be shortened. Consequently, the energy required for saving and loading data (access energy) can be reduced, thereby reducing the power consumption of the semiconductor device 810.

[0447] [Working Example 1] Figure 17 It is an explanation Figure 16 A timing chart showing an operation example of the semiconductor device 810 is shown.

[0448] In this working example 1, an operating example of the semiconductor device 810 when a power gating operation is performed in the above-described electronic computer 900 will be described.

[0449] Here, as an example for explaining the operation of the semiconductor device 810 , the number of holding circuits 831 included in the backup circuit 830 is set to four (G=4).

[0450] In the following description of the operation, the flip-flop circuit 852 stores data supplied to the input terminal Df and outputs the data from the output terminal Qf in synchronization with the timing (rising edge) when the clock signal supplied to the wiring PCK changes from the potential L to the potential H. Furthermore, the wiring GBK is supplied with the potential L. Furthermore, the wiring CM is supplied with a constant potential (e.g., the potential VSS).

[0451] Figure 17 The timing diagram shown shows the state (potential H or potential L) of the signal supplied to wiring PCK, wiring BK[1], wiring RV[1], and wiring SE during each operation period (period T811 to period T814). Note that the illustration of wiring BK[2] to wiring BK[4] and wiring RV[2] to wiring RV[4] is omitted. In addition, the state of data supplied to wiring D, wiring Q, wiring SD, and wiring SN[1] (any of data D1 to data D3) is shown. Note that the illustration of wiring SN[2] to wiring SN[4] is omitted. In addition, the state in which power is supplied to the scan flip-flop circuit 850 (power on) and the state in which power is not supplied (power off) are shown.

[0452] 18A to 18D It is shown in Figure 17The diagram shows how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] included in the backup circuit 830 during each period of the timing diagram. This diagram shows how data is input and output (data flow) as indicated by dotted arrows.

[0453] Before period T811, the potential L is supplied to wirings BK[1] to BK[4], wirings RV[1] to RV[4], and wiring SE. Furthermore, the states of the data supplied to wirings SN[1] and SN[2] are indeterminate (data D1 to D3 are not shown). Furthermore, a clock signal is supplied to wiring PCK. Furthermore, power is supplied to scan flip-flop circuit 850. Furthermore, data D1 is stored in scan flip-flop circuit 850. Note that in the following description, unless otherwise specified, the previous state is maintained.

[0454] In the period T811, first, the clock signal supplied to the wiring PCK is stopped.

[0455] Next, by supplying a potential of H to the wiring BK[1], the data D1 output to the wiring Q is stored in the wiring SN[1] of the holding circuit 831[1]. Then, by supplying a potential of L to the wiring BK[1], the data D1 stored in the wiring SN[1] is held.

[0456] During period T812, the power supply to the scan flip-flop circuit 850 is cut off. As a result, the data D1 stored in the scan flip-flop circuit 850 disappears. At this time, the data D1 held in the wiring SN[1] of the holding circuit 831[1] is held.

[0457] In the period T813 , first, the power supply to the scan flip-flop circuit 850 is resumed.

[0458] Next, data D1 stored in the wiring SN[1] of the holding circuit 831[1] is supplied to the wiring SD by supplying the potential H to the wiring RV[1], and the wiring SD is selected by supplying the potential H to the wiring SE.

[0459] Next, by supplying a pulse signal to the wiring PCK, data D1 supplied to the wiring SD is stored in the scan flip-flop circuit 850 in synchronization with the rising edge and output to the wiring Q. Then, the potential L is supplied to the wiring RV[1] and the wiring SE.

[0460] During period T814, the clock signal is first restarted to be supplied to wiring PCK. Furthermore, data D2 is supplied to wiring D. Consequently, data D2 supplied to wiring D is stored in scan flip-flop circuit 850 and output to wiring Q in synchronization with the rising edge of the clock signal.

[0461] Thus, the semiconductor device 810 can be Figure 17 Thus, when power gating is performed in the electronic computer 900, for example, when the scan flip-flop circuit 850 is in the power-on state, it can be quickly returned to the state before the power-off state, thereby shortening the time required to resume processing.

[0462] [Working Example 2] Figure 19 It is an explanation Figure 16 A timing chart showing an operation example of the semiconductor device 810 is shown.

[0463] In this working example 2, an operating example of the semiconductor device 810 will be described when processing is performed while switching between multiple tasks in the electronic computer 900 .

[0464] Here, as an example for explaining the operation of the semiconductor device 810 , the number of holding circuits 831 included in the backup circuit 830 is set to four (G=4).

[0465] In the following description of operation, flip-flop circuit 852 stores data supplied to input terminal Df and outputs the data from output terminal Qf in synchronization with the timing (rising edge) when the clock signal supplied to wiring PCK changes from potential L to potential H. Furthermore, wiring GBK is supplied with potential L. Furthermore, wiring CM is supplied with a constant potential (e.g., potential VSS).

[0466] Figure 19 The timing diagram shown shows the states (potential H or potential L) of signals supplied to wiring PCK, wiring BK[1], wiring BK[2], wiring RV[1], wiring RV[2], and wiring SE during each period of operation (period T821 to period T827). Note that wiring BK[3], wiring BK[4], wiring RV[3], and wiring RV[4] are omitted. Furthermore, the states of data (any of data D1 to data D7) supplied to wiring D, wiring Q, wiring SD, wiring SN[1], and wiring SN[2] are shown. Note that wiring SN[3] and wiring SN[4] are omitted.

[0467] Figures 20A to 20G It is shown in Figure 19 The diagram shows how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] included in the backup circuit 830 during each period of the timing diagram shown. This diagram shows how data is input and output (data flow) as indicated by dotted arrows.

[0468] Before period T821, the wirings BK[1] to BK[4], the wirings RV[1] to RV[4], and the wiring SE are each supplied with a potential L. Furthermore, the states of the data supplied to the wirings SN[1] and SN[2] are indeterminate (data D1 to D7 are not shown). Note that in the following description, unless otherwise specified, the previous states are maintained.

[0469] In the period T821, data D1 supplied to the wiring D is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the signal supplied to the wiring PCK and is output to the wiring Q.

[0470] In period T822, data D2 supplied to wiring D is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the signal supplied to wiring PCK and is output to wiring Q.

[0471] At this time, by supplying the potential H to the wiring BK[1], the data D2 output to the wiring Q is stored in the wiring SN[1] of the holding circuit 831[1]. Then, by supplying the potential L to the wiring BK[1], the data D2 stored in the wiring SN[1] is held.

[0472] In period T823, data D3 supplied to wiring D is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the signal supplied to wiring PCK and is output to wiring Q.

[0473] At this time, by supplying the potential H to the wiring BK[2], the data D3 output to the wiring Q is stored in the wiring SN[2] of the holding circuit 831[2]. Then, by supplying the potential L to the wiring BK[2], the data D3 stored in the wiring SN[2] is held.

[0474] In period T824, data D4 supplied to wiring D is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the signal supplied to wiring PCK and is output to wiring Q.

[0475] During period T825, first, by supplying potential H to wiring RV[1], data D2 stored in wiring SN[1] of holding circuit 831[1] is supplied to wiring SD. Note that although data D5 is supplied to wiring D, wiring SD is selected by supplying potential H to wiring SE.

[0476] Next, data D2 supplied to the wiring SD is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the wiring PCK and is output to the wiring Q. Then, the potential L is supplied to the wiring RV[1].

[0477] In period T826, first, by supplying potential H to wiring RV[2], data D3 stored in wiring SN[2] of holding circuit 831[2] is supplied to wiring SD. Furthermore, data D6 is supplied to wiring D, but by supplying potential H to wiring SE, wiring SD is selected.

[0478] Next, data D3 supplied to wiring SD is stored in scan flip-flop circuit 850 in synchronization with the rising edge of wiring PCK and output to wiring Q. Then, potential L is supplied to wiring RV[2], and potential L is supplied to wiring SE.

[0479] In period T827, data D7 supplied to wiring D is stored in the scan flip-flop circuit 850 in synchronization with the rising edge of the signal supplied to wiring PCK and is output to wiring Q.

[0480] Thus, the semiconductor device 810 can be Figure 19 Thus, when processing is performed in a state where multiple tasks are switched in the electronic computer 900, for example, data of the interrupted task can be saved and data of the resumed task can be loaded.

[0481] This embodiment mode can be combined with other embodiment modes as appropriate. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be combined as appropriate.

[0482] (Implementation Method 2) In this embodiment, an example of an arithmetic processing device that can include the storage device 720 according to one embodiment of the present invention will be described.

[0483] Figure 21 It is a block diagram of the computing device 960. Figure 21 The computing device 960 shown can be used, for example, as a CPU. Furthermore, the computing device 960 can also be used as a processor such as a GPU, a TPU (Tensor Processing Unit), or an NPU (Neural Processing Unit), which includes more (tens to hundreds) processor cores capable of parallel processing than a CPU.

[0484] Figure 21The illustrated computing device 960 includes an ALU 991 (Arithmetic Logic Unit, arithmetic logic unit), an ALU controller 992, an instruction decoder 993, an interrupt controller 994, a timing controller 995, registers 996, a register controller 997, a bus interface 998, a cache 999, and a cache interface 989 on a substrate 990. Substrate 990 may be a semiconductor substrate, an SOI substrate, a glass substrate, or the like. A rewritable ROM and a ROM interface may also be included. Cache 999 and cache interface 989 may also be provided on separate chips.

[0485] The cache memory 999 is connected to the main memory provided on a different chip via the cache interface 989. The cache interface 989 has the function of supplying part of the data held in the main memory to the cache memory 999. The cache interface 989 also has the function of outputting part of the data held in the cache memory 999 to the ALU 991, register 996, or the like via the bus interface 998.

[0486] As described later, the memory array 721 may be provided in a stacked manner on the computing device 960. The memory array 721 may be used as a cache memory. In this case, the cache memory interface 989 may have a function of supplying data stored in the memory array 721 to the cache memory 999. In this case, it is preferable that a driver circuit 722 be included as part of the cache memory interface 989.

[0487] Note that the cache memory 999 may not be provided and only the memory array 721 may be used as a cache memory.

[0488] Figure 21 The computing device 960 shown is only an example of a simplified structure, so the actual computing device 960 has various structures depending on its use. For example, it is preferable to use a computing device including Figure 21 The structure of the computing device 960 shown is a so-called multi-core structure in which a plurality of cores are provided for one core and are operated simultaneously. The more cores there are, the higher the computing performance can be. The more cores there are, the more preferred it is, for example, preferably 2, more preferably 4, further preferably 8, further preferably 12, and further preferably 16 or more. In addition, when very high computing performance is required, such as when used in a server, it is preferred to adopt a multi-core structure including 16 or more cores, preferably 32 or more, and more preferably 64 or more cores. In addition, the number of bits that can be processed in the internal computing circuit, data bus, etc. of the computing device 960 can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.

[0489] The instructions input to the operation device 960 through the bus interface 998 are input to the instruction decoder 993 and decoded, and then input to the ALU controller 992, the interrupt controller 994, the register controller 997, and the timing controller 995.

[0490] The ALU controller 992, interrupt controller 994, register controller 997, and timing controller 995 perform various controls based on decoded instructions. Specifically, the ALU controller 992 generates signals to control the operation of the ALU 991. Furthermore, while the arithmetic unit 960 is executing a program, the interrupt controller 994 identifies interrupt requests from external input / output devices, peripheral circuits, etc. based on their priority, mask status, and other factors, and processes these requests. The register controller 997 generates the address of the register 996 and reads or writes to the register 996 based on the state of the arithmetic unit 960.

[0491] Furthermore, the timing controller 995 generates signals for controlling the operation timing of the ALU 991, the ALU controller 992, the instruction decoder 993, the interrupt controller 994, and the register controller 997. For example, the timing controller 995 includes an internal clock generator that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.

[0492] exist Figure 21 In the illustrated arithmetic device 960, register controller 997 selects a hold operation for register 996 based on instructions from ALU 991. In other words, register controller 997 selects whether data is held in the memory cells of register 996 by flip-flops or by capacitors. If data is held by flip-flops, power supply voltage is supplied to the memory cells in register 996. If data is held by capacitors, data is rewritten to the capacitors, and the supply of power supply voltage to the memory cells in register 996 may be stopped.

[0493] The memory array 721 and the computing device 960 may be arranged in an overlapping manner. Figure 22A and Figure 22B This is a perspective view of a semiconductor device 970A. The semiconductor device 970A includes a layer 933 on which a memory array is provided on a computing device 960. The layer 933 includes a memory array 721L1, a memory array 721L2, and a memory array 721L3. The computing device 960 and the memory arrays have overlapping areas. To facilitate understanding of the structure of the semiconductor device 970A, Figure 22B The computing device 960 and the layer 933 are shown separately in FIG.

[0494] By overlapping the memory array layer 933 and the computing device 960, the distance between them can be shortened. This increases the communication speed between them. Furthermore, the shorter distance reduces power consumption.

[0495] The following methods can be used to stack the memory array layer 933 and the computing device 960: directly stacking the memory array layer 933 on the computing device 960 (also known as monolithic stacking); or forming the computing device 960 and layer 933 on separate substrates, bonding the two substrates together, and electrically connecting them using through-hole bonding or conductive film bonding techniques (such as Cu-Cu bonding). The former method eliminates the need to consider misalignment during bonding, thus reducing chip size and manufacturing costs.

[0496] Here, the computing device 960 may not include the cache 999, and the memory array 721L1, memory array 721L2, and memory array 721L3 provided in the layer 933 may all be used as caches. In this case, for example, the memory array 721L1, memory array 721L2, and memory array 721L3 may be used as an L1 cache (also known as a first-level cache), an L2 cache (also known as a second-level cache), and an L3 cache (also known as a third-level cache), respectively. Of the three memory arrays, the memory array 721L3 has the largest capacity and the lowest access frequency. Furthermore, the memory array 721L1 has the smallest capacity and the highest access frequency.

[0497] Note that when the cache 999 provided in the computing device 960 is used as an L1 cache, each memory array provided in the layer 933 can be used as a lower-level cache or a main memory. The main memory is a memory having a larger capacity and a lower access frequency than the cache.

[0498] In addition, if Figure 22B As shown, a driver circuit 722L1, a driver circuit 722L2, and a driver circuit 722L3 are provided. Driver circuit 722L1 is connected to memory array 721L1 via connection electrode 940L1. Similarly, driver circuit 722L2 is connected to memory array 721L2 via connection electrode 940L2, and driver circuit 722L3 is connected to memory array 721L3 via connection electrode 940L3.

[0499] Note that although the case where three memory arrays are used as cache memory is shown here, the number may be one, two, or four or more.

[0500] When the memory array 721L1 is used as a cache, the driver circuit 722L1 can be used as part of the cache interface 989 or can be connected to the cache interface 989. Similarly, the driver circuits 722L2 and 722L3 can also be used as part of the cache interface 989 or can be connected to a part of the cache interface 989.

[0501] Whether the memory array 721 is used as a cache or a main memory depends on the control circuit 772 included in each driver circuit 722. The control circuit 772 can use part of the plurality of memory cells 741 included in the memory device 720 as RAM based on a signal supplied from the arithmetic device 960.

[0502] In the storage device 720, some of the multiple storage units 741 can be used as cache and others as main memory. In other words, the storage device 720 can function as both a cache and a main memory. The storage device 720 according to one embodiment of the present invention can be used as a general-purpose memory, for example.

[0503] Alternatively, a layer 933 including one memory array 721 may be provided so as to overlap with the computing device 960 . Figure 23A It is a perspective view of the semiconductor device 970B.

[0504] In the semiconductor device 970B, one memory array 721 can be divided into a plurality of areas, and different functions can be assigned to the plurality of areas for use. Figure 23A An example is shown in which the area L1, the area L2, and the area L3 are used as an L1 cache, an L2 cache, and an L3 cache, respectively.

[0505] Furthermore, in semiconductor device 970B, the capacity of each of regions L1 through L3 can be adjusted depending on the situation. For example, to increase the capacity of the L1 cache, this can be achieved by increasing the area of ​​region L1. This configuration improves processing efficiency and increases processing speed.

[0506] Furthermore, a plurality of memory arrays may be stacked. Figure 23B It is a perspective view of a semiconductor device 970C.

[0507] The semiconductor device 970C is stacked with a layer 933L1 including a memory array 721L1, a layer 933L2 above it including a memory array 721L2, and a layer 933L3 above it including a memory array 721L3. The memory array 721L1, which is physically closest to the computing device 960, can be used as an upper-level cache, while the memory array 721L3, which is farthest from the computing device 960, can be used as a lower-level cache or main memory. This structure increases the capacity of each memory array, thereby further improving processing capabilities.

[0508] This embodiment mode can be combined with other embodiment modes as appropriate.

[0509] (Implementation 3) In this embodiment, an application example of a storage device according to one embodiment of the present invention will be described.

[0510] Generally speaking, various memory devices are used in semiconductor devices such as computers according to their applications. Figure 24A Various memory devices used in semiconductor devices are shown in a hierarchical manner. Memory devices in the upper layers are required to have faster operating speeds, while memory devices in the lower layers are required to have larger storage capacities and higher recording densities. Figure 24A In the example, from the top layer, it includes memory installed as registers in arithmetic processing devices such as a CPU, L1 cache, L2 cache, L3 cache, main memory, storage, etc. Note that although the example includes up to L3 cache, it can also include lower-level caches.

[0511] Because memory, incorporated as registers in a CPU or other processing unit, is used to temporarily store computation results, it is frequently accessed by the processing unit. Consequently, faster operating speed is required over storage capacity. Registers also hold configuration information for the processing unit.

[0512] Cache memory copies and stores a portion of the information stored in main memory. By copying and storing frequently used data in the cache, data access speed can be improved. While cache memory requires less storage capacity than main memory, it requires a higher operating speed. Furthermore, data that has been overwritten in the cache memory is copied and stored in main memory.

[0513] The main memory has a function of holding programs, data, and the like read from storage.

[0514] Storage is used to store data that requires long-term preservation and various programs used by processing devices. Therefore, storage requires large storage capacity and high recording density over operating speed. For example, high-capacity nonvolatile storage devices such as 3D NAND can be used.

[0515] A storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long time. Figure 24A As shown, the storage device according to one embodiment of the present invention can be applied to both a hierarchy including cache and a hierarchy including main memory. In addition, the storage device according to one embodiment of the present invention can also be used in a hierarchy including storage.

[0516] also, Figure 24B An example is shown in which an SRAM is used for a part of the cache and an OS memory according to one embodiment of the present invention is used for the other part.

[0517] The cache at the lowest level can be called an LLC (Last Level Cache). The LLC does not need to operate faster than the cache above it, but preferably has a larger storage capacity. The OS memory of one embodiment of the present invention has a fast operating speed and can retain data for a long time, so it is suitable for use in the LLC. Note that the OS memory of one embodiment of the present invention can also be used for the FLC (Final Level Cache).

[0518] For example, Figure 24B As shown in FIG. 1 , SRAM can be used for upper level cache (L1 cache, L2 cache, etc.) and the OS memory of one embodiment of the present invention can be used for LLC. Figure 24B As shown, DRAM can be used in addition to the OS memory as the main memory.

[0519] This embodiment mode can be combined with other embodiment modes as appropriate.

[0520] (Implementation 4) In this embodiment, an example of a method for manufacturing a memory device according to one embodiment of the present invention is described with reference to the drawings.

[0521] <Example of Method for Manufacturing Memory Device> Next, a method for manufacturing a memory device according to one embodiment of the present invention will be described. Figures 5A to 6 An example of a method for manufacturing a memory device is shown.

[0522] Figure 25A 、 Figure 27A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 35A 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 47A and Figure 49A Shown is a plan view. In addition, Figure 25B 、 Figure 27B 、 Figure 29B 、 Figure 31B 、 Figure 33B 、 Figure 35B 、 Figure 37B 、 Figure 39B 、 Figure 41B 、 Figure 43B 、 Figure 45B 、 Figure 47B and Figure 49B are respectively corresponding to the Figure 25A 、 Figure 27A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 35A 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 47A and Figure 49A A cross-sectional view of the portion of the dot-dash line A1-A2. Figure 25C 、 Figure 27C 、 Figure 29C 、 Figure 31C 、 Figure 33C 、 Figure 35C 、 Figure 37C 、 Figure 39C 、 Figure 41C 、 Figure 43C 、 Figure 45C 、 Figure 47C and Figure 49C are respectively corresponding to the Figure 25A 、 Figure 27A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 35A 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 47A and Figure 49A A cross-sectional view of the portion of the dot-dash line A3-A4. Figure 26 、 Figure 28 、 Figure 30 、 Figure 32 、 Figure 34 、 Figure 36 、 Figure 38 、 Figure 40 、 Figure 42 、 Figure 44 、 Figure 46 、 Figure 48 and Figure 50 are respectively corresponding to the Figure 25A 、 Figure 27A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 35A 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 47A and Figure 49A Note that for ease of understanding, Figure 25A 、 Figure 27A 、 Figure 29A 、 Figure 31A 、 Figure 33A 、 Figure 35A 、 Figure 37A 、 Figure 39A 、 Figure 41A 、 Figure 43A 、 Figure 45A 、 Figure 47A and Figure 49A Some components are omitted in the plan view.

[0523] Next, an insulating material for forming an insulator, a conductive material for forming a conductor, or a semiconductor material for forming a semiconductor can be deposited using a deposition method such as sputtering, CVD, MBE, PLD, or ALD as appropriate.

[0524] Note that examples of sputtering methods include RF sputtering, which uses a high-frequency power source for the sputtering power supply; DC sputtering, which utilizes a direct current power source; and pulsed DC sputtering, which varies the voltage applied to the electrode in a pulsed manner. RF sputtering is primarily used for depositing insulating films, while DC sputtering is primarily used for depositing metallic conductive films. Furthermore, pulsed DC sputtering is primarily used for depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0525] Note that CVD methods can be categorized into plasma CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD (photo CVD) using light. Furthermore, CVD methods can be further categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0526] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce the plasma damage caused to the object to be processed. For example, the wiring, electrodes and components (transistors, capacitors, etc.) included in the storage device sometimes generate charge accumulation due to receiving charges from the plasma. At this time, the wiring, electrodes or components included in the storage device are sometimes damaged due to the accumulated charge. On the other hand, since the above-mentioned plasma damage does not occur when the thermal CVD method without plasma is used, the yield of the storage device can be improved. In addition, in the thermal CVD method, plasma damage is not generated during deposition, so a film with fewer defects can be obtained.

[0527] As the ALD method, a thermal ALD method in which a precursor and a reactant react using only thermal energy, a PEALD method using a reactant excited by plasma, or the like can be used.

[0528] CVD and ALD differ from sputtering, which deposits particles released from a target material. Therefore, ALD is a deposition method that is less affected by the shape of the object being processed and exhibits excellent step coverage. In particular, ALD exhibits excellent step coverage and thickness uniformity, making it suitable for coating surfaces with openings having high aspect ratios. However, ALD has a relatively slow deposition rate, making it sometimes preferable to combine it with other deposition methods, such as CVD, which have faster deposition rates.

[0529] Furthermore, when using CVD, films of arbitrary compositions can be deposited depending on the source gas flow ratio. For example, by varying the source gas flow ratio while deposition is performed, films with continuously varying compositions can be deposited. When deposition is performed while varying the source gas flow ratio, the time required for transfer and pressure adjustment is eliminated, thus shortening the deposition time compared to deposition using multiple deposition chambers. Consequently, the productivity of storage devices can sometimes be improved.

[0530] When using the ALD method, a film of any composition can be deposited by simultaneously introducing multiple different precursors. Alternatively, when introducing multiple different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0531] First, a substrate (not shown) is prepared, and an insulating layer 101 is formed on the substrate. Any of the above-mentioned insulating materials can be used as appropriate for the insulating layer 101. The insulating layer 101 can be formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0532] Next, a conductive layer 111a ( Figures 25A to 26 For example, the conductive layer 111a can be formed by forming a conductive film to be the conductive layer 111a and processing the conductive film. The conductive material that can be used for the conductive layer 111a described above can be appropriately used as the conductive film to be the conductive layer 111a.

[0533] The conductive film to become the conductive layer 111a can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD, as appropriate. For example, the conductive film to become the conductive layer 111a can be formed by sequentially depositing tungsten and titanium nitride using CVD. After the conductive film to become the conductive layer 111a is formed, it can be patterned using, for example, photolithography, and then processed using dry etching or wet etching according to the pattern to form the conductive layer 111a. Dry etching is preferred because it allows for microfabrication of the conductive film.

[0534] Note that in lithography, first, a resist is exposed through a mask. Then, a developer is used to remove or leave the exposed areas to form a resist mask. Thus, a pattern is formed.

[0535] For example, a resist can be exposed to form a resist mask using a KrF excimer laser, an ArF excimer laser or EUV light. In addition, an immersion technique in which exposure is performed in a state where a liquid (e.g., water) is filled between the substrate and the projection lens can also be utilized. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, a mask is not required. In addition, the resist mask can be removed by performing a dry etching process such as ashing, performing a wet etching process, performing a wet etching process after performing a dry etching process, or performing a dry etching process after performing a wet etching process.

[0536] Then, etching is performed through the resist mask, thereby processing the conductive layer, semiconductor layer, insulating layer, etc. into a desired shape.

[0537] When dry etching is performed as the etching process, an etching gas containing a halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. For example, the etching gas can be one or a mixture of two or more of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, NF3 gas, CHF3 gas, Cl2 gas, BCl3 gas, SiCl4 gas, CCl4 gas, and BBr3 gas. Furthermore, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or hydrocarbon gas can be added to the etching gas as appropriate. Etching conditions can be appropriately set depending on the etching target.

[0538] As a dry etching device, for example, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0539] Next, an insulating layer 103a serving as an interlayer insulating layer is formed on the insulating layer 101 and the conductive layer 111a. The insulating layer 103a can be formed using any of the above-mentioned insulating materials as appropriate. The insulating layer 103a can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. For example, a silicon oxide film can be deposited as the insulating layer 103a using sputtering. Furthermore, the insulating layer 103a is preferably subjected to chemical mechanical polishing (CMP) after deposition to flatten its top surface. By performing the planarization treatment on the insulating layer 103a, the conductive layer 112a, which serves as the other of the source and drain electrodes of the transistor 41, can be smoothly formed in a subsequent step. Alternatively, after depositing aluminum oxide on the insulating layer 103a using sputtering, a CMP treatment can be performed until the insulating layer 103a is reached. This CMP treatment can flatten and smooth the surface of the insulating layer 103a. By placing this aluminum oxide on the insulating layer 103 a and performing CMP treatment, the end point of the CMP treatment can be easily detected.

[0540] Note that CMP treatment may not be performed. In this case, the top surface of the insulating layer 103a has a convex curved surface. By not performing planarization treatment, manufacturing costs can be reduced and the yield can be improved.

[0541] Alternatively, a recess may be provided in the insulating layer 101, and the conductive layer 111a may be formed to fill the recess. After the insulating layer 101 and the conductive layer 111a are formed so that the top surface height is substantially the same, the insulating layer 103a may be formed on the insulating layer 101 and the conductive layer 111a.

[0542] By depositing the insulating layer 103a by sputtering in an oxygen-containing atmosphere, the insulating layer 103a can be formed to contain excess oxygen. Furthermore, by utilizing a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 103a can be reduced. Depositing the insulating layer 103a in this manner allows oxygen to be supplied from the insulating layer 103a to the channel formation region of the semiconductor layer 113a formed in a subsequent step, thereby reducing oxygen vacancies and VoH.

[0543] Next, a conductive film 112A (which will later become a conductive layer 112a) is formed on the insulating layer 103a. Figures 27A to 28 ) The conductive film 112A can appropriately use a conductive material that can be used for the above-described conductive layer 112. The conductive film 112A can be appropriately formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0544] Next, a portion of the conductive film 112A and a portion of the insulating layer 103a are processed to form an opening 121a ( 29A to 30 The opening 121a can be formed by, for example, photolithography and etching. Through this processing, a conductive layer 112f including an opening is formed using the conductive film 112A.

[0545] Here, the sidewalls of the opening 121a are preferably perpendicular to the top surface of the conductive layer 111a. This structure allows for miniaturization or high integration of the memory device. Furthermore, the sidewalls of the opening 121a may also have a tapered shape. The tapered sidewalls of the opening 121a improve coverage with, for example, the metal oxide film that will become the semiconductor layer 113a, which will be described later, and can reduce defects such as voids.

[0546] The maximum width of the opening 121a (the diameter of the opening 121a when viewed from a plane and formed into a circle) is preferably small. For example, the maximum width of the opening 121a is preferably 1 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, or 5 nm to 20 nm.

[0547] Because the aspect ratio of the opening 121a is high, it is preferable to process a portion of the conductive film 112A and a portion of the insulating layer 103a using anisotropic etching. Dry etching is particularly preferred because it is suitable for microfabrication. Furthermore, these processes can be performed under different conditions. Note that depending on the processing conditions for a portion of the conductive film 112A and a portion of the insulating layer 103a, the inclination of the side surface of the conductive layer 112f within the opening 121a may differ from the inclination of the side surface of the insulating layer 103a within the opening 121a.

[0548] Next, heat treatment may be performed. The heat treatment can be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment can be performed, for example, under a nitrogen or inert gas atmosphere. The heat treatment can also be performed under reduced pressure. This heat treatment can reduce impurities such as water in the insulating layer 103a and the like before depositing the metal oxide film that will become the semiconductor layer 113a, described later.

[0549] Furthermore, the gas used in the heat treatment is preferably highly purified. For example, the water content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. Using highly purified gas for the heat treatment can minimize water absorption by the insulating layer 103a, for example.

[0550] Next, conductive layer 112f is processed to form conductive layer 112a so that it has a region overlapping with conductive layer 111a when viewed from above. For example, conductive layer 112a can be formed by forming a pattern using photolithography and processing conductive layer 112f using dry etching or wet etching according to the pattern. Dry etching is preferred because it allows for fine processing of conductive layer 112f.

[0551] Next, a metal oxide film, which will later become the semiconductor layer 113a, is formed in contact with the top surface of the conductive layer 112a, the side surfaces of the conductive layer 112a within the opening 121a, the side surfaces of the insulating layer 103a within the opening 121a, and the top surface of the conductive layer 111a within the opening 121a. The metal oxide film that will become the semiconductor layer 113a can be formed using any of the metal oxides that can be used for the aforementioned semiconductor layer 113. The metal oxide film that will become the semiconductor layer 113a can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film that will become the semiconductor layer 113a is preferably formed in contact with the side surfaces of the conductive layer 112a, the side surfaces of the insulating layer 103a, and the top surface of the conductive layer 111a within the opening 121a having a large aspect ratio. Therefore, the metal oxide film that will become the semiconductor layer 113a is preferably formed using a deposition method with good coverage, more preferably using CVD or ALD. For example, as a metal oxide film to be the semiconductor layer 113 a , In—Ga—Zn oxide is deposited by an ALD method.

[0552] Note that when the sidewall of the opening 121a has a tapered shape, the method for depositing the metal oxide film to be the semiconductor layer 113a is not limited to the CVD method or the ALD method. For example, sputtering may be used.

[0553] Furthermore, when the semiconductor layer 113a has a stacked-layer structure, the deposition methods of the various layers included in the semiconductor layer 113a may be the same or different. For example, when the semiconductor layer 113a has a two-layer stacked-layer structure, the lower layer of the metal oxide film that will become the semiconductor layer 113a may be deposited using sputtering, and the upper layer may be deposited using ALD. Metal oxide films deposited using sputtering tend to have crystallinity. Therefore, by providing a crystalline metal oxide film as the lower layer of the metal oxide film that will become the semiconductor layer 113a, the crystallinity of the upper layer can be improved. Furthermore, even if pinholes or breaks are formed in the lower layer of the metal oxide film deposited using sputtering, the portions overlapping these pinholes or breaks can be filled with the upper layer of the metal oxide film deposited using ALD, which provides good coverage.

[0554] Here, the metal oxide film to become the semiconductor layer 113a is preferably formed so as to be in contact with the top surface of the conductive layer 111a within the opening 121a, the side surfaces of the insulating layer 103a within the opening 121a, the side surfaces of the conductive layer 112a within the opening 121a, and the top surface of the conductive layer 112a. By forming this metal oxide film in contact with the conductive layer 111a, the conductive layer 111a serves as one of the source electrode and the drain electrode of the transistor 41.

[0555] Next, heat treatment is preferably performed. The heat treatment can be performed within a temperature range that does not cause polycrystallization of the metal oxide film to become the semiconductor layer 113a. The heat treatment can be performed at a temperature of 250°C to 650°C, preferably 400°C to 600°C. For details of the heat treatment, refer to the above description.

[0556] Here, the metal oxide film to become the semiconductor layer 113a is preferably subjected to the above-described heat treatment while being placed in contact with the insulating layer 103a containing excess oxygen. This heat treatment allows oxygen to be supplied from the insulating layer 103a to the metal oxide film to become the semiconductor layer 113a, thereby reducing oxygen vacancies and VoH in the semiconductor layer 113a to be formed later.

[0557] Note that in the above description, the heat treatment is performed after the metal oxide film to be the semiconductor layer 113a is deposited, but the present invention is not limited to this. Furthermore, the heat treatment may be performed in a later step.

[0558] Next, the metal oxide film to be the semiconductor layer 113a is processed to form the semiconductor layer 113a ( Figures 31A to 32). For example, after the metal oxide film that will become the semiconductor layer 113a is patterned using lithography, it is processed using etching according to the pattern. In this way, the semiconductor layer 113a can be formed in a manner having a region overlapping with the opening 121a. As a result, a portion of the semiconductor layer 113a is formed in the opening 121a. In addition, the semiconductor layer 113a is in contact with the top surface of the conductive layer 112a. In this way, the semiconductor layer 113a is formed to have the following regions: a region in the opening 121a that is in contact with the top surface of the conductive layer 111a; a region in the opening 121a that is in contact with the side surface of the insulating layer 103a; a region in the opening 121a that is in contact with the side surface of the conductive layer 112a; and a region in contact with the top surface of the conductive layer 112a.

[0559] Notice, Figure 31A and Figure 31B In the example shown, the end of the semiconductor layer 113a is substantially aligned with the end of the conductive layer 112a in the X direction, but the present invention is not limited to this. The end of the semiconductor layer 113a may be located inward of the end of the conductive layer 112a in the X direction. Furthermore, the end of the semiconductor layer 113a may be located outward of the end of the conductive layer 112a in the X direction, and the bottom surface of the semiconductor layer 113a may be in contact with the side surface of the conductive layer 112a that does not face the opening 121a and the top surface of the insulating layer 103a.

[0560] In addition, the above description is based on the case where the semiconductor layer 113a is formed after the conductive layer 112a is formed, but the present invention is not limited thereto. For example, in one embodiment of the present invention, the semiconductor layer 113a may be formed after the opening 121a is formed ( 29A to 30 ) forms a metal oxide film which will become the semiconductor layer 113a, the metal oxide film is processed to form the semiconductor layer 113a, and then the conductive layer 112f is processed to form the conductive layer 112a.

[0561] Next, an insulating layer 105a ( Figures 33A to 34 ). The insulating layer 105a can be formed using any of the above-mentioned insulating materials as appropriate. The insulating layer 105a can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. Here, the insulating layer 105a is preferably formed in contact with the top surface of the semiconductor layer 113a within the opening 121a having a large aspect ratio. Therefore, the insulating layer 105a is preferably deposited using a deposition method with good coverage, more preferably using CVD or ALD. For example, silicon oxide is deposited using ALD as the insulating layer 105a.

[0562] Note that when the sidewall of the opening 121a has a tapered shape, the deposition method of the insulating layer 105a is not limited to the CVD method or the ALD method. For example, a sputtering method may also be used.

[0563] By forming insulating layer 105a after semiconductor layer 113a, the side edges of semiconductor layer 113a are covered by insulating layer 105a. This prevents short circuits between semiconductor layer 113a and conductive layer 115a, which is formed in a subsequent step. Furthermore, with the above-described structure, the side edges of conductive layer 112a are covered by insulating layer 105a. This prevents short circuits between conductive layer 112a and conductive layer 115a.

[0564] Next, a conductive film to become the conductive layer 115a is formed on the insulating layer 105a in such a manner as to fill the opening 121a. The conductive film to become the conductive layer 115a can be formed using any conductive material that can be used for the conductive layer 115. The conductive film to become the conductive layer 115a can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD. The conductive film to become the conductive layer 115a is preferably formed so as to be in contact with the insulating layer 105a provided in the opening 121a having a high aspect ratio. Therefore, when forming the conductive film to become the conductive layer 115a, a deposition method with good coverage or embedding properties is preferably used, and CVD, ALD, or the like is more preferred.

[0565] Note that when the conductive film to be the conductive layer 115a is formed by CVD, the average surface roughness of the top surface of the conductive film may become large. In this case, the conductive film is preferably planarized by CMP. In this case, a silicon oxide film or a silicon oxynitride film may be deposited on the conductive film before CMP, and CMP may be performed until the silicon oxide film or silicon oxynitride film is removed. Alternatively, CMP may not be performed.

[0566] Note that in the above description, the conductive film to become the conductive layer 115a is provided so as to fill the opening 121a, but the present invention is not limited to this. For example, a recessed portion reflecting the shape of the opening 121a may be formed in the upper portion of the conductive film to become the conductive layer 115a. Alternatively, the recessed portion may be filled with, for example, an inorganic insulating material. Alternatively, the recessed portion may not be filled with an inorganic insulating material.

[0567] Next, a portion of the conductive film to be the conductive layer 115a is processed to form the conductive layer 115a ( Figures 35A to 36 The conductive layer 115a can be formed, for example, by forming a pattern using lithography and then etching the conductive film to be the conductive layer 115a according to the pattern. This etching can be performed using dry etching or wet etching, with dry etching being preferred because it is suitable for microfabrication. The conductive layer 115a is formed on the insulating layer 105a so as to have a region overlapping with the semiconductor layer 113a.

[0568] Through the above steps, the transistor 41 including the conductive layer 111 a , the conductive layer 112 a , the semiconductor layer 113 a , the insulating layer 105 a , and the conductive layer 115 a can be formed.

[0569] As described above, the conductive layer 111a serves as one of the source electrode and the drain electrode of the transistor 41. The conductive layer 112a serves as the other of the source electrode and the drain electrode of the transistor 41. The insulating layer 105a serves as a gate insulating layer of the transistor 41. The conductive layer 115a serves as a gate electrode of the transistor 41.

[0570] Next, an insulating layer 107a is formed to cover the conductive layer 115a and the insulating layer 105a. Then, an insulating layer 135 is formed over the insulating layer 107a. The insulating layer 107a and the insulating layer 135 can each use the insulating materials described above for the insulating layer 107 and the insulating layer 135, as appropriate. The insulating layer 107a and the insulating layer 135 can be formed using a deposition method such as sputtering, CVD, MBE, PLD, or ALD, as appropriate.

[0571] Next, a conductive film 141f (which will later become the conductive layer 141) is formed on the insulating layer 135. Figures 37A to 38 ) The conductive film 141f can appropriately use a conductive material that can be used for the above-mentioned conductive layer 141. The conductive film 141f can be appropriately formed by a deposition method such as sputtering, CVD, MBE, PLD, or ALD.

[0572] Next, the conductive film 141f is processed so as to have a region overlapping with the conductive layer 115a when viewed from above, forming the conductive layer 141 ( Figures 39A to 40 Conductive layer 141 can be formed, for example, by forming a pattern using lithography and then etching the conductive film 141f according to the pattern. This etching can be performed using dry etching or wet etching, with dry etching being preferred due to its suitability for microfabrication. Conductive layer 141 is formed so as to be spaced apart from opening 121a when viewed from above.

[0573] Next, an insulating layer 103b serving as an interlayer insulating layer is formed over the conductive layer 141 and the insulating layer 135. The insulating layer 103b can be formed using the same material and method as the insulating layer 103a described above. Furthermore, the insulating layer 103b is preferably subjected to a CMP treatment after deposition to flatten its top surface. By flattening the insulating layer 103b, the conductive layer 112b serving as the other of the source and drain electrodes of the transistor 42 can be smoothly formed in a subsequent step.

[0574] Note that CMP treatment may not be performed. In this case, the top surface of the insulating layer 103b has a convex curved surface. By not performing planarization treatment, manufacturing costs can be reduced and the yield can be improved.

[0575] By depositing the insulating layer 103b using a sputtering method in an oxygen-containing atmosphere, the insulating layer 103b can be formed to contain excess oxygen. Furthermore, by utilizing a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating layer 103b can be reduced. Depositing the insulating layer 103b in this manner allows oxygen to be supplied from the insulating layer 103b to the channel formation region of the semiconductor layer 113b to be formed in a subsequent step, thereby reducing oxygen vacancies and VoH.

[0576] Next, a conductive film 112B (which will later become a conductive layer 112b) is formed on the insulating layer 103b. Figures 41A to 42 ). The conductive film 112B can be formed using the same material and method as the conductive film 112A described above.

[0577] Next, a portion of the conductive film 112B, a portion of the insulating layer 103b, a portion of the insulating layer 135, and a portion of the insulating layer 107a are processed to form an opening 121b ( Figures 43A to 44 The opening 121b can be formed by the same method as the above-mentioned method for forming the opening 121a. Through this processing, the conductive layer 112s having an opening can be formed from the conductive film 112B.

[0578] Here, the sidewalls of the opening 121b are preferably perpendicular to the top surface of the conductive layer 115a. This structure allows for miniaturization or high integration of the storage device. Alternatively, the sidewalls of the opening 121b may have a tapered shape. By tapering the sidewalls of the opening 121b, for example, the coverage of the metal oxide film, which will become the semiconductor layer 113b described later, can be improved, thereby reducing defects such as voids.

[0579] The maximum width of the opening 121b (the diameter of the opening 121b when viewed from above and formed as a circle) is preferably small. For example, the maximum width of the opening 121b is preferably 1 nm to 60 nm, 5 nm to 50 nm, 5 nm to 40 nm, 5 nm to 30 nm, or 5 nm to 20 nm.

[0580] Since the aspect ratio of the opening 121b is large, it is preferable to process a portion of the conductive film 112B, a portion of the insulating layer 103b, a portion of the insulating layer 135, and a portion of the insulating layer 107a using anisotropic etching. Processing using a dry etching method is particularly preferred because it is suitable for micro-processing. In addition, the processing can also be performed under different conditions. Note that depending on the processing conditions of a portion of the conductive film 112B, a portion of the insulating layer 103b, a portion of the insulating layer 135, and a portion of the insulating layer 107a, the inclination of the side surface of the conductive layer 112s within the opening 121b, the inclination of the side surface of the insulating layer 103b within the opening 121b, the inclination of the side surface of the insulating layer 135 within the opening 121b, and the inclination of the side surface of the insulating layer 107a within the opening 121b may differ from each other.

[0581] Next, a heat treatment may be performed. For details of the heat treatment, refer to the description of the heat treatment that can be performed after the formation of the opening 121a described above. This heat treatment can reduce impurities such as water in the insulating layer 103b and the like before depositing the metal oxide film that will become the semiconductor layer 113b described later.

[0582] Next, conductive layer 112s is processed to form conductive layer 112b so that it has a region overlapping with conductive layer 115a when viewed from above. For example, conductive layer 112b can be formed by forming a pattern using photolithography and processing conductive layer 112s according to the pattern using dry etching or wet etching. Dry etching is preferred because it allows for microfabrication of conductive layer 112s.

[0583] Next, a metal oxide film, which will later become the semiconductor layer 113b, is formed in contact with the top surface of the ...

Claims

1. A semiconductor device comprising: a first transistor; a second transistor; capacitors; a first insulating layer; as well as The second insulating layer, The second transistor and the capacitor are both arranged overlappingly on the first transistor. The source electrode and the drain electrode of each of the first transistor and the second transistor are located at different heights relative to the substrate surface. The first insulating layer is disposed between a source electrode and a drain electrode of the first transistor and includes a first opening reaching one of the source electrode and the drain electrode of the first transistor. The other of the source electrode and the drain electrode of the first transistor is disposed on the first insulating layer, The semiconductor layer of the first transistor has a region in contact with a top surface of one of the source electrode and the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the other of the source electrode and the drain electrode of the first transistor in the first opening, and a top surface of the other of the source electrode and the drain electrode of the first transistor. The gate insulating layer of the first transistor is provided on the semiconductor layer of the first transistor in a manner of being in contact with the gate insulating layer. The gate electrode of the first transistor is provided on the gate insulating layer of the first transistor in a manner having a region overlapping with the semiconductor layer of the first transistor, and is used as one of the source electrode and the drain electrode of the second transistor and one electrode of the capacitor. The second insulating layer is disposed between the source electrode and the drain electrode of the second transistor and includes a second opening reaching the gate electrode of the first transistor. The other of the source electrode and the drain electrode of the second transistor is provided on the second insulating layer, The semiconductor layer of the second transistor has a region in contact with a top surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, a side surface of the other of the source electrode and the drain electrode of the second transistor in the second opening, and a top surface of the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer of the second transistor is provided on the semiconductor layer of the second transistor in a manner of being in contact with the gate insulating layer. The gate electrode of the second transistor is provided on the gate insulating layer of the second transistor in such a manner as to have a region overlapping with the semiconductor layer of the second transistor. The dielectric layer of the capacitor is disposed on the gate electrode of the first transistor, Furthermore, the other electrode of the capacitor is provided on the dielectric layer of the capacitor so as to have a region overlapping with the gate electrode of the first transistor and to be spaced apart from the second opening when viewed from a planar perspective.

2. The semiconductor device according to claim 1, At least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is a transistor including metal oxide.

3. The semiconductor device according to claim 1 or 2, A region in which a side surface of the semiconductor layer of the first transistor is substantially aligned with a side surface of the other of the source electrode and the drain electrode of the first transistor is provided, And there is a region where a side surface of the semiconductor layer of the second transistor is substantially aligned with a side surface of the other of the source electrode and the drain electrode of the second transistor.

4. The semiconductor device according to claim 1 or 2, An end portion of the other electrode of the capacitor that does not face the first opening is located outside an end portion of the gate electrode of the first transistor.

5. The semiconductor device according to claim 1 or 2, The other electrode of the capacitor is provided on both a first end portion of the gate electrode of the first transistor and a second end portion opposite to the first end portion.

6. The semiconductor device according to claim 1 or 2, The other electrode of the capacitor has a region overlapping with a top surface of the gate electrode of the first transistor in a manner surrounding the second opening.

7. The semiconductor device according to claim 1 or 2, The dielectric layer of the capacitor includes any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

8. The semiconductor device according to claim 1 or 2, The dielectric layer of the capacitor comprises any one of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium bismuth tantalate, bismuth ferrite and barium titanate.

9. The semiconductor device according to claim 1 or 2, The first insulating layer and the second insulating layer include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate and acrylic resin.

10. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer and a first conductive film on the first conductive layer; processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, and forming a first opening in the first conductive film and the first insulating layer that reaches the first conductive layer; processing the second conductive layer to form a third conductive layer; forming a first metal oxide film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the third conductive layer in the first opening, and a top surface of the third conductive layer; processing the first metal oxide film to form a first semiconductor layer having a region overlapping the first opening; forming a second insulating layer in contact with a top surface of the first semiconductor layer; forming a second conductive film on the second insulating layer; processing the second conductive film to form a fourth conductive layer having a region overlapping with the first semiconductor layer; forming a third insulating layer on the fourth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; processing the third conductive film to form a fifth conductive layer having a region overlapping with the fourth conductive layer; forming a fourth insulating layer and a fourth conductive film on the fifth conductive layer and the third insulating layer; processing the fourth insulating layer and the fourth conductive film to form a sixth conductive layer from the fourth conductive film, and forming a second opening in the fourth conductive film and the fourth insulating layer to reach the fourth conductive layer; processing the sixth conductive layer to form a seventh conductive layer; forming a second metal oxide film in contact with a top surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the seventh conductive layer in the second opening, and a top surface of the seventh conductive layer; processing the second metal oxide film to form a second semiconductor layer having a region overlapping the second opening; forming a fifth insulating layer in contact with a top surface of the second semiconductor layer; forming a fifth conductive film on the fifth insulating layer; as well as The fifth conductive film is processed to form an eighth conductive layer having a region overlapping with the second semiconductor layer.

11. A method for manufacturing a semiconductor device, comprising the following steps: forming a first conductive layer; forming a first insulating layer and a first conductive film on the first conductive layer; processing the first insulating layer and the first conductive film to form a second conductive layer from the first conductive film, and forming a first opening in the first conductive film and the first insulating layer that reaches the first conductive layer; forming a first metal oxide film in contact with a top surface of the first conductive layer in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the second conductive layer in the first opening, and a top surface of the second conductive layer; processing the first metal oxide film to form a first semiconductor layer having a region overlapping the first opening; processing the second conductive layer to form a third conductive layer having a region overlapping with the first semiconductor layer; forming a second insulating layer in contact with a top surface of the first semiconductor layer; forming a second conductive film on the second insulating layer; processing the second conductive film to form a fourth conductive layer having a region overlapping with the first semiconductor layer; forming a third insulating layer on the fourth conductive layer and the second insulating layer; forming a third conductive film on the third insulating layer; processing the third conductive film to form a fifth conductive layer having a region overlapping with the fourth conductive layer; forming a fourth insulating layer and a fourth conductive film on the fifth conductive layer and the third insulating layer; processing the fourth insulating layer and the fourth conductive film to form a sixth conductive layer from the fourth conductive film, and forming a second opening in the fourth conductive film and the fourth insulating layer to reach the fourth conductive layer; forming a second metal oxide film in contact with a top surface of the fourth conductive layer in the second opening, a side surface of the third insulating layer in the second opening, a side surface of the fourth insulating layer in the second opening, a side surface of the sixth conductive layer in the second opening, and a top surface of the sixth conductive layer; processing the second metal oxide film to form a second semiconductor layer having a region overlapping the second opening; processing the sixth conductive layer to form a seventh conductive layer having a region overlapping with the second semiconductor layer; forming a fifth insulating layer in contact with a top surface of the second semiconductor layer; forming a fifth conductive film on the fifth insulating layer; as well as The fifth conductive film is processed to form an eighth conductive layer having a region overlapping with the second semiconductor layer.

12. A semiconductor device comprising: Storage Department; as well as Processing Department, The storage unit includes a storage device and a sense amplifier. The processing unit includes a CPU, an MPU or a GPU, The sense amplifier and the processing unit are provided on the first layer. The memory device is configured on the second layer and includes a first transistor, a second transistor, a capacitor, a first insulating layer, and a second insulating layer. The second layer is stacked on the first layer, The second transistor and the capacitor are both arranged to overlap with the first transistor. The source electrode and the drain electrode of each of the first transistor and the second transistor are located at different heights relative to the substrate surface. The first insulating layer is disposed between a source electrode and a drain electrode of the first transistor and includes a first opening reaching one of the source electrode and the drain electrode of the first transistor. The other of the source electrode and the drain electrode of the first transistor is disposed on the first insulating layer, The semiconductor layer of the first transistor has a region in contact with a top surface of one of the source electrode and the drain electrode of the first transistor in the first opening, a side surface of the first insulating layer in the first opening, a side surface of the other of the source electrode and the drain electrode of the first transistor in the first opening, and a top surface of the other of the source electrode and the drain electrode of the first transistor. The gate insulating layer of the first transistor is provided on the semiconductor layer of the first transistor in a manner of being in contact with the gate insulating layer. The gate electrode of the first transistor is provided on the gate insulating layer of the first transistor in a manner having a region overlapping with the semiconductor layer of the first transistor, and is used as one of the source electrode and the drain electrode of the second transistor and one electrode of the capacitor. The second insulating layer is disposed between the source electrode and the drain electrode of the second transistor and includes a second opening reaching the gate electrode of the first transistor. The other of the source electrode and the drain electrode of the second transistor is provided on the second insulating layer, The semiconductor layer of the second transistor has a region in contact with a top surface of the gate electrode of the first transistor in the second opening, a side surface of the second insulating layer in the second opening, a side surface of the other of the source electrode and the drain electrode of the second transistor in the second opening, and a top surface of the other of the source electrode and the drain electrode of the second transistor. The gate insulating layer of the second transistor is provided on the semiconductor layer of the second transistor in a manner of being in contact with the gate insulating layer. The gate electrode of the second transistor is provided on the gate insulating layer of the second transistor in such a manner as to have a region overlapping with the semiconductor layer of the second transistor. The dielectric layer of the capacitor is disposed on the gate electrode of the first transistor, Furthermore, the other electrode of the capacitor is provided on the dielectric layer of the capacitor so as to have a region overlapping with the gate electrode of the first transistor and to be spaced apart from the second opening when viewed from a planar perspective.

13. The semiconductor device according to claim 12, At least one of the semiconductor layer of the first transistor and the semiconductor layer of the second transistor is a transistor including metal oxide.

14. The semiconductor device according to claim 12 or 13, A region in which a side surface of the semiconductor layer of the first transistor is substantially aligned with a side surface of the other of the source electrode and the drain electrode of the first transistor is provided, And there is a region where a side surface of the semiconductor layer of the second transistor is substantially aligned with a side surface of the other of the source electrode and the drain electrode of the second transistor.

15. The semiconductor device according to claim 12 or 13, An end portion of the other electrode of the capacitor that does not face the first opening is located outside an end portion of the gate electrode of the first transistor.

16. The semiconductor device according to claim 12 or 13, The other electrode of the capacitor is provided on both a first end portion of the gate electrode of the first transistor and a second end portion opposite to the first end portion.

17. The semiconductor device according to claim 12 or 13, The other electrode of the capacitor has a region overlapping with a top surface of the gate electrode of the first transistor in a manner surrounding the second opening.

18. The semiconductor device according to claim 12 or 13, The dielectric layer of the capacitor includes any one of aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

19. The semiconductor device according to claim 12 or 13, The dielectric layer of the capacitor comprises any one of hafnium oxide, zirconium oxide, lead titanate, barium strontium titanate, strontium titanate, lead zirconate titanate, strontium bismuth tantalate, bismuth ferrite and barium titanate.

20. The semiconductor device according to claim 12 or 13, The first insulating layer and the second insulating layer include any one of silicon oxide, silicon oxynitride, silicon nitride oxide, polyester, polyolefin, polyamide, polyimide, polycarbonate and acrylic resin.

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