Asynchronous integrating clear high dynamic infrared readout circuit

Abstract

The application belongs to the technical field of infrared detection, and provides a high-dynamic infrared readout circuit with asynchronous integration and zero reset, comprising a CTIA integration circuit, a gain control module, a capacitor reset module and an N-bit counter; wherein the CTLA integration circuit comprises a CTIA amplifier, a first capacitor, a second capacitor, a first switch tube and a second switch tube; the CTIA amplifier, the first capacitor, the second capacitor, the first switch tube and the second switch tube are connected in parallel; the first switch tube is connected in series on one side of the first capacitor; the output end of the CTIA integration circuit is connected to the input end of the gain control module, the output end of the gain control module is connected to the input end of the capacitor reset module, and the output end of the capacitor reset module is connected to the N-bit counter. The application can effectively improve the dynamic range of the readout circuit, enhance the infrared imaging quality, and be applied to linear array and area array infrared detectors in the future.

Description

Technical Field

[0001] This invention relates to the field of infrared detection technology, and in particular to a high dynamic infrared readout circuit with asynchronous integration and zeroing. Background Technology

[0002] Infrared focal plane arrays (IR FPAs) have been applied in defense and civilian fields, such as missile systems, search and tracking systems, and other tactical and strategic systems. The ability to detect temperatures at the mK level is an important direction for the development of high-sensitivity infrared focal plane arrays. Achieving this goal relies on infrared focal plane array readout circuits with larger charge capacity and higher dynamic range.

[0003] To meet the requirements of high dynamic range, several techniques based on integrating capacitors or integrating time control have been studied for a long time. The traditional approach involves using a larger integrating capacitor. The main problem with this method is that the size of the capacitor is limited by manufacturing processes and the area of ​​the unit circuit. Furthermore, when detecting distant targets, a large capacitor leads to high noise and very low signal levels.

[0004] On the other hand, some readout circuits for infrared focal plane arrays have two or three capacitors, which can be selected to suit the target conditions and applications to achieve the maximum signal-to-noise ratio (SNR). However, such readout circuits struggle to respond quickly and effectively to rapidly changing conditions because the capacitors of all pixels in the readout circuit are controlled by a uniform control signal. Summary of the Invention

[0005] This invention provides a high dynamic infrared readout circuit with asynchronous integral zeroing to solve the technical problems mentioned in the background art.

[0006] A high dynamic range infrared readout circuit with asynchronous integration and zeroing includes a CTIA integrator circuit, a gain control module, a capacitor reset module, and an N-bit counter. The CTIA integrator circuit includes a CTIA amplifier, a first capacitor, a second capacitor, a first switch, and a second switch. The second capacitor, a buffer, the first capacitor + the first switch, and the second switch are connected in parallel. The first switch is connected in series on one side of the first capacitor. The output of the CTIA integrator circuit is connected to the input of the gain control module, the output of the gain control module is connected to the input of the capacitor reset module, the output of the capacitor reset module is connected to one end of the second switch, and the output of the capacitor reset module is connected to an N-bit counter.

[0007] As a further technical solution of the present invention, the gain control module includes a voltage comparator, the non-inverting terminal of the voltage comparator is connected to the CTIA integrator circuit, the inverting terminal of the voltage comparator is connected to the voltage Vref, and the output terminal of the voltage comparator is connected to the capacitor reset module and the first switching transistor.

[0008] As a further technical solution of the present invention, the capacitor reset module includes two RS latches and a third... The device comprises a switching transistor, a D flip-flop, and a NAND gate. The third switching transistor is located between two RS latches. The output of the voltage comparator is connected to the input (S) of one RS latch, and the D flip-flop is connected to the output (Q) of the other RS ​​latch. The output of the D flip-flop is connected to the NAND gate.

[0009] As a further technical solution of the present invention, the first switching transistor, the second switching transistor and the third switching transistor are specifically MOSFETs.

[0010] As a further technical solution of the present invention, the first capacitor and the second capacitor are a large capacitor and a small capacitor, respectively.

[0011] The beneficial effects achieved by this invention are as follows: The photocurrent passes through the CTIA integrator circuit, which integrates the current value and converts it into a voltage V. When the current is small, the voltage is fully integrated onto the small capacitor. When the photocurrent is large, the capacitor is connected in parallel with the small capacitor, and the charge on the capacitor is redistributed. When the integration reaches the threshold voltage, the integrating capacitor is reset to zero and the integrated value is sent to the up counter.

[0012] This increases the integration time and the effective dynamic range. It can accommodate more charge capacity, making the integrated voltage less prone to saturation and enabling wide dynamic range integrated voltage readout. Attached Figure Description

[0013] Figure 1 This is a schematic diagram of a high dynamic infrared readout circuit with asynchronous integral clearing provided in an embodiment of the present invention.

[0014] Figure 2 This is a schematic diagram of the design principle of the gain control module and capacitor reset module provided in the embodiment of the present invention.

[0015] Figure 3 This is a schematic diagram of pixel integrated voltage. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to represent selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0017] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0018] Please see Figures 1 to 3 In the diagram, Cint is the integrating capacitor, GAIN is the output signal of the gain control module, Cap-Rset is the output signal of the capacitor reset module, Comparator is the voltage comparator, points S and R are the latch input terminals, and Q is the latch output terminal. This embodiment of the invention provides a high dynamic infrared readout circuit with asynchronous integration and zeroing, including a CTIA integrating circuit, a gain control module, a capacitor reset module, and an N-bit counter. The CTIA integrating circuit includes a CTIA amplifier (CTIA), a first capacitor (Large Cint), a second capacitor (Small Cint), a first switch (V1), and a second switch (V2). The second capacitor (Small Cint), the buffer (CTLA), the first capacitor (Large Cint), the first switch (V1), and the second switch (V2) are connected in parallel. The first switch (V1) is connected in series with the first capacitor (Large Cint). The CTIA integrator is connected to one side of the capacitor reset module; the output of the CTIA integrator is connected to the input of the gain control module, the output of the gain control module is connected to the input of the capacitor reset module, the output of the capacitor reset module is connected to one end of the second switch, and the output of the capacitor reset module is connected to an N-bit counter, where Count1 and Count2 are the counter output values.

[0019] In this embodiment, the gain control module includes a voltage comparator. (Comparator)'s non-inverting input terminal is connected to the CTIA integrating circuit, the inverting input terminal of the voltage comparator is connected to the voltage Vref, and the output terminal of the voltage comparator is connected to the capacitor reset module and the first switching transistor.

[0020] In this embodiment, the capacitor reset module includes two RS latches, a third switching transistor (V3), a D flip-flop (SET DFF), and a NAND gate. The third switching transistor (V3) is between the two RS latches. The output terminal of the voltage comparator is connected to the input terminal (S) of one side RS latch. The D flip-flop is connected to the output terminal (Q) of the other side RS latch. The output terminal of the D flip-flop is connected to the NAND gate. In the attached figure, points S and R are the input terminals of the latch, and Q is the output terminal of the latch.

[0021] In this embodiment, the first switching transistor (V1), the second switching transistor (V2), and the third switching transistor (V3) can specifically be MOS transistors.

[0022] In this embodiment, the first capacitor (Large Cint) and the second capacitor (Small Cint) are respectively a large capacitor (Large Cint) and a small capacitor (Small Cint).

[0023] In this embodiment, when the integrated voltage reaches the threshold value, the gain control module clears and latches it with a counter, extends the integration time of the effective target signal, and improves the signal-to-noise ratio of the focal plane.

[0024] In this embodiment, through the capacitor reset module and the N-bit counter, the integrated voltage reaching the threshold value is converted into a digital signal and latched, so as to achieve the purpose of high dynamics.

[0025] For an infrared readout circuit, after the detector photosensitive array receives light radiation, photo-generated carriers will be generated. Since the photocurrent formed by the generated photo-generated carriers is very weak, an infrared readout circuit is required to process and amplify the weak signal.

[0026] (1) First, when the input signal current is small, the output signal voltage of the integrating capacitor Cint is lower than the reference voltage (i.e., Vout < Vref). At this time, the switch is in the off state (Vgain = 0), and the input signal current continuously and stably integrates onto the small integrating capacitor (Small Cint). In the case of a large input signal current, the output signal of the small capacitor during integration will be higher than the reference voltage (Vout > Vref). The input signal current is integrated onto the large capacitor (Large Cint) plus the small capacitor.

[0027] (2) When the integrated voltages of the large and small capacitors are connected in parallel, the integrated charge is redistributed. At this time, the GAIN signal output is high and the circuit enters low gain mode. (3) When the signal integration voltage of the large capacitor and the small capacitor is higher than the reference voltage (Vref), the cap reset block outputs the reset signal (VHDR) of the integration capacitor.

[0028] (4) After each integration reaches the threshold, the n-bit counter counts the number of reset signals. The number of bits in the counter can be determined based on the pixel size.

[0029] (5) When the integration is completed, the integrated voltage value V, the counter Count1, the counter Count2, and the output values ​​are output through different output devices.

[0030] It should be noted that, in this document, the term "comprising" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0031] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A high dynamic infrared readout circuit with asynchronous integral clearing, characterized in that... The system includes a CTIA integrator circuit, a gain control module, a capacitor reset module, and an N-bit counter. The gain control module includes a voltage comparator; the non-inverting input of the voltage comparator is connected to the CTIA integrator circuit, the inverting input is connected to the voltage Vref, and the output is connected to the capacitor reset module and a first switching transistor. The CTIA integrator circuit includes a CTIA amplifier, a first capacitor, a second capacitor, a first switching transistor, and a second switching transistor. The first and second capacitors are a large capacitor and a small capacitor, respectively. The second capacitor, a buffer, the first capacitor + the first switching transistor, and the second switching transistor are connected in parallel. The first switching transistor is connected in series with the first capacitor. One side; the output of the CTIA integrator circuit is connected to the input of the gain control module, the output of the gain control module is connected to the input of the capacitor reset module, the output of the capacitor reset module is connected to one end of the second switch, and the output of the capacitor reset module is connected to an N-bit counter; the capacitor reset module includes two RS latches, a third switch, a D flip-flop, and a NAND gate, the third switch is located between the two RS latches, the output of the voltage comparator is connected to the input of one RS latch, the D flip-flop is connected to the output of the other RS ​​latch, and the output of the D flip-flop is connected to the NAND gate.

2. The high dynamic infrared readout circuit with asynchronous integral clearing according to claim 1, characterized in that... The first, second, and third switching transistors are specifically MOSFETs.

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