Vernier type time-to-digital converter circuit with gating enabling function

Abstract

The invention provides a vernier type time-to-digital converter circuit with a gate control enabling function, which comprises a gate control signal generation circuit module for generating an enabling signal according to a start signal and a stop signal, and determining a conversion ending moment according to output information of an arbiter module so as to enable the enabling signal to end; the ring oscillator module comprises a first ring oscillator and a second ring oscillator, oscillates according to the enable signal and outputs first phase information and second phase information; the phase-locked loop circuit module is used for providing current for the ring oscillator module; the arbiter module is used for comparing the first phase information with the second phase information, and determining the moment when the fast loop triggered by the stop signal follows the slow loop triggered by the start signal; and the decoder circuit module is used for decoding the output information of the arbiter module. According to the vernier type time-to-digital converter circuit, the ring oscillator module only oscillates during the working period, so that the power consumption of the vernier type time-to-digital converter circuit is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a vernier-type time-to-digital converter circuit with a gate-enabling function. Background Art

[0002] With the development of technologies such as facial recognition, 3D gaming, autonomous driving, augmented reality, and machine vision, three-dimensional area array imaging technology is playing an increasingly important role. Common image sensor array structures can generally be divided into fully parallel, column-parallel, and 3D integrated structures. Fully parallel structures impose strict requirements on area, while 3D integrated structures are costly and complex. Column-parallel structures significantly improve the high-speed performance of image sensors and can suppress image quality degradation caused by noise introduced during analog signal transmission. As the core component of a three-dimensional area array image sensor, the resolution, power consumption, and area of ​​the time-to-digital converter (TDC) directly impact its performance.

[0003] As 3D area array image sensors develop towards high resolution, low power consumption, and a small footprint, TDCs (Time Delay Clocked Displays) must deliver high performance while maintaining high resolution, low power consumption, and a small footprint. To achieve this high resolution, vernier TDCs are becoming increasingly popular. Because their resolution depends on the difference between the delay elements in the two loops, they can achieve resolutions below the gate delay. Vernier TDCs can be categorized as either vernier delay chain TDCs or vernier ring oscillator TDCs.

[0004] A common method for reducing delay cell mismatch is to use a Vernier Ring Oscillator (RRO) structure. This structure, created by connecting the end of the delay chain back to its starting point, avoids the mismatch problem caused by increasing the number of delay cells in the delay chain. However, if the RRO design employs this traditional structure and the ring oscillator is constantly oscillating, it consumes significant power, resulting in high power consumption. Summary of the Invention

[0005] In view of this, the present invention provides a vernier time-to-digital converter circuit with a gated enable function, which is used to solve the problem of high power consumption of the existing vernier ring oscillator.

[0006] An embodiment of the present invention provides a vernier time-to-digital converter circuit with a gated enable function, comprising: a gated signal generating circuit module, a ring oscillator module, a phase-locked loop circuit module, an arbiter module, and a decoder circuit module;

[0007] The gate control signal generating circuit module is used to generate an enable signal according to the start signal and the stop signal, and is used to determine the conversion end time according to the output information of the arbiter module to terminate the enable signal;

[0008] The ring oscillator module includes a first ring oscillator and a second ring oscillator, wherein the first ring oscillator and the second ring oscillator are configured to oscillate according to an enable signal and output first phase information and second phase information respectively;

[0009] The phase-locked loop circuit module is used to provide the current required for oscillation to the ring oscillator module;

[0010] The arbiter module is configured to compare the first phase information and the second phase information, and determine a moment when the fast loop triggered by the stop signal catches up with the slow loop triggered by the start signal;

[0011] The decoder circuit module is used to perform decoding operations on the output information of the arbitrator module.

[0012] According to an embodiment of the present invention, the gate control signal generating circuit module includes: a plurality of AND gates, a plurality of NAND gates, a plurality of NOT gates, a trigger, a first latch, and a second latch;

[0013] The plurality of AND gates form an AND gate array in a tree structure, the plurality of input terminals of the AND gate array are connected to the plurality of output terminals of the arbiter module, the output terminal of the AND gate array is connected to the first input terminal of the trigger via a first NOT gate, and the second input terminal of the trigger is connected to a power supply voltage Vdd;

[0014] The output end of the trigger is connected to the first input end of the OR gate, the second input end of the OR gate is connected to the reset signal, and the output end of the OR gate is connected to the first latch and the second latch through a second NOT gate;

[0015] The start signal is connected to the input end of the first latch through a third NOT gate, the output end of the first latch generates a first enable signal through an AND gate, and then generates a second enable signal through a first delay unit;

[0016] The stop signal circuit is connected to the input end of the second latch through a fourth NOT gate, and the output end of the second latch generates a third enable signal through an AND gate, and then generates a fourth enable signal through a second delay unit.

[0017] According to an embodiment of the present invention, the phase-locked loop circuit module includes a first phase-locked loop and a second phase-locked loop, and the gating signal generating circuit module has a first output port for outputting the first enable signal, a second output port for outputting the second enable signal, a third output port for outputting the third enable signal, and a fourth output port for outputting the fourth enable signal;

[0018] An input end of the first phase-locked loop is connected to the first output port, and an output end of the first phase-locked loop is connected to the first ring oscillator, for supplying a first current to the first ring oscillator;

[0019] The input end of the first ring oscillator is connected to the second output port, and is used to send the first phase information to the arbitrator module, where the first phase information includes a plurality of first phases;

[0020] An input end of the second phase-locked loop is connected to the third output port, and an output end of the second phase-locked loop is connected to the second ring oscillator, for supplying a second current to the second ring oscillator;

[0021] The input end of the second ring oscillator is connected to the fourth output port, and is used to send the second phase information to the arbitrator module, where the second phase information includes a plurality of second phases.

[0022] According to an embodiment of the present invention, the first delay time length of the first delay unit is greater than the first locking time length of the first phase-locked loop;

[0023] The second delay time length of the second delay unit is greater than the second locking time length of the second phase-locked loop.

[0024] According to an embodiment of the present invention, the first delay duration is greater than the second delay duration.

[0025] According to an embodiment of the present invention, the vernier time-to-digital converter circuit further includes a counter;

[0026] The counter is connected to the output end of the second ring oscillator. The second ring oscillator is used to send the second phase to the counter. The counter is used to count the number of oscillations of the second ring oscillator.

[0027] According to an embodiment of the present invention, the arbitrator module is an array structure, and the arbitrator module includes a plurality of arbitrators, and each of the arbitrators includes a plurality of MOS transistors.

[0028] According to an embodiment of the present invention, in each of the arbitrators,

[0029] The source of MOS tube Q1, the source of MOS tube Q5, the source of MOS tube Q6, the source of MOS tube Q9, the source of MOS tube Q 13 The source and MOS tube Q 14 The sources are connected to the power supply voltage VDD;

[0030] The gate of the MOS tube Q2, the gate of the MOS tube Q6, the gate of the MOS tube Q8 and the gate of the MOS tube Q 11 The gates of are all connected to the PF signal;

[0031] The gates of the MOS transistor Q1 and the MOS transistor Q4 are both connected to the PS signal;

[0032] The gate of the MOS tube Q3, the gate of the MOS tube Q5, the MOS tube Q 10 The gate and the MOS tube Q 13 The gates of the MOSFETs are all connected to the RESET signal;

[0033] The drain of the MOS transistor Q1 is connected to the source of the MOS transistor Q2. The drain of the MOS transistor Q2, the drain of the MOS transistor Q3, the drain of the MOS transistor Q5, and the gate of the MOS transistor Q7 are connected to each other. The source of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4.

[0034] The drain of the MOS transistor Q6, the drain of the MOS transistor Q7, the gate of the MOS transistor Q9 and the gate of the MOS transistor Q 12 The gates of the MOS tube Q7 are connected to each other; the source of the MOS tube Q7 is connected to the drain of the MOS tube Q8;

[0035] The drain of the MOS tube Q9, the MOS tube Q 10 The source of the MOS tube Q 13 The drain of the MOS tube Q 14 The gate and MOS tube Q 15 The gates are connected to each other;

[0036] The MOS tube Q 10 The drain of the MOS tube Q 11 The drain connection of the MOS tube Q 11 The source of the MOS tube Q 12 The drain connection;

[0037] The MOS tube Q 14 The drain of the MOS tube Q 15 The drain is connected to the output terminal Q;

[0038] The source of the MOS transistor Q4, the source of the MOS transistor Q8, and the source of the MOS transistor Q 12 The source and the MOS tube Q 15 The sources of the MOSFETs are connected to the ground terminal GND.

[0039] According to an embodiment of the present invention, the plurality of arbiters output third phase information to the decoder circuit module and the gating signal generating circuit module.

[0040] According to an embodiment of the present invention, the third phase information includes multiple third phases.

[0041] The vernier time-to-digital converter circuit with a gated enable function provided by an embodiment of the present invention can achieve at least the following technical effects: a gated signal generating circuit module generates an enable signal based on a start signal and a stop signal, causing the first ring oscillator and the second ring oscillator in the ring oscillator module to start oscillating sequentially. The arbiter module determines the moment when the fast ring catches up with the slow ring by comparing the first phase information and the second phase information, and transmits a timing signal to the gated signal generating circuit module. When the conversion is completed, the enable signal becomes low, and the first and second ring oscillators stop oscillating. The ring oscillator module oscillates only during operation, effectively reducing the power consumption of the vernier time-to-digital converter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0043] Figure 1 The structure diagram of the vernier time-to-digital converter circuit according to an embodiment of the present invention is schematically shown;

[0044] Figure 2 The following schematically shows a structural diagram of a gate signal generating circuit module according to an embodiment of the present invention;

[0045] Figure 3 Schematically shows an operation timing diagram of a gate control signal generating circuit module according to an embodiment of the present invention;

[0046] Figure 4 The figure schematically shows the structure of an arbitrator module according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific embodiments and the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0048] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0049] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0050] In the prior art, vernier-type TDCs can be divided into vernier delay chain TDCs and vernier ring oscillator TDCs. TDCs, also known as time-to-digital converters, face mismatch and area increases as the number of delay elements increases. Furthermore, they consume high power, which is inconsistent with the development trend of low-power and low-area integrated circuits. A vernier ring oscillator structure, by connecting the end of the delay back to its starting point, creates a ring oscillator structure, avoiding the mismatch problem caused by increasing the number of delay elements in the delay chain. However, vernier ring oscillators using this traditional structure have at least the following disadvantages: If the vernier ring oscillator oscillates continuously, it consumes a large amount of power, resulting in increased power consumption. Traditional vernier ring oscillator TDCs have a complex gate enable circuit structure, and as the number of bits increases, their size and area increase. The delay elements corresponding to both loops of the vernier ring oscillator require an arbiter for phase detection. Traditional arbiter circuit arrays require complex structures such as comparators, triggers, and matching circuits, occupying a large area. Ring oscillators are susceptible to external PVT variations, resulting in unstable oscillation frequency and affecting time quantization.

[0051] The present invention provides a vernier time-to-digital converter circuit with a gated enable function, which solves the above-mentioned problems existing in the ring oscillator in the prior art.

[0052] The following combination Figures 1 to 4 A vernier time-to-digital converter circuit with a gate enable function according to an embodiment of the present invention is described. For ease of description, the vernier time-to-digital converter circuit with a gate enable function is referred to as a vernier time-to-digital converter circuit.

[0053] like Figure 1 As shown, the vernier time-to-digital converter circuit provided by the embodiment of the present invention includes a gate signal generating circuit module, a ring oscillator module, a phase-locked loop circuit module, an arbiter module and a decoder circuit module.

[0054] The gate signal generating circuit module is used to generate an enable signal based on the start signal and the stop signal, and is used to determine the moment when the conversion ends based on the output information of the arbitrator module to terminate the enable signal; the ring oscillator module includes a first ring oscillator and a second ring oscillator, the first ring oscillator and the second ring oscillator are used to oscillate according to the enable signal and output first phase information and second phase information respectively; the phase-locked loop circuit module is used to provide the current required for oscillation to the ring oscillator module; the arbitrator module is used to compare the first phase information and the second phase information to determine the moment when the fast loop triggered by the stop signal catches up with the slow loop triggered by the start signal; and the decoder circuit module is used to decode the output information of the arbitrator module.

[0055] Specifically, the vernier time-to-digital converter circuit includes two links: a fast loop and a slow loop. A gating signal generation circuit module generates a first enable signal and a second enable signal based on a start signal. When the start signal arrives, the first enable signal enables the phase-locked loop circuit module, locking the phase-locked loop to a stable frequency. After passing through a delay unit, the gating signal generation circuit module uses a second enable signal to enable the first ring oscillator in the slow loop, causing it to begin oscillating. The first ring oscillator then transmits first phase information to the arbitrator module.

[0056] The gating signal generating circuit module can generate a third enable signal and a fourth enable signal based on the stop signal. When the stop signal arrives, the third enable signal enables the phase-locked loop circuit module, allowing the phase-locked loop to lock to a stable frequency. After passing through a delay unit, the gating signal generating circuit module enables the second ring oscillator in the fast loop through the fourth enable signal to cause it to start oscillating. The second ring oscillator transmits the second phase information to the arbitrator module.

[0057] exist Figure 1 、 Figure 2 、 Figure 3 and Figure 4 In the embodiment, the first enable signal is represented by EN1, the second enable signal is represented by EN2, the third enable signal is represented by EN3, and the fourth enable signal is represented by EN4; the start signal is represented by START, the stop signal is represented by STOP, and the reset signal is represented by RESET.

[0058] The phase-locked loop circuit module provides the current required for oscillation to the first ring oscillator and the second ring oscillator. The current provided to the first ring oscillator is I s The current provided to the second ring oscillator is represented by I f express.

[0059] The vernier time-to-digital converter circuit includes two links: a fast loop and a slow loop. Taking the four-stage differential ring oscillator circuit as an example, the phase generated by the slow loop is converted to PS Indicates that the slow loop generates PS <1> ~PS <8> There are 8 first phases in total, that is, the first phase information output by the first ring oscillator includes PS <1> ~PS <8> There are 8 first phases in total. The phase generated by the fast loop is converted to PF Indicates that the fast ring generates PF <1> ~PF <8> There are 8 second phases in total, that is, the second phase information output by the second ring oscillator includes PF <1> ~PF <8> There are 8 second phases in total. It is understandable that the number of first phases can also be 4, 16, etc., and the number of second phases can also be 4, 16, etc., and the number of first phases is equal to the number of second phases.

[0060] The arbiter module uses the phase PF of the fast loop Phase PS of the slow loop Sampling and outputting timing signal Q <1> ~Q <8> , when the first PF Catch up with PS When , the enable signal ends. Figure 3 Middle Q <6> As shown, Q <6> The gate signal generation circuit module outputs Q <1> ~Q <8> Read back, when the conversion is detected to be complete, that is, the first PF Catch up with PS When the enable signal ends, the first ring oscillator and the second ring oscillator stop oscillating.

[0061] After the enable signal ends, the current measurement ends. If the next measurement is required, a reset operation is performed before the next start signal arrives. The gate signal generation circuit module is connected to the reset signal circuit. When the gate signal generation circuit module receives the reset signal, it performs a reset operation.

[0062] The output terminal of the arbiter module outputs the timing signal Q <1> ~Q <8> To the decoder circuit module, the decoder circuit module outputs 8-phase i after decoding operation <1> ~i <8> .

[0063] High power consumption is a major issue facing vernier-type time-to-digital converters. Using two constantly operating ring oscillator chains consumes significant power. In the vernier-type time-to-digital converter circuit of the present invention, when a signal arrives, the gated signal generation circuit module generates an enable signal, causing the first and second ring oscillators in the ring oscillator module to sequentially begin oscillating. When the conversion is complete, the enable signal goes low, and the ring oscillator module stops operating. This avoids power consumption loss and effectively reduces the power consumption of the vernier-type time-to-digital converter circuit.

[0064] In an embodiment of the present invention, the gating signal generating circuit module generates an enable signal based on the start signal and the stop signal, causing the first ring oscillator and the second ring oscillator in the ring oscillator module to start oscillating in sequence. The arbiter module determines the moment when the fast ring catches up with the slow ring by comparing the first phase information and the second phase information, and transmits a timing signal to the gating signal generating circuit module. When the conversion is completed, the enable signal becomes low, and the first and second ring oscillators stop oscillating. The ring oscillator module oscillates only during operation, effectively reducing the power consumption of the vernier time-to-digital converter circuit.

[0065] like Figure 1 、 Figure 2 and Figure 3 As shown, in an optional embodiment, the gating signal generating circuit module includes a plurality of AND gates, a plurality of NAND gates, a plurality of NOT gates, a trigger, a first latch and a second latch.

[0066] A plurality of AND gates form an AND gate array with a tree structure, wherein the plurality of input terminals of the AND gate array are connected to the plurality of output terminals of the arbiter module, the output terminal of the AND gate array is connected to the first input terminal of a trigger through a first NOT gate, and the second input terminal of the trigger is connected to a power supply voltage Vdd; the output terminal of the trigger is connected to the first input terminal of an OR gate, the second input terminal of the OR gate is connected to a reset signal, and the output terminal of the OR gate is connected to the first latch and the second latch through a second NOT gate.

[0067] The start signal is connected to the input end of the first latch through the third NOT gate, and the output end of the first latch generates a first enable signal through an AND gate, and then generates a second enable signal through the first delay unit; the stop signal circuit is connected to the input end of the second latch through the fourth NOT gate, and the output end of the second latch generates a third enable signal through an AND gate, and then generates a fourth enable signal through the second delay unit.

[0068] Specifically, the first ring oscillator outputs PS <1> ~PS <8> A total of 8 first phase, second ring oscillator output PF <1> ~PF <8> For illustration purposes, an example is used in which the arbiter module has eight output terminals, each of which has eight second phases. It is understood that the first ring oscillator may also output four first phases, sixteen first phases, and so on, and the second ring oscillator may also output four second phases, sixteen second phases, and so on. The number of input terminals, the number of output terminals, the number of first phases, and the number of second phases of the arbiter module are equal.

[0069] Multiple AND gates form a tree-structured AND gate array. The AND gate array has eight inputs, which are sequentially connected to the eight outputs of the arbiter module. The eight inputs of AND gates U1, U2, U3, and U4 are sequentially connected to the eight outputs of the arbiter module. The four outputs of AND gates U1, U2, U3, and U4 are sequentially connected to the four inputs of AND gates U5 and U6. The two outputs of AND gates U5 and U6 are connected to the two inputs of AND gate U7. Thus, AND gates U1, U2, U3, U4, U5, U6, and U7 form a tree-structured AND gate array U. The output of AND gate U7 is connected to the input of a first NOT gate U8.

[0070] The output end of the first NOT gate U8 is connected to the first input end of the trigger U9, the second input end of the trigger U9 is connected to the power supply voltage Vdd, the output end of the trigger U9 is connected to the first input end of the OR gate U10, the second input end of the OR gate U10 is connected to the reset signal, the output end of the OR gate U10 is connected to the second NOT gate U11, and the output end of the second NOT gate U11 is connected to the first latch and the second latch.

[0071] The first latch includes a NAND gate U12 and a NAND gate U13. The start signal is connected to the input of the third NAND gate U14. The output of the third NAND gate U14 is connected to the input of the first latch. The output of the first latch is connected to the input of the AND gate U15. The first enable signal is generated by the AND gate U15, and the second enable signal is generated after passing through the first delay unit. The first delay time of the first delay unit is represented by τ1.

[0072] The second latch includes a NAND gate U16 and a NAND gate U17. The stop signal circuit is connected to the input end of the fourth NAND gate U18. The output end of the fourth NAND gate U18 is connected to the input end of the second latch. The output end of the second latch is connected to the input end of the AND gate U19. The third enable signal is generated by the AND gate U19, and the fourth enable signal is generated after passing through the second delay unit. The second delay time of the second delay unit is represented by τ2, and the first delay time is greater than the second delay time.

[0073] In the embodiment of the present invention, the tree-structured AND gate array enables the gate signal generating circuit module to use fewer MOS transistors than the traditional multi-channel parallel structure, thereby reducing the area occupied and facilitating the miniaturization of the vernier time-to-digital converter circuit.

[0074] like Figure 1 As shown, in an optional embodiment, the phase-locked loop circuit module includes a first phase-locked loop and a second phase-locked loop, and the gating signal generating circuit module has a first output port for outputting a first enable signal, a second output port for outputting a second enable signal, a third output port for outputting a third enable signal, and a fourth output port for outputting a fourth enable signal.

[0075] The input end of the first phase-locked loop is connected to the first output port, and the output end of the first phase-locked loop is connected to the first ring oscillator, which is used to deliver a first current to the first ring oscillator; the input end of the first ring oscillator is connected to the second output port, which is used to send first phase information to the arbitrator module, where the first phase information includes multiple first phases.

[0076] The input end of the second phase-locked loop is connected to the third output port, and the output end of the second phase-locked loop is connected to the second ring oscillator, which is used to deliver a second current to the second ring oscillator; the input end of the second ring oscillator is connected to the fourth output port, which is used to send second phase information to the arbitrator module, where the second phase information includes multiple second phases.

[0077] Specifically, the phase-locked loop circuit module includes a first phase-locked loop and a second phase-locked loop. Figure 1 In the embodiment, the first phase-locked loop is represented by PLL1 and the second phase-locked loop is represented by PLL2. The input end of the first phase-locked loop is connected to the first output port, which is used to output the first enable signal. The output end of the first phase-locked loop is connected to the first ring oscillator, and the first current required for oscillation is provided to the first ring oscillator through the first phase-locked loop circuit. The first current is represented by I s The input end of the first ring oscillator is connected to the second output port, and the second output port is used to output the second enable signal. The first ring oscillator is used to send first phase information including multiple first phases to the arbiter module.

[0078] The locking time of the first phase-locked loop is defined as a first locking time, and the first delay time is greater than the first locking time, to ensure that a stable current signal is provided before the first ring oscillator starts to oscillate.

[0079] When the start signal comes, the gate signal generating circuit module enables the first phase-locked loop circuit in the slow loop through the first enable signal, so that the first phase-locked loop is locked to a stable frequency, and the first phase-locked loop circuit provides a current I to the first ring oscillator. s The first delay unit then generates a second enable signal, and the gate signal generation circuit module enables the first ring oscillator in the slow ring through the second enable signal, causing it to start oscillating.

[0080] The input end of the second phase-locked loop is connected to the third output port, and the third output port is used to output a third enable signal. The output end of the second phase-locked loop is connected to the second ring oscillator, and the second current required for oscillation is provided to the second ring oscillator through the second phase-locked loop circuit. The second current is I f The input end of the second ring oscillator is connected to the fourth output port, and the fourth output port is used to output the fourth enable signal. The second ring oscillator is used to send second phase information including multiple second phases to the arbiter module.

[0081] The locking time of the second phase-locked loop is defined as a second locking time, and the second delay time is greater than the second locking time, to ensure that a stable current signal is provided before the second ring oscillator starts to oscillate.

[0082] When the stop signal comes, the gate signal generating circuit module enables the second phase-locked loop circuit in the fast loop through the third enable signal, so that the second phase-locked loop is locked to a stable frequency, and the second phase-locked loop circuit provides a current I to the second ring oscillator. f The fourth enable signal is then generated by the second delay unit, and the gate signal generating circuit module enables the second ring oscillator in the fast ring through the fourth enable signal, causing it to start oscillating.

[0083] In the embodiment of the present invention, the first phase-locked loop and the second phase-locked loop are enabled by the first enable signal and the third enable signal, so that the first phase-locked loop and the second phase-locked loop are locked to a stable frequency, and the current I is provided to the first ring oscillator through the first phase-locked loop circuit. s , providing current I to the second ring oscillator through the second phase-locked loop circuit f , which can obtain accurate oscillation frequency while suppressing the influence of PVT (process, voltage, temperature) on the stability of oscillation frequency, thereby helping to improve the stability of the circuit system.

[0084] like Figure 1 As shown, in an optional embodiment, the vernier time-to-digital converter circuit further includes a counter; the counter is connected to the output end of the second ring oscillator, the second ring oscillator is used to send a second phase to the counter, and the counter is used to count the number of oscillations of the second ring oscillator.

[0085] Specifically, the second ring oscillator outputs 8 second phases as an example for explanation. The second ring oscillator outputs PF <1> ~PF <8> There are 8 second phases in total, of which phase PF <8> Output to the counter, the counter according to the phase PF <8> The number of complete revolutions of the second ring oscillator is counted.

[0086] like Figure 1 As shown, in an optional embodiment, the arbitrator module is an array structure, the arbitrator module includes a plurality of arbitrators, and each arbitrator includes a plurality of MOS transistors.

[0087] Specifically, the arbitrator module includes a plurality of oscillators distributed in an array. The number of oscillators is set according to actual needs, and the number of oscillators can be 4, 8, 16, etc. Each arbitrator includes a plurality of MOS tubes.

[0088] The multiple arbitrators in the arbitrator module are all true single-phase clock arbitrators. Compared with traditional arbitrators, the arbitrator module eliminates complex structures such as comparators, triggers and matching units, ensuring the working speed while further reducing the area occupied.

[0089] like Figure 4 As shown, in an optional embodiment, in each arbitrator, the source of the MOS transistor Q1, the source of the MOS transistor Q5, the source of the MOS transistor Q6, the source of the MOS transistor Q9, the source of the MOS transistor Q 13 The source and MOS tube Q 14 The source of MOS tube Q2, the gate of MOS tube Q6, the gate of MOS tube Q8 and the gate of MOS tube Q 11 The gates of MOS tubes Q1 and Q4 are connected to the PS signal; the gates of MOS tubes Q3, Q5, and Q 10 The gate and MOS tube Q 13 The gates of MOS tube Q1 are connected to the RESET signal; the drain of MOS tube Q1 is connected to the source of MOS tube Q2, the drain of MOS tube Q2, the drain of MOS tube Q3, the drain of MOS tube Q5 and the gate of MOS tube Q7 are connected to each other, the source of MOS tube Q3 is connected to the drain of MOS tube Q4; the drain of MOS tube Q6, the drain of MOS tube Q7, the gate of MOS tube Q9 and the gate of MOS tube Q 12 The gates of the MOS tube Q7 are connected to each other; the source of the MOS tube Q8 is connected to the drain of the MOS tube Q9; the drain of the MOS tube Q 10 The source of MOS tube Q 13 The drain of MOS tube Q 14 The gate and MOS tube Q 15 The gates of the MOS tube Q are connected to each other; 10 The drain of MOS tube Q 11 The drain connection of MOS tube Q 11 The source and MOS tube Q 12 Drain connection of MOS tube Q 14 The drain of MOS tube Q 15 The drain of MOS tube Q4 is connected to the output terminal Q; the source of MOS tube Q8, the source of MOS tube Q 12 The source and MOS tube Q 15 The sources of the MOSFETs are connected to the ground terminal GND.

[0090] The voltage level of the arbiter input clock is unknown. If the initial clock level is high, the traditional TSPCDff-based counter will not be reset correctly. By adding MOS tubes Q3, Q5 and Q 10 To achieve correct reset and eliminate leakage current path.

[0091] As can be seen from the above, the arbitrator adopts a true single-phase clock arbitrator structure. The arbitrator module is composed of multiple true single-phase clock arbiters arranged in an array. While realizing phase detection, it further reduces the area and improves work efficiency.

[0092] like Figure 1 As shown, in an optional embodiment, a plurality of arbitrators output the third phase information to the decoder circuit module and the gating signal generating circuit module.

[0093] Specifically, a plurality of arbitrators output third phase information, where the third phase information includes a plurality of third phases. For example, the output terminals of eight arbitrators output eight third phases Q. <1> ~Q <8> The decoder circuit module generates 8-phase output i after decoding operation. <1> ~i <8> .

[0094] In summary, the vernier time-to-digital converter circuit with a gated enable function of the present invention has the following beneficial effects.

[0095] The tree-structured gating signal generation circuit module implements a gating enable function, allowing the first ring oscillator and the second ring oscillator to oscillate only during operation, thereby reducing power consumption. Compared with traditional gating signal generation circuits, the module uses fewer MOS transistors, which reduces area occupation and facilitates the miniaturization of the vernier time-to-digital converter circuit.

[0096] The arbiter module adopts a true single-phase clock arbiter structure. Compared with traditional arbiters, it eliminates complex structures such as comparators, triggers and matching units. While ensuring the operating speed, it reduces the area occupied, which is conducive to the miniaturization of the vernier time-to-digital converter circuit.

[0097] By providing current to the first ring oscillator and the second ring oscillator through the first phase-locked loop and the second phase-locked loop, it is possible to obtain a precise oscillation frequency while suppressing the influence of PVT (process, voltage, temperature) changes on the oscillation frequency, which is beneficial to improving the stability of the vernier time-to-digital converter circuit.

[0098] The foregoing is merely a specific embodiment of the present invention, but the scope of protection of this application is not limited thereto. Any changes or substitutions made within the spirit and principles of the present invention shall be included within the scope of protection of this application. Therefore, the scope of protection of this application shall be subject to the scope of protection of the claims.

Claims

1. A vernier time-to-digital converter circuit with a gated enable function, characterized in that: include: Gating signal generating circuit module, ring oscillator module, phase-locked loop circuit module, arbiter module and decoder circuit module; The gate control signal generating circuit module is used to generate an enable signal according to the start signal and the stop signal, and is used to determine the conversion end time according to the output information of the arbiter module to terminate the enable signal; The ring oscillator module includes a first ring oscillator and a second ring oscillator, wherein the first ring oscillator and the second ring oscillator are configured to oscillate according to an enable signal and output first phase information and second phase information respectively; The phase-locked loop circuit module is used to provide the current required for oscillation to the ring oscillator module; The arbiter module is configured to compare the first phase information and the second phase information, and determine a moment when the fast loop triggered by the stop signal catches up with the slow loop triggered by the start signal; The decoder circuit module is used to perform decoding operations on the output information of the arbitrator module.

2. The vernier time-to-digital converter circuit according to claim 1, wherein: The gate control signal generating circuit module includes: a plurality of AND gates, a plurality of NAND gates, a plurality of NOT gates, a trigger, a first latch and a second latch; The plurality of AND gates form an AND gate array in a tree structure, the plurality of input terminals of the AND gate array are connected to the plurality of output terminals of the arbiter module, the output terminal of the AND gate array is connected to the first input terminal of the trigger via a first NOT gate, and the second input terminal of the trigger is connected to a power supply voltage Vdd; The output end of the trigger is connected to the first input end of the OR gate, the second input end of the OR gate is connected to the reset signal, and the output end of the OR gate is connected to the first latch and the second latch through a second NOT gate; The start signal is connected to the input end of the first latch through a third NOT gate, the output end of the first latch generates a first enable signal through an AND gate, and then generates a second enable signal through a first delay unit; The stop signal circuit is connected to the input end of the second latch through a fourth NOT gate, and the output end of the second latch generates a third enable signal through an AND gate, and then generates a fourth enable signal through a second delay unit.

3. The vernier time-to-digital converter circuit according to claim 2, wherein: The phase-locked loop circuit module includes a first phase-locked loop and a second phase-locked loop, and the gating signal generating circuit module has a first output port for outputting the first enable signal, a second output port for outputting the second enable signal, a third output port for outputting the third enable signal, and a fourth output port for outputting the fourth enable signal; An input end of the first phase-locked loop is connected to the first output port, and an output end of the first phase-locked loop is connected to the first ring oscillator, for supplying a first current to the first ring oscillator; The input end of the first ring oscillator is connected to the second output port, and is used to send the first phase information to the arbitrator module, where the first phase information includes a plurality of first phases; An input end of the second phase-locked loop is connected to the third output port, and an output end of the second phase-locked loop is connected to the second ring oscillator, for supplying a second current to the second ring oscillator; The input end of the second ring oscillator is connected to the fourth output port, and is used to send the second phase information to the arbitrator module, where the second phase information includes a plurality of second phases.

4. The vernier time-to-digital converter circuit according to claim 3, wherein: A first delay duration of the first delay unit is greater than a first locking duration of the first phase-locked loop; The second delay time length of the second delay unit is greater than the second locking time length of the second phase-locked loop.

5. The vernier time-to-digital converter circuit according to claim 4, wherein: The first delay duration is greater than the second delay duration.

6. The vernier time-to-digital converter circuit according to claim 3, wherein: Also includes a counter; The counter is connected to the output end of the second ring oscillator. The second ring oscillator is used to send the second phase to the counter. The counter is used to count the number of oscillations of the second ring oscillator.

7. The vernier time-to-digital converter circuit according to any one of claims 1 to 6, characterized in that: The arbitrator module is an array structure, and includes a plurality of arbitrators, each of which includes a plurality of MOS transistors.

8. The vernier time-to-digital converter circuit according to claim 7, wherein: Each of said arbitrators, The source of MOS tube Q1, the source of MOS tube Q5, the source of MOS tube Q6, the source of MOS tube Q9, the source of MOS tube Q 13 The source and MOS tube Q 14 The sources are connected to the power supply voltage VDD; The gate of the MOS tube Q2, the gate of the MOS tube Q6, the gate of the MOS tube Q8 and the gate of the MOS tube Q 11 The gates of are all connected to the PF signal; The gates of the MOS transistor Q1 and the MOS transistor Q4 are both connected to the PS signal; The gate of the MOS tube Q3, the gate of the MOS tube Q5, the MOS tube Q 10 The gate and the MOS tube Q 13 The gates of the MOSFETs are all connected to the RESET signal; The drain of the MOS transistor Q1 is connected to the source of the MOS transistor Q2. The drain of the MOS transistor Q2, the drain of the MOS transistor Q3, the drain of the MOS transistor Q5, and the gate of the MOS transistor Q7 are connected to each other. The source of the MOS transistor Q3 is connected to the drain of the MOS transistor Q4. The drain of the MOS transistor Q6, the drain of the MOS transistor Q7, the gate of the MOS transistor Q9 and the gate of the MOS transistor Q 12 The gates of the MOS tube Q7 are connected to each other; the source of the MOS tube Q7 is connected to the drain of the MOS tube Q8; The drain of the MOS tube Q9, the MOS tube Q 10 The source of the MOS tube Q 13 The drain of the MOS tube Q 14 The gate and MOS tube Q 15 The gates are connected to each other; The MOS tube Q 10 The drain of the MOS tube Q 11 The drain connection of the MOS tube Q 11 The source of the MOS tube Q 12 The drain connection; The MOs tube Q 14 The drain of the MOS tube Q 15 The drain is connected to the output terminal Q; The source of the MOS transistor Q4, the source of the MOS transistor Q8, and the source of the MOS transistor Q 12 The source and the MOS tube Q 15 The sources of the MOSFETs are connected to the ground terminal GND.

9. The vernier time-to-digital converter circuit according to claim 7, wherein: The plurality of arbitrators output third phase information to the decoder circuit module and the gating signal generating circuit module.

10. The vernier time-to-digital converter circuit according to claim 9, wherein: The third phase information includes a plurality of third phases.

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