LDO low power transient boost circuit for large array image sensor

Abstract

The application relates to a LDO low-power transient enhancement circuit for a large-array image sensor and belongs to the field of integrated circuit design.The circuit comprises an overshoot voltage amplification module, an undershoot voltage amplification module and an adjustment module; the overshoot voltage amplification module plays a role when the load current suddenly changes from heavy load to light load, amplifies the transient overshoot voltage at the output end, transmits the amplified voltage to the adjustment module, then the adjustment module is turned on to charge the power tube gate to enhance the power tube gate swing rate; the undershoot voltage amplification module plays a role when the load current suddenly changes from light load to heavy load, amplifies the transient undershoot voltage at the output end, transmits the amplified voltage to the adjustment module, then the adjustment module is turned on to discharge the power tube gate to enhance the power tube gate swing rate; and the adjustment module is in an off state when the load current is stable.The application improves the transient response characteristic and realizes low-power design.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and relates to a low-power transient enhancement circuit for LDOs (Large Area Detectors) for large-area image sensors. Background Technology

[0002] Low dropout regulators (LDOs) play a crucial role in large-area image sensor chips and integrated systems, providing stable and precise power to various sensitive electronic devices. With technological advancements, electronic devices place increasingly higher demands on power supplies, requiring not only stable voltage but also rapid response to transient changes to ensure performance and reliability under various operating conditions. However, as the performance requirements of electronic devices continue to rise, LDOs face new challenges in transient response. Rapid load changes can cause transient fluctuations in output voltage. Low-power transient enhancement circuits can significantly improve the transient response capability of LDOs without significantly increasing power consumption, quickly suppressing voltage fluctuations caused by load changes and thus ensuring output voltage stability. Therefore, designing a low-power transient enhancement circuit for LDOs is of paramount importance.

[0003] Traditional transient enhancement circuits include dynamic bias circuits and slew rate enhancement circuits. Dynamic bias circuits, such as... Figure 1 As shown, Figure 1 In the middle, V IN M is the input voltage. S For sampling tubes, M p It is a P-type power transistor, and N is M. P With M S The size ratio, I MS For flow through M S The current of the tube, EA is the error amplifier, V REF For reference voltage terminal, V FB For feedback voltage, I B1 For a fixed current, I B2 For dynamic bias current, R F1 For the feedback network resistance, R F2 For the feedback network resistance, R L For load resistance, C L This is the load capacitor. Figure 1 The circuit shown operates by controlling the tail current of the error amplifier EA with the load current. When the circuit is under no-load and light-load conditions, the sampling transistor M...S The current is relatively small, and the dynamic bias current is fed back to the error amplifier EA through the current mirror. I B2 The current is also relatively small; at this time, the tail current of the error amplifier EA is mainly composed of a fixed current. I B1 Provided; when the circuit is under heavy load, the sampling tube M S The current is relatively large, and the dynamic bias current is fed back to the error amplifier EA through the current mirror. I B2 The current is also relatively large; at this time, the tail current of the error amplifier EA is mainly composed of the dynamic bias current. I B2 This provides increased bandwidth to the error amplifier, improving transient response. Dynamic bias circuits require increased bias current to enhance bandwidth under heavy loads, but this increases power consumption, and the increased loop bandwidth under heavy loads can easily lead to insufficient phase margin. Slew rate enhancement circuits, such as... Figure 2 As shown, Figure 2 In the middle, V IN V is the input voltage. G M is the gate of the LDO power transistor. SRE For PMOS transistors, M p It is a P-type power transistor. V REF_SRE The reference voltage at the positive terminal of the comparator. V IN_SRE The input voltage is the inverting input voltage of the comparator. R F1 For the feedback network resistance, R F2 For the feedback network resistance, R L For load resistance, C L For load capacitance, V FB For feedback voltage, V OUT This is the output voltage. Figure 2 The circuit shown works on the principle that when the input voltage V IN No change and V IN_SRE When the value decreases, the PMOS transistor M SRE Cut off, comparator output current I SRE When the voltage V is 0, IN_SRE When the value increases, the PMOS transistor M SRE On, I SRE The gate capacitor of the power transistor is charged quickly, thereby reducing the output voltage V. OUT The circuit can only reduce the overshoot voltage, not the undershoot voltage, and the comparator consumes a lot of power.

[0004] Therefore, there is an urgent need for a new type of low-power transient enhancement circuit to solve the problems of high power consumption, impact on loop stability, and inability to improve undershoot voltage in traditional transient enhancement circuits. Summary of the Invention

[0005] In view of this, the purpose of this invention is to provide a low-power transient enhancement circuit for LDOs in large-area image sensors. By sampling the output voltage, an adjustment signal is generated to rapidly charge and discharge the gate node of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor and suppressing overshoot / undershoot voltages. This circuit does not consume static power and does not affect loop stability in steady state, and it can suppress overshoot / undershoot voltages during load transitions, thus improving transient response characteristics.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A low-power transient enhancement circuit for LDOs (Light Detection and Ranging) in large-area image sensors improves transient response characteristics while achieving low-power design. The circuit includes an overshoot voltage amplification module, an undershoot voltage amplification module, and an adjustment module. The inputs of the overshoot and undershoot voltage amplification modules are connected to the outputs of the LDO, and their outputs are connected to the adjustment module. The adjustment module has two inputs: a first input connected to the overshoot voltage amplification module and a second input connected to the undershoot voltage amplification module; its output is connected to the gate of the LDO power transistor.

[0008] The overshoot voltage amplification module plays a role when the load current changes abruptly from heavy load to light load. It amplifies the transient overshoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. Then, the adjustment module turns on to charge the gate of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor.

[0009] The undershoot voltage amplification module plays a role when the load current changes abruptly from light load to heavy load. It amplifies the transient undershoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. Then, the adjustment module turns on to discharge the gate of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor.

[0010] The adjustment module is in the off state when the load current is stable, which does not affect the normal operation of the LDO. It only charges and discharges the gate of the LDO power transistor when the load changes, thereby enhancing the gate slew rate of the LDO power transistor.

[0011] Preferably, the overshoot voltage amplification module includes a first MOSFET M1, a second MOSFET M2, and a first capacitor. C 1. First resistor R 1 and the third resistor R 3; The gate of the first MOSFET M1 is connected to the first capacitor. C 1. LDO output terminal (i.e., output voltage)V OUT The connection is also made through the first resistor. R 1 Connect to the reference voltage terminal V REF The source of the first MOSFET M1 is connected to the third resistor. R 3. Grounding; the drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1 and the gate of the third MOSFET M3 in the adjustment module, and the gate is connected to the battery voltage V. BP The source is connected to the source of the third MOS transistor M3 of the adjustment module and the output terminal of the LDO.

[0012] Preferably, the undershoot voltage amplification module includes the fourth MOSFET M4 to the seventh MOSFET M7 and a second resistor. R 2 and second capacitor C 2; The source of the fourth MOSFET M4 is connected to the output of the LDO, and its gate and drain are both connected to the source of the fifth MOSFET M5; the gate and drain of the fifth MOSFET M5 are both connected to the source of the sixth MOSFET M6; the gate of the sixth MOSFET M6 is connected to the gate of the seventh MOSFET M7, and also connected through a second resistor. R 2 Connect to the reference voltage terminal V REF It also uses a second capacitor C 2. Connect to the LDO output terminal; the drain of the seventh MOSFET M7 is connected to the drain of the sixth MOSFET M6 and the gate of the eighth MOSFET M8 of the adjustment module, and the source is grounded.

[0013] Preferably, the adjustment module includes a third MOSFET M3, an eighth MOSFET M8, and a fourth resistor. R 4 and the fifth resistor R 5; The source of the third MOSFET M3 is connected to the output terminal of the LDO, and its gate is connected to the drain of the second MOSFET M2 in the overshoot voltage amplification module. The drain is connected to the gate of the LDO power transistor; the source of the eighth MOSFET M8 is connected to the fourth resistor. R 4. Grounded, the gate is connected to the drain of the seventh MOSFET M7 in the undershoot voltage amplification module, and the drain is connected to the fifth resistor. R 5 is connected to the gate of the LDO power transistor.

[0014] Preferably, when the load current changes from heavy load to light load, the output voltage rises, generating an overshoot voltage. The overshoot voltage is coupled to the gate of the first MOSFET M1 via the first capacitor C1, and after being amplified by the first MOSFET M1, it acts on the gate of the third MOSFET M3. The third MOSFET M3 turns on instantaneously, charging the gate of the LDO power transistor. The gate voltage of the LDO power transistor rises, the output current decreases, and the output voltage drops.

[0015] If the overshoot voltage is Adjust the voltage change at the gate of the third MOSFET M3 in the module as follows: Then the instantaneous charging current of the third MOSFET M3 to the gate of the LDO power transistor for: ,in Indicates hole mobility. Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L M3 indicates the channel length of the MOSFET, and M3 indicates the third MOSFET.

[0016] Preferably, when the load current jumps from light load to heavy load in a short time, the output voltage generates a downshoot voltage. The downshoot voltage is coupled to the gate of the sixth MOSFET M6 by the second capacitor C2. After being amplified by the sixth MOSFET M6, it acts on the gate of the eighth MOSFET M8. The eighth MOSFET M8 turns on instantaneously, discharging the gate of the LDO power transistor. The gate voltage of the LDO power transistor drops instantaneously, the output current increases, and the output voltage rises.

[0017] If the down-thrust voltage is The voltage change at the gate of the eighth MOSFET M8 in the adjustment module is... Then the instantaneous charging current of the eighth MOSFET M8 to the gate of the LDO power transistor for: ,in Indicates electron mobility, Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L This indicates the channel length of the MOSFET, and M8 indicates the eighth MOSFET.

[0018] Preferably, in steady state, the first MOSFET M1, the third MOSFET M3, the sixth MOSFET M6, and the eighth MOSFET M8 are not turned on, which can achieve low power consumption and keep the loop bandwidth unchanged, without affecting the loop phase margin.

[0019] The beneficial effects of this invention are as follows: By sampling the output voltage, this invention generates an adjustment signal to rapidly charge and discharge the gate node of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor and suppressing overshoot / undershoot voltages. The transient enhancement circuit designed in this way does not consume static power consumption or affect loop stability in steady state, and can suppress overshoot / undershoot voltages during load transitions, improving transient response characteristics. It solves the problems of high power consumption and impact on loop stability in traditional dynamic bias circuits, and also addresses the problems of high power consumption and inability to improve undershoot voltage in traditional slew rate enhancement circuits.

[0020] The following specific performance results were obtained through experimental verification:

[0021] 1) Low power consumption characteristics:

[0022] In steady state, it consumes only 22.57nA of static current and the module is completely shut down, achieving zero additional power consumption; in dynamic operation, it is only activated momentarily by load switching, avoiding the defect of continuous power consumption in traditional circuits.

[0023] 2) Stability Guarantee:

[0024] Under steady-state conditions, the loop bandwidth and phase margin are not disturbed, ensuring the original stability of the LDO; the dynamically adjusted signal is processed through an independent module, decoupled from the main loop design.

[0025] 3) Transient response optimization:

[0026] The overshoot voltage decreased from 312.6mV to 163.5mV, and the undershoot voltage decreased from 225.5mV to 160.5mV. The gate slew rate was enhanced bidirectionally through dual-module collaboration (overshoot / undershoot amplification), and the charging and discharging current was significantly improved.

[0027] In summary, this invention simultaneously addresses the three major pain points of traditional solutions: "high power consumption," "stability degradation," and "lack of undershoot improvement," making it suitable for high-precision power management scenarios.

[0028] Other advantages, objectives, and features of the invention will be set forth in part in the description which follows, and in part will be apparent to those skilled in the art from the following examination, or may be learned from practice of the invention. The objectives and other advantages of the invention can be realized and obtained through the following description. Attached Figure Description

[0029] To make the objectives, technical solutions, and advantages of the present invention clearer, the preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:

[0030] Figure 1 This is a dynamic bias circuit for traditional transient enhancement circuits;

[0031] Figure 2 This is a slew rate enhancement circuit for traditional transient enhancement circuits;

[0032] Figure 3 A schematic diagram of the LDO low-power transient enhancement circuit structure provided by the present invention;

[0033] Figure 4 This is a circuit diagram of an LDO low-power transient enhancement circuit provided in an embodiment of the present invention;

[0034] Figure 5 The transient response curves of the load before and after using the transient enhancement circuit of the present invention are shown.

[0035] Figure 6 This refers to the static power consumption of the transient enhancement circuit. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0037] The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures. They should not be construed as limiting the invention. To better illustrate the embodiments of the invention, some parts in the drawings may be omitted, enlarged, or reduced, and do not represent the actual product dimensions. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0038] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components. In the description of the present invention, it should be understood that if terms such as "upper," "lower," "left," "right," "front," and "rear" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the terms used to describe positional relationships in the drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0039] This invention provides a low-power transient enhancement circuit for LDOs used in large-area image sensors, such as... Figure 3 As shown, it includes an overshoot voltage amplification module, an undershoot voltage amplification module, and an adjustment module. The input terminals of the overshoot voltage amplification module and the undershoot voltage amplification module are connected to the output terminal of the LDO, and their output terminals are grounded to the adjustment module. The adjustment module has two input terminals: the first input terminal is connected to the overshoot voltage amplification module, the second input terminal is connected to the undershoot voltage amplification module, and its output terminal is connected to the gate of the LDO power transistor.

[0040] The overshoot voltage amplification module plays a role when the load current changes abruptly from heavy load to light load. It amplifies the transient overshoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. Then, the adjustment module is turned on to charge the gate of the power transistor and enhance the gate slew rate of the power transistor.

[0041] The undershoot voltage amplification module plays a role when the load current changes abruptly from light load to heavy load. It amplifies the transient undershoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. Then, the adjustment module turns on to discharge the gate of the power transistor and enhance the gate slew rate of the power transistor.

[0042] The adjustment module is in the off state when the load current is stable, which does not affect the normal operation of the LDO. It only charges and discharges the gate of the power transistor when the load changes, thereby enhancing the gate slew rate of the power transistor.

[0043] like Figure 4 As shown, R 1. C 1. R 3. M1 and M2 constitute an overshoot voltage amplifier circuit. R 2. C 2. M4~M7 form a downshoot voltage amplifier circuit. The overshoot / downshoot voltage amplifier circuit can control the output voltage. V OUT Sampling, M3, M8 R 4. R 5. The adjustment module consists of the LDO power transistor gate. V G Connected to the gate of the LDO power transistor, it allows for rapid charging and discharging of the power transistor's gate capacitance.

[0044] Example 1:

[0045] like Figure 4 As shown, the overshoot voltage amplification module includes a first MOSFET M1, a second MOSFET M2, and a first capacitor. C 1. First resistor R 1 and the third resistor R 3; The gate of the first MOSFET M1 is connected to the first capacitor. C 1. LDO output terminal (i.e., output voltage) V OUT The connection is also made through the first resistor. R 1 Connect to the reference voltage terminal V REF The source of the first MOSFET M1 is connected to the third resistor. R 3. Grounded; the drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1 and the gate of the third MOSFET M3, and the gate is connected to the battery voltage V. BP The source is connected to the source of the third MOSFET M3 and the output terminal of the LDO.

[0046] The specific working principle is as follows: When the load current changes from heavy load to light load, the output voltage rises, generating an overshoot voltage. The overshoot voltage is coupled to the gate of the first MOSFET M1 through the first capacitor C1, and after being amplified by the first MOSFET M1, it acts on the gate of the third MOSFET M3. The third MOSFET M3 turns on instantaneously, charging the gate of the LDO power transistor. The gate voltage of the LDO power transistor rises, the output current decreases, and the output voltage drops.

[0047] If the overshoot voltage is Adjust the voltage change at the gate of the third MOSFET M3 in the module as follows: Then the instantaneous charging current of the third MOSFET M3 to the gate of the LDO power transistor for: ,in Indicates hole mobility. Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L M3 indicates the channel length of the MOSFET, and M3 indicates the third MOSFET.

[0048] Example 2:

[0049] like Figure 4 As shown, the undershoot voltage amplification module includes the fourth MOSFET M4 to the seventh MOSFET M7, and the second resistor. R 2 and second capacitor C 2; The source of the fourth MOSFET M4 is connected to the output of the LDO, and its gate and drain are both connected to the source of the fifth MOSFET M5; the gate and drain of the fifth MOSFET M5 are both connected to the source of the sixth MOSFET M6; the gate of the sixth MOSFET M6 is connected to the gate of the seventh MOSFET M7, and also connected through a second resistor. R 2 Connect to the reference voltage terminal V REF It also uses a second capacitor C 2. Connect to the LDO output terminal; the drain of the seventh MOSFET M7 is connected to the drain of the sixth MOSFET M6 and the gate of the eighth MOSFET M8, and the source is grounded.

[0050] The specific working principle is as follows: When the load current jumps from light load to heavy load in a short time, the output voltage generates a downshoot voltage. The downshoot voltage is coupled to the gate of the sixth MOSFET M6 by the second capacitor C2. After being amplified by the sixth MOSFET M6, it acts on the gate of the eighth MOSFET M8. The eighth MOSFET M8 turns on instantaneously, discharging the gate of the LDO power transistor. The gate voltage of the LDO power transistor drops instantaneously, the output current increases, and the output voltage rises.

[0051] If the down-thrust voltage is The voltage change at the gate of the eighth MOSFET M8 in the adjustment module is... Then the instantaneous charging current of the eighth MOSFET M8 to the gate of the LDO power transistor for: ,in Indicates electron mobility, Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L This indicates the channel length of the MOSFET, and M8 indicates the eighth MOSFET.

[0052] Example 3:

[0053] The adjustment module includes the third MOSFET M3, the eighth MOSFET M8, and the fourth resistor. R 4 and the fifth resistor R 5; The source of the third MOSFET M3 is connected to the output terminal of the LDO (i.e., the output voltage). V OUT The gate of the MOSFET is connected to the drain of the second MOSFET M2, and the drain is connected to the gate of the LDO power transistor. V G Connection; the source of the eighth MOSFET M8 is connected to the fourth resistor. R 4 is grounded, and its gate is connected to the drain of the seventh MOSFET M7. The drain is connected to the fifth resistor. R 5 and LDO power transistor gate V G connect.

[0054] The specific working principle is as follows: In steady state, the first MOSFET M1, the third MOSFET M3, the sixth MOSFET M6, and the eighth MOSFET M8 are not turned on, which can achieve low power consumption and the loop bandwidth remains unchanged, without affecting the loop phase margin.

[0055] Verification experiment:

[0056] right Figure 4 The circuit was schematically built on the Cadence platform using Virtuoso and verified using Spectre simulation. Transient response refers to the change in output voltage caused by a rapid change in load current; undershoot and overshoot occur during sudden changes from light load to heavy load and from heavy load to light load, respectively. To demonstrate the optimization of transient response characteristics by the transient enhancement circuit of this invention, load transient response curves before and after using the transient enhancement circuit are plotted on the same coordinate system, as shown below. Figure 5As shown in the figure, the load current abruptly changes between 1mA and 100mA, with a change-through time of 15µs. Simulation results show that without the slew rate enhancement circuit, the LDO output voltage undershoot reaches 225.5mV, while with the slew rate enhancement circuit, the output voltage undershoot is only 160.5mV; the output overshoot without the slew rate enhancement circuit is 312.6mV, while with the slew rate enhancement circuit, the output voltage overshoot is 163.5mV. The slew rate enhancement circuit can significantly reduce the undershoot and overshoot of the LDO output voltage, optimizing the transient response characteristics of the LDO.

[0057] Figure 6 This represents the static power consumption of the transient enhancement circuit of this invention. The load current abruptly changes between 1mA and 100mA, with a change-through time of 15µs. Simulation results show that when the load current does not change abruptly, i.e., in steady state, the static power consumption of the transient enhancement circuit is only 22.57nA, exhibiting low power consumption characteristics.

[0058] As can be seen, the present invention is designed to perform large-current charging and discharging of the power transistor gate when the load changes, which significantly enhances the gate slew rate of the power transistor and thus improves the transient response characteristics of the circuit.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A low-power transient enhancement circuit for LDO (Large-area image sensor), characterized in that, It includes an overshoot voltage amplification module, an undershoot voltage amplification module, and an adjustment module; the input terminals of the overshoot voltage amplification module and the undershoot voltage amplification module are connected to the output terminal of the LDO, and the output terminal is connected to the adjustment module; the adjustment module has two input terminals, the first input terminal is connected to the overshoot voltage amplification module, the second input terminal is connected to the undershoot voltage amplification module, and the output terminal is connected to the gate of the LDO power transistor; The overshoot voltage amplification module functions when the load current suddenly changes from heavy load to light load. It amplifies the transient overshoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. The adjustment module then turns on to charge the gate of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor. The overshoot voltage amplification module includes a first MOSFET M1, a second MOSFET M2, and a first capacitor. C 1. First resistor R 1 and the third resistor R 3; The gate of the first MOSFET M1 is connected to the first capacitor. C 1 is connected to the LDO output terminal, and also through the first resistor. R 1 Connect to the reference voltage terminal V REF The source of the first MOSFET M1 is connected to the third resistor. R 3. Grounded; the drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1, and the gate is connected to the battery voltage V. BP The source is connected to the adjustment module and the LDO output. The undershoot voltage amplification module functions when the load current suddenly changes from light load to heavy load. It amplifies the transient undershoot voltage at the output terminal and transmits the amplified voltage to the adjustment module. Then, the adjustment module turns on to discharge the gate of the LDO power transistor, thereby enhancing the gate slew rate of the LDO power transistor. The undershoot voltage amplification module includes the fourth MOSFET M4 to the seventh MOSFET M7 and a second resistor. R 2 and second capacitor C 2; The source of the fourth MOSFET M4 is connected to the output of the LDO, and its gate and drain are both connected to the source of the fifth MOSFET M5; the gate and drain of the fifth MOSFET M5 are both connected to the source of the sixth MOSFET M6; the gate of the sixth MOSFET M6 is connected to the gate of the seventh MOSFET M7, and also connected through a second resistor. R 2 Connect to the reference voltage terminal V REF It also uses a second capacitor C 2. Connect to the LDO output terminal; the drain of the seventh MOSFET M7 is connected to the drain of the sixth MOSFET M6 and the adjustment module, and the source is grounded; The adjustment module is in a turned-off state when the load current is stable, which does not affect the normal operation of the LDO. It only charges and discharges the gate of the LDO power transistor when there is a load change, thereby enhancing the gate slew rate of the LDO power transistor. The adjustment module includes a third MOSFET M3, an eighth MOSFET M8, and a fourth resistor. R 4 and the fifth resistor R 5; The source of the third MOSFET M3 is connected to the output terminal of the LDO, and its gate is connected to the drain of the second MOSFET M2 in the overshoot voltage amplification module. The drain is connected to the gate of the LDO power transistor; the source of the eighth MOSFET M8 is connected to the fourth resistor. R 4. Grounded, the gate is connected to the drain of the seventh MOSFET M7 in the undershoot voltage amplification module, and the drain is connected to the fifth resistor. R 5 is connected to the gate of the LDO power transistor.

2. The LDO low-power transient enhancement circuit according to claim 1, characterized in that, When the load current changes from heavy load to light load, the output voltage rises, generating an overshoot voltage. The overshoot voltage is coupled to the gate of the first MOSFET M1 through the first capacitor C1, and after being amplified by the first MOSFET M1, it acts on the gate of the third MOSFET M3. The third MOSFET M3 turns on instantaneously, charging the gate of the LDO power transistor. The gate voltage of the LDO power transistor rises, the output current decreases, and the output voltage drops.

3. The LDO low-power transient enhancement circuit according to claim 2, characterized in that, If the overshoot voltage is Adjust the voltage change at the gate of the third MOSFET M3 in the module as follows: Then the instantaneous charging current of the third MOSFET M3 to the gate of the LDO power transistor for: ,in Indicates hole mobility. Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L M3 indicates the channel length of the MOSFET, and M3 indicates the third MOSFET.

4. The LDO low-power transient enhancement circuit according to claim 1, characterized in that, When the load current jumps from light load to heavy load in a short time, the output voltage generates a downshoot voltage. The downshoot voltage is coupled to the gate of the sixth MOSFET M6 by the second capacitor C2. After being amplified by the sixth MOSFET M6, it acts on the gate of the eighth MOSFET M8. The eighth MOSFET M8 turns on instantaneously, discharging the gate of the LDO power transistor. The gate voltage of the LDO power transistor drops instantaneously, the output current increases, and the output voltage rises.

5. The LDO low-power transient enhancement circuit according to claim 4, characterized in that, If the down-thrust voltage is The voltage change at the gate of the eighth MOSFET M8 in the adjustment module is... Then the instantaneous charging current of the eighth MOSFET M8 to the gate of the LDO power transistor for: ,in Indicates electron mobility. Indicates the oxide layer capacitance of the MOSFET. W Indicates the MOSFET channel width. L This indicates the channel length of the MOSFET, and M8 indicates the eighth MOSFET.

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