An address access control system, method, electronic device and storage medium

Abstract

This application discloses an address access control system, method, electronic device, and storage medium, relating to the field of computer technology. By polling the request input ports of each access storage controller core using an input module, it determines whether there is overlap between the current address to be accessed and the target address included in the address access control request, thus obtaining the address access control result for the current address to be accessed. This allows it to determine whether the current address to be accessed conflicts with the target address currently undergoing read / write operations. The address access control result is returned to the storage controller core through the result output port. Then, the storage controller core performs corresponding access operations on the current address to be accessed based on the result. This achieves address access control for multi-core storage controllers, improving the read / write performance of storage devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and particularly relates to an address access control system and method, an electronic device and a storage medium. BACKGROUND

[0002] A storage device such as a solid state disk (SSD) generally uses a special storage controller to read and write data in the storage device. In the read and write process of the storage device, there may be a case of accessing the same logical block address (LBA) before and after, such as initiating a write operation on an LBA address that is being read. Therefore, the storage controller needs to control the LBA address in the read and write process through an address access control module to avoid the impact of the subsequently initiated write operation on the execution of the read operation.

[0003] In related technologies, since the current storage device generally uses a multi-core storage controller, there is an urgent need for an address access control method that can be applied to a multi-core storage controller, which is of great significance to improving the read and write performance of the storage device. SUMMARY

[0004] The present application provides an address access control system and method, an electronic device and a storage medium to at least solve the problem of how to control the address access of a multi-core storage controller in related technologies to improve the read and write performance of the storage device.

[0005] The present application provides an address access control system, comprising: an input module, a control module and an output module.

[0006] The input module is configured to poll each storage controller core corresponding request input port to receive the address access control request sent by each storage controller core. The request input port is one-to-one corresponding to the storage controller core, and the address access control request at least includes a to-be-controlled access address, and the to-be-controlled access address includes a current to-be-accessed address.

[0007] The control module is configured to, when receiving the address access control request sent by any storage controller core, in response to the address access control request, judge whether there is an overlap between the current to-be-accessed address and a target access address to obtain an address access control result of the current to-be-accessed address.

[0008] The output module is configured to return the address access control result to the corresponding storage controller core through the result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result. The result output port is one-to-one corresponding to the storage controller core.

[0009] The application further provides an address access control method, comprising:

[0010] The request input port corresponding to each storage controller core is polled to receive an address access control request sent by each storage controller core; the request input port corresponds to the storage controller core one by one, and the address access control request at least comprises a to-be-controlled access address, and the to-be-controlled access address comprises a current to-be-accessed address;

[0011] When the address access control request sent by any storage controller core is received, whether there is an overlap between the current to-be-accessed address and a target access address is judged in response to the address access control request, so as to obtain an address access control result of the current to-be-accessed address;

[0012] The address access control result is returned to the corresponding storage controller core through the result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result;

[0013] The result output port corresponds to the storage controller core one by one.

[0014] The application further provides an address access control device, comprising:

[0015] The input module is used for polling the request input port corresponding to each storage controller core to receive an address access control request sent by each storage controller core; the request input port corresponds to the storage controller core one by one, and the address access control request at least comprises a to-be-controlled access address, and the to-be-controlled access address comprises a current to-be-accessed address;

[0016] The control module is used for, when the address access control request sent by any storage controller core is received, judging whether there is an overlap between the current to-be-accessed address and a target access address in response to the address access control request, so as to obtain an address access control result of the current to-be-accessed address;

[0017] The output module is used for returning the address access control result to the corresponding storage controller core through the result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result;

[0018] The application further provides an electronic device, comprising: a memory used for storing a computer program; and a processor used for executing the computer program to realize the steps of any one of the address access control methods.

[0019] The application further provides a computer readable storage medium, and the computer readable storage medium stores a computer program.

[0020] The application further provides a computer program product, which comprises a computer program.

[0021] According to the application, the address access control request sent by each request input port accessing the storage controller core is polled by the input module, it is judged whether there is an overlap between the current to-be-accessed address and the target access address contained in the address access control request, the address access control result of the current to-be-accessed address is obtained, that is, it is judged whether there is a conflict between the current to-be-accessed address and the target access address which is being read or written, the address access control result is returned to the storage controller core through the result output port, and then the storage controller core performs corresponding access operation on the current to-be-accessed address according to the result, so that the address access control of the multi-core storage controller is realized, and the read-write performance of the storage device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0023] Figure 1 An interactive flowchart of the address access control system provided by the embodiments of the application is shown.

[0024] Figure 2 An exemplary structural diagram of the address access control system provided by the embodiments of the application is shown.

[0025] Figure 3 An exemplary structural diagram of the arbiter in the address access control system provided by the embodiments of the application is shown.

[0026] Figure 4 An exemplary structural diagram of the control module in the address access control system provided by the embodiments of the application is shown.

[0027] Figure 5 An exemplary structural diagram of the control unit state machine in the address access control system provided by the embodiments of the application is shown.

[0028] Figure 6 A flowchart of the address access control method provided by the embodiments of the application is shown.

[0029] Figure 7 A structural schematic diagram of an address access control device provided by an embodiment of the present application is shown in FIG. 1.

[0030] Figure 8 A structural schematic diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 2. DETAILED DESCRIPTION

[0031] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0032] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0033] The SSD controller is the core control unit of the solid state disk, which undertakes the management of data read-write scheduling, address conversion, wear leveling and other functions. The SSD controller is also called a storage controller. The host and the SSD interact with each other through logical block addresses.

[0034] In related technologies, since the current storage device usually adopts a multi-core storage controller, there is an urgent need for an address access control method that can be applied to a multi-core storage controller, which is of great significance to improving the read-write performance of the storage device.

[0035] Embodiments of the present application are provided to solve the above technical problems, and provide an address access control system, method, electronic device and storage medium. In the address access control system, the address access control request sent by each request input port of the access storage controller core is polled by the input module, and it is determined whether there is an overlap between the current to-be-accessed address and the target access address included in the address access control request, so as to obtain the address access control result of the current to-be-accessed address, that is, it can be determined whether there is a conflict between the current to-be-accessed address and the target access address which is being read and written. The address access control result is returned to the storage controller core through the result output port, and then the storage controller core performs corresponding access operation on the current to-be-accessed address according to the result, thereby realizing address access control of the multi-core storage controller and improving the read and write performance of the storage device.

[0036] In order for those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0037] Embodiments of the present application provide an address access control system for performing address access control on a multi-core storage controller.

[0038] As shown in Figure 1 , an interaction flow diagram of the address access control system provided by the embodiments of the present application is shown, and the system includes an input module, a control module and an output module.

[0039] The input module is configured to poll each request input port corresponding to the storage controller core to receive the address access control request sent by each storage controller core. The request input port is in one-to-one correspondence with the storage controller core, and the address access control request at least includes a to-be-controlled access address, and the to-be-controlled access address includes a current to-be-accessed address. The control module is configured to, when receiving the address access control request sent by any storage controller core, in response to the address access control request, determine whether there is an overlap between the current to-be-accessed address and the target access address, so as to obtain the address access control result of the current to-be-accessed address. The output module is configured to return the address access control result to the corresponding storage controller core through the result output port, so that the storage controller core performs corresponding access operation on the current to-be-accessed address according to the address access control result. The result output port is in one-to-one correspondence with the storage controller core.

[0040] Specifically, the storage controller core can send an address access control request, and before the storage controller core performs a read operation or a write operation, determine whether to perform an access operation on a current to-be-accessed address by judging whether there is a conflict between the current to-be-accessed address in the address access control request and an address being used and allowed to be used by other storage controller cores. The input module includes a plurality of request input ports, one storage controller core corresponding to one request input port, the number of request input ports can be determined by the number of storage controller cores, and the request input ports are set according to the actual demand of the storage controller cores, and the request input ports are used to input the address access control request. The output module includes a plurality of result output ports, one storage controller core corresponding to one result output port, the number of result output ports can also be determined by the storage controller cores, and the result output ports are set according to the actual demand of the storage controller cores, and are used to output the obtained address access control result corresponding to the current to-be-accessed address to the corresponding storage controller core. The address access control request includes a to-be-controlled access address, and the to-be-controlled access address includes a current to-be-accessed address. The current to-be-accessed address refers to an address space that the storage controller core polls the input module and wants to access in the address access control request sent by the storage controller core. The address space may have an address space overlap with a target access address, wherein the overlap includes that the two address spaces are completely same or partially same.

[0041] For example, as Figure 2As shown, the structural schematic diagram of the exemplary address access control system provided by the embodiment of the present application, the register list can store some configuration information according to the needs, the configuration information can include the capacity of the intermediate buffer and the destination buffer, the control module controls the operation of the whole system, the flow direction of the data. First, a storage controller core corresponds to a request input port, the input module will poll each request input port, the address access control request of the storage controller core will be sent to the corresponding request input port through the bus, when the input module polls any request input port, the request input port exists an address access control request, the control module will receive the address access control request, then the control module analyzes the address access control request, obtains the corresponding data content in the address access control request, the data content includes the current to-be-accessed address, then compares the obtained current to-be-accessed address with the target access address in the control module, judges whether the address spaces of the two exist overlap, and then sends the obtained result to the output module, the result output port returns the address access control result to the corresponding storage controller core through the bus, and the storage controller core performs corresponding access operation on the current to-be-accessed address according to the obtained result. For example: the storage controller core 0 corresponds to the request input port 0 (Inbound 0) and the result output port (Outbound 0), the Inbound 0 receives the address access control request sent by the storage controller core 0 through the advanced extensible interface bus (Advanced eXtensible Interface Bus, AXI BUS for short), processes the address access control request sent by the Inbound 0 through the control module, judges whether there is overlap between the current to-be-accessed address in the address access control request and the target access address, obtains the address access control result of the current to-be-accessed address, inputs the address access control result to the Outbound 0, and then the Outbound 0 returns the address access control result to the corresponding storage controller core 0, and then the storage controller core 0 performs corresponding access operation on the current to-be-accessed address according to the address access control result. Similarly, the storage controller core 2 corresponds to the Inbound 2 and the Outbound 2, the storage controller core 3 corresponds to the Inbound 3 and the Outbound 3, and so on.

[0042] Correspondingly, by judging whether there is overlap between the current to-be-accessed address and the target access address, the obtained address access control result can judge whether the access operation can be performed before the storage controller core formally accesses the current to-be-accessed address, so as to avoid access conflict of the storage controller core to the same address.

[0043] On the basis of the above embodiment, as a kind of implementable mode, in an embodiment, input module includes:

[0044] The arbiter is configured to poll a request input port corresponding to each storage controller core, and determine whether a result output port corresponding to the currently polled request input port meets a preset output condition when the currently polled request input port is not empty; and receive an address access control request sent by the currently polled request input port when the result output port corresponding to the currently polled request input port meets the preset output condition.

[0045] Specifically, one storage controller core corresponds to one request input port. When the input module polls to any request input port corresponding to a storage controller core, the request input port is the currently polled request input port. When the storage controller core sends an address access control request to the corresponding request input port, the corresponding request input port is not empty. At this time, the input module determines whether the result output port corresponding to the storage controller core is full. When the result output port is not full, i.e., the preset output condition is met, the control module receives the address access control request sent by the currently polled request input port.

[0046] Correspondingly, by determining the state of the result output port of the currently polled request input port through the arbiter, it can be determined whether the input module responds to the address access control request of the storage controller core. If the response is received, the address access control request is provided for the subsequent control module.

[0047] Specifically, in an embodiment, the arbiter is further configured to poll a next request input port in sequence when the currently polled request input port is empty or the result output port corresponding to the currently polled request input port does not meet the preset output condition.

[0048] Specifically, one storage controller core corresponds to one request input port. When the input module polls to any request input port corresponding to a storage controller core, the request input port is the currently polled request input port. When the storage controller core sends an address access control request to the corresponding request input port, the corresponding request input port is not empty. At this time, the input module determines whether the result output port corresponding to the storage controller core is full. When the result output port is not full, i.e., the preset output condition is met, the control module receives the address access control request sent by the currently polled request input port.

[0049] As shown in Figure 3 As shown in the structure diagram of the arbiter in the address access control system provided by the embodiment of the present application, it is assumed that there are four request input ports, Inbound 0, Inbound 1, Inbound 2 and Inbound 3, X in Inbound X represents the serial number of the request input port, and in the embodiment, X can be 0, 1, 2 and 3. First, the polling mode is adopted to obtain the address access control request from Inbound 0, and the data in Inbound 0 is obtained first when there is data in Inbound 0. 1 represents that Inbound has data, and 0 represents that Inbound has no data. There are 16 cases in total, as shown in Table 1:

[0050] Table 1

[0051]

[0052] The order of polling of Inbound 0 -> Inbound 1 -> Inbound 2 -> Inbound 3 -> Inbound 0, the input module first checks whether there is an address access control request in Inbound 0, X number of request input port empty signal (iq_X_empty), X number of request input port request read signal (iq_X_req), arbiter selection signal (iq_arb=X), X number of result output port full signal (oq_X_full), X number of request input port allows reading signal (iq_X_pop), and the specific data of the corresponding address access control request in X number of request input port (iq_X_rdata). Inbound 0 sends a 0 number of request input port empty request (iq_0_empty) to the arbiter, that is, judges iq_0_empty, if iq_0_empty is 0, it means that there is an address access control request to be taken in Inbound 0, then sends a 0 number of request input port request read signal (iq_0_req), which means that the input module requests to read the address access control in Inbound 0. By default, Inbound 0 is selected for polling judgment first, at this time the arbiter selection signal selects the 0 number of request input port (iq_arb=0), which means that the arbiter selects Inbound 0 for polling judgment. Then the input module judges whether the 0 number of result output port full signal (oq_0_full) is 1, which means judging whether the corresponding Outbound 0 of Inbound 0 is full, if oq_0_full is not 1, then calculate the 0 number of request input port allows reading signal (iq_0_pop), iq_0_pop=(iq_0_req)&(iq_arb=0)&(!oq_0_full), when iq_X_pop=1, the arbiter sends a 0 number of request input port allows reading signal (iq_0_pop) to Inbound 0, which means allowing the address access control request in Inbound 0 to be sent to the arbiter, and the FSM samples the specific address access control request data (iq_0_rdata) in the 0 number of request input port, which means that Inbound 0 sends the content of the address access control request to the arbiter. In order to realize the polling control, when iq_X_req is issued, iq_arb+1 is executed, and the value of iq_arb is 0, 1, 2 and 3.

[0053] Specifically, assuming there are pending address access control requests in Inbound 0 through Inbound 3, and oq_X_full=0, firstly, it is checked that there are address access control requests in Inbound X that need to be retrieved. At this time, there is data in Inbound 0 through Inbound 3, so iq_0_empty=0, iq_1_empty=0, iq_2_empty=0, iq_3_empty=0. At this time, iq_0_req, iq_1_req, iq_2_req, and iq_3_req will be issued, and iq_arb=0. Secondly, iq_X_pop is issued. Because iq_arb=0 at this time, iq_0_pop = (iq_X_req) & (iq_arb=0) & (!oq_0_full), iq_0_pop is issued, and the FSM samples the data of iq_0_rdata. Incrementing `iq_arb` by 1 makes `iq_arb` equal to 1. Following this process, the input module can then poll the requested input port.

[0054] Accordingly, by judging the status of the current access request input port and result output port through the arbitrator, it can be determined whether the input module responds to the address access control request of the storage controller core. If it does not respond, the next request input port can be polled directly to achieve polling access.

[0055] Based on the above embodiments, as one implementable approach, in one embodiment, the control module includes:

[0056] An intermediate buffer is used to cache the first access address, which includes historical addresses that are not allowed to be accessed.

[0057] A destination cache is used to cache a second access address; wherein the second access address includes an address that any storage controller core is currently accessing and a historical address that is allowed to be accessed, and the target access address includes the first access address and the second access address.

[0058] The control unit is used to determine whether there is an overlap between the current address to be accessed and the target address when it receives an address access control request sent by any storage controller core, so as to obtain the address access control result of the address to be accessed.

[0059] Specifically, for any polled selected storage controller core, all the first access addresses and the second access addresses previously stored in the destination buffer and the intermediate buffer are historical to-be-accessed addresses. The destination buffer is used to store the address space being used by the storage controller core and the historical to-be-accessed addresses, i.e., the second access addresses, which are allowed to be accessed. The intermediate buffer is used to store the addresses, i.e., the first access addresses, for which the current to-be-accessed addresses received by the control module in the previous polling process exist address space overlap with the second access addresses. The first access addresses are not allowed to be accessed because they exist overlap with the second access addresses, i.e., with the address space being used or allowed to be used by each storage controller core, and thus the first access addresses include the historical to-be-accessed addresses which are not allowed to be accessed.

[0060] The intermediate buffer can reduce the operation of the storage controller core on the module, for example, when adding a command, if the current to-be-accessed address exists overlap with the second access addresses in the destination buffer, the address cannot be accessed by the corresponding storage controller core immediately, and can be temporarily cached in the intermediate buffer to wait for being extracted to perform the access operation, without the need for the storage controller core to resend the address access control request. For any polled selected storage controller core, the control module responds to the address access control request when receiving the address access control request sent by the storage controller core, and judges whether there exists address space overlap between the current to-be-accessed address in the address access control request and the target access address, and the target access address includes the first access address and the second access address, and then obtains the address access control result of the to-be-accessed address.

[0061] For example, as shown in FIG. 1, an exemplary address access control system provided by an embodiment of the present application includes a control module, a plurality of storage controller cores, and a plurality of storage devices. Figure 4 As shown in FIG. 2, an exemplary structure diagram of the control module in the address access control system provided by the embodiment of the present application is shown. The destination buffer is a data storage space composed of static random access memory (SRAM), and is used to store the second access addresses, i.e., the addresses being accessed by the storage controller core and the historical to-be-accessed addresses which are allowed to be accessed, and any two LBAs stored in the addresses do not exist overlap. The intermediate buffer is a data storage space used to store the first access addresses, and adopts a first-in-first-out mechanism, i.e., stores the current to-be-accessed addresses which exist overlap with the second access addresses in the destination buffer or stores the current to-be-accessed addresses which exist overlap with the first access addresses in the intermediate buffer. The control unit state machine is a finite state machine (FSM) used to control the running of the entire system, and different states will transmit data to different positions.

[0062] For example, as shown in FIG. 3, an exemplary structure diagram of the storage controller core in the address access control system provided by the embodiment of the present application is shown. The storage controller core includes a control module, a plurality of storage devices, and a plurality of address access control request queues. Figure 5As shown, the structure diagram of the control unit state machine in the exemplary address access control system provided by the embodiment of the present application is shown, the states in the control unit state machine include an initial state (IDLE), an intermediate buffer checking state (check pend, CKP for short) for checking the state of the intermediate buffer, a destination buffer checking state (check array, CKA for short) for checking the state of the destination buffer, and a result output state (SCPL) for writing the return result into the result output port. The data for starting the control unit state machine can be the data taken out from the request input port, or the data taken out from the intermediate buffer.

[0063] Correspondingly, by setting the intermediate buffer and the destination buffer, the current address to be accessed can be distinguished, so as to avoid the conflict that the storage controller core being polled accesses the address being used and allowed to be used by the storage controller core.

[0064] Specifically, in an embodiment, the control unit is specifically used for:

[0065] When receiving the address access control request sent by any storage controller core, the control command in the address access control request is parsed;

[0066] In the case that the control command in the address access control request is a checking command, the control unit state machine is switched from the initial state to the intermediate buffer checking state;

[0067] In the intermediate buffer checking state, it is judged whether there is an overlap between the current address to be accessed and the first access address in the intermediate buffer, a first overlap judgment result is obtained, and the control unit state machine is switched from the intermediate buffer checking state to the destination buffer checking state;

[0068] In the destination buffer checking state, it is judged whether there is an overlap between the current address to be accessed and the second access address in the destination buffer, a second overlap judgment result is obtained, and the control unit state machine is switched from the destination buffer checking state to the result output state;

[0069] In the result output state, the first overlap judgment result and the second overlap judgment result are written into the result output port corresponding to the storage controller core;

[0070] Among them, the address access control result includes the first overlap judgment result and the second overlap judgment result.

[0071] Specifically, for any polled selected storage controller core, the control module parses the control command in the address access control request sent by the storage controller core to the request input port through the bus when receiving the address access control request, wherein the control command includes a check command, and the address access control request of the check command is usually a write operation, and the current to-be-accessed address in the address access control request is parsed. In the case where the control command in the address access control request is the check command, the control unit state machine is input from the initial state, that is, the IDLE state, to the intermediate buffer empty state, that is, whether the intermediate buffer empty signal (P_EMPTY) is 0, when the intermediate buffer is in the non-empty state, that is, P_EMPTY=0, the control unit state machine is switched to the intermediate buffer check state, that is, the CKP state, in the intermediate buffer check state, whether there is an address space overlap between the current to-be-accessed address and all the first access addresses in the intermediate buffer is determined, and the address space overlap between the current to-be-accessed address and all the first access addresses in the intermediate buffer is obtained, that is, the first overlap judgment result, including three cases that the address space between the current to-be-accessed address and the first access address in the intermediate buffer exists full overlap, partial overlap and no overlap, after the comparison between the current to-be-accessed address and all the first access addresses in the intermediate buffer is completed, that is, the intermediate buffer check completion signal is 1 (CKP_DONE=1), the control unit state machine is switched from the intermediate buffer check state to the destination buffer check state, that is, the CKA state, in the destination buffer check state, whether there is an address space overlap between the current to-be-accessed address and the second access address in the destination buffer is determined, and the address space overlap between the current to-be-accessed address and the second access address in the destination buffer is obtained, that is, the second overlap judgment result, including three cases that the address space between the current to-be-accessed address and the second access address in the destination buffer exists full overlap, partial overlap and no overlap, after the comparison between the current to-be-accessed address and all the second access addresses in the destination buffer is completed, that is, the destination buffer check completion signal is 1 (CKA_DONE=1), the control unit state machine is switched from the destination buffer check state to the result output state, that is, the SCPL state, in the result output state, the first overlap judgment result and the second overlap judgment result are written into the result output port corresponding to the storage controller core, wherein the address access control result includes the first overlap judgment result and the second overlap judgment result.

[0072] Correspondingly, through the check command, it can be judged whether the current to-be-accessed address conflicts with the address being accessed by the polled storage controller core and being used and allowed to be used by the storage controller core, and whether there is an overlap with the first access address.

[0073] Specifically, in an embodiment, the control unit is further configured to:

[0074] In a case where the control command in the address access control request is an add command, the control unit state machine is switched from the initial state to an intermediate buffer checking state;

[0075] In the intermediate buffer checking state, it is judged whether there is an overlap between the current to-be-accessed address and the first access addresses in the intermediate buffer, to obtain a first overlap judgment result;

[0076] In a case where the first overlap judgment result indicates that there is an overlap between the current to-be-accessed address and any first access address, the current to-be-accessed address is written into the intermediate buffer as a new first access address.

[0077] Specifically, for any storage controller core selected by polling, the control module, when receiving an address access control request sent by the storage controller core to the request input port through the bus, parses the control command in the address access control request, wherein the control command includes an add command, and the address access control request of the add command is usually a read operation, and parses the current to-be-accessed address in the address access control request. In a case where the control command in the address access control request is an add command, the control unit state machine is switched from the initial state, i.e., the IDLE state, to the input module judging whether the intermediate buffer is empty, i.e., whether P_EMPTY is 0. When the intermediate buffer is in a non-empty state, i.e., P_EMPTY=0, the control unit state machine is switched to the intermediate buffer checking state, i.e., the CKP state. In the intermediate buffer checking state, it is judged whether there is an overlap between the current to-be-accessed address and all first access addresses in the intermediate buffer, to obtain a first overlap judgment result. After the current to-be-accessed address is compared with all first access addresses in the intermediate buffer, i.e., CKP_DONE=1, if there is an overlap between the current to-be-accessed address and the first access addresses in the intermediate buffer, the current to-be-accessed address cannot be accessed, and therefore the current to-be-accessed address is directly written into the intermediate buffer as a new first access address. When the intermediate buffer is in an empty state, i.e., P_EMPTY=1, the control unit state machine is switched to the destination buffer checking state, i.e., the CKA state.

[0078] Correspondingly, through the add command, it can be judged whether there is an overlap between the current to-be-accessed address and the first access address. When there is an overlap, it indicates that the address must have an overlap with the second access address, and the data content of the address space is being accessed by other storage controller cores. The current to-be-accessed address can be classified into the intermediate buffer, and the storage controller core temporarily does not perform an access operation on the address.

[0079] Specifically, in an embodiment, the control unit is further configured to:

[0080] In a case where the first overlap judgment result indicates that the current to-be-accessed address does not overlap with each first access address, the control unit state machine is switched from the intermediate cache checking state to a destination cache checking state;

[0081] In the destination cache checking state, it is judged whether the current to-be-accessed address overlaps with a second access address in the destination cache, to obtain a second overlap judgment result;

[0082] In a case where the second overlap judgment result indicates that the current to-be-accessed address overlaps with any second access address, the current to-be-accessed address is written into the intermediate cache as a new first access address.

[0083] Specifically, because there is a case where the current to-be-accessed address does not overlap with the first access address in the intermediate cache but may overlap with the second access address in the destination cache, the storage controller core polled in this case also cannot perform an access operation on the current to-be-accessed address, therefore, in a case where the current to-be-accessed address does not overlap with all first access addresses in the intermediate cache, the control unit state machine is switched from the intermediate cache checking state (CKP state) to the destination cache checking state (CKA state). Or when the intermediate cache is empty, i.e., P_EMPTY=1, the control unit state machine is switched to the destination cache checking state, i.e., CKA state. In the destination cache checking state, it is judged whether the current to-be-accessed address overlaps with the second access address in the destination cache, to obtain a second overlap judgment result. It is judged whether the current to-be-accessed address overlaps with any address being used or allowed to be used by a storage controller core, in a case where the current to-be-accessed address is compared with all first access addresses in the intermediate cache, i.e., CKP_DONE=1, if the current to-be-accessed address overlaps with the second access address in the destination cache, the access operation on the current to-be-accessed address cannot be performed, and the current to-be-accessed address is written into the intermediate cache as a new first access address.

[0084] Correspondingly, even if the current to-be-accessed address does not overlap with the first access address in the intermediate cache, it is also judged whether it overlaps with the second access address in the destination cache. When overlap occurs, it indicates that the data content of the address space is being accessed by another storage controller core, and the current to-be-accessed address is also included in the intermediate cache, so that the storage controller core temporarily does not perform an access operation on the address, to avoid an access conflict.

[0085] Specifically, in an embodiment, the control unit is further configured to, in a case where the second overlap judgment result indicates that the current to-be-accessed address does not overlap with each of the second access addresses, write the current to-be-accessed address as a new second access address into the destination buffer, and switch the control unit state machine from the destination buffer checking state to a result output state; and in the result output state, generate the cache location information of the current to-be-accessed address in the destination buffer. The address access control result of the to-be-accessed address includes the cache location information of the current to-be-accessed address in the destination buffer.

[0086] Specifically, in a case where the current to-be-accessed address neither overlaps with the first access address in the intermediate buffer nor overlaps with the second access address in the destination buffer, the current to-be-accessed address can be normally accessed by the corresponding storage controller core, and thus the current to-be-accessed address is written as a new second access address into the destination buffer, and then the control unit state machine is switched from the destination buffer checking state to a result output state, and in the result output state, the cache location information of the current to-be-accessed address in the destination buffer is generated. The address access control result of the to-be-accessed address includes the cache location information of the current to-be-accessed address in the destination buffer.

[0087] Correspondingly, in a case where the current to-be-accessed address does not overlap with the second access address in the destination buffer, it indicates that the storage controller core polled can perform an access operation on the address.

[0088] Specifically, in an embodiment, the control unit is further configured to, in a case where the control command in the address access control request is a delete command, the to-be-controlled access address includes a to-be-deleted access address; and delete the to-be-deleted access address in the destination buffer.

[0089] Specifically, the to-be-controlled access address includes a to-be-deleted access address. For any polled storage controller core, when the control module receives an address access control request sent by the storage controller core to the request input port through the bus, the control module parses the control command in the address access control request, where the control command includes a delete command, and parses the to-be-deleted access address in the address access control request. In a case where the control command in the address access control request is a delete command, the control unit state machine is in an initial state, i.e., an IDLE state, and at this time, the to-be-deleted access address is deleted in the destination buffer.

[0090] Correspondingly, when the storage controller core completes the access operation on the address, the address is a to-be-deleted access address, and by deleting the to-be-deleted access address in the destination buffer, other addresses can be normally accessed.

[0091] Specifically, in an embodiment, the control unit is further configured to:

[0092] After any to-be-deleted access address in the target cache is deleted, the control unit state machine is switched from the initial state to a target cache checking state, taking the first access address written into the intermediate cache as a target first access address in the order of writing into the intermediate cache;

[0093] In the target cache checking state, it is determined whether there is overlap between the target first access address and the second access addresses in the target cache, to obtain a second overlap determination result;

[0094] In a case where the second overlap determination result indicates that there is no overlap between the target first access address and each of the second access addresses in the target cache, the target first access address is written into the target cache as a new second access address, and the control unit state machine is switched from the target cache checking state to a result output state;

[0095] In the result output state, cache location information of the target first access address in the target cache is generated.

[0096] Specifically, after the to-be-deleted access address in the target cache is deleted, a new address is extracted from the intermediate cache and written into the target cache. In the intermediate cache, the first access address is extracted as a target first access address in the order of writing into the intermediate cache, and then the control unit state machine is switched from the initial state (IDLE state) to a target cache checking state (CKA state). In the target cache checking state, it is determined whether there is overlap between the target first access address and all the second access addresses in the target cache, i.e., CKA_DONE=1, to obtain a second overlap determination result. In a case where there is no overlap between the target first access address and all the second access addresses in the target cache, the target first access address is written into the target cache as a new second access address, and the control unit state machine is switched from the target cache checking state to a result output state (SCPL state). In the result output state, cache location information of the target first access address in the target cache is generated.

[0097] Correspondingly, by taking the first access address written into the intermediate cache as a target first access address in the order of writing into the intermediate cache, the historical to-be-accessed data in the intermediate cache can be extracted, and the first access address in the intermediate cache can be prevented from being accessed for a long time.

[0098] Specifically, in an embodiment, the control unit is further configured to:

[0099] In the case that the second overlap judgment result represents that there is an overlap between the target first access address and any second access address in the destination buffer, the target first access address is written into the intermediate buffer as a new first access address.

[0100] Specifically, in the destination buffer checking state, when there is an overlap between the target first access address and any second access address in the destination buffer, the storage controller core cannot perform an access operation on the target first access address, and the target first access address is written into the intermediate buffer as a new first access address. The meanings of the bit segments of the request input port, the intermediate buffer and the result output port are shown in Table 2 as follows:

[0101] Table 2

[0102]

[0103] Specifically, the request input port includes Inbound 0, Inbound 1, Inbound 2 and Inbound 3, etc., and the result output port includes Outbound 0, Outbound 1, Outbound 2 and Outbound 3, etc. The meanings of the bits in the request input port are as follows: bit[2:0] represents a command, 3’b001 represents a checking command, 3’b010 represents an adding command, and 3’b100 represents a deleting command. When the deleting command is executed, the corresponding bit[114:104] position in Inbound X is written as all 0. bit[15:3] is a reserved bit. When the number of bits of the operation code number is insufficient, the reserved bit is used for extension. bit[31:16] is used to represent the number of address access control requests initiated in the system. bit[53:32] is the length of the current access address. bit[63:54] is a reserved bit, which provides a range for the length of the current access address. bit[103:64] is the start address of the current access address. The address space of the entire current access address is LBA start address+LBA length-1. bit[114:104] is the position of the LBA on the target buffer.

[0104] In particular, the meaning of each bit of the intermediate cache is as follows: bit[103:0] has the same meaning as bit[103:0] in the request input port, wherein bit

[54] is 1, indicating that the current to-be-accessed address is added to the intermediate cache as a new first access address because the current to-be-accessed address overlaps with the first access address in the intermediate cache, or indicating that the current to-be-accessed address is added to the intermediate cache as a new first access address because the current to-be-accessed address overlaps with the second access address in the destination cache. bit[15:3] is a reserved bit used for extension when the number of bits of the opcode number is insufficient. bit[105:104] indicates the data of which request input port, and when the current to-be-accessed address in the intermediate cache is taken out and added to the destination cache, the result is returned to the corresponding result output port.

[0105] In particular, the meaning of each bit of the result output port is as follows: bit[2:0] has the same meaning as bit[2:0] in the request input port. bit[3] indicates that the execution operation is completed, and the data in the result output port is valid at this time. bit[15:4] is a reserved bit used for extension when the number of bits of the opcode number is insufficient. bit[31:16] is consistent with bit[31:16] in the request input port. bit[42:32] is the LBA storage position of the corresponding opcode id in the destination cache, which is used for execution of the delete command and is an important return result of the add command. bit

[43] is an overlap flag, which is an important return result of the check command and is set to 1 when there is an overlap with the intermediate cache or the destination cache.

[0106] Correspondingly, by taking the first access address written in the intermediate cache in the order of writing as the target first access address, the historical to-be-accessed data in the intermediate cache can be extracted, but when the target first access address overlaps with the second access address in the destination cache, the address cannot perform an access operation, and therefore the first access address in the intermediate cache is written at the end again, so that other first access addresses have the opportunity to be extracted.

[0107] The address access control system provided by the embodiment of the present application comprises an input module, a control module and an output module. The input module is configured to poll a request input port corresponding to each storage controller core to receive an address access control request sent by each storage controller core. The request input port and the storage controller core are in one-to-one correspondence, and the address access control request comprises at least a to-be-controlled access address, which comprises a current to-be-accessed address. The control module is configured to, when receiving the address access control request sent by any storage controller core, determine whether there is an overlap between the current to-be-accessed address and a target access address in response to the address access control request, to obtain an address access control result of the current to-be-accessed address. The output module is configured to return the address access control result to the corresponding storage controller core through a result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result. The result output port and the storage controller core are in one-to-one correspondence. The method provided by the above scheme can determine whether there is a conflict between the current to-be-accessed address and the target access address that is being read and written by judging whether there is an overlap between the current to-be-accessed address and the target access address contained in the address access control request, obtaining the address access control result of the current to-be-accessed address, returning the address access control result to the storage controller core through the result output port, and then performing a corresponding access operation on the current to-be-accessed address according to the result by the storage controller core. The method realizes address access control of the multi-core storage controller and improves the read and write performance of the storage device. Moreover, the address access control result obtained by judging whether there is an overlap between the current to-be-accessed address and the target access address can be used to judge whether the current to-be-accessed address can be accessed before the storage controller core formally accesses the current to-be-accessed address, thereby avoiding access conflicts of the storage controller core on the same address. The state of the request input port and the result output port of the current access can be judged by the arbitrator to determine whether the input module responds to the address access control request of the storage controller core. If the response is received, the address access control request can be provided with data for the subsequent control module. The state of the request input port and the result output port of the current access can be judged by the arbitrator to determine whether the input module responds to the address access control request of the storage controller core. If the response is not received, the next request input port can be directly polled to realize polling access. The current to-be-accessed address can be distinguished by setting the intermediate buffer and the destination buffer, thereby avoiding conflicts between the storage controller core being polled and the address being used or allowed to be used by the storage controller core.

[0108] The command is used to determine whether the current address to be accessed conflicts with the address being accessed by the polled storage controller core and being used and allowed to be used by the storage controller core, and to determine whether there is an overlap with the first access address. The command is used to determine whether there is an overlap between the current address to be accessed and the first access address. When there is an overlap, it indicates that the address certainly overlaps with the second access address, and the data content of the address space is being accessed by other storage controller cores. The current address to be accessed can be classified into the intermediate buffer, and the storage controller core temporarily does not access the address. Even if the current address to be accessed does not overlap with the first access address in the intermediate buffer, it is determined whether it overlaps with the second access address in the destination buffer. When there is an overlap, it indicates that the data content of the address space is being accessed by other storage controller cores. The current address to be accessed is also classified into the intermediate buffer, and the storage controller core temporarily does not access the address, thereby avoiding access conflicts. When the current address to be accessed does not overlap with the second access address in the destination buffer, it indicates that the polled storage controller core can access the address. When the storage controller core completes the access operation on the address, the address is a to-be-deleted access address. By deleting the to-be-deleted access address in the destination buffer, other addresses can be normally accessed. By writing the first access address in the intermediate buffer in the order of writing, the first access address written in the intermediate buffer earliest is taken as a target first access address, the historical access data in the intermediate buffer can be extracted, and the first access address in the intermediate buffer can be prevented from being accessed for a long time. By writing the first access address in the intermediate buffer in the order of writing, the first access address written in the intermediate buffer earliest is taken as a target first access address, the historical access data in the intermediate buffer can be extracted. However, when the target first access address overlaps with the second access address in the destination buffer, the address cannot perform an access operation. Therefore, the first access address is written at the end of the intermediate buffer again, so that other first access addresses have the opportunity to be extracted.

[0109] Specifically, in an embodiment, the current address to be accessed is set with a priority, and the historical access address in the intermediate buffer also contains the corresponding priority. When the current address to be accessed is compared with the historical access address in the intermediate buffer, the current address to be accessed with a high priority is ranked higher than the current address to be accessed with a low priority, and is extracted into the destination buffer first. Generally, the current address to be accessed required for an urgent task and an important task is set as a high priority.

[0110] Through the above description of the embodiments, those skilled in the art can clearly understand that the system according to the above embodiments can be implemented by means of software on a general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation.

[0111] The embodiment of the application provides an address access control method, which is applied to the host end of the address access control system provided by the above embodiment. The execution subject of the embodiment of the application is an electronic device, such as a server, a desktop computer, a notebook computer, a tablet computer and other electronic devices that can be used for heterogeneous computing.

[0112] As shown in Figure 6 , it is a flowchart of an address access control method provided by the embodiment of the application. The method comprises the following steps:

[0113] Step 601: Polling access to a request input port corresponding to each storage controller core to receive an address access control request sent by each storage controller core; wherein the request input port and the storage controller core are one-to-one corresponding, and the address access control request at least comprises a to-be-controlled access address, and the to-be-controlled access address comprises a current to-be-accessed address;

[0114] Step 602: When receiving the address access control request sent by any storage controller core, in response to the address access control request, it is judged whether there is an overlap between the current to-be-accessed address and a target access address, so as to obtain an address access control result of the current to-be-accessed address;

[0115] Step 603: Return the address access control result to the corresponding storage controller core through a result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result;

[0116] Wherein, the result output port and the storage controller core are one-to-one corresponding.

[0117] The features of the embodiment of the address access control method can be referred to the related description of the embodiment of the address access control system, which will not be repeated here.

[0118] The embodiment of the application further provides an address access control device, which is applied to the address access control method provided by the above embodiment.

[0119] As shown in Figure 7 , it is a structural diagram of an address access control device provided by the embodiment of the application. The address access control device 70 comprises an input module 701, a control module 702 and an output module 703.

[0120] The input module is configured to poll each request input port corresponding to each storage controller core to receive an address access control request sent by each storage controller core; the request input port corresponds to the storage controller core one by one, and the address access control request at least includes a to-be-controlled access address, and the to-be-controlled access address includes a current to-be-accessed address; the control module is configured to, when receiving the address access control request sent by any storage controller core, judge whether there is an overlap between the current to-be-accessed address and a target access address in response to the address access control request, to obtain an address access control result of the current to-be-accessed address; and the output module is configured to return the address access control result to the corresponding storage controller core through a result output port, so that the storage controller core performs a corresponding access operation on the current to-be-accessed address according to the address access control result.

[0121] The features of the embodiments of the address access control device can be understood by referring to the related descriptions of the embodiments of the address access control method, which will not be repeated here.

[0122] The embodiments of the present application also provide an electronic device, as shown in the accompanying drawings, which includes a processor 10 and a memory 20, the memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above address access control method embodiments. Figure 8 The embodiments of the present application also provide an electronic device, as shown in the accompanying drawings, which includes a processor 10 and a memory 20, the memory 20 stores a computer program, and the processor 10 is configured to run the computer program to perform the steps in any of the above address access control method embodiments.

[0123] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program, wherein the computer program is configured to perform the steps in any of the above address access control method embodiments when running.

[0124] In an exemplary embodiment, the above computer readable storage medium can include, but is not limited to, a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk, and various media that can store computer programs.

[0125] The embodiments of the present application also provide a computer program product, which includes a computer program, and the computer program is configured to perform the steps in any of the above address access control method embodiments when running by a processor.

[0126] The embodiments of the present application also provide another computer program product, which includes a non-volatile computer readable storage medium, and the non-volatile computer readable storage medium stores a computer program, and the computer program is configured to perform the steps in any of the above address access control method embodiments when running by a processor.

[0127] Those skilled in the art will further appreciate that the units and algorithms described in connection with the examples disclosed herein can be embodied directly in hardware, in software, or in a combination of the two. For the sake of brevity, descriptions of a method of execution of the examples in software have not been presented in full detail in order to avoid obscuring the concepts of the present application. Those skilled in the art will appreciate that the components and steps of the examples can be implemented in software or hardware, or a combination thereof, and that various modifications are possible without materially departing from the application. Accordingly, the software implementation can include, but is not limited to, a computer program product stored on a computer readable medium, which can be executed by a computer, a microprocessor, a microcomputer, a programmable logic device, a microprocessor, a microcontroller, a digital signal processor, a central processing unit, a state machine, a programmable logic device, a field programmable gate array, a secure microprocessor, a secure microcontroller, a hardware implementation, or any suitable combination thereof.

[0128] The above provides a kind of address access control system, method, electronic equipment and storage medium provided by the present application in detail.The principle and implementation of the present application are described in this paper by applying specific examples, the above example is only applicable to help understand the method of the present application and its core idea.It should be pointed out that, for the ordinary skilled in the art, under the premise of not departing from the principle of the present application, the present application can be improved and modified in several ways, and these improvements and modifications also fall within the scope of the claims of the present application.

Claims

1. An address access control system, characterized in that, include: An input module is used to poll the request input port corresponding to each storage controller core to receive address access control requests sent by each storage controller core; wherein, the request input port corresponds one-to-one with the storage controller core, and the address access control request includes at least the address to be controlled, and the address to be controlled includes the current address to be accessed; The control module is used to, when receiving an address access control request sent by any of the storage controller cores, respond to the address access control request and determine whether there is an overlap between the current address to be accessed and the target access address, so as to obtain the address access control result of the current address to be accessed. The output module is used to return the address access control result to the corresponding storage controller core through the result output port, so that the storage controller core can perform the corresponding access operation on the currently accessed address according to the address access control result; wherein, the result output port corresponds one-to-one with the storage controller core; The control module includes: An intermediate buffer is used to cache a first access address, wherein the first access address includes historical addresses that are not allowed to be accessed; A destination cache is used to cache a second access address; wherein the second access address includes an address where any of the storage controller cores is currently performing an access operation and a historical address that is allowed to be accessed, and the target access address includes the first access address and the second access address; The control unit is configured to, upon receiving an address access control request sent by any of the storage controller cores, respond to the address access control request and determine whether there is an overlap between the current address to be accessed and the target access address, so as to obtain the address access control result of the address to be accessed. The control unit is specifically used for: When an address access control request is received from any of the storage controller cores, the control commands in the address access control request are parsed. When the control command in the address access control request is a check command, the control unit state machine switches from the initial state to the intermediate buffer check state. In the intermediate buffer check state, it is determined whether there is an overlap between the current address to be accessed and the first access address in the intermediate buffer, and the first overlap judgment result is obtained. The control unit state machine switches from the intermediate buffer check state to the destination buffer check state. In the destination buffer check state, it is determined whether there is an overlap between the current address to be accessed and the second access address in the destination buffer, and a second overlap judgment result is obtained. The control unit state machine switches from the destination buffer check state to the result output state. In the result output state, the first overlap judgment result and the second overlap judgment result are written to the result output port corresponding to the storage controller core; The address access control result includes the first overlap judgment result and the second overlap judgment result.

2. The address access control system according to claim 1, characterized in that, The input module includes: The arbitrator is used to poll the request input port corresponding to each storage controller core. When the currently accessed request input port is not empty, it determines whether the result output port corresponding to the currently accessed request input port meets the preset output conditions. If the result output port corresponding to the currently accessed request input port meets the preset output conditions, it receives the address access control request sent by the currently accessed request input port.

3. The address access control system according to claim 2, characterized in that, The arbitrator is also used for: If the currently accessed request input port is empty or the result output port corresponding to the currently accessed request input port does not meet the preset output conditions, the next request input port is accessed in sequence.

4. The address access control system according to claim 1, characterized in that, The control unit is also used for: If the control command in the address access control request is an add command, the control unit state machine switches from the initial state to the intermediate buffer check state. In the intermediate buffer check state, it is determined whether there is an overlap between the current address to be accessed and the first access address in the intermediate buffer, and the first overlap judgment result is obtained; If the first overlap determination result indicates that the current address to be accessed overlaps with any of the first access addresses, the current address to be accessed is written as a new first access address into the intermediate buffer.

5. The address access control system according to claim 4, characterized in that, The control unit is also used for: When the first overlap judgment result indicates that the current address to be accessed does not overlap with any of the first access addresses, the control unit state machine switches from the intermediate buffer check state to the destination buffer check state. In the destination cache check state, it is determined whether there is an overlap between the current address to be accessed and the second access address in the destination cache, and a second overlap determination result is obtained; If the second overlap determination result indicates that the current address to be accessed overlaps with any of the second access addresses, the current address to be accessed is written as a new first access address into the intermediate buffer.

6. The address access control system according to claim 5, characterized in that, The control unit is also used for: If the second overlap judgment result indicates that the current address to be accessed does not overlap with any of the second access addresses, the current address to be accessed is written as a new second access address into the destination buffer, and the control unit state machine switches from the destination buffer check state to the result output state. In the result output state, generate the cache location information of the current address to be accessed in the destination cache; The address access control result of the address to be accessed includes the cache location information of the current address to be accessed in the destination cache.

7. The address access control system according to claim 1, characterized in that, The control unit is also used for: If the control command in the address access control request is a delete command, the access address to be controlled includes the access address to be deleted; Delete the access address to be deleted from the destination cache.

8. The address access control system according to claim 7, characterized in that, The control unit is also used for: After any of the access addresses to be deleted in the destination buffer is deleted, the first access address written to the intermediate buffer is taken as the target first access address according to the writing order of the first access address in the intermediate buffer, and the control unit state machine switches from the initial state to the destination buffer check state. In the destination cache check state, it is determined whether there is an overlap between the target first access address and the second access address in the destination cache, and a second overlap determination result is obtained; If the second overlap judgment result indicates that there is no overlap between the target first access address and each of the second access addresses in the destination buffer, the target first access address is written as a new second access address into the destination buffer, and the control unit state machine switches from the destination buffer check state to the result output state. In the result output state, the cache location information of the target first access address in the destination cache is generated.

9. The address access control system according to claim 8, characterized in that, The control unit is also used for: If the second overlap determination result indicates that there is an overlap between the target first access address and any of the second access addresses in the destination cache, the target first access address is rewritten as the new first access address into the intermediate cache.

10. An address access control method, characterized in that, include: The system polls the request input port corresponding to each storage controller core to receive address access control requests sent by each storage controller core; wherein, each request input port corresponds one-to-one with a storage controller core, and each address access control request includes at least the address to be controlled, including the current address to be accessed; When an address access control request is received from any of the storage controller cores, in response to the address access control request, it is determined whether there is an overlap between the current address to be accessed and the target access address, so as to obtain the address access control result of the current address to be accessed. The address access control result is returned to the corresponding storage controller core through the result output port, so that the storage controller core can perform the corresponding access operation on the current address to be accessed according to the address access control result; The result output ports correspond one-to-one with the core of the storage controller; When an address access control request is received from any of the storage controller cores, in response to the address access control request, it is determined whether there is overlap between the current address to be accessed and the target address, so as to obtain the address access control result of the current address to be accessed, including: When an address access control request is received from any of the storage controller cores, the control commands in the address access control request are parsed. When the control command in the address access control request is a check command, the control unit state machine switches from the initial state to the intermediate buffer check state. In the intermediate buffer check state, it is determined whether there is an overlap between the current address to be accessed and the first access address in the intermediate buffer, and a first overlap judgment result is obtained. The control unit state machine switches from the intermediate buffer check state to the destination buffer check state. The intermediate buffer is used to cache the first access address, wherein the first access address includes historical addresses to be accessed that are not allowed to be accessed. In the destination cache check state, it is determined whether there is an overlap between the current address to be accessed and the second access address in the destination cache, and a second overlap judgment result is obtained. The control unit state machine switches from the destination cache check state to the result output state. The destination cache is used to cache the second access address. The second access address includes the address of any of the storage controller cores that is currently performing an access operation and the historical address to be accessed that is allowed to perform the access operation. The target access address includes the first access address and the second access address. In the result output state, the first overlap judgment result and the second overlap judgment result are written to the result output port corresponding to the storage controller core; The address access control result includes the first overlap judgment result and the second overlap judgment result.

11. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the address access control method as described in claim 10 when executing the computer program.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the address access control method as described in claim 10.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the address access control method as described in claim 10.

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