Storage system and operating procedures thereof

Abstract

Method of operating a storage system (100, 1440) with a non-volatile storage device (60) and a storage controller (29, 200, 1020, 1010, 1110, 1441, 1511) that controls the non-volatile storage device (60), wherein the method comprises: Reading data (711, D1-Dm, DT1, DT2...) from a memory cell arrangement (100) in a unit of a memory page (110b, 400, 440) comprising a plurality of sectors (411-41k, 610-880); Performing error correction decoding on the read data (711, D1-Dm, DT1, DT2...) in one unit of a sector (411-41k, 610-880) of the memory page (110b, 400, 440); Selecting at least one target sector that has at least one uncorrectable error in the read data (711, D1-Dm, DT1, DT2...) thereof, and selecting at least one success sector (411-41k, 610-880) wherein all errors in the read data (711, D1-Dm, DT1, DT2...) of the success sector (411-41k, 610-880) are correctable by error correction decoding; Preventing preloading of bit lines (BL, BL(1)-BL(m), 611-661) connected to the at least one success sector (411-41k, 610-880) while preloading bit lines (BL, BL(1)-BL(m), 611-661) connected to the at least one destination sector; and Performing a re-attempt read operation for data (711, D1-Dm, DT1, DT2...) stored in the at least one target sector.

Description

Background of the invention 1. Technical field

[0001] Exemplary embodiments generally relate to a semiconductor storage device and, in particular, to a storage system comprising a non-volatile storage device and a storage controller, and to a method for operating the same. 2. Description of the state of the art

[0002] A non-volatile memory device, such as a flash memory device, is a type of electrically erasable, programmable solid-state memory (EEPROM) in which multiple memory areas can be erased or programmed by a single programming operation. In a typical EEPROM, one memory area can be erased or programmed at a time. Accordingly, the flash memory device can operate at high speed when systems using the flash memory device are simultaneously reading and writing data to and from different areas. All types of flash memory and EEPROMs degrade after a certain number of erase cycles due to the degradation of the charge storage device used to store data and the degradation of the insulating layer surrounding the charge storage device.

[0003] Flash memory stores information on a silicon chip without requiring any power to retain that information. This means that even if the power supply to the silicon chip is interrupted, the information is preserved without any power consumption. Furthermore, flash memory offers very fast read access times and resistance to physical shock. Because of these characteristics, flash memory has been widely used as a data storage device in battery-powered devices.

[0004] US 2011 / 0066899 A1 concerns a storage system with flash memory and a storage controller, wherein, in the event of an uncorrectable read error, the storage controller performs repeated read attempts on a memory block until correct data is read, and then initiates an erase refresh operation for that memory block.

[0005] US 2010 / 0232221 A1 relates to a method for reading a non-volatile memory in which adjacent aggressor cells are identified by reading neighboring memory cells and separate preloading operations are performed for bit lines of memory cells with adjacent aggressor cells and for those without adjacent aggressor cells. Summary

[0006] The object of the present invention is to provide a method for operating a storage system that is capable of reducing electricity consumption.

[0007] The problem is solved by a method according to claim 1 and by a method according to dependent claim 9; further developments of the methods according to the invention are the subject of the subordinate claims.

[0008] According to some exemplary embodiments, a method for operating a storage system is provided, comprising a non-volatile storage device and a storage controller that controls the non-volatile storage device.The method may include: reading data from a memory cell array in a unit of a memory page comprising a plurality of sectors; performing error-correcting decoding on the data read from a unit of a sector of the memory page; selecting at least one destination sector containing at least one uncorrectable error in the data read from it; selecting at least one success sector, wherein all errors in the data read from the success sector are correctable by error-correcting decoding; preventing the preloading of bit lines connected to the at least one success sector while preloading destination bit lines connected to the at least one destination sector; and performing a retry read operation on data stored in the at least one destination sector.

[0009] In one embodiment, each sector stores one or more parity bits generated based on the data stored in the sectors, wherein a number of errors included in the at least one target sector may be greater than a number of parity bits, and a number of errors included in at least one success sector may be less than or equal to the number of parity bits.

[0010] In one embodiment, the reread attempt operation can be repeated for the data to be read, which is stored in the at least one target sector, until the uncorrectable errors are corrected by error correction decoding.

[0011] In one embodiment, the reread attempt operation for the data in at least one target sector can be repeated a predetermined reference number of repetitions.

[0012] The procedure may further include performing a delete-refresh operation to copy a memory block containing the at least one target sector to another memory block if the re-attempt operation for the data stored in the at least one target sector can be repeated more often than the predetermined reference number of attempts, and to delete the memory block containing the at least one target sector.

[0013] In one embodiment, the at least one target sector can be selected because the memory controller inputs a data pattern into the memory cells included in the target sector that differs from a pattern of data input into the memory cells of the memory side other than the target sector.

[0014] Data values ​​of "0" can be entered into the memory cells that are included in the target sector, and data values ​​of "1" can be entered into the memory cells that are included in other sectors.

[0015] In one embodiment, the sizes of the sectors can each be set according to a defined feature setting command of the memory controller.

[0016] The sector sizes can be determined using at least some of the data transferred to the non-volatile storage device after the feature setting command.

[0017] In one embodiment, the sizes of the sectors can be stored in a fuse unit encompassed in the non-volatile storage device by a wafer-level or packet-level fuse option, and they can be set according to the data stored in the fuse unit during a power-on sequence of the non-volatile storage device.

[0018] In one embodiment, the memory controller can provide a sector selection instruction and a sector address for the non-volatile storage device to select the at least one target sector.

[0019] According to some exemplary embodiments, a storage system comprises a non-volatile storage device and a storage controller designed to control the non-volatile storage device. The storage controller includes an error-correcting code block designed to read data from the non-volatile storage device in a unit of a memory page comprising a plurality of sectors, and designed to perform error-correcting decoding on the read data in a unit of a sector of the memory page.and a control block designed to select at least one destination sector containing at least one uncorrectable error, and to select at least one success sector, wherein all errors of the success sector are correctable by error correction decoding, the control block further being designed to control the non-volatile storage device in such a way as to prevent the preloading of bit lines associated with the at least one destination sector, and the control block further being designed to perform a retry read operation on the data in the at least one destination sector.

[0020] In one embodiment, the error correction block can provide a flag signal to the control block indicating success or failure of the error correction decoding performed for each sector.

[0021] The control block can include a sector table which stores a sector number for the sectors and flag signals for the sectors.

[0022] In one embodiment, the flash memory device may include control logic, wherein the control logic may include a register that stores sector size information contained in a specified feature setting instruction provided by the memory controller, and wherein the control logic sets sizes of the sectors according to the sector size information.

[0023] According to some other exemplary embodiments, a method for operating a storage system is provided, comprising a non-volatile storage device and a storage controller that controls the non-volatile storage device, wherein the non-volatile storage device comprises a plurality of memory cells organized into a plurality of memory pages, each of which comprises a plurality of sectors for storing data therein.The procedure may include: reading data from a selected memory page of the non-volatile storage device; performing error-correcting decoding on the read data on a sector-by-sector basis for each of the sectors of the selected memory page; and if the error-correcting decoding is unable to correct at least one data error in at least one target sector of the selected memory page, but is able to correct all data errors in one or more success sectors of the selected memory page, transmitting a target sector selection instruction from the memory controller to the non-volatile storage device.The target sector selection instruction can cause the non-volatile storage device to: change a voltage applied to the memory cells of the at least one target sector, preload target bit lines connected to the at least one target sector while changing the preload of bit lines connected to the one or more success sectors, and perform a re-attempt read operation on data stored in the at least one target sector with the changed voltage.

[0024] Accordingly, the memory controller can perform a read operation on the memory cell array in a unit of a memory page, perform error detection and correction on the read data in a unit of a sector, prevent the preloading of bit lines connected to at least one success sector containing correctable errors, while preloading the bit lines connected to at least one destination sector containing uncorrectable errors, and perform a re-attempt read operation on data in at least one destination sector, thereby reducing power consumption. Brief description of the characters

[0025] Illustrative, non-limiting exemplary embodiments will become clearer with reference to the following detailed description in conjunction with the accompanying figures. Fig. Figure 1 is a flowchart that represents a method of operating a storage system comprising a non-volatile storage device and a storage controller according to exemplary embodiments. Fig. Figure 2A is a block diagram that illustrates a design of a storage system according to exemplary embodiments. Fig. 2B is a block diagram that shows a detailed design of a memory controller used in Fig. 2B is shown according to exemplary embodiments. Fig. Figures 3 to 8 are diagrams that illustrate examples of specific memory cell arrangements used in the non-volatile storage device. Fig. 2A may be included. Fig. 9 is a diagram that represents a layout of a memory page encompassed in a memory cell arrangement that is in Fig. 2 is shown. Fig. 10 represents a threshold voltage distribution that applies to each memory cell of a memory cell arrangement located in Fig. 2A is shown, and can be formed. Fig. 11 and Fig. 12 represent modified examples of the threshold voltage, which are in Fig. 10 is shown. Fig. 13 provides an example of an interpretation of a sector table, which is in Fig. 2B is shown according to exemplary embodiments. Fig. 14 represents destination bit lines that are connected to a destination sector and are selective in the event that in Fig. 13 are shown, who have been summoned. Fig. 15A is a timing diagram that describes a procedure for determining a target sector in the storage system that is in Fig. 2A is shown according to exemplary embodiments. Fig. 15B and Fig. Section 15C presents example input data patterns for specifying the target sector according to exemplary embodiments. Fig. Figure 16 is a timing diagram that illustrates a procedure for determining a target sector in the storage system that is in Fig. 2A is shown, according to other exemplary embodiments. Fig. Figure 17 is a view that represents a connection between sectors and memory page buffers according to exemplary embodiments. Fig. Figure 18 is a block diagram illustrating a design for a memory page buffer according to exemplary embodiments, which is derived from the memory page buffers described in Fig. The 17 figures shown are included. Fig. Figure 19 is a block diagram representing an interpretation of a control logic according to exemplary embodiments described in Fig. 2A is shown. Fig. Figure 20 is a time sequence diagram that illustrates a method for determining a sector size according to exemplary embodiments. Fig. Figure 21 is a flowchart illustrating a method of operating the storage system according to exemplary embodiments. Fig. Figure 22 is a flowchart illustrating a method of operating the storage system according to exemplary embodiments. Fig. Figure 23 is a block diagram representing a memory card that may include a storage system according to embodiments. Fig. 24 represents a solid state hard drive (SSD) which includes a storage controller and a plurality of non-volatile storage devices. Fig. Figure 25 is a diagram representing a mobile system that may be included in a storage system according to exemplary embodiments. Fig. Figure 26 is a diagram representing a data processing system which may include a storage system according to exemplary embodiments. Detailed description of the embodiments

[0026] Exemplary embodiments are described below with reference to the accompanying figures. The same reference symbols are used throughout the figures to refer to the same elements, and a detailed description of these elements is omitted to avoid redundancy.

[0027] Fig. Figure 1 is a flowchart depicting a procedure for operating a storage system comprising a non-volatile storage device and a storage controller, according to storage implementation forms. Here, the non-volatile storage device is assumed to comprise a memory cell array for storing data. The memory cell array can comprise a plurality of blocks, each storing data. Each block can comprise a plurality of memory pages, each storing data. Each memory page can comprise a plurality of sectors, each storing data.

[0028] With reference to Fig. 1 In a process step (S110) of the process for operating a storage system comprising a non-volatile storage device and a storage controller for controlling the non-volatile storage device, data is read from a memory cell arrangement of the non-volatile storage device in a unit of a memory page comprising a plurality of sectors.

[0029] In operation S120, an error correction code (hereinafter referred to as 'ECC') block of the memory controller performs ECC decoding on the data read from a unit of a sector within a memory page. This ECC decoding determines whether the read data contains a read error. Based on the ECC decoding, the ECC block can then notify a central processing unit (CPU), which includes the memory controller, whether a read error is correctable or uncorrectable within a unit of a sector (e.g., on a sector-by-sector basis).Based on the notification, the memory controller in operation (S130) can select at least one target sector containing at least one uncorrectable read error and capable of performing a retry read operation, and at least one success sector where any errors in the data read from the success sector(s) are correctable. To select the target sector, the memory controller can write the same data to memory cells that are contained within the target sector. This same data can include values ​​of "0". The memory controller can use a target sector selection instruction to select the target sector.

[0030] In one operation (S140), the memory controller can control the non-volatile storage device to prevent the preloading of bit lines connected to the success sector(s), while preloading only destination bit lines connected to the destination sector. It can then perform a retry read operation on the data in the destination sector. The retry read operation can be repeated until all read errors in the destination sector are corrected. Furthermore, the retry read operation can be repeated a predetermined number of times. If the retry read operation is performed more than the predetermined number of times, a clear refresh operation can be performed on a memory block encompassing the destination sector.

[0031] In the prior art storage system, if an uncorrectable read error occurs in a sector encompassed by a memory page, all bit lines connected to that memory page are preloaded, and then the re-read operation is performed for sectors containing the uncorrectable read error, thus increasing power consumption. In the exemplary embodiments, however, only bit lines connected to the target sector of a memory page are preloaded, thereby reducing power consumption.

[0032] Fig. Figure 2A is a block diagram that represents a design of a storage system 100 according to exemplary embodiments.

[0033] With reference to Fig. 2A can comprise a storage system 100, a storage controller 20, and a non-volatile storage device 60.

[0034] The non-volatile storage device 60 can be a flash storage device and it can include a memory cell array 100, a memory page buffer unit 210, a column selector circuit or decoder 320, a row selector circuit or decoder 340, an input / output buffer 330, a voltage generator 345 and control logic 350.

[0035] The control logic 350 can control the operation of the non-volatile storage device 60 for an access operation, for example, a program operation, a delete operation, a read operation under the control of the memory controller 20.

[0036] The memory cell arrangement 100 comprises a plurality of memory cells connected by a plurality of word lines WL and a plurality of bit lines BL. As below with reference to Fig. As described in 3 to 8, each of the memory cells can comprise a NAND or NOR flash memory cell and the memory cells can be arranged in a two-dimensional array structure or a three-dimensional array structure.

[0037] In the exemplary embodiments, each of the memory cells can comprise a single-level memory cell (SLC) for storing one data bit and a multi-level memory cell (MLC) for storing multiple data bits. In the case of the MLC, a program scheme in a write operation state can comprise different program schemes, such as a shadow program scheme, a reprogramming scheme, or an on-chip buffered program scheme.

[0038] The control logic 350 is designed to control the overall operation of a non-volatile storage device 60. The voltage generator 345 generates read voltage signals, i.e., a select read voltage Vrd and a non-select read voltage Vread, in response to a control signal CTR from the control logic 350. It provides these read voltage signals to the row selector circuit 340, enabling the read operation to be performed with respect to the memory cell array 100. Furthermore, the voltage generator 345 modifies the level of the select read voltage Vrd in response to the control read signal CTR from the control logic 350, allowing the re-attempt read operation to be performed for data from the target sector. The row selector circuit 340 is controlled by the control logic 350 and is designed to select and operate rows of the memory cell array in response to a row address XADD and the select read voltage Vrd.

[0039] The memory page buffer unit 310 is controlled by the control logic 350 and functions as either a read amplifier or a write driver, depending on its operating state. For example, during a read operation, the memory page buffer unit 310 acts as a read amplifier to acquire data from memory cells in a selected row. During a programming operation, the memory page buffer unit 310 can act as a write driver to operate memory cells in a selected row, using programming data. Furthermore, under the control of the control logic 350, during a re-read operation, the memory page buffer unit 310 can selectively preload only those bit lines connected to the target sector containing an uncorrectable read error. The memory page buffer unit 310 can comprise buffers, each corresponding to a single bit line or pairs of bit lines.If each of the memory cells stores multibit data, each memory page buffer of the memory page buffer unit 310 can be designed to include at least two signal memories.

[0040] The column selector circuit 320 is controlled by the control logic 350 and sequentially selects columns (or memory page buffers) in a predetermined unit during read / program operations in response to a column address YADD. The input / output (I / O) buffer 300 transfers data from the memory page buffer unit 310 from the column selector circuit 320 to the memory controller 20.

[0041] With reference to Fig. 2A The memory controller 20 can include a control block 30, a data buffer 50 and an ICC block 55.

[0042] Whenever the non-volatile storage device 60 performs a read operation, the ICC block 55 determines whether error correction decoding of the read data in a unit of a sector (i.e., on a sector-by-sector basis) that forms a memory page is successful with respect to data provided by the non-volatile storage device 60, and outputs a flag signal to the control block 30 indicating the result of the error correction decoding for each sector. The control block 30 can provide a CMD instruction to control an operation of the control logic 350 so that the re-attempt read operation for the target sector containing the uncorrectable error can be performed in response to the flag signal.

[0043] The non-volatile storage device 60, for example, transfers initial data in a unit of a memory page (i.e., on a memory page-to-memory page basis), which is output from the memory cell array according to an initial read voltage during the read operation to the data buffer 50 of the memory controller 20. The ECC block 55 performs ECC decoding in a unit of the sector (i.e., on a sector-to-sector basis) with respect to the transferred data in a unit of a memory page and determines whether the ECC decoding is successful for each sector.

[0044] A memory page comprises a plurality of sectors. Each sector stores data that has been processed for error detection and correction. For example, in some embodiments, each sector stores the data along with an error correction code, which includes one or more error correction bits generated based on the data after the error correction code. In one exemplary embodiment, the error correction bit(s) may include one or more parity bits that can form a parity value. ECC block 55 determines whether the ECC decoding is successful for each sector with respect to the parity bits.For example, if the number of error bits in each of the sectors encompassed in a memory page is less than or equal to the number of error bits that can be corrected by ECC Block 55, ECC Block 55 can identify and correct the error bits in one unit of a sector and transfer the error-corrected data to a host. If the read operation for the first data is successful, the first read operation is aborted.

[0045] However, if the number of error bits in at least one sector of the sectors encompassed in one memory page is greater than the number of error bits that can be corrected by the ECC block—that is, if ECC decoding fails for the at least one sector—the ECC block 55 transmits a sector number to the control block 30, which includes a correctable error bit and a flag signal indicating that error correction has failed. The control block 30 then controls the operation of a non-volatile memory device 60 so that, in response to the flag signal, a re-read operation can be performed for a sector containing a correctable error bit.

[0046] Accordingly, the non-volatile storage device 60 performs the re-read operation for data of the sector containing the correctable error bit, while, under the control of the memory controller 20, it varies a read voltage until the ECC decoding for the sector's data is successful. In this case, the re-read operation performed by the non-volatile storage device 60 and the error detection and correction operations performed by the memory controller 20 can be achieved simultaneously. The ECC block 55 performs error detection and correction for both the data output by the re-read operation and the data output by the read operation.

[0047] According to exemplary embodiments, in order to prevent the re-read attempt operation from being performed in an infinite loop, the re-read attempt operation can be limited to being performed only for a predetermined number of repetitions.

[0048] Fig. 2B is a block diagram that shows a detailed design of a memory controller used in Fig. 2A is shown according to an exemplary embodiment.

[0049] With reference Fig. 2B The memory controller 20 can include a control block 30, a data buffer 50, an ECC block 55, and a host buffer 57. The control block 30 can include a direct memory access (DMA) 33 and a sector table 35.

[0050] The ECC block 55 and the DMA 33 can, in any read operation, take on the function of a determination block, which is able to determine whether a read operation for data first output from a memory cell arrangement 100 will succeed or fail.

[0051] For example, ECC block 55 can perform ECC decoding on a unit of a sector (i.e., on a sector-by-sector basis) of the initial output data read from a unit of a memory page, and it can provide the ECC decoding result to CPU 31 as a flag signal. DMA 33 can determine whether error-corrected data has been transferred to the host, while ECC block 55 can control the transfer of the error-corrected data from the data buffer to the host buffer 57.

[0052] For example, the success of the first output data read operation can denote a state in which the first output data is being transferred from memory cell arrangement 100 to the host, or a state in which the transfer of the first output data is complete.

[0053] CPU 31 can update a flag field FLAG in sector table 35 according to the flag signal. Sector table 35 includes as one entry a sector number SECTOR NO, which indicates the number of sectors encompassed by a memory page that is the subject of the read operation, and a flag signal FLAG, which indicates whether the ECC decoding for a sector is successful. The flag signal FLAG can be written as either "Success P" or "Failure F", depending on whether the ECC decoding for a given sector is successful. For example, "Success P" can be at a high level (e.g., logic "1") and "Failure F" can be at a low level (e.g., logic "0"). Even if in Fig. While Figure 2B, for the sake of simplicity, shows that sector table 35 is separate from CPU 31, sector table 35 can be implemented as part of CPU 31. In this case, sector table 33 can be provided as non-volatile memory, such as synchronous random access memory (SRAM).

[0054] The CPU 31 can, using information stored in the sector table 35, generate a CMD instruction with information to perform the re-attempt read operation of the target sector containing an uncorrectable error, and transmit the generated CMD instruction to the control logic 350.

[0055] Accordingly, the control logic 350 can generate a voltage control signal VCON according to the information contained in the received CMD instruction and provides this signal to the voltage generator 345. In response to the voltage control signal VCON, the voltage generator 345 changes the level of the select read voltage Vrd and applies it to the row selector circuit 340, enabling the re-attempt read operation for the target sector. The memory side buffer unit 310 then uses the modified select read voltage Vrd to read data stored in the target sector of the memory cell array 100. The data read by the memory side buffer unit 310 is transferred to the input / output buffer 300 according to the decoding result of the column selector circuit 320 and then through the data buffer 350 to the ECC block 55.Under the control of CPU 31, ECC block 55 can determine whether the ECC decoding for the data that was reread from the target sector is successful.

[0056] Fig. Figures 3 to 8 are diagrams that illustrate examples of specific memory cell arrangements used in the non-volatile storage device. Fig. 2A may be included.

[0057] Fig. Figure 3 is a circuit diagram representing a memory cell arrangement contained in a NOR flash memory device. Fig. Figure 4 is a circuit diagram representing a memory cell arrangement contained in a NAND flash memory device. Fig. Figure 5 is a circuit diagram representing a memory cell arrangement contained in a vertical flash memory device. Fig. Figure 6 is a perspective diagram for describing a vertical flash storage device. Fig. Figure 7 is a cross-sectional view of the vertical flash storage device. Fig. 6, cut along line I-I'. Fig. Figure 8 is a cross-sectional view of the vertical flash storage device. Fig. 6, cut along line II-II'.

[0058] With reference to Fig. 3. A memory cell arrangement 100a can comprise a plurality of memory cells MC1. Memory cells in the same column can be connected in parallel between a common source line CSL and a plurality of bit lines BL(1), ..., BL(m). Memory cells in the same row can be connected to the same word line from a plurality of word lines WL(1), ..., WL(n). For example, memory cells in a first column can be connected in parallel to a first bit line BL(1) and the common source line CSL. Memory cells in a first column can be connected to a first word line WL(1). The memory cells MC1 can be controlled by a voltage applied to the word lines WL(1), ..., WL(n).

[0059] In the NOR flash memory device, which comprises the memory cell arrangement 100a, one read operation and one program operation can be performed per byte or word, and one erase operation can be performed per block 120a. During the program operation, a collector voltage in the range of approximately -0.1 to -0.7 volts can be applied to a collector substrate of the NOR flash memory device.

[0060] With reference to Fig. 4. The memory cell arrangement can comprise 100 string selector transistors (SST), ground selector transistors (GST), and a plurality of memory cells (MC2). The string selector transistors (SST) can be connected to bit lines BL(1), ..., BL(m), and the ground selector transistors (GST) can be connected to a common source line (CSL). The memory cells (MC2) can be connected in series between the string selector transistors (SST) and the ground selector transistors (GST). Memory cells in the same column can be connected to the same word line from the plurality of word lines (WL(1), ..., WL(n)). For example, 16, 32, or 64 word lines can be arranged between a string selector line (SSL) and a ground selector line (GSL).

[0061] The string selector transistors SST can be connected to the string selector line SSL and can be controlled by a voltage applied to the string selector line. The ground selector transistors GST can be connected to the ground selector line GSL and can be controlled by a voltage applied to the ground selector line. The memory cells MC2 can be controlled by a voltage applied to the word lines WL(1), ..., WL(n).

[0062] In the NAND flash memory device, which comprises the memory cell arrangement 100b, one read operation and one program operation can be performed per memory page 110b, and one erase operation can be performed per block 120b. During the programming operation, a collector voltage at a level of approximately 0 volts can be applied to a collector substrate of the NAND flash memory device. According to the embodiments, each memory page buffer 310 can be composed of Fig. 2. A bit line with an odd number and a bit line with an even number are connected. In this case, the odd-numbered bit lines can form odd-numbered memory pages, the even-numbered bit lines can form even-numbered memory pages, and program operations on the odd-numbered memory pages and the odd-numbered memory pages can be performed alternately.

[0063] With reference to Fig. 5. A memory cell array 100c can comprise a plurality of strings 130c, each of which has a vertical structure. Each string can comprise string selector transistors SSTV, ground selector transistors GSTV, and a plurality of memory cells MC3 configured in a first direction D1 and connected in series between the string selector transistors SSTV and the ground selector transistors GSTV. The plurality of strings 130c can be configured in a second direction D2 to define a string column, and a plurality of string columns can be configured in a third direction D3 to define a string array.

[0064] The string selector transistors SSTV can be connected to bit lines BL(1), ..., BL(m), and the ground selector transistors can be connected to a common source line CSL. Furthermore, the string selector transistors SSTV can be connected to string selector lines SSL11, SSL12, ..., SSLi1, SSLi2, and the ground selector transistors GSTV can be connected to ground selector lines GSL11, GSL12, ..., GSLi1, GSLi2. Memory cells of the same layer can be connected to the same word line via word lines WL(1), WL(2), ..., WL(n-1), WL(n). Each string selector line and each ground selector line can extend in the second direction D2, and the string selector lines SSL11, ..., SSLi1 and the ground selector lines GSL11, ..., GSLi1 can be arranged or stacked in the third direction D3. Each word line can extend in the second direction D2 and the third direction D3 and the word lines WL(1), ...WL(n) can be arranged or stacked in the first direction D1. Each bit line can extend in the third direction D3, and the bit lines WL(1), ..., WL(n) can be arranged or stacked in the second direction D2. The memory cells MC3 can be controlled by a voltage applied to the word lines WL(1), ..., WL(n).

[0065] Similar to the NAND flash memory device, in the vertical flash memory device, which includes the memory cell arrangement 101c, one read operation and one program operation can be performed per memory page, and one erase operation can be performed per block.

[0066] Even if not in Fig. As shown in Figure 5, according to some embodiments, two string selector transistors contained in a single string can be connected to a single string selector line, and two ground selector transistors contained in the single string can be connected to a single ground selector line. According to some embodiments, the single string can contain one string selector transistor and one ground selector transistor.

[0067] With reference to Fig. 6, Fig. 7 and Fig. 8. The vertical flash memory device can comprise a ground select line 256, a word line 252, and a string select line 154, which are arranged along a first direction D1 substantially perpendicular to an upper surface of a substrate 101, and a channel 142 extending from the substrate 101 in the first direction D1 along the side walls of the ground select line 256, word line 252, and string select line 254. The vertical flash memory device can further comprise a bit line 290, which is electrically connected to the channel 142, and a common source line 105. The bit line 290 can be electrically connected to the channel 142 via a pad 162 and a bit line contact 280.

[0068] Channel 142 can comprise polysilicon or doped polysilicon. For example, channel 142 can comprise polysilicon doped with p-type impurities, such as polysilicon doped with indium or gallium. Channel 142 can further comprise carbon and / or germanium. A plurality of channels 142 can be formed in a second direction D2 substantially parallel to the upper surface of the substrate 101 to define a channel cleft, and a plurality of channel clefts can be formed in a third direction D3 substantially perpendicular to the second direction D2 to define a channel arrangement.

[0069] The channel 142 can be cup-shaped and / or tall and cylindrical. A filler layer pattern 150 can be formed in a space enclosed by an inner side wall of the cup-shaped channel, for example, 142. Filler layer patterns 150 can, for example, comprise an insulating material (e.g., an oxide).

[0070] A pad 162 can be located on the filler layer pattern 150 and the channel 140, and it can electrically connect the channel 142 to the bit line contact 280. The pad 162 can serve as a source / drain region through which charges can be moved via the channel 142. The pad 162 can comprise doped polysilicon. For example, the contact point 162 can comprise polysilicon doped with impurities, e.g., phosphorus, arsenic, etc. If the pad 162 comprises polysilicon doped with phosphorus, the pad 162 can further comprise carbon.

[0071] Each of the mass selection line 256, word line 252 and string selection line 254 can exist on a single level (e.g. one each, each at a different level) or on more than one level, and a first insulation layer pattern 115 can be interposed between them. Fig. 6. The mass selector line 256 and the string selector line 254 can each be located at two levels (e.g., two different heights), and the word line 252 can be located at four levels between the mass selector line 256 and the string selector line 254. However, the mass selector line 256 and the string selector line 254 can be located at the same level, and the word line 252 can be configured at 2, 8, 16, or any other suitable number of levels. According to the embodiments, each of the mass selector line 256, word line 252, and string selector line 254 can extend in the second direction D2, and a plurality of mass selector lines 256, a plurality of word lines 252, and a plurality of string selector lines 254 can be arranged in the third direction D3. For example, a first insulation layer pattern 115 can include a silicon oxide (e.g. silicon dioxide (SiO2), silicon oxide carbide (SiOC) and / or silicon oxyfluoride (SiOF)).

[0072] A tunnel insulation layer pattern 220, a charge trap layer pattern 230, and a blocking layer pattern 240 can be arranged between each of the ground selector line 256, word line 252, and string selector line 254 and an outer side wall of the channel 142 in a direction substantially perpendicular to the outer side wall of the channel 142. The tunnel insulation layer pattern 220, the charge trap layer pattern 230, and the blocking layer pattern 240 can be arranged between each of the ground selector line 256, word line 252, and string selector line 254 and the first insulation layer pattern 115 and / or on a side wall of the first insulation layer pattern 115. According to certain embodiments of the inventive concept, the tunnel insulation layer pattern 220 can be arranged only on the outer side wall of the channel 142.

[0073] The ground selector line 256, the word line 252, and the string selector line 254 can, for example, comprise a metal and / or metal nitride. For example, the ground selector line 256, the word line 252, and the string selector line 254 can comprise a metal and / or a metal nitride with low electrical resistance (e.g., tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, and / or platinum). According to at least one exemplary embodiment, each of the ground selector line 256, word line 252, and string selector line 254 can be a multilayer structure with a barrier layer, for example, a metal nitride and / or metal layer comprising a metal.

[0074] The tunnel insulation layer pattern 220 can comprise a silicon oxide, and the charge trapping layer pattern 230 can comprise a nitride (e.g., a silicon nitride and / or a metal oxide). The blocking layer pattern 240 can comprise a silicon oxide and / or a metal oxide (e.g., aluminum oxide, hafnium oxide, lanthanum aluminum oxide, lanthanum hafnium oxide, hafnium aluminum oxide, titanium oxide, tantalum oxide, and / or zirconium oxide). The blocking layer pattern 240 can be a multilayer structure consisting of a silicon oxide layer and a metal oxide layer.

[0075] A second insulating layer pattern 260 can be arranged between structures, each of which can include a mass selector line 256, a word line 252, and a string selector line 254 extending in the second direction, as well as a first insulating layer pattern 115 interposed between them. The second insulating layer pattern 260 can comprise an insulating material (e.g., an oxide). An impurity region can be arranged on an upper portion of the substrate 100 beneath the second insulating layer pattern 260, extending in the second direction D2 and serving as a common source line 105. The impurity region of the common source line 105 can comprise n-type impurities, for example, phosphorus and / or arsenic.

[0076] The bit line 190 can be electrically connected to the pad 162 via the bit line contact 280 and it can be electrically connected to the channel 142. The bit line 290 can, for example, comprise a metal, metal nitride, and / or doped polysilicon. The bit line 290 can extend in the third direction. The bit line contact 280 can be enclosed in a third insulating layer 270 and the contact pad 162. The bit line contact 280 can, for example, comprise a metal, a metal nitride, and / or doped polysilicon. Metal lines 291 can be electrically connected to the ground selector line 156, word line 262, and string selector line 254 via contact connectors 281, and thus electrical signals applied to the metal lines 291 can be made available to the ground selector line 256, word line 252, and string selector line 254.

[0077] A third insulation layer 270 can be arranged on the first and second insulation layer patterns 115 and 260, the channel 152, the pad 162, the blocking layer pattern 240, the charge trapping layer pattern 230, and the tunnel insulation layer pattern 220. The third insulation layer 270 can comprise an insulating material, for example, an oxide.

[0078] Fig. Figure 9 is a diagram representing a configuration of a memory page 400, which is contained in a memory cell arrangement that is in Fig. 2A is shown.

[0079] With reference to Fig. Memory page 440, among a plurality of memory pages encompassed in memory cell arrangement 100, comprises a plurality of sectors 411 to 41k. Each of the sectors 411 to 41k stores data and is a basic unit for data input / output in the non-volatile storage device 60. ECC parity values ​​421 to 42k, each comprising one or more parity bits and serving as an error detection and correction code, are generated based on the data, i.e., sector data, stored in each of the sectors 411 to 41k. The ECC parity values ​​421 to 42k are generated for each set of data to be stored in the sectors 411 to 41k. In this case, the respective sizes of the sectors 411 to 41k suitable for error correction can vary according to the ECC block 55.

[0080] Fig. 10 represents a threshold voltage distribution that applies to each memory cell of a memory cell arrangement located in Fig. 2A is shown, and can be formed.

[0081] Fig. 11 and Fig. 12 represent modified examples of the threshold voltage, which are in Fig. 10 is shown.

[0082] With reference to Fig. 10 Each of the memory cells can be programmed into one of four data states E0, P, P2 and P3 if the memory cell arrangement 100 of the non-volatile storage device 60, which is in Fig. Figure 2 is implemented by an MLC where data of 2 bits per cell is programmed. The data states E0, P, P2, and P3 can each be detected by applying a plurality of selection read voltages Vrd1, Vrd2, and Vrd3. However, the threshold voltage distribution shown in Fig. The figures shown in 10 may vary unintentionally due to various factors.

[0083] For example, the charge retention property of a flash memory cell can be degraded by thermoionic emission due to a defect in an inter-poly insulation layer, charge diffusion, ion defects, programming errors, and hot-temperature stress (HTS). Additionally, the threshold voltage distribution of a flash memory cell can be altered by factors such as soft programming and over-programming. As a result, the threshold voltage distribution of the flash memory cell can change from the states "Eo, P1, P2, P3", as shown in Fig. 11 and Fig. Figure 12 shows that changes in the threshold voltage distribution of the flash memory cell can reduce the read distance and cause a read error.

[0084] To compensate for the read error, the memory controller 20 can perform an ECC error correction operation in response to the read sector data and the ECC parity bit(s) from the non-volatile storage device 60 to correct any errors in the read sector data. Furthermore, if the number of errors occurring during the read operation exceeds a range that can be corrected in the ECC error correction operation, the memory controller 20 can control the non-volatile storage device to perform a re-attempt read operation.

[0085] With reference to Fig. 11. During the re-read attempt operation, the read operation can be repeated while increasing the voltage from a predetermined initial voltage VRS by a predetermined voltage increment ΔV, and repeated until correct data is read. In another exemplary embodiment, a read operation can be repeated during the re-read attempt operation while decreasing the voltage from a predetermined initial voltage VRS by the predetermined voltage increment ΔV until accurate data is read, as in Fig. Figure 12 illustrates this. In exemplary embodiments, a series of operations to acquire accurate read data can be defined, for the sake of simplicity, as a retry read operation. For example, a plurality of read operations can be performed during a retry read operation by applying a plurality of variable selection read voltages until correct data is read. The data, which has been read by the retry read operation to have a correct value, can be made available to the host by the memory controller 20.

[0086] Fig. 13 presents an example of an interpretation of a sector table 500, which may be an exemplary embodiment of the sector table 35, which is in Fig. 2 is shown.

[0087] With reference to Fig. Section 13 of sector table 500 includes, as one entry, a sector number SECTOR NO 510, which refers to sectors 411 to 41k, and a flag signal FLAG 520, which indicates whether the ECC decoding for the data of the respective sectors 411 to 41k is successful. As an example, with reference to Fig. 13 described a case in which a memory page from Fig. The system is designed with 8k data cells and 8 sectors, sector 1 to sector 8. Accordingly, the 8 sectors, sector 1 to sector 8, can each be represented as "000, 001, 010, 011, 100, 101, 110, 111". Furthermore, it Fig. 13 represents a case where the flag signal FLAG 520 of the third sector (Sector 3) is at a low level of "0" because the sector data of the third sector (Sector 3) contains an uncorrectable error as a result of the ECC decoding for each sector. Accordingly, the third sector (Sector 3) is selected as the target sector, and the remaining sectors are selected as success sectors.

[0088] Fig. 14 represents destination bit lines connected to a destination sector and selectively preloaded for the case that occurs in Fig. 13 is shown.

[0089] With reference to Fig. 13 and Fig. 14. The exemplary embodiments can, if the data of the third sector (Sector 3) contains an uncorrectable error as an ECC decoding result, prevent the preloading of the bit lines connected to the success sector, while preloading only the bit lines connected to the third sector (Sector 3), and they can perform a re-read attempt operation for the data of the third sector (Sector 3). That is, if the ECC decoding result for sectors 610 to 680 indicates that the data of the third sector (Sector 630) contains an uncorrectable error, as in Fig. As shown in Figure 13, a selection read voltage Vrd is applied to a selected word line WLg after selectively preloading only the bit lines connected to the third sector 630. Then, a non-selection read voltage Vread is applied to the non-selected word line WLg + 1. Accordingly, memory cells can be turned on or off according to the data programmed into them, based on the memory cells connected to the selected word line WLg and located in the third sector 630. Current is also applied to a common source line CSL.

[0090] Fig. 15A is a timing diagram that describes a procedure for determining a target sector in the storage system that is in Fig. 2A is shown according to exemplary embodiments.

[0091] With reference to Fig. 2A and Fig. 15A, after a serial data input instruction 80h is entered into the non-volatile storage device 60, an address C1C2R1R2R3 for a memory page containing the target sector and data (D1 to Dm) 711 for setting the target sector are transferred from the memory controller 20 to the non-volatile storage device 60 at the preselected timing. The data 711 for setting the target sector is loaded into the memory page buffer 310 through the input / output buffer 330 and the column selector circuit 320. The data 711 for setting the target sector includes a data pattern of the target sector and a data pattern of a non-target sector, and the data pattern of the target sector differs from the data pattern of the non-target sector. That is, the data pattern of the third sector 630, which is in Fig. The data pattern of sector 14, which serves as the target sector, differs from that of the other sectors 610, 620, 640 to 680. When the data 711 is loaded into memory page buffer unit 320 to specify the target sector, memory page buffer unit 120 only preloads the target bit lines that are connected to the target sector (712).

[0092] Next, when a read operation begins, a '00h' instruction, an address C1C2R1R2R3 for a memory page encompassing the target sector, and a '30h' instruction are sequentially transmitted to the non-volatile memory device 60 at a preselected time interval. When the '30h' instruction is entered into the non-volatile memory device 60, the memory page buffer 310 captures the sector data of the target sector of the memory cell array 100 and temporarily stores it under the control of the control logic 350 (713). Once the capture and temporary storage of the target sector data is complete, data such as DT1, DT2, ..., stored in the memory page buffer unit 310, are made available to the data buffer 50 by the memory controller 50 through the column selector circuit 320 and the input / output buffer 330 (714).Data buffer 50 transfers the reread data to ECC block 55, and ECC block 55 can perform ECC decoding on the reread sector data of the target sector and make the decoded sector data available to control block 30. The above reread operations can be repeated until all errors in the sector data of the target sector are corrected.

[0093] Fig. 15B and Fig. Section 15C presents example input data patterns for specifying the target sector according to exemplary embodiments.

[0094] With reference to Fig. 15B means that all data patterns entered into the third sector 630, which serves as the target sector, are “0” and all data patterns entered into other sectors 610, 620, 640 to 680 are “1”.

[0095] With reference to Fig. 15C means that all data patterns entered into the third sector 630, which serves as the target sector, are “1” and all data patterns entered into other sectors 610, 620, 640 to 680 are “0”.

[0096] Fig. Figure 16 is a timing diagram that illustrates a procedure for determining a target sector in the storage system that is in Fig. 2A is shown, according to other exemplary embodiments.

[0097] With reference to Fig. 2A and Fig. 16. After a target sector selection instruction XXh is entered into the non-volatile memory device 60, a sector address (S1S2S3) 712 for selecting the target sector is provided by the memory controller 20 to the non-volatile memory device 60 at the preselected time. When the sector address (S1S2S3) 712 for selecting the target sector is entered into the non-volatile memory device 60, the memory page buffer unit 320 preloads only the target bit lines associated with the target sector (722) based on the sector address (S1S2S3) 712.

[0098] Next, when a read operation begins, a '00h' instruction, an address C1C2R1R2R3 for a memory page encompassing the target sector, and a '30h' instruction are sequentially transmitted to the non-volatile memory device 60 in the preselected timing sequence. When the '30h' instruction is entered into the non-volatile memory device 60, the memory page buffer unit 310 acquires and temporarily stores the sector data of the target sector of the memory cell array 100 under the control of the control logic 350 (723). When the acquisition and temporary storage of the target sector data is complete, data DT1, DT2, ...Data buffer 50 transfers the reread data to ECC block 55, and ECC block 55 can perform ECC decoding of the sector data of the reread target sector and make the decoded sector data available to control block 30. The above reread operations can be repeated until all errors in the target sector's sector data are corrected.

[0099] Fig. 17 represents a connection between sectors and memory side buffers according to exemplary embodiments.

[0100] With reference to Fig. 17, a plurality of sectors 610 to 680 can each be connected by bit lines 611 to 661 to corresponding memory page buffers 710 to 780. If the sector data of the third sector 630 contains an uncorrectable error, as with reference to Fig. As described in Section 15B, a data pattern "0" is written into memory page buffer 730, and a data pattern "1" is written into the other memory page buffers 710, 720, and 740 through 780. Accordingly, only memory page buffer 730 can perform the re-attempt operation by preloading the bit lines 631. Furthermore, if the sector data of the third sector 630 contains an uncorrectable error, as described in Section 15B, a data pattern "0" is written into memory page buffer 730. Fig. As described in section 16, a sector address S1S2S3 of “011” is entered into the selected third sector 630 and the memory page buffers 730 can perform the re-attempt read operation by preloading the bit lines 631 connected to the third sector 630.

[0101] Fig. 18 is a block diagram that represents a layout of a memory page buffer of the memory page buffers according to exemplary embodiments shown in Fig. The 17 figures shown are included.

[0102] With reference to Fig. A memory side buffer 371 can comprise a p-type metal-oxide-semiconductor (PMOS) transistor 732 and a buffer unit 733. The PMOS transistor 732 pre-charges a corresponding bit line BLj in response to a pre-charge control signal with a current source voltage VDD level. The buffer unit 733 can comprise a plurality of buffers SLT, DLT1, and DLT2. The sampling buffer SLT detects and stores a voltage change of a sampling node Sn connected to the bit line BLJ during a capture operation. The data buffers DLT1 and DLT2 are used for a programming operation. The data buffer DLT1 is used to transfer programming data to the bit line BLJ, and the data buffer DLT2 stores the programming data received by the memory controller 20.The memory side buffer 731 may further include a combinational circuit for determining the activation of the precharge control signal PRCH according to data patterns stored in the data buffers DLT1 and DLT2.

[0103] As with reference to Fig. As shown in Figure 15B, when a specific data pattern is entered into the data buffers DLT1 and DLT2, the preload control signal PRCH is activated at a low level, allowing the bit line BLJ to be preloaded. Furthermore, as referenced in Fig. Figure 16 shows a sector selection command XXh and the sector address S1S2S3 being entered, the preload control signal PRCH is activated with a low level so that the bit line BLJ can be preloaded.

[0104] Fig. 19 is a block diagram that illustrates an interpretation of a control logic that is in Fig. 2A is shown according to exemplary embodiments.

[0105] With reference to Fig. 19 The control logic 350 can include a register 351 and / or a backup unit 353.

[0106] Register 351 can store sector size information 352, which, together with a defined feature setting command EFH, is sent from the memory controller 20. Fig. 1 are received, and according to the stored information, the sizes of sectors encompassed by a memory page are determined. The sizes of the sectors contained in a memory page 400 from Fig. The sizes of the sectors included in a memory page can be determined based on the sector data and parity bits stored in the respective sectors. The Memory Controller 200 can set the sizes of the sectors included in a memory page using the specified feature setting command Efh.

[0107] Furthermore, a fuse unit 353 can store sector size information 354. If the fuse unit 353 stores sector size information 354, the fuse unit 353 can store the sizes of the sectors that are in a memory page 400 from Fig. 9 are defined based on the sector size information 354 during a power-on sequence of the non-volatile storage device 60. In this case, the sector size information 354 can be defined by a fuse option at the wafer level or the package level. In another exemplary embodiment, the sector size information SCT_L can be non-volatile trim information and can be stored in the memory cell array 100. If the sector size information SCT_L is stored as non-volatile trim information in the memory cell array 100, the sector size information SCT_L can be loaded into the control logic 350 by the memory side buffer unit 310 from the memory cell array 100 during the power-on sequence under the control of the control logic 350.

[0108] Fig. Figure 20 is a time sequence diagram to illustrate a method for determining a sector size according to exemplary embodiments.

[0109] With reference to Fig. 2A, Fig. 19 and Fig. The specified feature command EFH, the address Addr, and the data D1 to Dm for setting the sector size are transferred from the memory controller 20 to the non-volatile storage device 60 in the preselected time sequence. The address Addr can be used to specify a location of register 351, in which data D1 to Dm are stored, specifying the sector size information 352. The process of setting the sector size can be achieved by transferring the sector size SCT_L from the memory controller 200 to the non-volatile storage device 60 together with the specified feature setting command EFH after power-up. In the exemplary embodiments, only a portion of the data D1 to Dm, which is provided together with the specified feature setting command EFH, can be used as data specifying the sector size SCT_L. The remaining data can be used to determine other parameters.

[0110] Fig. Figure 21 is a flowchart illustrating a method of operating the storage system according to exemplary embodiments.

[0111] With reference to Fig. 2A, Fig. 2B and Fig. 21 In the method of operating a storage system according to the exemplary embodiments, the non-volatile storage device 60 receives a read command from the storage controller 20 (S810). The non-volatile storage device 60, having received the read command, performs a read operation on the data in a unit of a memory page (i.e., on a memory page-to-memory page basis) (820) and transfers the read data to the storage controller 20. The memory page here comprises a plurality of sectors. In this case, as with reference to Fig. As shown in Figure 9, parity values ​​comprising one or more parity bits are transferred by the storage device 60, along with the sector data for each sector of the memory page, to the memory controller 20. Using the sector parity value, the memory controller 20's ECC block 50 performs ECC decoding on the memory page data read in units of the sectors (i.e., on a sector-by-sector basis) to determine if any read errors are detected from any of the sectors (S830). If no read error is detected in step S830, the read data is transferred to the host through the host buffer 57. If a read error is detected in step S830 (YES), the memory controller 20's ECC block 55 determines for each sector whether any errors detected for that sector are uncorrectable (S840).If, in step S840, all errors in the sector of the memory page are determined to be correctable (NO), the EEC block 55 of the memory controller 20 corrects the errors in each sector (S850) and transfers the error-corrected data to the host through the host buffer 57. If, in step S840, the data being read is determined to include at least one sector with at least one uncorrectable error, the memory controller 200 controls the non-volatile storage device to perform the retry read operation for the sector(s) with the uncorrectable error (S860).

[0112] Fig. Figure 22 is a flowchart illustrating a method of operating the storage system according to exemplary embodiments.

[0113] With reference to Fig. 2A, Fig. 2B and Fig. In the method of operating a storage system according to exemplary embodiments, the non-volatile storage device 16 receives a read command from the storage controller 20 (S910). The non-volatile storage device 60, which has received the read command, performs a read operation on data in a unit of a memory page (S920) and transfers the read data to the memory controller 20. The memory page here comprises a plurality of sectors. In this case, as with reference to Fig. Figure 9 shows parity values ​​comprising one or more parity bits, which are transferred along with sector data through the storage device 60 to the storage controller 20. The ECC block 55 of the storage controller 20 performs ECC decoding on the data read from the memory page in units of sectors (i.e., on a sector-by-sector basis) to determine if any read errors are detected from any of the sectors (S930). If a read error is not detected in step S930, the read data is transferred to the host through the host buffer 57. If a read error is detected in step S930 (YES), it is determined for each sector whether the detected errors are uncorrectable (S940). If step S940 determines that the errors in all sectors are correctable, the ECC block of the storage controller 20 corrects the errors in the sectors (S950) and transfers the error-corrected data to the host through the host buffer 57.If, in step S940, it is determined that the read data includes at least one sector (target sector) with at least one uncorrectable error (YES), it is determined whether a reread operation for the target sector will be performed more often than the predetermined reference number of repetitions P (S960). If, in step S960, it is determined that the reread operation for the target sector will be performed less frequently than the preselected reference number of repetitions P, a reread operation will be performed (S970). If, in step S960, it is determined that the reread operation for the target sector will be performed more frequently than the preselected reference number of repetitions P, the reread operation for the target sector will be performed (S980).After performing the re-attempt read operation for the target sector, the ECC block 55 of the memory controller 20 performs an erase-refresh operation, which copies a memory block containing the target sector to another block and erases the memory block containing the target sector (S990).

[0114] Fig. Figure 23 is a block diagram representing a memory card that may include a storage system according to exemplary embodiments.

[0115] With reference to Fig. 23. A memory card 1000 can comprise a plurality of connecting pins 1010, a memory controller 1020, and a non-volatile storage device 1030.

[0116] The 1010 connection pins can be coupled to a host (not shown) to transmit signals between the host and the 1000 memory card. The 1010 connection pins can include a clock pin, a command pin, a data pin, and / or a reset pin.

[0117] The memory controller 1020 can receive data from the host (e.g. via connection pins 1010) and it can store the received data in the non-volatile storage device 1030.

[0118] The non-volatile storage device 1030 can comprise memory cells, and the memory controller 1020 can perform a read operation on the memory cell arrangement in a unit of a memory page, perform error detection and correction on the read data in a unit of a sector, prevent bit lines associated with at least one success sector containing correctable errors from being preloaded while destination bit lines associated with at least one destination sector containing uncorrectable errors are preloaded, and it can perform a re-read attempt operation on data in at least one destination sector, thereby consuming less power than if all sectors of the memory page to be read were preloaded for the re-read attempt operation.

[0119] The memory card 1000 can include, for example, an MMC, an embedded MMC (eMMC), a hybrid embedded MMC (hybrid eMMC), a secure digital (SD) card, a micro SD card, a memory stick, an ID card, a personal computer memory card international association (PCMCIA) card, a chip card, a USB card, a smart card, a compact flash (CF) card, etc.

[0120] The 1000 memory card can be paired with the host, such as a desktop computer, a laptop computer, a tablet computer, a mobile phone, a smartphone, a music player, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital television, a digital camera, a portable game console, etc.

[0121] Fig. Figure 24 is a diagram representing a solid-state drive that may include a storage system according to exemplary embodiments.

[0122] With reference to Fig. 24. A solid-state drive (SSD) can comprise a storage controller 1110 and a plurality of non-volatile storage devices 1120.

[0123] The 1110 storage controller can receive data from a host (not shown). The 1010 storage controller can store the received data in a majority of 1120 non-volatile storage devices.

[0124] Each of the non-volatile storage devices 1120 can comprise memory cells, and the memory controller 1110 can perform a read operation on the memory cell arrangement in a unit of a memory page, perform error detection and correction on the read data in a unit of a sector, prevent the preloading of bit lines connected to at least one success sector containing correctable errors while preloading bit lines connected to at least one destination sector containing uncorrectable errors, and it can perform a retry read operation on data in at least one destination sector, thereby reducing power consumption.

[0125] In some embodiments, the 1100 solid-state drive can be coupled to a host, such as a mobile device, mobile phone, smartphone, PDA, PMP, digital camera, portable game console, music player, desktop computer, notebook computer, tablet computer, speaker, video, digital television, etc.

[0126] Fig. Figure 25 is a diagram representing a mobile system that may include a storage system according to exemplary embodiments. With reference to Fig. A mobile system 1400 can comprise an application processor 1410, a connectivity unit 1420, a volatile storage device 1430, a non-volatile storage system 1440, a user interface 1450, and a power supply 1460. The mobile system 1400 can be any mobile system, such as a mobile phone, a smartphone, a tablet computer, a laptop computer, a PDA, a PMP, a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation system, etc.

[0127] The 1410 application processor can run applications such as a web browser, a game application, a video player application, etc. The 1410 application processor can consist of a single processor core or multiple processor cores. For example, the 1410 application processor can be a multi-core processor, such as a dual-core processor, a quad-core processor, a hexa-core processor, etc. The 1410 application processor can also include cache memory located either inside or outside the 1410 application processor.

[0128] The 1420 connectivity unit can perform wired or wireless communication with an external device. For example, the 1420 connectivity unit can perform USB communication, Ethernet communication, near field communication (NFC), radio frequency identification (RFID) communication, mobile telecommunications, memory card communication, wireless internet, wireless fidelity (Wi-Fi), global positioning system (GPS), Bluetooth (BT), global system for mobile communication (GSM), general packet radio system (GPRS), wideband code division multiple access (WCDMA), high-speed uplink / downlink packet access (HSxPA), etc. The 1420 connectivity unit can include a baseband chipset.

[0129] The volatile memory device 1430 can store an instruction / data to be processed by the application processor 1410, or it can serve as working memory. For example, the volatile memory device 1430 can be implemented as DRAM, SRAM, mobile DRAM, or the like.

[0130] The non-volatile memory system 1440 can comprise a memory controller 1441 and a non-volatile memory device 1443. The non-volatile memory system 1440 can store a boot image for booting the mobile system 1400. For example, the non-volatile memory system 1440 can be implemented by an electrically erasable programmable random-access memory (EEPROM), flash memory, PRAM, RRAM, MRAM, FRAM, nano floating-gate memory (NFGM), polymer random-access memory (PoRAM), or the like.The non-volatile memory system 1440 can comprise memory cells and can perform a read operation on the memory cell array in a unit of a memory page, perform error detection and correction on the read data in a unit of a sector, prevent the preloading of bit lines connected to at least one success sector containing correctable errors, while preloading bit lines connected to at least one destination sector containing uncorrectable errors, and perform a retry read operation on data in at least one destination sector, thereby consuming less power than if all sectors of the memory page to be read were preloaded for the retry read operation.

[0131] The user interface 1450 can include at least one input device, such as a keypad, touchscreen, microphone, etc., and at least one output device, such as a display, speaker, etc. The power supply 1460 can power the mobile system 1400. The mobile system 1400 can further include a camera image processor (CIS), a storage device, such as a memory card, SSD, CD-ROM, etc.

[0132] The mobile system 1400 and / or components of the mobile system 1400 can be packaged in various forms, such as package on package (Pop), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), which are in waffle pack, which are in wafer form, chip on board (COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), thin quad flat pack (TQFP), small outline IC (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), or wafer-level processed stack package (WSP).

[0133] Fig. Figure 26 is a diagram representing a data processing system that may include a storage system according to exemplary embodiments.

[0134] With reference to Fig. 26. A data processing system 1500 can comprise a processor 1510, an I / O hub 1520, an I / O controller node 1530, at least one memory module 1540, and a graphics card 1550. According to the embodiments, a data processing system 1500 can be any data processing system, such as a personal computer (PC), a server computer, a workstation computer, a tablet computer, a laptop computer, a mobile phone, a smartphone, a PDA, a PMP, a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation system, etc.

[0135] The 1510 processor can perform certain calculations or tasks. For example, the 1510 processor can be a microprocessor, a central processing unit (CPU), a digital signal processor, or something similar. The 1510 processor can have a single processor core or multiple processor cores. The 1510 processor can be a multi-core processor, such as a dual-core processor, a quad-core processor, a six-core processor, etc. Even if the example in Fig. While the embodiment shown in Figure 22 comprises only one processor 1510, other embodiments may include multiple processors. In certain embodiments, the processor 1510 may have an associated cache memory located either inside or outside the processor 1510.

[0136] The 1510 processor can include a memory controller (not shown) that controls the operation of a 1540 memory module. The memory controller included by the 1510 processor can be referred to as an integrated memory controller (IMC). A memory interface between the memory controller and the 1500 memory module can be implemented by a single channel comprising multiple signal lines or by multiple channels. Each channel can be coupled to at least one 1540 memory module. The memory controller can be included by the 1520 I / O hub. The 1520 I / O hub comprising the memory controller can be referred to as a memory controller node (MCH).

[0137] The 1540 memory module can include multiple non-volatile memory devices that store the data provided by the 1511 memory controller. The non-volatile memory devices can include memory cells, and they can perform a read operation on the memory cell array in a unit of a memory page, perform error detection and correction on the read data in a unit of a sector, prevent the preloading of bit lines connected to at least one success sector containing correctable errors while preloading bit lines connected to at least one destination sector containing uncorrectable errors, and perform a retry read operation on the data in at least one destination sector, thereby consuming less power than if all sectors of the memory page being read were preloaded for the retry read operation.

[0138] The I / O Hub 1520 can manage data transfer between the 1510 processor and devices such as the 1550 graphics card. The I / O Hub 1520 can be connected to the 1510 processor via at least one of several interfaces, such as a front-side bus (FSB), a system bus, HyperTransport, Lightning Data Transport (LDT), QuickPath Interconnect (QPI), a common system interface (CSI), etc. Even if Fig. 26 An example of a data processing system 1500 that includes an I / O hub 1520, according to embodiments data processing systems 1500 may include a plurality of I / O hubs.

[0139] The I / O Hub 1520 can provide various interfaces with devices. For example, the I / O Hub 1520 can provide an accelerated graphics port (AGP) interface, a peripheral component interface express (PCIe), a communications streaming architecture (CSA) interface, etc.

[0140] The 1550 graphics card can be coupled to the 1520 I / O hub via AGP or PCIe. The 1550 graphics card can control a display device (not shown) to render an image. The 1550 graphics card can include an internal processor and internal memory to process the image. In certain embodiments, the 1520 input / output node can include an internal graphics device along with, or instead of, the 1550 graphics card. The internal graphics device can be referred to as integrated graphics, and an I / O hub that includes the memory controller and the internal graphics device can be referred to as a graphics and memory controller node (GMCH).

[0141] The I / O Controller Hub 1530 can perform data buffering and interface switching to efficiently operate various system interfaces. The I / O Controller Hub 1530 can be coupled to the I / O Hub 1520 via an internal bus. For example, the I / O Controller Hub 1530 can be coupled to the I / O Hub 520 via at least one of several interfaces, such as a direct media interface (DMI), a node interface, an enterprise southbridge interface (ESI), PCIe, etc.

[0142] The I / O Controller Hub 1530 can provide various interfaces for different devices. For example, the I / O Controller Hub 1530 can provide a universal serial bus (USB) port, a serial advanced technology attachment (SATA) port, a general purpose input / output (GPIO), a low pin count (LPC) bus, a peripheral serial interface (SPI), a PCI, a PCIe, etc.

[0143] In certain embodiments, the processor 1510, the I / O hub 1520, and the I / O controller hub 1530 can be implemented as separate chipsets or separate integrated circuits. In other embodiments, at least two of the processor 1510, I / O hub 1520, and I / O controller hub 1530 can be implemented as a single chipset.

[0144] The exemplary embodiments relate to a non-volatile storage device and various devices and systems that use it. Therefore, the exemplary embodiments can be used in any device or system that includes a non-volatile storage device, such as a mobile phone, a smartphone, a PDA, a PMP, a digital camera, a digital television, a set-top box, a music player, a portable game console, a navigation device, a PC, a server computer, a desktop computer, a tablet computer, a laptop computer, a smart card, a printer, etc.

Claims

[1] Method of operating a storage system (100, 1440) with a non-volatile storage device (60) and a storage controller (29, 200, 1020, 1010, 1110, 1441, 1511) controlling the non-volatile storage device (60), the method comprising: Reading data (711, D1-Dm, DT1, DT2...) from a memory cell arrangement (100) in a unit of a memory page (110b, 400, 440) comprising a plurality of sectors (411-41k, 610-880); Performing error correction decoding on the read data (711, D1-Dm, DT1, DT2...) in one unit of a sector (411-41k, 610-880) of the memory page (110b, 400, 440); Selecting at least one target sector that has at least one uncorrectable error in the read data (711, D1-Dm, DT1, DT2...) thereof, and selecting at least one success sector (411-41k, 610-880) wherein all errors in the read data (711, D1-Dm, DT1, DT2...) of the success sector (411-41k, 610-880) are correctable by error correction decoding; Preventing preloading of bit lines (BL, BL(1)-BL(m), 611-661) connected to the at least one success sector (411-41k, 610-880) while preloading bit lines (BL, BL(1)-BL(m), 611-661) connected to the at least one destination sector; and Performing a re-attempt read operation for data (711, D1-Dm, DT1, DT2...) stored in the at least one target sector. [2] Method according to claim 1, wherein each sector (411-41k, 610-880) stores one or more parity bits generated based on the data (711, D1-Dm, DT1, DT2...) stored in the sector (411-41k, 610-880), wherein a number of errors in the read data (711, D1-Dm, DT1, DT2...) of the at least one target sector is greater than a number of parity bits, and wherein a number of errors in the read data (711, D1-Dm, DT1, DT2...) of the at least one success sector (411-41k, 610-880) is less than or equal to the number of parity bits. [3] Method according to claim 1, wherein the reread attempt operation is repeated for the data to be read (711, D1-Dm, DT1, DT2...) which are stored in at least one target sector until the uncorrectable errors are corrected by the error correction decoding. [4] Method according to claim 1, wherein the re-read operation for the data (711, D1-Dm, DT1, DT2...) of the at least one target sector is repeated a predetermined reference number of repetitions, the method further comprising: performing a delete-refresh operation to copy a memory block comprising the at least one target sector to another memory block when the re-read operation for the data (711, D1-Dm, DT1, DT2...) stored in the at least one target sector is repeated more often than a predetermined reference number of repetitions, and to delete the memory block comprising the at least one target sector. [5] Method according to claim 1, wherein the at least one target sector is selected when the memory controller (29, 200, 1020, 1010, 1110, 1441, 1511) inputs a pattern of data (711, D1-Dm, DT1, DT2...) into memory cells (MC1, MC2, MC3) included in the target sector, which differs from a pattern of data (711, D1-Dm, DT1, DT2...) that is inputted into memory cells (MC1, MC2, MC3) of other sectors (411-41k, 610-880) of the memory side (110b, 400, 440) other than the target sector, and wherein data values ​​of “0” are inputted into the memory cells (MC1, MC2, MC3) included in the target sector and data values ​​of “1” are inputted into the memory cells (MC1, MC2, MC3) are entered, which are contained in the other sectors (411-41k, 610-880). [6] Method according to claim 1, wherein the sizes of the sectors (411-41k, 610-880) are set according to a feature setting command by the memory controller (29, 200, 1020, 1010, 1110, 1441, 1511) and the sizes of the sectors (411-41k, 610-880) are set using at least some of the data (711, D1-Dm, DT1, DT2...) that are transferred to the non-volatile storage device after the feature setting command. [7] Method according to claim 1, wherein the sizes of the sectors (411-41k, 610-880) are stored in a fuse unit (353) which is contained in the non-volatile storage device (60) by a fuse option at a wafer level or a package level, and data (711, D1-Dm, DT1, DT2...) are set accordingly, which are stored in the fuse unit (353) during a power-on sequence of the non-volatile storage device (60). [8] Method according to claim 1, wherein the memory controller (29, 200, 1020, 1010, 1110, 1441, 1511) provides a sector selection instruction and a sector address for the non-volatile storage device (60) for selecting the at least one target sector. [9] Method of operating a storage system (100, 1440) with a non-volatile storage device (60) and a storage controller (29, 200, 1020, 1010, 1110, 1441, 1511) controlling the non-volatile storage device (60), wherein the storage device has a plurality of memory cells (MC1, MC2, MC3) organized into a plurality of memory pages (110b, 400, 440), each of which has a plurality of sectors (411-41k, 610-880) for storing data (711, D1-Dm, DT1, DT2...) therein, wherein the method comprises: Reading data (711, D1-Dm, DT1, DT2...) from a selected memory page (110b, 400, 440) of the non-volatile storage device (60); Performing error correction decoding on the read data (711, D1-Dm, DT1, DT2...) on a sector-by-sector basis for each of the sectors (411-41k, 610-880) of the selected memory page (110b, 400, 440); and If the error correction decoding is unable to correct at least one data error from at least one target sector of the selected memory page (110b, 400, 440), but is able to correct all data errors of one or more sectors (411-41k, 610-880) of the selected memory page (110b, 400, 440), transmit a target sector selection instruction from the memory controller (29, 200, 1020, 1010, 1110, 1441, 1511) to the non-volatile storage device (60), wherein the target sector selection instruction causes the non-volatile storage device (60) to: to change a voltage that is to be applied to the memory cells (MC1, MC2, MC3) of at least one target sector, to preload destination bit lines connected to the at least one destination sector, while preventing the preloading of bit lines (BL, BL(1)-BL(m), 611-661) connected to the one or more success sectors (411-41k, 610-880), and to perform a new read attempt operation with the changed voltage for the data (711, D1-Dm, DT1, DT2...) that are stored in the at least one target sector. [10] The method of claim 9, wherein each sector (411-41k, 610-880) stores one or more parity bits generated on the basis of the data (711, D1-Dm, DT1, DT2...) stored in the sector (411-41k, 610-880), wherein a number of errors in the read data (711, D1-Dm, DT1, DT2...) of the at least one target sector is greater than a number of parity bits, and wherein a number of errors in the read data (711, D1-Dm, DT1, DT2...) of each of the one or more success sectors (411-41k, 610-880) is less than or equal to the number of parity data and the reread attempt operation for the data to be read (711, D1-Dm, DT1, DT2...) of at least one target sector is repeated until the error correction decoding is able to correct all data errors of the at least one target sector of the selected memory page (110b, 400, 440) or a predetermined reference number of repetitions, whichever occurs first.

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