Resolver soft decoding verification method and system applied to universal microcontroller before chip returning

Abstract

The invention discloses a resolver soft decoding verification method applied to a universal microcontroller before returning a chip, which comprises the following steps of: setting a plurality of groups of sinusoidal signals with different frequencies and voltages by using a signal generator, enabling a shaping unit and an integrating unit not to be enabled, and independently verifying a digital filtering unit; under the condition of different static angles or different rotating speed motion conditions, resolver soft decoding is carried out by using an access, and a waveform generator, a shaping unit and an integration unit are verified; the method for carrying out resolver soft decoding by using the access comprises the following steps of: generating a carrier excitation signal by using a to-be-verified DSAC module, sending the carrier excitation signal into a resolver excitation circuit, entering a resolver motor, and generating four paths of analog signals Sin +, Sin-, Cos + and Cos-after the carrier excitation signal passes through an excitation winding coil of the resolver motor; and the four paths of analog signals are input into an external analog modulator chip through an external return buffer circuit, the four paths of analog signals are converted into Sin and Cos digital code stream signals, the Sin and Cos digital code stream signals are returned to the to-be-verified DSCADC module for rotary transformer soft decoding, and Sin and Cos results are demodulated.

Description

Technical Field

[0001] The present invention belongs to the field of electronic technology, and more specifically, relates to a resolver soft decoding verification method and system applied to a general microcontroller before chip return. Background Art

[0002] New energy vehicles are mainly powered by electricity and driven by electric motors. A resolver (hereinafter referred to as "resolver") is needed to analyze the current angular position and speed information of the motor.

[0003] A resolver (or transformer) is an electromagnetic sensor consisting of a stator and a rotor. The stator winding, serving as the primary side of the transformer, receives the excitation voltage, typically at frequencies such as 400Hz, 3000Hz, and 5000Hz. The rotor winding, serving as the secondary side of the transformer, generates an induced voltage through electromagnetic coupling. The output voltage varies with the rotor angle. When the excitation winding is excited with an AC voltage of a certain frequency, the voltage amplitude of the output winding is proportional to the rotor angle, either in a sine or cosine function or in a certain proportional relationship.

[0004] During operation, the R1-R2 winding inputs a sinusoidal excitation signal Vr for excitation from an external circuit. As the motor rotates, the feedback windings S2-S4 and S1-S3 output sine and cosine feedback signals Va and Vb related to the motor position, as shown in the following example: Figure 1 The expression of the excitation signal is shown in equation (1), and the expression of the sine and cosine feedback signal is shown in equation (2)(3).

[0005] Vr=Vp × sin(ωt) (1) Va=Vq × sin(ωt) × cos(θ‌) (2) Vb=Vq × sin(ωt) × sin (θ‌) (3) Resolvers require dedicated decoding chips, which are expensive. An increasing number of resolver applications are now using the microprocessor's built-in DSADC (Delta Sigma Analog-to-Digital Converter) for software decoding. Integrating a DSADC module with decoding functionality in a microcontroller presents significant complexity and design risks. Verifying the DSADC module and its software decoding functionality before chip return is currently a challenge in chip design and verification. Summary of the Invention

[0006] To address the difficulty of completing the verification and soft decoding functions of the DSADC module before chip return, the present invention provides a resolver soft decoding verification method for a general-purpose microcontroller before chip return. The method uses the microcontroller's own module DSADC to perform resolver soft decoding verification. In hardware, an off-chip universal DSADC analog chip collects the differential signal input from the resolver and converts it into a digital code stream signal, which is transmitted to the FPGA (simulating the digital part of the microprocessor's soft decoding DSADC module). Combined with the software's FOC motor control algorithm and angle analysis strategy, the resolver angle signal is calculated and compared to verify the correctness and accuracy of the module's soft decoding, thus confirming the performance of the DSADC module's soft decoding design verification in advance before chip return.

[0007] According to one aspect of the present invention, a resolver soft decoding verification method for a general microcontroller before chip re-spin is provided, comprising: Use a signal generator to set multiple sets of sinusoidal signals with different frequencies and voltages. Disable the shaping unit and the integration unit, and verify the digital filter unit alone. Under different static angles or different speed motion conditions, the path is used to perform resolver soft decoding to verify the waveform generator, shaping unit and integration unit; wherein, the use of the path for resolver soft decoding includes: using the DSADC module to be verified to generate a carrier excitation signal, which is sent into the resolver excitation circuit and then into the resolver motor, and after passing through the resolver motor excitation winding coil, four analog signals of Sin+, Sin-, Cos+, and Cos- are generated, and input into the external analog modulator chip through an external return buffer circuit to convert the four analog signals into two digital code stream signals of Sin and Cos, and return to the DSADC module to be verified for resolver soft decoding, and demodulate the Sin and Cos results.

[0008] As a further technical solution, the digital filter unit is verified separately, which also includes: Use a signal generator to generate different signal frequencies and set different voltage ranges of 0~3.3V. The signals are input into an external analog modulator chip to convert the four analog signals into two digital streams of Sin and Cos. The signals are then returned to the DSADC module to be verified, undergoing resolver soft decoding through various filter chains, and demodulating the Sin and Cos results. Analyze the demodulated Sin and Cos results to confirm whether the sampling period is correct at different decimation rates; Compare the maximum and minimum values ​​of the sinusoidal signal in the soft decoding results to confirm whether the voltage results of each part within the sinusoidal waveform period are consistent with the voltage value of the signal generator.

[0009] As a further technical solution, a channel is used to perform resolver soft decoding under different static angle conditions, including: Set the resolver motor at different angles and perform incremental tests with fixed angle steps.

[0010] As a further technical solution, the method further includes: Confirm that the PWM signal with the set frequency is generated by the waveform generator, and whether the frequency of the sine wave after passing through the excitation circuit is the expected value; By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal; The shaped data is integrated using an integration unit, and the angle of the integrated data is calculated to compare whether the calculated angle is consistent with the set motor stall angle.

[0011] As a further technical solution, a channel is used to perform resolver soft decoding under different speed motion conditions, including: Set the input SpeedRef parameter, which, after passing through PI, is input into the FOC algorithm to control the motor speed to a set constant speed.

[0012] As a further technical solution, the method further includes: Confirm that the PWM signal with the set frequency is generated by the waveform generator, and whether the frequency of the sine wave after passing through the excitation circuit is the expected value; By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal; The shaped data is integrated using an integration unit, and the angle of the integrated data is calculated to compare whether the calculated angle is consistent with the set motor stall angle.

[0013] According to one aspect of the present invention, a resolver soft decoding verification system for a general microcontroller before chip return is provided. The system is implemented based on an FPGA, and a DSADC module to be verified and a motor control algorithm module are integrated on the FPGA. The motor control algorithm module is used to control the angle, speed and period of the resolver motor in different working modes; the DSADC module to be verified generates a carrier excitation signal, which is sent into the resolver excitation circuit and then into the resolver motor. After passing through the resolver motor excitation winding coil, four analog signals Sin+, Sin-, Cos+, and Cos- are generated. The four analog signals are input into an external analog modulator chip through an external return buffer circuit to convert the four analog signals into two digital code streams Sin and Cos, and then returned to the DSADC module to be verified for resolver soft decoding, forming a test path.

[0014] As a further technical solution, the DSADC module to be verified includes: The carrier generator is used to generate a PWM carrier excitation signal and simultaneously generate a carrier symbol signal to be transmitted to the shaping unit; A digital filtering unit, used for oversampling and filtering the collected digital code stream signal; A shaping unit, used for performing data shaping in combination with a carrier symbol signal; The integration unit is used to integrate the shaped data to obtain the demodulation result.

[0015] As a further technical solution, the system further includes: a PWM output module for generating a PWM signal to control the on and off of the power tube of the three-phase voltage source inverter, thereby controlling the operation of the PMSM motor.

[0016] As a further technical solution, the system further includes: A resolver excitation circuit, used for sending a carrier excitation signal into the resolver motor; The return buffer circuit is used to transmit the four analog signals output by the resolver motor to the external analog modulator chip; The external analog modulator chip is used to convert four analog signals into two digital code stream signals: Sin and Cos.

[0017] Compared with the prior art, the present invention has the following beneficial effects: The present invention is based on FPGA and uses a signal generator to perform resolver soft decoding when the motor is stationary and rotating. By verifying the design of the digital filter unit and further comparing the resolver soft-decoding angle data with the motor control algorithm angle data, the waveform generator, shaping unit, and integration unit are verified. The soft decoding correctness and decoding angle smoothness are confirmed by comparison, thereby verifying the complete digital function of the entire DSADC, ensuring that the microprocessor chip meets the performance requirements of the resolver decoding application during the design phase, and effectively reducing the risk of chip development. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] FIG1 shows the structure of a rotary transformer provided by an embodiment of the present invention.

[0020] FIG2 is a rotary transformer signal provided by an embodiment of the present invention.

[0021] FIG3 shows an FPGA provided by an embodiment of the present invention, including the complete digital functions of a microprocessor and a motor control algorithm.

[0022] FIG4 is a schematic diagram of the internal flow of the DSADC module provided by an embodiment of the present invention.

[0023] FIG5 is a block diagram of FOC vector control provided by an embodiment of the present invention.

[0024] FIG6 is a schematic diagram of a digital filter unit system for verifying the digital part of a DSADC module according to an embodiment of the present invention.

[0025] FIG7 is a schematic diagram of a system for verifying a DSADC module resolver soft decoding according to an embodiment of the present invention.

[0026] FIG8 is a flowchart of a workflow for comparing and verifying resolver soft decoding results according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention are arbitrarily combined with each other to form a new technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0028] An embodiment of the present invention provides a resolver soft decoding verification method for a general microcontroller before chip re-spin, comprising: Use a signal generator to set multiple sets of sinusoidal signals with different frequencies and voltages. Disable the shaping unit and the integration unit, and verify the digital filter unit alone. Under different static angles or different speed motion conditions, the path is used to perform resolver soft decoding to verify the waveform generator, shaping unit and integration unit; wherein, the use of the path for resolver soft decoding includes: using the DSADC module to be verified to generate a carrier excitation signal, which is sent into the resolver excitation circuit and then into the resolver motor, and after passing through the resolver motor excitation winding coil, four analog signals of Sin+, Sin-, Cos+, and Cos- are generated, and input into the external analog modulator chip through an external return buffer circuit to convert the four analog signals into two digital code stream signals of Sin and Cos, and return to the DSADC module to be verified for resolver soft decoding, and demodulate the Sin and Cos results.

[0029] The embodiment of the present invention is implemented using FPGA. Figure 3 As shown, the FPGA simulates the complete digital functions of the microprocessor, realizing the digital part functions of the microprocessor soft decoding DSADC module, the motor FOC control algorithm function, and the PWM module motor control output function.

[0030] like Figure 4 As shown in the figure, the digital portion of the DSADC module consists of four parts: a waveform generator, a digital filter unit, a shaping unit, and an integration unit. The digital filter unit includes a sinc filter, calibration function, FIR0, FIR1, and a high-pass filter. The shaping unit includes shaping configuration, signal synchronization configuration, and return signal acquisition. The integration unit includes the number of integrals, shift, and integration function configurations.

[0031] The waveform generator generates a set of PWM carrier excitation signals and simultaneously generates a carrier symbol signal, which is internally transmitted to the shaping unit. The digital filter unit oversamples and filters the data, converting the high-frequency, 1-bit data stream signal into a low-frequency, multi-bit digital output. The shaping unit synchronizes with the data stream signal and shapes the data using the carrier symbol signal. The integration unit integrates the shaped data to obtain the demodulated result.

[0032] like Figure 5 As shown in Figure 1, the motor control algorithm sets the target current Iqref vector current and the target angle to control the resolver motor to rotate to any angle between 0 and 360 degrees.

[0033] The three-phase current of the resolver motor is controlled by the FOC algorithm. The three-phase current values ​​ia, ib, and ic of the motor are collected and the current in the two-phase stationary coordinate system is obtained through the Clark transformation. , , and then through park transformation, the dq axis current id and iq in the rotating coordinate system are obtained, which are used as the feedback current of the dq axis current loop respectively, and the motor current control is completed through the PI of the current loop.

[0034] The motor control output functions of the PWM module include: the outputs of the dq axis current loop PI are the dq axis voltages respectively. The dq axis voltages are transformed through inverse park to obtain the αβ axis voltages in the two-phase stationary coordinate system, and then through space vector PWM modulation (SVPWM) to obtain six PWM signals to control the conduction and shutdown of the power tube of the three-phase voltage source inverter (VSI), thereby controlling the operation of the PMSM motor.

[0035] The method described in the embodiment of the present invention can be divided into three steps to verify the digital part of the DSADC module: Step 1: Use a signal generator to set multiple sets of sinusoidal signals with different frequencies and voltages. Disable the shaping unit and integration unit, and verify the digital filter unit alone.

[0036] Step 2: Under different static angles, use the channel to perform resolver soft decoding to further verify the waveform generator, shaping unit, and integration unit.

[0037] Step 3: Under different speed motion conditions, use the channel to perform resolver soft decoding to verify the waveform generator, shaping unit, and integration unit.

[0038] The specific steps are as follows: 1) Step 1: In the configuration shown in Table 1, a signal generator is used to generate sinusoidal signals with different signal frequencies and voltage ranges of 0 to 3.3 V.

[0039] ①Analyze the soft decoding result data of DSADC to confirm whether the sampling period is correct under different decimation rates.

[0040] ② Analyze the maximum and minimum values ​​of the sinusoidal signal in the soft decoding results, and compare the voltage results of each part within the sinusoidal waveform period with the voltage value of the signal generator to see if they are consistent.

[0041] Table 1 Configuration table

[0042] like Figure 6 As shown in the figure, step 1 uses the digital filtering unit of the DSADC (Delta Sigma Analog-to-Digital Converter) module on the FPGA. By using a signal generator to set different signal frequencies and set sinusoidal signals with different voltage ranges of 0~3.3V, the four analog signals are input to an external analog modulator chip to convert them into two digital code streams of Sin and Cos. The signals are returned to the DSADC module and soft-decoded through each filter chain to finally demodulate the Sin and Cos results.

[0043] 2) Step 2: Set the resolver motor at different angles: 0-90°, 90-180°, 180-270°, and 270-360°, and perform incremental tests with fixed angle steps. ①Confirm that the frequency of the sine wave after the excitation circuit is 9.765KHz when the PWM signal with a frequency of 625KHz is generated by the waveform generator.

[0044] ② By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal.

[0045] ③ Use the integration unit to integrate the shaped data, analyze the integrated data, calculate the angle by ATAN2, and compare the angle with the set motor stall angle to see if they are consistent.

[0046] 3) Step three, such as Figure 5 As shown in the figure, by setting the input SpeedRef parameter (i.e., target speed), after passing through the PI, it is input into the FOC algorithm, which controls the motor speed to the set speed for constant speed rotation. Set several groups of different motor speeds and control constant speed rotation for each group.

[0047] ①Confirm that the frequency of the sine wave after the excitation circuit is 9.765KHz when the PWM signal with a frequency of 625KHz is generated by the waveform generator.

[0048] ② By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal.

[0049] ③ Use the integration unit to integrate the shaped data, analyze the integrated data, calculate the angle using the angle observation algorithm or ATAN2, and compare the angle with the set motor stall angle to see if they are consistent.

[0050] When performing the shaping and integration functions in steps 2 and 3, the number of integrals configured during the integration of the shaped data must follow the following example rules, and the frequency of the soft decoding result must be consistent with the output sine wave frequency.

[0051] Table 2 Rules table

[0052] Step 2 and step 3 process as follows Figure 7As shown in the figure, the path uses the DSADC (Delta Sigma Analog-to-Digital Converter) module on the FPGA and its internal PWM to generate a carrier excitation signal. After passing through the external resolver excitation circuit, it enters the resolver motor. After passing through the resolver motor excitation winding coil, four signals, Sin+, Sin-, Cos+, and Cos-, are generated. After passing through the external return buffer circuit, they are input into the external analog modulator chip to convert the four analog signals into two digital code streams, Sin and Cos. The signals are returned to the DSADC module and pass through the filter chains and the shaping and integrating demodulator for resolver soft decoding, and finally the Sin and Cos results are demodulated.

[0053] The pathway processes the resolver soft decoding result data on an FPGA, calculates the resolver angle data and rotational speed through an algorithm, analyzes the data, and compares the angle and rotational speed of the resolver motor controlled by the motor control algorithm to confirm the correctness of the resolver decoding by the microcontroller before the chip is returned.

[0054] 3. Result Verification Step 1: Compare the configurations of various digital filter functions at different signal frequencies. When the overall decimation rate remains unchanged, compare the sampling period at 4096 sampling points to ensure that it complies with the theoretical situation.

[0055] Step 2: Use an oscilloscope to confirm that the sine wave frequency is 9.765 kHz, verifying the correct design of the waveform generator. Analyze the resolver soft decoding results after configuring the shaping unit and integrator. Based on the decimation rate and number of integrals, configure the resolver soft decoding output to match the sine wave frequency of 9.765 kHz. Analyze the soft decoding results, calculate the angle data using ATAN2 or the angle observation algorithm, and calculate the mean, variance, and standard deviation for each angle. Record the motor's static angle set by the motor control algorithm and the corresponding angle. By comparing the microcontroller's resolver decoding results at each angle with the static angle set by the motor control algorithm, verify the correct design of the shaping unit and integrator, and verify the correctness of the resolver soft decoding.

[0056] The mean expression is shown in formula (4), the standard deviation expression is shown in formula (5), and the variance expression is shown in formula (6).

[0057]

[0058] Step 3: Record the motor speed and period set in the motor control algorithm, analyze the resolver soft decoding results after configuring the shaping unit and integration unit, configure the resolver soft decoding output to conform to a sine wave frequency of 9.765 kHz based on the decimation rate and number of integrations, analyze the soft decoding results, and calculate the angle data and period using the ATAN2 function or the angle observation algorithm, as well as the motor speed. Comparing the recorded motor speed and period with the resolver soft-decoding angle data and angle smoothness verifies the correct design of the shaping unit and integration unit, and the correctness of the resolver soft-decoding results.

[0059] exist Figure 4 In the illustrated embodiment, path 1 uses the DSADC (Delta Sigma Analog-to-Digital Converter) module on the FPGA. This module's internal PWM generates a carrier excitation signal, providing a sinusoidal excitation signal (PWM_P) and its complement (PWM_N) to the resolver. The excitation signal is derived from a periodic duty-cycle square wave passing through an external low-pass filter. The typical modulation frequency of the carrier signal is 312.5 kHz, resulting in a carrier harmonic signal with a frequency of 9.7656 kHz.

[0060] After passing through the resolver motor excitation winding coil, four signals, Sin+, Sin-, Cos+, and Cos-, are generated. These signals are then input into an external analog modulator through a return buffer circuit to convert the four analog signals into two digital code streams, Sin and Cos. These signals are then input into the DSADC module on the FPGA. The module then performs resolver soft decoding through a digital filter, shaping unit, and integration unit, and finally demodulates the Sin and Cos soft decoding results.

[0061] Figure 6 This is a system diagram of the digital filtering unit for the digital part of the DSADC module for verifying an embodiment of the present invention. The digital filtering unit of the DSADC module is used. By using a signal generator to set different signal frequencies and sinusoidal signals with different voltage ranges of 0~3.3V, the four analog signals are input into an external analog modulator chip to convert them into two digital code streams, Sin and Cos. The signals are returned to the DSADC module and passed through the filter chains of the digital filtering unit for resolver soft decoding. Finally, the Sin and Cos results are demodulated to verify the digital filtering unit of the digital part of the microcontroller.

[0062] Figure 7This is a schematic diagram of the internal flow of the DSADC module according to one embodiment of the present invention. While the DSADC module generates a carrier excitation signal, it also generates a carrier symbol signal internally and inputs it into the shaping unit. The excitation signal is input into the external analog modulator chip through the resolver motor and the resolver return buffer circuit, modulated into Sin and Cos digital code stream signals, and then input into the DSADC module. The code stream is filtered by the module's digital filter unit and then input into the shaping unit. The shaping unit synchronizes the returned code stream signal with the carrier coincidence signal, and shapes and flips the waveform. Finally, the integration unit decodes the Sinθ and Cosθ soft decoding results, verifying the overall digital part of the microcontroller DSADC module.

[0063] Figure 8 This is a workflow diagram for comparing and verifying resolver soft decoding results according to an embodiment of the present invention.

[0064] In step S701 , the DSADC module of the channel generates a PWM excitation signal.

[0065] In steps S702 and S703 , the modes of the resolver motor are controlled to respectively control the motor to rotate at a constant speed at different stationary angles and different speeds.

[0066] In step S704 , the channel selects the resolver motor to be in mode 1 or mode 2.

[0067] In step S705 , the DSADC module of the path performs resolver soft decoding on the resolver signal and demodulates the results Sin and Cos.

[0068] In step S706 , the angle position information of each angle of the motor in the path is calculated, and the angle data is analyzed in terms of mean, variance, and standard deviation.

[0069] In step S711, the correctness of the resolver soft decoding is confirmed by comparing the recorded motor speed and period with the resolver soft decoding angle data and angle smoothness, and by comparing the resolver decoding results of the microcontroller at each angle with the static angle set by the motor control algorithm.

[0070] In summary, the key points of the present invention are: 1. A method for verifying the digital function of a DSADC module designed for resolver soft decoding, which is applied to a general-purpose microprocessor before chip return, includes a waveform generator, a digital filter unit, a shaping unit, and an integration unit.

[0071] 2. Use the signal generator in step 1 to verify the digital filter unit separately to verify the results and cycle correctness of the soft decoding.

[0072] 3. Perform resolver soft decoding on the digital part of the DSADC module in different scenarios of steps 2 and 3 to confirm that the resolver soft decoding results are consistent with the control angle and speed cycle of the motor control algorithm, and verify the correctness of the design of the waveform generator, shaping unit, and integration unit of the digital part.

[0073] 4. This verification method confirms that the MCU's DSADC module correctly decodes the resolver's angular position and rotational speed. It also compares the mean, standard deviation, and variance of the resolver soft decoding results from both channels, including angular smoothness and phase difference, to verify resolver soft decoding performance. This verification system effectively verifies the digital functionality of the DSADC module and, by extension, its resolver soft decoding performance.

[0074] The terms "including" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions, for example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A resolver soft decoding verification method for a general microcontroller before chip return is characterized in that: include: Use a signal generator to set multiple sets of sinusoidal signals with different frequencies and voltages. Disable the shaping unit and the integration unit, and verify the digital filter unit alone. Under different static angles or different speed motion conditions, the path is used to perform resolver soft decoding to verify the waveform generator, shaping unit and integration unit; wherein, the use of the path for resolver soft decoding includes: using the DSADC module to be verified to generate a carrier excitation signal, which is sent into the resolver excitation circuit and then into the resolver motor, and after passing through the resolver motor excitation winding coil, four analog signals of Sin+, Sin-, Cos+, and Cos- are generated, and input into the external analog modulator chip through an external return buffer circuit to convert the four analog signals into two digital code stream signals of Sin and Cos, and return to the DSADC module to be verified for resolver soft decoding, and demodulate the Sin and Cos results.

2. The resolver soft decoding verification method for a general microcontroller before chip re-spinning according to claim 1 is characterized in that: Verify the digital filter unit separately, also including: Use a signal generator to generate different signal frequencies and set different voltage ranges of 0~3.3V. The signals are input into an external analog modulator chip to convert the four analog signals into two digital streams of Sin and Cos. The signals are then returned to the DSADC module to be verified, undergoing resolver soft decoding through various filter chains, and demodulating the Sin and Cos results. Analyze the demodulated Sin and Cos results to confirm whether the sampling period is correct at different decimation rates; Compare the maximum and minimum values ​​of the sinusoidal signal in the soft decoding results to confirm whether the voltage results of each part within the sinusoidal waveform period are consistent with the voltage value of the signal generator.

3. The resolver soft decoding verification method for a general microcontroller before chip re-spinning according to claim 1 is characterized in that: At different static angles, the channels are used for resolver soft decoding, including: Set the resolver motor at different angles and perform incremental tests with fixed angle steps.

4. The resolver soft decoding verification method for a general microcontroller before chip re-spinning according to claim 3 is characterized in that: The method further comprises: Confirm that the PWM signal with the set frequency is generated by the waveform generator, and whether the frequency of the sine wave after passing through the excitation circuit is the expected value; By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal; The shaped data is integrated using an integration unit, and the angle of the integrated data is calculated to compare whether the calculated angle is consistent with the set motor stall angle.

5. The resolver soft decoding verification method for a general microcontroller before chip re-spinning according to claim 1 is characterized in that: Under different speed motion conditions, the resolver soft decoding is performed using channels, including: Set the input SpeedRef parameter, which, after passing through PI, is input into the FOC algorithm to control the motor speed to a set constant speed.

6. The resolver soft decoding verification method for a general microcontroller before chip re-spinning according to claim 5 is characterized in that: The method further comprises: Confirm that the PWM signal with the set frequency is generated by the waveform generator, and whether the frequency of the sine wave after passing through the excitation circuit is the expected value; By stalling the resolver motor at different angles, confirm whether the shaping unit can synchronize with the data stream signal and complete data shaping through the carrier symbol signal; The shaped data is integrated using an integration unit, and the angle of the integrated data is calculated to compare whether the calculated angle is consistent with the set motor stall angle.

7. The resolver soft decoding verification system used in general microcontrollers before chip return is characterized by: The system is implemented based on an FPGA. The FPGA integrates a DSADC module to be verified and a motor control algorithm module. The motor control algorithm module is used to control the angle, speed and period of the resolver motor in different operating modes. The DSADC module to be verified generates a carrier excitation signal, which is sent to the resolver excitation circuit and then enters the resolver motor. After passing through the resolver motor excitation winding coil, four analog signals Sin+, Sin-, Cos+, and Cos- are generated. After passing through an external return buffer circuit, they are input into an external analog modulator chip to convert the four analog signals into two digital code streams Sin and Cos. The signals are then returned to the DSADC module to be verified for resolver soft decoding, forming a test path.

8. The resolver soft decoding verification system for a general microcontroller before chip re-entry according to claim 7, characterized in that: The DSADC module to be verified includes: The carrier generator is used to generate a PWM carrier excitation signal and simultaneously generate a carrier symbol signal to be transmitted to the shaping unit; A digital filtering unit, used for oversampling and filtering the collected digital code stream signal; A shaping unit, used for performing data shaping in combination with a carrier symbol signal; The integration unit is used to integrate the shaped data to obtain the demodulation result.

9. The resolver soft decoding verification system for a general microcontroller before chip re-entry according to claim 7, characterized in that: The system further includes: a PWM output module for generating a PWM signal to control the on and off of the power tubes of the three-phase voltage source inverter, thereby controlling the operation of the PMSM motor.

10. The resolver soft decoding verification system for a general microcontroller before chip re-entry according to claim 7, characterized in that: The system further comprises: A resolver excitation circuit, used for sending a carrier excitation signal into the resolver motor; The return buffer circuit is used to transmit the four analog signals output by the resolver motor to the external analog modulator chip; The external analog modulator chip is used to convert four analog signals into two digital code stream signals: Sin and Cos.

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