Processor core detection method, device, storage medium and program product

Abstract

The application discloses a processor core detection method and device, a storage medium and a program product, relates to the technical field of computer testing, and comprises reading and detecting the core quantity based on a plurality of preset methods, determining a core quantity test result; if the core quantity test result is test passed, determining a first pressure test result based on first pressure test of each core; if the first pressure test result is test passed, carrying out second pressure test on a high-speed interface on the basis of the first pressure test; determining a second pressure test result based on the first pressure test and the second pressure test. The application detects the core quantity from multiple aspects and multiple angles, thereby improving the accuracy and reliability of the detection of the number of processor cores; floating point operation pressure test and memory read-write pressure test are respectively carried out for each core, the processor core is comprehensively and deeply detected, and the accuracy and reliability of the stability detection of the processor core are improved.

Description

Technical Field

[0001] This invention relates to the field of computer testing technology, and in particular to processor core testing methods, equipment, storage media, and program products. Background Technology

[0002] To ensure stable operation of processor cores under high concurrency and high stress scenarios, it is necessary to test the number and stability of processor cores. Related technologies typically use direct instruction parsing to obtain the number of processor cores. However, this data may not accurately reflect the actual number of usable cores in the processor, leading to inaccurate core counts. Furthermore, stress testing in these technologies often tests the entire processor, lacking in-depth testing of the cores. This results in stress tests only covering surface-level phenomena, leading to inaccurate stability assessments of the processor cores. Summary of the Invention

[0003] This invention provides a processor core detection method, device, storage medium, and program product to at least solve the problems of low accuracy and reliability in the detection of the number and stability of processor cores in related technologies.

[0004] This invention provides a processor core detection method, comprising:

[0005] The number of cores of the target processor is read and detected using multiple preset methods to determine the test results of the number of cores of the target processor.

[0006] If the core count test result is a pass, then the first stress test result of the target processor is determined based on the first stress test of each core in the target processor, wherein the first stress test is a floating-point operation stress test of each core;

[0007] If the first stress test passes, a second stress test is conducted on the high-speed interface of the target processor based on the first stress test. The second stress test is a memory read and write stress test on each core.

[0008] Based on the first and second stress tests on the target processor, the results of the second stress test on the target processor are determined.

[0009] The present invention also provides a processor core detection device, comprising:

[0010] The core count testing module is used to read and detect the core count of the target processor based on multiple preset methods, and determine the core count test result of the target processor.

[0011] The first test result module is used to determine the first stress test result of the target processor based on the first stress test of each core in the target processor if the core quantity test result is a pass test. The first stress test is a floating-point operation stress test of each core.

[0012] The second stress test module is used to perform a second stress test on the high-speed interface of the target processor based on the first stress test if the first stress test result is a pass. The second stress test is a memory read and write stress test on each core.

[0013] The second test result module is used to determine the second stress test result of the target processor based on the first stress test and the second stress test on the target processor.

[0014] The present invention also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the processor core detection methods described above when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the processor core detection methods described above.

[0016] The present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the steps of any of the processor core detection methods described above.

[0017] This invention uses multiple preset methods to read and detect the number of cores in a target processor, providing a multi-layered and multi-angle-based detection of the core count, thereby improving the accuracy and reliability of core count detection. A first stress test is performed on each core of the target processor, followed by a second stress test on the high-speed interfaces. This allows for separate floating-point operation stress tests and memory read / write stress tests for each core, achieving in-depth core detection. Furthermore, combining these tests provides a comprehensive and in-depth detection of the cores, improving the accuracy and reliability of core stability detection. Therefore, this invention addresses the low accuracy and reliability issues in related technologies for detecting the number and stability of processor cores, achieving a significant improvement in accuracy and reliability. Attached Figure Description

[0018] To more clearly illustrate the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a processor core detection method provided in an embodiment of the present invention;

[0020] Figure 2 This is a flowchart illustrating another processor core detection method provided in an embodiment of the present invention;

[0021] Figure 3 This is a flowchart illustrating another processor core detection method provided in an embodiment of the present invention;

[0022] Figure 4 This is a flowchart illustrating the processor core detection method provided in an embodiment of the present invention;

[0023] Figure 5 This is a flowchart illustrating a specific embodiment of a processor core detection method provided by the present invention.

[0024] Figure 6 This is a schematic diagram of the structure of a processor core detection device provided in an embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present invention.

[0027] It should be noted that, in the description of this invention, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., used in this invention are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0028] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] To ensure stable operation of processor cores under high concurrency and high stress scenarios, it is necessary to test the number and stability of processor cores. Related technologies typically use commands such as ` / proc / cpuinfo` or `lscpu` to directly parse processor information and obtain the number of processor cores. However, this data may not accurately reflect the actual number of usable cores in the processor, leading to inaccurate core counts. Furthermore, stress tests often test the entire processor, failing to correlate test data with the number of cores and providing a lack of in-depth core testing. This results in stress tests only covering surface-level phenomena, leading to inaccurate stability assessments of the processor cores.

[0030] Based on this, the present invention provides a processor core detection method. This method reads and detects the number of cores in a target processor using multiple preset methods, detecting the number of cores from multiple levels and angles, thereby improving the accuracy and reliability of core count detection. A first stress test is performed on each core in the target processor, and based on this first stress test, a second stress test is performed on the high-speed interfaces in the target processor. This allows for separate floating-point operation stress tests and memory read / write stress tests for each core in the target processor, achieving in-depth detection of the processor cores. Furthermore, by combining the floating-point operation stress test and the memory read / write stress test, a comprehensive and in-depth detection of the processor cores is achieved, improving the accuracy and reliability of core stability detection.

[0031] The processor core detection method provided by this invention can be applied to any computer device, such as mobile terminal devices, servers, etc., and can detect the core of any processor in any computer device, without being limited to a specific processor type or architecture.

[0032] On one hand, embodiments of the present invention provide a processor core detection method. It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions, and although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in a different order than that shown here.

[0033] This embodiment provides a processor core detection method. Figure 1 This is a flowchart illustrating a processor core detection method provided in an embodiment of the present invention, as shown below. Figure 1As shown, this processor core detection method includes:

[0034] Step S101: The number of cores of the target processor is read and detected based on multiple preset methods to determine the test result of the number of cores of the target processor.

[0035] In this embodiment of the invention, based on multiple preset methods, the number of cores of the target processor is read and detected from multiple levels, including the operating system and hardware. The number of usable cores in the target processor at different levels is obtained, and the core numbers at different levels are compared. If all core numbers are consistent, the core number test result of the target processor is considered passed; if there are inconsistencies, the core number test result of the target processor is considered failed. Therefore, by using multiple preset methods to detect the core number of the target processor from multiple levels, the limitations of single-level detection are avoided. Furthermore, cross-validation through multi-level detection comprehensively covers the availability of processor cores at different levels, achieving accuracy and reliability in detecting the core number of the target processor.

[0036] In an optional implementation, considering the actual production process, before step S101, it further includes determining whether the target processor used in the current device is correct, that is, judging whether the processor material used in the current device is correct. Specifically, based on the identification information of the target processor, a preset database is searched to determine the first attribute information corresponding to the target processor. The first attribute information is the attribute information corresponding to the identification information of the target processor stored in the preset database, which is the attribute information of the processor that should be used in the current device. The preset database is used to store the correspondence between the identification information and the attribute information of the processor. The identification information can be the name information of the processor, the material number written by the user, etc. The preset database maintains the identification information and specific attribute information of all processors. The attribute information can include the processor manufacturer, number of cores, nominal frequency, cache information, model and description, etc., and a processor can be uniquely identified through the attribute information. The second attribute information of the target processor in the operating system is obtained. The second attribute information is the attribute information of the processor actually used in the current device. If the second attribute information is consistent with the first attribute information, it indicates that the processor actually used in the current device is consistent with the processor that should be used, and the target processor is not used incorrectly. At this time, step S101 is executed to read and detect the number of cores of the target processor based on multiple preset methods to determine the test result of the number of cores of the target processor. If the second attribute information is inconsistent with the first attribute information, it indicates that the processor actually used in the current device is inconsistent with the processor that should be used, and the target processor is used incorrectly. At this time, an alarm message is issued to indicate that the wrong processor is used.

[0037] Step S102: If the core count test result is a pass, then the first stress test result of the target processor is determined based on the first stress test of each core in the target processor.

[0038] In this embodiment of the invention, if the core count test passes, a further stress test is performed on the target processor's cores to test their stability. Specifically, depending on the hardware and operating scenario design of different processor cores, the stress test on the target processor's cores can be divided into a first stress test (stress test of the internal modules of the processor core) and a second stress test (stress test of the external interactions of the processor core).

[0039] In this embodiment of the invention, when stress testing the core of the target processor, a first stress test is first performed on each core of the target processor. This first stress test, which is a stress test on the operation of the internal modules of the processor core, is a floating-point operation stress test on each core. It is used to test the integrity of the hardware functions of the floating-point processing unit inside the processor core, the stability of the core under continuous high load, and the reliability of the core operating independently.

[0040] In this embodiment of the invention, based on a first stress test on each core of the target processor, test data of each core in the target processor during the first stress test is obtained, and the first stress test result of the target processor is determined based on the test data. The test data may be relevant parameter data of each core in the target processor during the first stress test, and the parameter data may include the temperature, operating frequency, etc. of each core.

[0041] In this embodiment of the invention, if the obtained test data meets the preset test requirements, the first stress test result can be determined as a test pass; if the obtained test data does not meet the preset test requirements, the first stress test result can be determined as a test fail.

[0042] In one alternative implementation, the preset test requirements can be set by the tester based on the performance requirements of the target processor, or they can be set based on the rated parameters of the target processor. For example, if the critical temperature of the target processor is A, then the temperature limitation condition in the preset test requirements can be set to A.

[0043] In one optional implementation, before performing the first stress test on each core of the target processor, the number of cores of the target processor is verified again to ensure that the target processor is in a stable state during the current test and that no core loss occurs, thereby ensuring the reliability of the first stress test. Specifically, a processor identification instruction is invoked to obtain the attribute information of the target processor, wherein the processor identification instruction can be a CPUID instruction; the number of cores in the attribute information is compared with the number of cores of the target processor detected based on multiple preset methods, that is, compared with the number of cores of the target processor detected in step S101, to verify the number of cores of the target processor; if the number of cores in the attribute information is inconsistent with the number of cores of the target processor detected in step S101, it indicates that the verification has failed, and the target processor has experienced core loss, so the first stress test is not performed; if the number of cores in the attribute information is consistent with the number of cores of the target processor detected in step S101, it indicates that the verification has passed, and the target processor has not experienced core loss, so the first stress test continues.

[0044] In one optional implementation, before performing the first stress test on the target processor, functional tests are also performed on each target instruction set for the target processor to determine the functional status of each target instruction set, thereby ensuring that each instruction set functions normally during the first stress test and avoiding its impact on the first stress test; wherein, the target instruction set may include instruction sets such as SSE (Streaming SIMD Extensions), AVX (Advanced Vector Extensions), and AES (Advanced Encryption Standard).

[0045] In an optional implementation, if the first stress test result is a pass, that is, after the first stress test is passed, the above step S101 will be executed again to read and detect the number of cores of the target processor based on multiple preset methods to determine the core count test result. After the first stress test is passed, the core count will be detected again to determine whether the cores of the target processor have a core loss fault, so as to further verify the stability and reliability of the processor cores under high load.

[0046] Step S103: If the first stress test result is a pass, then a second stress test is performed on the high-speed interface in the target processor based on the first stress test.

[0047] In this embodiment of the invention, if the first stress test result is a pass, a second stress test is further performed on each core of the target processor. The second stress test, namely the stress test of external interaction between the processor cores, is a memory read / write stress test on each core. It is used to test the processing capability and stability of the memory controller during memory read / write communication between the processor cores, the consistency and effectiveness of the multi-level cache in the processor cores, and the reliability of data transmission between the processor cores and memory.

[0048] In this embodiment of the invention, the second stress test on each core is achieved by performing a second stress test on the high-speed interface of the target processor, that is, by performing high-frequency, large-capacity memory read and write operations on the high-speed interface of the target processor to achieve the second stress test on each core.

[0049] In this embodiment of the invention, after the first stress test is passed, the first stress test is not stopped. Instead, a second stress test is performed based on the first stress test, thus superimposing the first and second stress tests. This approach, on the one hand, simulates real-world application scenarios, avoiding the inability of a single test to reflect the actual working capabilities of the processor core and improving test reliability. On the other hand, it triggers hardware resource contention and intensifies extreme high-load testing conditions, preventing omissions of potential risks and hidden dangers due to a single test or insufficient test pressure, achieving comprehensive testing of the processor core. Furthermore, superimposing the first and second stress tests verifies the entire process of processor core operation, achieving verification of the consistency and reliability of the entire processor core chain.

[0050] Step S104: Based on the first stress test and the second stress test on the target processor, determine the result of the second stress test on the target processor.

[0051] In this embodiment of the invention, based on a first stress test and a second stress test on each core of the target processor, test data of each core in the target processor during the first and second stress tests are obtained, and the second stress test result of the target processor is determined based on the test data. The test data may be relevant parameter data of each core in the target processor during the first and second stress tests, and the parameter data may include the temperature, operating frequency, etc. of each core.

[0052] In this embodiment of the invention, if the obtained test data meets the preset test requirements, the second stress test result can be determined as a test pass; if the obtained test data does not meet the preset test requirements, the second stress test result can be determined as a test fail.

[0053] In one alternative implementation, the preset test requirements can be set by the tester based on the performance requirements of the target processor, or they can be set based on the rated parameters of the target processor. For example, if the critical temperature of the target processor is A, then the temperature limitation condition in the preset test requirements can be set to A.

[0054] In an optional implementation, if the second stress test result is a pass, that is, after the second stress test is passed, the above step S101 will be executed again to read and detect the number of cores of the target processor based on multiple preset methods to determine the core count test result. In this way, after the first stress test is passed, the core count will be detected again to determine whether the cores of the target processor have a core loss fault, so as to further verify the stability and reliability of the processor cores under high load.

[0055] The processor core detection method provided in this invention reads and detects the number of cores of a target processor based on multiple preset methods, detecting the number of cores of the target processor from multiple levels and angles, thereby improving the accuracy and reliability of detecting the number of processor cores. A first stress test is performed on each core in the target processor, and based on the first stress test, a second stress test is performed on the high-speed interfaces in the target processor. This allows for separate floating-point operation stress tests and memory read / write stress tests for each core in the target processor, achieving in-depth detection of the processor cores. Furthermore, by combining the floating-point operation stress test and the memory read / write stress test, a comprehensive and in-depth detection of the processor cores is achieved, improving the accuracy and reliability of detecting the stability of the processor cores.

[0056] This embodiment provides a processor core detection method. Figure 2 This is a flowchart illustrating another processor core detection method provided in an embodiment of the present invention, as shown below. Figure 2 As shown, this processor core detection method includes:

[0057] Step S201: The number of cores of the target processor is read and detected based on multiple preset methods to determine the test result of the number of cores of the target processor.

[0058] Specifically, step S201 includes:

[0059] Step S2011: Call the operating system to parse the information of the target processor and obtain the number of the first cores.

[0060] In this embodiment of the invention, based on the operating system's parsing of information about the target processor, the number of cores in the target processor is detected at the operating system level, and the detection result is used as the first core count. The first core count detected at the operating system level represents the number of cores currently available for scheduling in the target processor.

[0061] In one alternative implementation, the command "lscpu | grep 'Core(s) persocket' | awk -F ':' '{print $2}'" is executed in the operating system to obtain the number of the first cores.

[0062] Step S2012: Read the number of cores integrated in the target processor to obtain the second core count.

[0063] In this embodiment of the invention, the number of cores integrated in the target processor is read from the hardware level to obtain the second core count; the second core count represents the actual number of cores integrated in the target processor at the hardware level, and the second core count can detect the core loss problem of the target processor.

[0064] In one alternative implementation, the command "dmidecode -t processor | grep 'CoreCount' | awk –F : '{print $2}'" is executed to obtain the number of the second core.

[0065] Step S2013: Detect the activation status of each core in the target processor and count the number of cores in the activation state to obtain the number of third cores.

[0066] In this embodiment of the invention, the enabling status of each core in the target processor is detected to identify and intercept cores with ACPI (Advanced Configuration and Power Interface) configuration errors. If a core is disabled, it indicates an ACPI configuration error and cannot be scheduled by the operating system; if a core is enabled, it indicates no ACPI configuration error and can be scheduled normally by the operating system. The number of enabled cores in the target processor is counted to obtain the third core count.

[0067] In one alternative implementation, execute the command "dmidecode -t processor | grep 'CoreEnabled' | awk –F : '{print $2}'" to obtain the number of third cores.

[0068] Step S2014: If the number of the first core, the number of the second core, and the number of the third core are the same, then the core count test result is determined to be a successful test.

[0069] In this embodiment of the invention, the first number of cores, the second number of cores, and the third number of cores are compared. If the three are the same, it indicates that the target processor does not have a core loss problem, there is no error in the operating system's interpretation of the number of cores, and all cores can be used normally. At this time, the core count test result is determined to be a successful test.

[0070] In one optional implementation, when comparing the number of the first core, the number of the second core, and the number of the third core, the three are also compared with the number of cores in the corresponding attribute information of the target processor in a preset database. This comparison is based on the number of cores in the corresponding attribute information of the target processor in the preset database to detect whether there are faults in the cores of the target processor at various levels, thereby ensuring the accuracy and reliability of the detection of the number of cores of the target processor.

[0071] Step S202: If the core count test result is a pass, then based on the first stress test on each core of the target processor, determine the first stress test result of the target processor. For details, please refer to [link to details]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0072] Step S203: If the first stress test passes, a second stress test is performed on the high-speed interface of the target processor based on the first stress test result. See details below. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0073] Step S204: Based on the first and second stress tests on the target processor, determine the result of the second stress test on the target processor. See details below. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0074] The processor core detection method provided in this invention detects the number of cores in a target processor from three levels: the operating system level, the hardware level, and the core activation status. It detects whether the target processor has core loss issues, whether the operating system has errors in resolving the number of cores, and whether the cores are properly activated. This multi-angle and multi-layer approach improves the accuracy and reliability of detecting the number of processor cores.

[0075] This embodiment provides a processor core detection method. Figure 3 This is a flowchart illustrating another processor core detection method provided in an embodiment of the present invention, as shown below. Figure 3 As shown, this processor core detection method includes:

[0076] Step S301: The number of cores of the target processor is read and detected using multiple preset methods to determine the test result of the number of cores of the target processor. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0077] Step S302: If the core count test result is a pass, then the first stress test result of the target processor is determined based on the first stress test of each core in the target processor.

[0078] Specifically, step S302 includes:

[0079] Step S3021: Perform core binding operation on each core and perform floating-point operation stress test on each core.

[0080] In this embodiment of the invention, a core-binding operation is performed on each core of the target processor, assigning a corresponding process or thread to each core to ensure that all cores of the target processor can participate in the first stress test. After the core-binding operation is completed, a floating-point operation stress test is performed on each core to execute the first stress test.

[0081] Step S3022: During the floating-point operation stress test, at a first preset time interval, acquire the temperature and frequency information of each core to obtain the first temperature set and the first frequency set.

[0082] In this embodiment of the invention, during the first stress test, i.e. the floating-point operation stress test, the temperature information and frequency information of each core are acquired every first preset time interval, and the acquired temperature information and frequency information are used to form a first temperature set and a first frequency set, so as to analyze the test status of the processor core under the first stress test based on the first temperature set and the first frequency set; that is, the test status of each core in the target processor is detected every first preset time interval.

[0083] Step S3023: Determine the first pressure test result based on the first temperature set and the first frequency set.

[0084] In this embodiment of the invention, based on a first temperature set and a first frequency set, the changes in temperature and frequency of each core in the target processor under a first stress test are analyzed to determine the results of the first stress test.

[0085] In this embodiment of the invention, the temperature of each core in the target processor is first analyzed; if there is temperature information in the first temperature set that exceeds the preset temperature threshold, it indicates that there is at least local high temperature in the target processor, causing the temperature of some cores to exceed the critical temperature, and therefore the first stress test result is determined to be a test failure; if all temperature information in the first temperature set is lower than the preset temperature threshold, the overall performance of the target processor core is further analyzed from the perspective of the target processor as a whole.

[0086] Specifically, based on the maximum and minimum values ​​of temperature information in the first temperature set, the temperature difference corresponding to the first temperature set is calculated. By analyzing the temperature difference of the core in the target processor, it is determined whether the target processor core has problems with poor heat dissipation or inadequate stability. Based on the maximum and minimum values ​​of frequency information in the first frequency set, the frequency fluctuation value corresponding to the first frequency set is calculated. By analyzing the frequency fluctuation value of the core in the target processor, it is determined whether the target processor has problems with inadequate stability. If the temperature difference exceeds a first preset temperature difference, it indicates that the target processor core has problems with poor heat dissipation or inadequate stability; or, if the frequency fluctuation value exceeds a first preset fluctuation value, it indicates that the target processor has problems with inadequate stability. In this case, the first stress test result is determined to be a failure, indicating that the target processor core may pose a risk of system crash under high concurrency and high load application scenarios. If the temperature difference is lower than the first preset temperature difference, and the frequency fluctuation value is lower than the first preset fluctuation value, it indicates that the target processor core does not have problems with poor heat dissipation or inadequate stability. In this case, the first stress test result is determined to be a success.

[0087] Step S303: If the first stress test passes, a second stress test is performed on the high-speed interface of the target processor based on the first stress test. See details below. Figure 1 Step S103 of the illustrated embodiment will not be described again here.

[0088] Step S304: Based on the first and second stress tests on the target processor, determine the result of the second stress test on the target processor. See details below. Figure 1 Step S104 of the illustrated embodiment will not be described again here.

[0089] The processor core detection method provided in this invention, through core binding, assigns a corresponding process or thread to each core, thereby distributing the pressure to each core and ensuring that all cores in the target processor can participate in the first stress test. Simultaneously, during the first stress test, temperature and frequency information of each core are acquired, forming a first temperature set and a first frequency set. Based on the first temperature set and the first frequency set, analysis is performed from both the perspective of a single core and the perspective of the target processor as a whole to determine whether any cores of the target processor fail to meet stability standards during the first stress test. This achieves comprehensive and in-depth detection of the processor cores, improving the accuracy and reliability of the stability detection of the processor cores.

[0090] This embodiment provides a processor core detection method. Figure 4 This is a flowchart illustrating the processor core detection method provided in an embodiment of the present invention, as shown below. Figure 4 As shown, this processor core detection method includes:

[0091] Step S401: The number of cores of the target processor is read and detected using multiple preset methods to determine the test result of the number of cores of the target processor. For details, please refer to [link to relevant documentation]. Figure 1 Step S101 of the illustrated embodiment will not be described again here.

[0092] Step S402: If the core count test result is a pass, then based on the first stress test on each core of the target processor, determine the first stress test result of the target processor. For details, please refer to [link to details]. Figure 1 Step S102 of the illustrated embodiment will not be described again here.

[0093] Step S403: If the first stress test result is a pass, then a second stress test is performed on the high-speed interface in the target processor based on the first stress test.

[0094] Specifically, step S403 includes:

[0095] Step S4031: Based on the first stress test, allocate memory to each core.

[0096] In this embodiment of the invention, after the first stress test is passed, the first stress test is not stopped. Instead, the first stress test and the second stress test are superimposed, and stress tests are performed on each core of the target processor simultaneously. During the second stress test, memory is first allocated to each core of the target processor. Then, during the second stress test, each core of the target processor is controlled to perform high-frequency, high-capacity data reads and writes to its corresponding memory.

[0097] Step S4032: Perform read / write stress tests on the memory corresponding to each core through a high-speed interface.

[0098] In this embodiment of the invention, high-frequency, large-capacity data read and write operations are performed on the memory corresponding to each core through the high-speed interface of the target processor, so as to achieve high-pressure read and write tests on each core of the target processor.

[0099] Step S404: Based on the first stress test and the second stress test on the target processor, determine the result of the second stress test on the target processor.

[0100] Specifically, step S404 includes:

[0101] Step S4041: During the first pressure test and the second pressure test, at a second preset time interval, acquire the temperature information and frequency information of each core to obtain the second temperature set and the second frequency set.

[0102] In this embodiment of the invention, during the first stress test and the second stress test, temperature information and frequency information of each core are acquired every second preset time interval, and the acquired temperature information and frequency information are used to form a second temperature set and a second frequency set, so as to analyze the test status of the processor core under the first stress test and the second stress test based on the second temperature set and the second frequency set; that is, the test status of each core in the target processor is detected every second preset time interval.

[0103] Step S4042: Based on the second temperature set and the second frequency set, determine the second stress test result of the target processor.

[0104] In this embodiment of the invention, based on a second temperature set and a second frequency set, the temperature and frequency changes of each core in the target processor under the first stress test and the second stress test are analyzed to determine the results of the second stress test.

[0105] In this embodiment of the invention, based on the maximum and minimum values ​​of temperature information in the second temperature set, the temperature difference corresponding to the second temperature set is calculated. The temperature difference of the core in the target processor is used to determine whether the target processor core has problems with poor heat dissipation or inadequate stability. Based on the maximum and minimum values ​​of frequency information in the second frequency set, the frequency fluctuation value corresponding to the second frequency set is calculated. The frequency fluctuation value of the core in the target processor is used to determine whether the target processor has problems with inadequate stability. If the temperature difference exceeds a second preset temperature difference, it indicates that the target processor core has problems with poor heat dissipation or inadequate stability; or, if the frequency fluctuation value exceeds a second preset fluctuation value, it indicates that the target processor has problems with inadequate stability. In this case, the second stress test result is determined to be a failure, indicating that the target processor core may pose a risk of system crash under high concurrency and high load application scenarios. If the temperature difference is lower than the second preset temperature difference, and the frequency fluctuation value is lower than the second preset fluctuation value, it indicates that the target processor core does not have problems with poor heat dissipation or inadequate stability. In this case, the second stress test result is determined to be a success.

[0106] The processor core detection method provided in this invention performs a second stress test on top of a first stress test. This simulates real-world application scenarios, avoiding the inaccuracy of a single test in reflecting the processor core's actual operational capabilities and improving test reliability. Furthermore, it triggers hardware resource contention and intensifies extreme high-load testing conditions, preventing omissions of potential risks and hidden dangers due to single tests or insufficient test pressure, thus achieving comprehensive testing of the processor core. Moreover, the superposition of the first and second stress tests verifies the entire process of processor core operation, verifying the continuity and reliability of the entire processor core chain. Simultaneously, by analyzing the temperature differences and frequency fluctuations of each core in the target processor, the testing status of each core is analyzed from the overall perspective of the target processor. This allows for the determination of whether any cores in the target processor exhibit stability issues during the second stress test, thereby achieving comprehensive and in-depth detection of the processor core and improving the accuracy and reliability of processor core stability testing.

[0107] In one alternative implementation, in the above... Figure 3 or Figure 4 In the illustrated embodiment, the temperature difference can be calculated as follows: the difference between the maximum and minimum values ​​of the temperature information is taken as the temperature difference. The frequency fluctuation value can be calculated as follows: the difference between the maximum and minimum values ​​of the frequency information is calculated to obtain the frequency difference; the average value of the frequency information is calculated; the frequency difference is divided by the average value of the frequency information to obtain the frequency fluctuation value.

[0108] Figure 5This is a flowchart illustrating a specific embodiment of a processor core detection method provided by the present invention. The following is a schematic diagram of the process flow. Figure 5 Taking an example, the processor core detection method of the present invention will be further explained:

[0109] like Figure 5 As shown, the material information of the processor is maintained in the preset database. A material number is assigned to each processor, and the material number and attribute information of each processor are stored in the preset database, thereby associating the material number and attribute information of the processor in the preset database.

[0110] When testing processor cores, the first step is to check the number of cores, which involves the following steps: Execute the `lscpu` command ("lscpu | grep 'Core(s) per socket' | awk -F ':' '{print $2}'") to obtain the first core count; execute the `dmidecode` command ("dmidecode -t processor | grep 'Core Count' | awk –F : '{print $2}'") to obtain the second core count; execute the `dmidecode` command ("dmidecode -t processor | grep 'Core Enabled' | awk –F : '{print $2}'") to obtain the third core count. Compare the first, second, and third core counts to determine if they match. If they don't match, the core count test fails, an error is reported, and the test ends. If they match, the core count test passes, and the processor core stability is then checked.

[0111] When testing the stability of the processor core, the first stress test is performed. The first stress test tool, i.e., the ipt tool, is executed. Specifically, ". / ipt -p ipt.ini" is executed to generate the stress test configuration file. The first stress test is configured through the stress test configuration file, such as testing the instruction set of the processor, performing core binding operations, etc. After the configuration is completed, the first stress test begins. After the first stress test begins, the processor core temperature and frequency are captured every first preset time interval (5 minutes in this example). The temperature difference between the processor cores is calculated based on the captured temperature, and the frequency fluctuation value is calculated based on the captured frequency. It is then determined whether the temperature difference exceeds a first preset temperature (20°C in this example) and whether the frequency fluctuation value exceeds a first preset fluctuation value (8% in this example). If either the temperature difference or the frequency fluctuation value exceeds the first preset fluctuation value, the first stress test result is "test failed," an error is reported, and the test ends. Otherwise, the first stress test result is "test passed." The number of the first, second, and third cores is then acquired again to determine if the processor experienced core loss after the first stress test, and a second stress test is then performed.

[0112] During the second stress test, the second stress test tool, namely the IMT tool, is executed. This tool starts a corresponding number of threads based on the current number of processor cores and allocates a memory block to each processor for memory read / write tests. After the second stress test begins, the processor core temperature and frequency are captured every second preset time interval (5 minutes in this example). The temperature difference between the processor cores is calculated based on the captured temperature, and the frequency fluctuation value is calculated based on the captured frequency. It is then determined whether the temperature difference exceeds a second preset temperature (20°C in this example) and whether the frequency fluctuation value exceeds a second preset fluctuation value (8% in this example). If either the temperature difference or the frequency fluctuation value exceeds the second preset fluctuation value, the second stress test fails, an error is reported, and the test ends. Otherwise, the second stress test passes. The number of the first, second, and third cores is then retrieved again to determine if the processor experienced core loss during the second stress test, and the test ends.

[0113] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0114] On the other hand, embodiments of the present invention also provide a processor core detection device. Figure 6This is a schematic diagram of the structure of a processor core detection device provided in an embodiment of the present invention, as shown below. Figure 6 As shown, the processor core detection device includes:

[0115] The core count testing module 601 is used to read and detect the core count of the target processor based on multiple preset methods, and determine the core count test result of the target processor.

[0116] The first test result module 602 is used to determine the first stress test result of the target processor based on the first stress test of each core in the target processor if the core number test result is a pass test. The first stress test is a floating-point operation stress test of each core.

[0117] The second stress test module 603 is used to perform a second stress test on the high-speed interface in the target processor based on the first stress test if the first stress test result is a pass. The second stress test is a memory read and write stress test on each core.

[0118] The second test result module 604 is used to determine the second stress test result of the target processor based on the first stress test and the second stress test of the target processor.

[0119] In one optional implementation, the core quantity test module 601 includes:

[0120] The first core count unit is used to call the operating system to parse the information of the target processor and obtain the first core count;

[0121] The second core count unit is used to read the number of cores integrated in the target processor to obtain the second core count.

[0122] The third core count unit is used to detect the activation status of each core in the target processor and count the number of cores that are in the activation state to obtain the third core count.

[0123] The core count comparison unit is used to determine the core count test result as passed if the first core count, second core count, and third core count are consistent.

[0124] In one optional implementation, the first test result module 602 includes:

[0125] The computational stress testing unit is used to perform core binding operations on each core and to perform floating-point operation stress tests on each core.

[0126] The first information acquisition unit is used to acquire temperature and frequency information of each core at a first preset time interval during the floating-point operation stress test, and obtain a first temperature set and a first frequency set.

[0127] The first test result unit is used to determine the first pressure test result based on the first temperature set and the first frequency set.

[0128] In one optional implementation, the first test result unit includes:

[0129] The first test result subunit is used to determine the first pressure test result as a test failure if there is temperature information in the first temperature set that exceeds a preset temperature threshold.

[0130] In one optional implementation, the first test result unit includes:

[0131] The temperature difference calculation subunit is used to calculate the temperature difference corresponding to the first temperature set based on the maximum and minimum values ​​of the temperature information in the first temperature set if all temperature information in the first temperature set is lower than a preset temperature threshold.

[0132] The frequency fluctuation calculation subunit is used to calculate the frequency fluctuation value corresponding to the first frequency set based on the maximum and minimum values ​​of the frequency information in the first frequency set.

[0133] The first test result subunit is also used to determine the first pressure test result as a test failure if the temperature difference exceeds the first preset temperature difference or the frequency fluctuation value exceeds the first preset fluctuation value.

[0134] The first test result subunit is further configured to determine the first pressure test result as a test pass if the temperature difference is lower than the first preset temperature difference and the frequency fluctuation value is lower than the first preset fluctuation value.

[0135] In one alternative implementation, the second stress test module 603 includes:

[0136] The memory allocation unit is used to allocate memory to each core based on the initial stress test.

[0137] The read / write stress test unit is used to perform read / write stress tests on the memory corresponding to each core through a high-speed interface.

[0138] In one optional implementation, the second test result module 604 includes:

[0139] The second information acquisition unit is used to acquire temperature and frequency information of each core at intervals of a second preset time during the first pressure test and the second pressure test, so as to obtain a second temperature set and a second frequency set.

[0140] The second test result unit is used to determine the second stress test result of the target processor based on the second temperature set and the second frequency set.

[0141] In one optional implementation, the second test result unit includes:

[0142] The temperature difference calculation subunit is used to calculate the temperature difference corresponding to the second temperature set based on the maximum and minimum values ​​of the temperature information in the second temperature set;

[0143] The frequency fluctuation calculation subunit is used to calculate the frequency fluctuation value corresponding to the second frequency set based on the maximum and minimum values ​​of the frequency information in the second frequency set.

[0144] The second test result subunit is used to determine the second pressure test result as a test failure if the temperature difference exceeds the second preset temperature difference or the frequency fluctuation value exceeds the second preset fluctuation value.

[0145] The second test result subunit is also used to determine the second pressure test result as a pass if the temperature difference is lower than the second preset temperature difference and the frequency fluctuation value is lower than the second preset fluctuation value.

[0146] In one optional implementation, the temperature difference calculation subunit is used to take the difference between the maximum and minimum values ​​of the temperature information as the temperature difference;

[0147] The frequency fluctuation calculation subunit includes:

[0148] The frequency difference calculation submodule is used to calculate the difference between the maximum and minimum values ​​of frequency information to obtain the frequency difference;

[0149] The average value calculation submodule is used to calculate the average value of frequency information;

[0150] The frequency fluctuation calculation submodule is used to divide the frequency difference by the average value of the frequency information to obtain the frequency fluctuation value.

[0151] In one alternative implementation, it further includes:

[0152] The first attribute information module is used to search a preset database based on the identification information of the target processor to determine the first attribute information corresponding to the target processor. The preset database is used to store the correspondence between the identification information and attribute information of the processor.

[0153] The second attribute information module is used to obtain the second attribute information of the target processor in the operating system;

[0154] The attribute information comparison module is used to read and detect the number of cores of the target processor based on multiple preset methods if the second attribute information is consistent with the first attribute information, and to determine the test result of the number of cores of the target processor.

[0155] In one alternative implementation, it further includes:

[0156] The instruction invocation module is used to invoke the processor identification instruction to obtain the attribute information of the target processor;

[0157] The core count verification module is used to compare the core count in the attribute information with the core count of the target processor detected based on multiple preset methods in order to verify the core count of the target processor.

[0158] In one alternative implementation, it further includes:

[0159] The instruction set testing module is used to perform functional tests on each target instruction set for the target processor to determine the functional status of each target instruction set.

[0160] In an optional implementation, the core count testing module 601 is further configured to, if the first stress test result is a pass, and / or if the second stress test result is a pass, read and detect the core count of the target processor based on multiple preset methods to determine the core count test result.

[0161] For a description of the features in the embodiment corresponding to the processor core detection device, please refer to the relevant description in the embodiment corresponding to the processor core detection method, which will not be repeated here.

[0162] On the other hand, embodiments of the present invention also provide an electronic device, such as... Figure 7 As shown, it includes a memory 10 and a processor 20. The memory 10 stores a computer program, and the processor 20 is configured to run the computer program to perform the steps in any of the processor core detection method embodiments described above.

[0163] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the processor core detection method embodiments described above when running.

[0164] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0165] On the other hand, embodiments of the present invention also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the processor core detection method embodiments described above.

[0166] On the other hand, embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the processor core detection method embodiments described above.

[0167] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0168] The present invention has provided a detailed description of a processor core detection method, device, storage medium, and program product. Specific examples have been used to illustrate the principles and implementation methods of the invention. The descriptions of these embodiments are only intended to aid in understanding the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A method for detecting processor cores, characterized in that, include: The number of cores of the target processor is read and detected using multiple preset methods to determine the test result of the number of cores of the target processor. The step of reading and detecting the number of cores of the target processor based on multiple preset methods to determine the core count test result includes: calling the operating system to parse the information of the target processor to obtain a first core count; reading the number of cores integrated in the target processor to obtain a second core count; detecting the activation status of each core in the target processor and counting the number of cores in the activation state to obtain a third core count; if the first core count, the second core count, and the third core count are consistent, then the core count test result is determined to be a pass. If the core count test result is a pass, then based on the first stress test on each core in the target processor, the first stress test result of the target processor is determined, wherein the first stress test is a floating-point operation stress test on each core; If the first stress test result is a pass, then based on the first stress test, a second stress test is performed on the high-speed interface in the target processor, wherein the second stress test is a memory read and write stress test on each core. The second stress test result of the target processor is determined based on the first stress test and the second stress test of the target processor.

2. The processor core detection method according to claim 1, characterized in that, The determination of the first stress test result of the target processor based on the first stress test of each core in the target processor includes: Each core is subjected to a core-binding operation, and each core is subjected to a floating-point operation stress test. During the floating-point operation stress test, at a first preset time interval, the temperature information and frequency information of each core are obtained to obtain a first temperature set and a first frequency set. The first pressure test result is determined based on the first temperature set and the first frequency set.

3. The processor core detection method according to claim 2, characterized in that, Determining the first pressure test result based on the first temperature set and the first frequency set includes: If any temperature information in the first temperature set exceeds a preset temperature threshold, then the first pressure test result is determined to be a test failure.

4. The processor core detection method according to claim 2, characterized in that, Determining the first pressure test result based on the first temperature set and the first frequency set includes: If all temperature information in the first temperature set is lower than a preset temperature threshold, then the temperature difference corresponding to the first temperature set is calculated based on the maximum and minimum values ​​of the temperature information in the first temperature set. Based on the maximum and minimum values ​​of frequency information in the first frequency set, calculate the frequency fluctuation value corresponding to the first frequency set; If the temperature difference exceeds the first preset temperature difference, or if the frequency fluctuation value exceeds the first preset fluctuation value, then the first pressure test result is determined to be a test failure. If the temperature difference is lower than the first preset temperature difference, and the frequency fluctuation value is lower than the first preset fluctuation value, then the first pressure test result is determined to be a successful test.

5. The processor core detection method according to claim 1, characterized in that, The second stress test, based on the first stress test, is performed on the high-speed interface of the target processor, including: Based on the first stress test, memory is allocated to each of the cores; The high-speed interface is used to perform read / write stress tests on the memory corresponding to each core.

6. The processor core detection method according to claim 1, characterized in that, The step of determining the second stress test result of the target processor based on the first stress test and the second stress test of the target processor includes: During the first stress test and the second stress test, at a second preset time interval, the temperature information and frequency information of each core are acquired to obtain a second temperature set and a second frequency set. Based on the second temperature set and the second frequency set, the second stress test result of the target processor is determined.

7. The processor core detection method according to claim 6, characterized in that, The determination of the second stress test result of the target processor based on the second temperature set and the second frequency set includes: Based on the maximum and minimum values ​​of the temperature information in the second temperature set, calculate the temperature difference corresponding to the second temperature set; Based on the maximum and minimum values ​​of the frequency information in the second frequency set, calculate the frequency fluctuation value corresponding to the second frequency set; If the temperature difference exceeds the second preset temperature difference, or if the frequency fluctuation value exceeds the second preset fluctuation value, then the second pressure test result is determined to be a test failure. If the temperature difference is lower than the second preset temperature difference, and the frequency fluctuation value is lower than the second preset fluctuation value, then the second pressure test result is determined to be a successful test.

8. The processor core detection method according to claim 4 or 7, characterized in that, Based on the maximum and minimum values ​​of temperature information, calculate the temperature difference, including: The difference between the maximum and minimum values ​​of the temperature information is taken as the temperature difference; Based on the maximum and minimum values ​​of frequency information, calculate the frequency fluctuation value, including: The frequency difference is obtained by calculating the difference between the maximum and minimum values ​​of the frequency information. Calculate the average value of frequency information; Divide the frequency difference by the average value of the frequency information to obtain the frequency fluctuation value.

9. The processor core detection method according to claim 1, characterized in that, Also includes: Based on the identification information of the target processor, a search is performed in a preset database to determine the first attribute information corresponding to the target processor, wherein the preset database is used to store the correspondence between the processor's identification information and attribute information; Obtain the second attribute information of the target processor in the operating system; If the second attribute information is consistent with the first attribute information, then the number of cores of the target processor is read and detected based on multiple preset methods to determine the test result of the number of cores of the target processor.

10. The processor core detection method according to claim 1, characterized in that, Prior to performing the first stress test on each core in the target processor, the method further includes: Invoke the processor identification instruction to obtain the attribute information of the target processor; The number of cores in the attribute information is compared with the number of cores of the target processor detected based on multiple preset methods to verify the number of cores of the target processor.

11. The processor core detection method according to claim 1, characterized in that, Prior to performing the first stress test on each core in the target processor, the method further includes: For the target processor, functional tests are performed on each target instruction set to determine the functional status of each target instruction set.

12. The processor core detection method according to claim 1, characterized in that, If the first stress test result is a pass, and / or if the second stress test result is a pass, then the method further includes: The number of cores of the target processor is read and detected using multiple preset methods to determine the core count test result.

13. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the processor core detection method as described in any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the processor core detection method as described in any one of claims 1 to 12.

15. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the processor core detection method as described in any one of claims 1 to 12.

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