Multi-channel high-speed data acquisition system based on FPGA (Field Programmable Gate Array)
Through an FPGA-based multi-channel high-speed data acquisition system, utilizing the clock signal module and the parallel processing capabilities of the FPGA, we can achieve precise acquisition of picosecond ultrafast physical processes, solve the problem of signal distortion in traditional systems, and improve the accuracy of data and the credibility of experimental results.
Patent Information
- Application Number
- CN202510818304.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-18
- Publication Date
- 2025-09-30
AI Technical Summary
When faced with ultrafast physical processes of picoseconds and below, traditional data acquisition systems have insufficient sampling rates, resulting in signal distortion, inability to restore the true characteristics of the signal, and lack of parallel multi-channel data acquisition capabilities.
A multi-channel high-speed data acquisition system based on FPGA is used. The clock signal module generates multi-channel clock signals, and the parallel processing capability of FPGA is combined to perform multi-channel sampling. The smoothing algorithm of the host computer is used to correct the timing deviation to achieve accurate acquisition of picosecond ultrafast physical processes.
It achieves precise acquisition of picosecond-level ultrafast physical processes, obtains enough data points, solves the problem of signal distortion, improves data accuracy and the credibility of experimental results, and meets the multi-channel parallel acquisition requirements of complex physical experiments.
Smart Images
Figure CN120723716A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of data acquisition, and more particularly to a multi-channel high-speed data acquisition system based on FPGA. Background Art
[0002] Modern physics experiments, such as those in laser physics, nuclear physics, and plasma physics, often involve the detection and acquisition of signals from ultrafast physical processes. For example, the interaction of high-intensity lasers with media produces a series of new strong-field physical phenomena, such as above-threshold ionization, sequential and non-sequential double ionization, and the generation of high-order harmonics. The entire process takes approximately 50-100 femtoseconds. Similarly, in particle experiments, the rising edge of transient radiation signals generated by particle collisions is only 20 picoseconds.
[0003] However, traditional data acquisition systems typically use an MCU or ASIC as their core controller, with sampling rates often in the hundreds of MHz range. Traditional high-sampling-rate ADCs typically operate at GHz levels. Consequently, for events with picosecond durations or less, these systems can only capture single-digit data points. This leads to distortion of the sampled signal due to insufficient temporal resolution, making it impossible to restore the true characteristics of each signal. Furthermore, a single experiment often involves collecting data from different locations and physical quantities, requiring the data acquisition system to be capable of parallel multi-channel data acquisition.
[0004] Therefore, how to perform fast multi-channel data acquisition for ultrafast physical processes is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention
[0005] In view of this, the present invention provides a multi-channel high-speed data acquisition system based on FPGA to solve the above problems.
[0006] In order to achieve the above object, the present invention provides the following technical solutions:
[0007] The present invention discloses a multi-channel high-speed data acquisition system based on FPGA, comprising: a clock signal module, several sensor modules, several multi-channel FPGA data acquisition modules, a data transmission module, a storage module and a host computer;
[0008] The clock signal module provides a multi-channel clock signal to each of the multi-channel FPGA data acquisition modules according to the instruction of the host computer;
[0009] The sensor module is arranged at each physical quantity acquisition position, collects the analog signal of each physical quantity and transmits it to the corresponding multi-channel FPGA data acquisition module;
[0010] The multi-channel FPGA data acquisition module performs multi-channel sampling on the analog signal based on the multi-channel clock signal, and obtains a sensor digital signal after splicing the sampling signals of each channel, and transmits the sensor digital signal to the storage module by the data transmission module;
[0011] The host computer reads the digital signals of each sensor from the storage module and performs smoothing processing to obtain the final experimental results.
[0012] Furthermore, the clock signal module includes: a crystal oscillator unit, a clock frequency multiplication circuit, a clock buffer and driving unit, and a delay circuit;
[0013] The crystal oscillator unit generates a reference clock signal, which is multiplied by the clock multiplication circuit and then input into the clock buffer and driving unit;
[0014] The clock buffer and drive unit amplifies and buffers the input clock signal, and according to the instruction of the host computer, divides the amplified clock signal into n channels and outputs them to the corresponding delay circuit;
[0015] Each delay circuit delays the input clock signal by a set time length and then outputs the delayed clock signal to obtain the multi-channel clock signal.
[0016] Furthermore, the set time length is determined by the following formula:
[0017] t i =(i-1)*T / n;
[0018] Among them, t i represents the signal delay time length of the i-th channel, and T is the period of the clock signal after frequency multiplication.
[0019] Furthermore, the multi-channel FPGA data acquisition module includes n-channel signal sampling units and an FPGA processor; each signal sampling unit samples the input analog signal according to the clock signal of the corresponding channel and transmits the digital signal to the corresponding port of the FPGA processor;
[0020] The FPGA processor adds a channel identifier and a timing identifier to the data of each sampling point of each channel, and splices the data of each sampling point of each channel into a complete sensor digital signal in a timing order, and transmits it to the data transmission module through the data interface.
[0021] Furthermore, the signal sampling unit includes a signal conditioning circuit, an analog-to-digital converter and a register connected in sequence; the signal conditioning circuit performs impedance matching and signal amplification on the analog signal, and the analog-to-digital converter samples the amplified analog signal to obtain the digital signal, and the digital signal is first stored in the register and then transmitted to the FPGA processor.
[0022] Furthermore, the data transmission module includes: a plurality of parallel transmission interfaces, a plurality of data buffer units, a protocol conversion module and a high-speed serial transmission unit;
[0023] The parallel transmission interface corresponds to the data buffer unit one by one, and the number is consistent with the multi-channel FPGA data acquisition module, and is used to receive digital signals from various sensors;
[0024] The data buffer unit is used to cache the sensor digital signals received by each parallel transmission interface to avoid data loss during high-speed transmission;
[0025] The protocol conversion module converts the digital signals of each sensor into messages that comply with the serial communication protocol, and the messages are sent by the high-speed serial transmission unit to the storage module for storage.
[0026] Furthermore, each analog-to-digital converter performs sampling at the rising edge of the received clock signal, and the length of the signal line between each analog-to-digital converter and the clock signal module is the same.
[0027] Furthermore, for one channel of sensor digital signals, the smoothing process includes:
[0028] Step 1: Based on all sampling point data and corresponding time series identifiers, a scatter curve is fitted with time as the horizontal axis and amplitude as the vertical axis;
[0029] Step 2: Calculate the nearest horizontal distance between each sampling point of channel i and the fitting curve, and determine the timing identifier correction amount of channel i based on the average of all the nearest horizontal distances;
[0030] Step 3: Repeat step 2 to determine the timing identifier correction values of all channels and sort them; determine whether the absolute value of the largest timing identifier correction value is less than the set threshold. If it is less than the threshold, the current fitting curve is used as the experimental result of the sensor digital signal; otherwise, proceed to step 4;
[0031] Step 4: Correct the timing identifiers of all sampling points of the channel with the largest absolute value of the timing identifier correction amount, and return to step 1.
[0032] Through the above technical solutions, it can be seen that compared with the prior art, the present invention discloses a multi-channel high-speed data acquisition system based on FPGA. The clock signal module generates multi-channel clock signals through crystal oscillator frequency multiplication and delay circuit, and the interval between the clock signals of each channel is at the picosecond level. The sampling rate breaks through the limitation of the traditional MCU or ASIC at the hundred-MHz level through parallel design. With the help of the parallel processing capability of FPGA for data splicing, it can realize the precise acquisition of picosecond-level ultra-fast physical processes, and can obtain enough data points to restore the true characteristics of the signal, solving the signal distortion problem caused by insufficient time resolution of the traditional system. The smoothing algorithm of the host computer avoids the timing deviation during multi-channel acquisition by iteratively correcting the timing identifier, further improving the accuracy of the data and the credibility of the experimental results. The present invention realizes the synchronous acquisition of different positions and different physical quantities, meets the multi-channel parallel acquisition requirements of complex physical experiments, and provides strong support for ultra-fast process physical experiments. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0034] Figure 1 Schematic diagram of the overall structure of an embodiment of the present invention.
[0035] Figure 2 Schematic diagram of the clock signal module structure according to an embodiment of the present invention.
[0036] Figure 3 This is a structural diagram of a multi-channel FPGA data acquisition module according to an embodiment of the present invention. DETAILED DESCRIPTION
[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0038] The embodiment of the present invention discloses a multi-channel high-speed data acquisition system based on FPGA. Figure 1 As shown, it includes: a clock signal module, several sensor modules, several multi-channel FPGA data acquisition modules, a data transmission module, a storage module and a host computer;
[0039] The clock signal module provides multi-channel clock signals to each multi-channel FPGA data acquisition module according to the instructions of the host computer;
[0040] The sensor module is set at each physical quantity collection position to collect the analog signal of each physical quantity and transmit it to the corresponding multi-channel FPGA data acquisition module;
[0041] The multi-channel FPGA data acquisition module performs multi-channel sampling on the analog signal based on the multi-channel clock signal. After the sampling signals of each channel are spliced together, a sensor digital signal is obtained and transmitted to the storage module by the data transmission module;
[0042] The host computer reads the digital signals of each sensor from the storage module and performs smoothing processing to obtain the final experimental results.
[0043] In a specific embodiment, Figure 2 As shown, the clock signal module includes: a crystal oscillator unit, a clock multiplication circuit, a clock buffer and drive unit, and a delay circuit;
[0044] The crystal oscillator unit generates a reference clock signal, which is multiplied by the clock multiplication circuit and then input into the clock buffer and drive unit;
[0045] The clock buffer and drive unit amplifies and buffers the input clock signal, and according to the instructions of the host computer, divides the amplified clock signal into n channels and outputs it to the corresponding delay circuit;
[0046] Each delay circuit delays the input clock signal by a set time length and then outputs it to obtain a multi-channel clock signal.
[0047] Specifically, the crystal oscillator unit generates a reference clock signal. A high-stability quartz crystal or oven-controlled crystal oscillator can be used to ensure the clock signal's frequency accuracy and stability. For example, a 100MHz differential crystal oscillator can be used. The clock multiplication circuit multiplies the reference clock signal to meet the system's clock frequency requirements. For example, a 100MHz reference clock signal can be multiplied to 200MHz using a phase-locked loop (PLL). The clock buffer and driver unit uses a clock buffer chip (such as TI's SN74CB3Q3253) to amplify and buffer the clock signal, reducing signal attenuation and clock jitter, and ensuring synchronization of multiple channel clock signals. Each delay circuit applies time delays of equal length to the synchronized clock signals, further subdividing the n clock signals within a clock cycle. This overcomes the limitations of the ADC's original sampling rate and achieves a multiple increase in the equivalent sampling rate. For example, while the original sampling frequency only allows for the acquisition of two data points, increasing the number of channels to 50 allows for the acquisition of 100 data points, doubling the resolution.
[0048] In a specific embodiment, the set time length is determined by the following formula:
[0049] t i =(i-1)*T / n;
[0050] Among them, t i represents the signal delay time length of the i-th channel, and T is the period of the clock signal after frequency multiplication.
[0051] In a specific embodiment, Figure 3 As shown, the multi-channel FPGA data acquisition module includes n-channel signal sampling units and an FPGA processor; each signal sampling unit samples the input analog signal according to the clock signal of the corresponding channel and transmits the digital signal to the corresponding port of the FPGA processor;
[0052] The FPGA processor adds a channel identifier and a timing identifier to the data of each sampling point of each channel, and splices the data of each sampling point of each channel into a complete sensor digital signal in a timing order, and transmits it to the data transmission module through the data interface.
[0053] Specifically, the FPGA processor, as the core hub of digital signal processing, can add a 24-bit high-precision timestamp to each sampling point as the timing identifier of each sampling point, specifically the timestamp of the Nth clock cycle of the i-th channel for: Gray code is used to encode each channel as the channel identifier for each sampling point, for example, channel 1 → 0000, channel 2 → 0001, channel 3 → 0011, and channel 4 → 0010, to reduce the bit error rate. Ultimately, the data structure for each sampling point is: [frame header (8 bits) | timing identifier (24 bits) | channel identifier (12 bits) | data bits (16 bits)].
[0054] In a specific embodiment, the signal sampling unit includes a signal conditioning circuit, an analog-to-digital converter, and a register connected in sequence; the signal conditioning circuit performs impedance matching and signal amplification on the analog signal, and the analog-to-digital converter samples the amplified analog signal to obtain a digital signal. The digital signal is first stored in the register and then transmitted to the FPGA processor.
[0055] Specifically, the signal conditioning circuit consists of a buffer and an amplifier. The buffer eliminates impedance mismatches between the signal source and subsequent circuits, preventing signal distortion and energy loss due to reflections. The amplifier amplifies the sensor signal to minimize the signal-to-noise ratio (SNR) of the sampled data due to weak signals. The analog signal is then converted to a digital binary code using the analog-to-digital converter (ADC) and input into a register. The conversion rate of the ADC differs from the data processing capabilities of the FPGA processor. Using registers to temporarily store digital signals prevents data loss due to timing mismatches and balances the speed difference between the two.
[0056] In a specific embodiment, the data transmission module includes: a plurality of parallel transmission interfaces, a plurality of data buffer units, a protocol conversion module and a high-speed serial transmission unit;
[0057] The parallel transmission interface and data buffer unit correspond one to one, and the number is consistent with the multi-channel FPGA data acquisition module, which is used to receive digital signals from various sensors;
[0058] The data buffer unit is used to cache the sensor digital signals received by each parallel transmission interface to avoid data loss during high-speed transmission;
[0059] The protocol conversion module converts the digital signals of each sensor into messages that comply with the serial communication protocol, and sends them to the storage module for storage by the high-speed serial transmission unit, thereby realizing long-distance and fast transmission of multi-channel sensor signals.
[0060] In one specific embodiment, each ADC samples on the rising edge of the received clock signal, and the signal lines between each ADC and the clock signal module are of the same length. All ADCs trigger sampling based on the rising edge of the same clock signal, ensuring strict time alignment of multi-channel signals. This equal-length signal line design eliminates clock skew and ensures timing synchronization.
[0061] In a specific embodiment, for a sensor digital signal, the smoothing process includes:
[0062] Step 1: Based on all sampling point data and corresponding time series identifiers, a scatter curve is fitted with time as the horizontal axis and amplitude as the vertical axis;
[0063] Step 2: Calculate the nearest horizontal distance between each sampling point of channel i and the fitting curve, and determine the timing identifier correction amount of channel i based on the average of all the nearest horizontal distances;
[0064] Step 3: Repeat step 2 to determine the timing identifier correction values of all channels and sort them; determine whether the absolute value of the largest timing identifier correction value is less than the set threshold. If it is less than the threshold, the current fitting curve is used as the experimental result of the sensor digital signal; otherwise, proceed to step 4;
[0065] Step 4: Correct the timing identifiers of all sampling points of the channel with the largest absolute value of the timing identifier correction amount, and return to step 1.
[0066] Specifically, while clock skew is minimized through the design of equal-length signal lines, the sampling process is still affected by parasitic capacitance and temperature consistency, resulting in some deviation in timing synchronization. Therefore, in the host computer, the received digital signals from each sensor must be smoothed to eliminate inaccurate experimental results caused by clock skew. The smoothing algorithm further improves data acquisition accuracy through mathematical fitting and iterative correction.
[0067] A least-squares method is used to fit a theoretical curve to all sampling points. The fitted curve represents the ideal signal waveform without clock offset and provides a benchmark for subsequent timing error analysis. For each sampling point, a point with the same amplitude on the fitted curve is found, and the horizontal distance between the two points is used as the timing error at that point. The average of the horizontal distances across all sampling points reflects the overall timing offset direction (positive or negative) for that channel. The correction amount can be used to shift the channel's sampling points to the theoretical timing position. The threshold is typically set based on system accuracy requirements. When the absolute value of the maximum correction amount is less than the threshold, the timing deviation of each channel is considered to be within an acceptable range, and the current fitted curve is the final result. By setting the threshold appropriately, overfitting caused by excessive correction can be avoided. Through continuous iteration, the clock offset of multiple channels is corrected. The resulting fitted curve is smoother and more accurate than a curve directly fitted based on the sensor's digital signal, improving the accuracy of data acquisition results.
[0068] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.
[0069] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A multi-channel high-speed data acquisition system based on FPGA, characterized in that: include: Clock signal module, several sensor modules, several multi-channel FPGA data acquisition modules, data transmission module, storage module and host computer; The clock signal module provides a multi-channel clock signal to each of the multi-channel FPGA data acquisition modules according to the instruction of the host computer; The sensor module is arranged at each physical quantity acquisition position, collects the analog signal of each physical quantity and transmits it to the corresponding multi-channel FPGA data acquisition module; The multi-channel FPGA data acquisition module performs multi-channel sampling on the analog signal based on the multi-channel clock signal, and obtains a sensor digital signal after splicing the sampling signals of each channel, and transmits the sensor digital signal to the storage module by the data transmission module; The host computer reads the digital signals of each sensor from the storage module and performs smoothing processing to obtain the final experimental results.
2. The FPGA-based multi-channel high-speed data acquisition system according to claim 1, characterized in that: The clock signal module includes: a crystal oscillator unit, a clock frequency multiplication circuit, a clock buffer and drive unit, and a delay circuit; The crystal oscillator unit generates a reference clock signal, which is multiplied by the clock multiplication circuit and then input into the clock buffer and driving unit; The clock buffer and drive unit amplifies and buffers the input clock signal, and according to the instruction of the host computer, divides the amplified clock signal into n channels and outputs them to the corresponding delay circuit; Each delay circuit delays the input clock signal by a set time length and then outputs the delayed clock signal to obtain the multi-channel clock signal.
3. The FPGA-based multi-channel high-speed data acquisition system according to claim 2, characterized in that: The set time length is determined by the following formula: t i =(i-1)*T / n; Among them, t i represents the signal delay time length of the i-th channel, and T is the period of the clock signal after frequency multiplication.
4. The FPGA-based multi-channel high-speed data acquisition system according to claim 1, characterized in that: The multi-channel FPGA data acquisition module includes n-channel signal sampling units and an FPGA processor; each signal sampling unit samples the input analog signal according to the clock signal of the corresponding channel and transmits the digital signal to the corresponding port of the FPGA processor; The FPGA processor adds a channel identifier and a timing identifier to the data of each sampling point of each channel, and splices the data of each sampling point of each channel into a complete sensor digital signal in a timing order, and transmits it to the data transmission module through the data interface.
5. The FPGA-based multi-channel high-speed data acquisition system according to claim 4, characterized in that: The signal sampling unit includes a signal conditioning circuit, an analog-to-digital converter and a register connected in sequence; the signal conditioning circuit performs impedance matching and signal amplification on the analog signal, and the analog-to-digital converter samples the amplified analog signal to obtain the digital signal. The digital signal is first stored in the register and then transmitted to the FPGA processor.
6. The FPGA-based multi-channel high-speed data acquisition system according to claim 1, characterized in that: The data transmission module includes: a plurality of parallel transmission interfaces, a plurality of data buffer units, a protocol conversion module and a high-speed serial transmission unit; The parallel transmission interface corresponds to the data buffer unit one by one, and the number is consistent with the multi-channel FPGA data acquisition module, and is used to receive digital signals from various sensors; The data buffer unit is used to cache the sensor digital signals received by each parallel transmission interface to avoid data loss during high-speed transmission; The protocol conversion module converts the digital signals of each sensor into messages that comply with the serial communication protocol, and the messages are sent by the high-speed serial transmission unit to the storage module for storage.
7. The FPGA-based multi-channel high-speed data acquisition system according to claim 5, characterized in that: Each analog-to-digital converter samples at the rising edge of the received clock signal, and the length of the signal line between each analog-to-digital converter and the clock signal module is the same.
8. The FPGA-based multi-channel high-speed data acquisition system according to claim 4, characterized in that: For one sensor digital signal, the smoothing process includes: Step 1: Based on all sampling point data and corresponding time series identifiers, a scatter curve is fitted with time as the horizontal axis and amplitude as the vertical axis; Step 2: Calculate the nearest horizontal distance between each sampling point of channel i and the fitting curve, and determine the timing identifier correction amount of channel i based on the average of all the nearest horizontal distances; Step 3: Repeat step 2 to determine the timing identifier correction values of all channels and sort them; determine whether the absolute value of the largest timing identifier correction value is less than the set threshold. If it is less than the threshold, the current fitting curve is used as the experimental result of the sensor digital signal; otherwise, proceed to step 4; Step 4: Correct the timing identifiers of all sampling points of the channel with the largest absolute value of the timing identifier correction amount, and return to step 1.