RFSoC-based in-board synchronization method and device without digital function, acquisition board card and phased array radio telescope

Abstract

The invention relates to the technical field of synchronous processing, and discloses an RFSoC-based in-board synchronization method without a digital function, which is suitable for an acquisition board card comprising a plurality of data channels. Under the condition that the acquisition board card works normally, time delays of a plurality of data channels in the acquisition board card are initialized; performing time delay test on the plurality of data channels by using the synchronous pulse clock and the time delay synchronous clock to obtain the queue time delay of each data channel; under the condition that difference exists between the queue time delays of the data channels, synchronously correcting the queue time delays to obtain synchronous time delay boundaries of the plurality of data channels; and carrying out time delay synchronization optimization on the plurality of data channels based on the synchronization time delay boundary. The method has the beneficial effects that the queue time delay of each data channel in the acquisition board card is measured by using the clock signal, and the data channels are subjected to automatic synchronization optimization according to the queue time delay, so that the accuracy of internal synchronization of the board card is improved, and the data channels are ensured to be in a time delay synchronization state.

Description

Technical Field

[0001] The present application relates to the field of synchronization processing technology, and in particular to an intra-board synchronization method, device, acquisition board, and phased array radio telescope based on RFSoC without digital functions. Background Art

[0002] Phased array systems are an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array, enabling precise control of electromagnetic wave transmission and reception. With its rapid development, phased array systems have played an important role in a variety of fields, including radio astronomy, radar, ultrasonic imaging, and meteorological detection, and have broad application prospects. Typically, a phased array has multiple data channels. The degree of synchronization between these channels significantly affects the signal quality and even determines whether the phased array can function properly. Therefore, data channel synchronization is necessary to improve synchronization between these channels.

[0003] In related technologies, methods for synchronizing data channels often rely on the operator's experience, and manual operation also brings uncertainty. The accuracy of related solutions still needs to be improved. Summary of the Invention

[0004] The present application provides an intra-board synchronization method, device, acquisition board, and phased array radio telescope without digital functions based on RFSoC. The method uses a clock signal to measure the queue delay of each data channel in the acquisition board, and automatically optimizes the synchronization of the data channels based on the queue delay, thereby improving the accuracy of the internal synchronization of the board and ensuring that the data channels are in a delay synchronization state.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include: In a first aspect, an embodiment of the present application provides an intra-board synchronization method without digital functions based on RFSoC, applicable to an acquisition board including multiple data channels; the method comprises: When the acquisition board is operating normally, initializing the delays of the plurality of data channels in the acquisition board; Performing a delay test on the plurality of data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay of each data channel; When there is a difference between the queue delays of each of the data channels, synchronously correcting the queue delays to obtain synchronization delay boundaries of the plurality of data channels; Delay synchronization optimization is performed on the plurality of data channels based on the synchronization delay boundary, so that the plurality of data channels can achieve synchronous signal acquisition.

[0006] The embodiment of the present application proposes an intra-board synchronization method based on RFSoC without digital functions. Under the premise of initializing the delay of several data channels, the synchronization pulse clock and the delay synchronization clock are used to obtain the queue delay of each data channel, and synchronization correction is performed according to the difference between the queue delays to determine the synchronization delay boundary, thereby automatically optimizing the delay synchronization of the data channel according to the synchronization delay boundary, ensuring that the data channels are in a delay synchronization state. Compared with the related art, the present application uses clock signals to test the delay of the data channel, which improves the accuracy and feasibility of the queue delay test results; on this basis, the present application also performs synchronization correction on the queue delay based on the difference between the queue delays to obtain the synchronization delay boundary for optimizing the delay synchronization of the data channel, so that the data channel can use the synchronization delay boundary as a benchmark to realize synchronization signal acquisition, improve the accuracy of the synchronization benchmark between the data channels, and significantly improve the synchronization between the data channels.

[0007] Optionally, performing delay tests on the plurality of data channels using the synchronous pulse clock and the delayed synchronous clock to obtain a queue delay for each data channel includes: Performing clock calibration on the plurality of data channels according to the synchronous pulse clock to obtain a delay test clock; Determining a measurement start time according to the delay synchronization clock; Delay measurement is performed on any data channel among the plurality of data channels according to the delay test clock and the measurement start time to obtain the queue delay of the any data channel.

[0008] Optionally, the synchronous pulse clock is a periodic signal that is output continuously, and the clock calibration is performed after a process in which the synchronous pulse clock is received by the plurality of data channels satisfies a preset capture condition.

[0009] Optionally, the synchronously correcting the queue delay to obtain synchronization delay boundaries of the plurality of data channels includes: Performing delay boundary screening on the queue delay, and taking the queue delay that meets the preset delay boundary condition as the optimized delay boundary; Redundant delay compensation is performed on the optimized delay boundary to obtain the synchronous delay boundary.

[0010] Optionally, the preset delay boundary condition is that the queue delay is the maximum value of all queue delays.

[0011] Optionally, the performing delay synchronization optimization on the plurality of data channels based on the synchronization delay boundary includes: The time-delay synchronization clock is used as a reference clock, and the synchronization delay boundary is synchronously configured to the plurality of data channels, so that the plurality of data channels start synchronous collection after the synchronization delay boundary.

[0012] Optionally, determine whether the acquisition board is working properly by the following method: Performing a status check on the acquisition board; Based on the result of the status check, it is determined whether the acquisition board is operating normally.

[0013] In a second aspect, an embodiment of the present application provides an intra-board synchronization device without digital functions based on RFSoC, which is applicable to an acquisition board card including multiple data channels; the device includes: A self-check initialization module is used to initialize the delays of the plurality of data channels in the acquisition board when the acquisition board is working normally; A delay test module is used to perform a delay test on the plurality of data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay of each data channel; a synchronization correction module, configured to perform synchronization correction on the queue delays of the data channels when there are differences between the queue delays of the data channels, so as to obtain synchronization delay boundaries of the data channels; The delay optimization module is used to perform delay synchronization optimization on the multiple data channels based on the synchronization delay boundary, so that the multiple data channels can achieve synchronous signal acquisition.

[0014] In a third aspect, an embodiment of the present application provides an acquisition board without digital functions based on RFSoC, which performs intra-board synchronization through the method described in any one of the above embodiments.

[0015] In a fourth aspect, an embodiment of the present application provides a phased array radio telescope, comprising an acquisition board according to any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 The embodiment of the present application provides a step diagram of the on-board synchronization method without digital functions based on RFSoC Figure 2 This is a step diagram of the delay test in an embodiment of the present application; Figure 3 This is a diagram showing the steps for synchronously correcting queue delay in an embodiment of the present application; Figure 4 This is a diagram showing the steps for determining whether the acquisition board is working properly in an embodiment of the present application; Figure 5 A module diagram of an intra-board synchronization device without digital functions based on RFSoC provided in an embodiment of the present application; Figure 6 This is a clock tree structure diagram of an acquisition board without digital functions based on RFSoC in an embodiment of the present application; Figure 7 A schematic structural diagram of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0018] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts shall fall within the scope of protection of this application.

[0019] Phased array systems are an advanced technology that precisely controls the phase and amplitude of multiple antenna elements in an array, enabling precise control of electromagnetic wave transmission and reception. With its rapid development, phased array systems have played an important role in a variety of fields, including radio astronomy, radar, ultrasonic imaging, and meteorological detection, and have broad application prospects. Typically, a phased array has multiple data channels. The degree of synchronization between these channels significantly affects the signal quality and even determines whether the phased array can function properly. Therefore, data channel synchronization is necessary to improve synchronization between these channels.

[0020] In the related art, methods for intra-board synchronization of multiple channels in an acquisition board include fixed delay compensation and manual delay setting. The fixed delay compensation method sets the same delay compensation value for each data channel so that the data channels can achieve synchronous signal acquisition. However, in actual situations, the fixed delay compensation value cannot adapt to timing changes caused by environmental changes during the signal acquisition process. The manual delay setting method manually measures the delay value of each data channel and performs delay compensation on each data channel based on the measurement results to ensure that the delay value of each data channel is the same. However, the process of manually measuring the delay value is limited by the operator's experience and cannot ensure the consistency of the measurement results. Therefore, there are still uncertainties in the related art, and the accuracy of its intra-board synchronization of multiple data channels on the acquisition board still needs to be improved.

[0021] Based on the above problems, the present application provides an intra-board synchronization method without digital functions based on RFSoC, which is suitable for an acquisition board containing several data channels; when the acquisition board is working normally, the delay of several data channels in the acquisition board is initialized; the delay of several data channels is tested using a synchronous pulse clock and a delay synchronization clock to obtain the queue delay of each data channel; when there are differences between the queue delays of each data channel, the queue delay is synchronously corrected to obtain the synchronization delay boundaries of several data channels; based on the synchronization delay boundaries, the delay synchronization of several data channels is optimized, so that several data channels can achieve synchronous signal acquisition.

[0022] The intra-board synchronization method without digital functions based on RFSoC provided in the present application, on the premise of delay initialization of several data channels, uses the synchronization pulse clock and the delay synchronization clock to obtain the queue delay of each data channel, and performs synchronization correction according to the difference between the delays of each queue, determines the synchronization delay boundary, and automatically optimizes the delay synchronization of the data channel according to the synchronization delay boundary, ensuring that the data channels are in a delay synchronization state.

[0023] Compared with related technologies, the present application uses clock signals to perform delay tests on data channels, thereby improving the accuracy and feasibility of queue delay test results. On this basis, the present application also performs synchronous correction on queue delays based on the differences between queue delays to obtain a synchronous delay boundary for delay synchronization optimization of data channels, so that data channels can use the synchronous delay boundary as a benchmark to achieve synchronous signal acquisition, thereby improving the accuracy of the synchronization benchmark between data channels and significantly improving the synchronization between data channels.

[0024] The RFSoC-based intra-board synchronization method without digital functionality provided in this specification can be applied to any acquisition board within a phased array system. Phased array systems are used in a variety of fields, including radio astronomy, radar, ultrasonic imaging, and meteorological detection. In radio astronomy, phased array systems can be used to construct phased array radio telescopes, enabling high-speed, real-time, and synchronous acquisition and preprocessing of large-scale, wide-band RF signals. It should be noted that this acquisition board does not include digital functionality, meaning that no digital signal processing is performed on the acquired signals.

[0025] According to an embodiment of the present application, an embodiment of an intra-board synchronization method without digital functions based on RFSoC is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0026] In this embodiment, a method for in-board synchronization without digital functions based on RFSoC is provided, which can be used for the above-mentioned acquisition board. Figure 1 As shown, the method is applicable to an acquisition board including several data channels; the method includes: S100. When the acquisition board is operating normally, initialize the delays of several data channels in the acquisition board.

[0027] S200. Perform delay tests on several data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay for each data channel.

[0028] S300 . When there is a difference between the queue delays of each data channel, perform synchronous correction on the queue delays to obtain synchronous delay boundaries of several data channels.

[0029] S400. Perform delay synchronization optimization on a plurality of data channels based on the synchronization delay boundary, so that the plurality of data channels can achieve synchronous signal acquisition.

[0030] The synchronization pulse clock can be a clock reference signal used during latency testing, setting a delay measurement starting point for multiple data channels, enabling each data channel to measure its own queue latency based on the same clock signal. For example, the synchronization pulse clock can be the low-frequency reference clock signal AMS_SYSREF generated and output by the clock chip on the acquisition board. Its frequency can be 10 MHz, and it is used to synchronize the RFDC IP core with other modules on the acquisition board.

[0031] The delay synchronization clock can be a trigger reference signal during delay testing, providing a delay measurement observation window for multiple data channels. This allows each data channel to measure its own queue delay within the same timeframe, thus enabling synchronization correction and delay synchronization optimization. For example, the delay synchronization clock can be the low-frequency reference clock signal PL_SYSREF, generated and output by the clock chip on the acquisition board. Its frequency can be 10 MHz and is used to control and synchronize logical operations within the programmable logic devices on the acquisition board.

[0032] Queue latency is the delay between signal data entering a First In First Out (FIFO) queue and being read out of it. It represents the time delay between signal acquisition and output for each of the multiple channels. As you can see, after signal data is acquired by a data channel, it is first stored in an independent FIFO buffer and then read out sequentially based on the order in which it entered the FIFO buffer for subsequent signal processing.

[0033] The synchronization delay boundary can be a common channel delay setting across all data channels. This allows for synchronized signal acquisition and output across all data channels, even when queue delays vary, minimizing timing misalignment between data channels. It should be understood that the synchronization delay boundary is designed to exceed the queue delay of any data channel to ensure synchronization between data channels is not affected by queue delay differences.

[0034] Specifically, for the acquisition board that needs to be synchronized within the board, first enable the synchronous sampling clock, synchronous pulse clock and delay synchronization clock in the acquisition board, wherein the synchronous sampling clock is used as the reference clock for each data channel in the signal acquisition process, so that all data channels can perform synchronous signal acquisition and reduce the timing error introduced in the signal acquisition process. Secondly, determine whether the acquisition board is working properly, ensure that the initial states of multiple modules and data channels on the acquisition board are stable, and that there is no fault in the acquisition board, and the synchronization process can be started between the data channels. When it is determined that the acquisition board is working properly, initialize the delay settings of each data channel in the acquisition board to ensure that the initial delay of each data channel is the same before the delay test is performed, thereby improving the accuracy of the delay test and thereby improving the accuracy of the intra-board synchronization. Exemplarily, the delay initialization process can be implemented by calling an API function. For Xilinx's RFDC IP core, the API function called can be XRFdc_MultiConverter_Sync.

[0035] Furthermore, the synchronous pulse clock and the delayed synchronous clock are used as the reference clocks of each data channel to perform clock alignment for the delay test, thereby ensuring the timing consistency of the delay test process, thereby improving the accuracy of the resulting queue delay. After the clocks are aligned, a delay test instruction is issued to each data channel to control each data channel to enter the automatic delay test mode, and obtain the queue delay of each data channel. It should be noted that in the automatic delay test mode, multiple data channels start delay testing at the same time, reducing the timing error that may occur when each data channel performs delay testing separately. Moreover, each data channel automatically performs delay testing without the need for manual intervention by the operator, reducing the impact of the operator's experience on the delay test results, and improving the efficiency and accuracy of the delay test. For example, the method of issuing the delay test instruction can be to set the initial delay for each data channel. For Xilinx's RFDC IP core, this method can be to set the Target_latency of each data channel to -1 to start the automatic delay test mode of each data channel.

[0036] Furthermore, after obtaining the queue delay of each data channel, all queue delays are compared to determine whether the queue delay needs to be synchronized. If the time lengths of all queue delays are consistent, or the differences between queue delays are within a tolerable range, it means that each data channel is already in a delay synchronization state and no further synchronization correction is required. If there are differences between the queue delays of each data channel, it means that each data channel is in a delay-asynchronous state. In this case, it is necessary to synchronize the queue delay according to the time length distribution of the queue delay to determine the synchronization delay boundary used for delay synchronization optimization of all data channels, ensuring that the synchronization of the data channel output signal is not affected by the queue delay difference.

[0037] Furthermore, based on the synchronization delay boundary, data channels are optimized for delay synchronization. The channel delay of all data channels is set to the synchronization delay boundary, so that the signal data in each data channel is output after the synchronization delay boundary. It can be understood that the duration of the synchronization delay boundary exceeds the queue delay of any data channel. After the synchronization delay boundary, the signal data of all channels has been read from the FIFO buffer and is ready for output. On this basis, using the synchronization pulse clock as the reference clock, all data channels output signal data simultaneously, achieving synchronized output between the collected signals.

[0038] It's understandable that for the same acquisition board, using the same logic file and clock system, the queue delay of each data channel is relatively stable and doesn't fluctuate significantly. Therefore, once the synchronization delay boundary for the acquisition board is determined, the same synchronization delay boundary can be used for signal acquisition at different time points on the acquisition board. By directly configuring the synchronization delay boundary, resources consumed during the on-board synchronization process are reduced, improving signal acquisition efficiency.

[0039] The intra-board synchronization method without digital functions based on RFSoC provided in this embodiment, on the premise of delay initialization of several data channels, uses a synchronous pulse clock and a delay synchronization clock to obtain the queue delay of each data channel, and performs synchronization correction based on the difference between the queue delays to determine the synchronization delay boundary, thereby automatically optimizing the delay synchronization of the data channels based on the synchronization delay boundary to ensure that the data channels are in a delay synchronization state.

[0040] Compared with related technologies, the present application uses clock signals to perform delay tests on data channels, thereby improving the accuracy and feasibility of queue delay test results. On this basis, the present application also performs synchronous correction on queue delays based on the differences between queue delays to obtain a synchronous delay boundary for delay synchronization optimization of data channels, so that data channels can use the synchronous delay boundary as a benchmark to achieve synchronous signal acquisition, thereby improving the accuracy of the synchronization benchmark between data channels and significantly improving the synchronization between data channels.

[0041] Reference Figure 2 As shown, as an embodiment of the present application, a delay test is performed on several data channels using a synchronous pulse clock and a delayed synchronous clock to obtain the queue delay of each data channel, including: S210. Perform clock calibration on several data channels according to the synchronous pulse clock to obtain a delay test clock.

[0042] S220. Determine the measurement start time according to the delay synchronization clock.

[0043] S230. Perform delay measurement on any data channel among the plurality of data channels according to the delay test clock and the measurement start time to obtain the queue delay of any data channel.

[0044] The clock frequencies of the synchronous pulse clock and the delayed synchronous clock are the same, and the phase difference between the two is constant.

[0045] Specifically, each data channel receives a synchronous pulse clock and a delay synchronous clock respectively. The data channel uses the synchronous pulse clock as its own clock reference signal and aligns its own clock to the synchronous pulse clock to obtain a common delay test clock for all data channels. It is understandable that when the delay test clock is used to perform a delay test, the starting time point of the measurement operation is determined according to the rising edge of each cycle in the synchronous pulse clock. Based on the delay test clock, each data channel can synchronously measure the queue delay according to the same clock signal, effectively improving the synchronization between the data channels during the delay test. In addition, the synchronous pulse clock can be stably captured by the data channel, and its stability further improves the synchronization of the data channel in the delay test.

[0046] Furthermore, the programmable logic area corresponding to the data channel is clock-aligned based on the delay synchronization clock, and the clock in the programmable logic area is aligned with the delay synchronization clock, so that the programmable logic area issues instructions about the delay test based on the delay synchronization clock to actually execute the delay test process. On this basis, the starting time point of the measurement operation is determined according to the rising edge in each cycle of the delay synchronization clock as the measurement start time. It should be noted that since the clock frequencies of the synchronous pulse clock and the delay synchronization clock are the same, the measurement start time corresponds to the rising edge in the synchronous pulse clock, so that the delay test process can be synchronized with the delay test clock, thereby performing delay testing with the same clock reference signal, thereby improving the synchronization of the data channel in the delay test.

[0047] Furthermore, based on the measurement start time, a delay measurement instruction is issued through the programmable logic area within the data channel. Using the rising edge of the delay test clock as the measurement reference point, the delay of each data channel is measured, resulting in the queue delay of each data channel. As can be understood, under the premise of the same delay test clock, the measurement start time of each data channel is the same, allowing each data channel to start the delay test simultaneously, reducing the impact of timing errors on the delay test results during the delay test process and improving the accuracy of the queue delay.

[0048] As an embodiment of the present application, the synchronous pulse clock is a periodic signal that is continuously output, and the clock calibration is performed after the synchronous pulse clock is received by several data channels and meets a preset capture condition.

[0049] Specifically, when enabling the required clock signal on the acquisition board, it's important to ensure the sync pulse clock is in a periodic, continuous output state. This improves its clock stability, thereby enhancing the timing synchronization between data channels when using the sync pulse clock as the reference clock signal. Furthermore, the periodicity of the sync pulse clock allows for repeated latency testing, improving the accuracy of latency test results.

[0050] Furthermore, the preset capture condition can be that the data channel can stably capture the synchronization pulse clock, the captured synchronization pulse clock has no or minimal clock jitter, the rising edge position of the synchronization pulse clock is predictable, and the periodicity between adjacent rising edges is met. Whether the synchronization pulse clock is received by multiple data channels satisfies the preset capture condition can be determined by a synchronization state machine within the data channel. If the preset capture condition is not met, clock calibration is not performed until the preset capture condition is met.

[0051] It should be noted that before being received by a data channel, the synchronization pulse clock passes through a path that includes the clock source and multiple other modules. These modules may experience timing errors when outputting the synchronization pulse clock due to internal or environmental factors, resulting in reduced synchronization pulse clock stability. By determining whether the synchronization pulse clock meets preset capture conditions during reception by multiple data channels, the stability of the synchronization pulse clock used for clock calibration can be ensured, reducing the uncertainty caused by unstable clock signals on intra-board synchronization, and thereby improving the synchronization between data channels after intra-board synchronization.

[0052] Reference Figure 3 As shown, as an embodiment of the present application, the queue delay is synchronously corrected to obtain the synchronization delay boundaries of several data channels, including: S310. Perform delay boundary screening on the queue delay, and use the queue delay that meets the preset delay boundary condition as the optimized delay boundary.

[0053] S320. Perform redundant delay compensation on the optimized delay boundary to obtain a synchronous delay boundary.

[0054] Specifically, the queue delay of each data channel is compared with a preset delay boundary condition. The queue delay that meets the preset delay boundary condition is selected from multiple queue delays to serve as the optimized delay boundary. For example, the preset delay boundary condition can be the maximum, minimum, average, or median value of the queue delays, and can be determined based on actual scenario needs.

[0055] Furthermore, to improve the reliability of the optimized delay boundary, redundant delay compensation is performed on top of the optimized delay boundary, ensuring that all queue delays are within the synchronization delay boundary, ensuring that the synchronization of data channel output signals is not affected by queue delay differences. For example, when the preset delay boundary condition is the maximum value of the queue delays, redundant delay compensation can be performed by adding a delay of multiple clock cycles to the optimized delay boundary, where the number of clock cycles can be 16.

[0056] As an embodiment of the present application, the preset delay boundary condition is that the queue delay is the maximum value of all queue delays.

[0057] Specifically, when the optimized delay boundary is the maximum value of the queue delay, after passing the synchronization delay boundary, the signal data of all data channels have been read out of the FIFO buffer and are in a state ready for output, thereby ensuring that all data channels can output signal data synchronously, avoiding the situation where data channels with large queue delays and small queue delays cannot be output synchronously, and reducing the probability of data loss or data inconsistency.

[0058] It can be understood that using the maximum value of all queue delays as the preset delay boundary condition can ensure that when the queue delay of any data channel is too large compared to other data channels, all data channels can still output signal data synchronously, thereby improving the stability of the synchronization results within the board.

[0059] As an embodiment of the present application, delay synchronization optimization is performed on multiple data channels based on a synchronization delay boundary, including: S410. Using the delayed synchronization clock as a reference clock, synchronously configuring the synchronization delay boundary to a plurality of data channels, so that the plurality of data channels start synchronous acquisition after the synchronization delay boundary.

[0060] Specifically, the delay synchronization clock serves as the reference clock signal for the programmable logic area in the data channel, ensuring that synchronization operations on each data channel are performed simultaneously. By synchronously configuring the synchronization delay boundary for each data channel, timing errors caused by the configuration lag of any data channel during the signal acquisition process are avoided. At the same time, clock drift and synchronization errors between data channels are reduced, effectively improving the stability of multiple data channels in the acquisition board during the synchronous signal acquisition process. For example, for Xilinx's RFDC IP core, the method for setting the synchronization delay boundary can be to call an API function, and the API function called in this case can be XRFdc_MultiConverter_Sync.

[0061] Reference Figure 4 As shown, as an embodiment of the present application, the following method is used to determine whether the acquisition board is working properly: S110. Check the status of the acquisition board.

[0062] S120. Determine whether the acquisition board is working normally based on the result of the status check.

[0063] Specifically, the status check includes a module enable status check, a phase-locked status check, a power-on status check, and a channel enable status check. The enable status check can be an enable status check of any module on the acquisition board to determine whether the module has been enabled. The phase-locked status check can be a status check of the phase-locked loop on the acquisition board to determine whether the phase-locked loop is in a phase-locked state or a normal working state, thereby ensuring the stability of multiple clock signals in the acquisition board through the phase-locked loop. The power-on status check can be a power-on status check of any module on the acquisition board to determine whether the module has been powered on and is in a normal working state. The channel enable status check can be an enable status check of any data channel on the acquisition board to determine whether each data channel has been enabled, ensuring that each data channel can participate in the synchronization operation during the on-board synchronization process.

[0064] Furthermore, the status check process includes: performing a module enable status check on the acquisition board to obtain the module enable status of the acquisition board; when the module enable mode meets the preset module enable mode requirement, performing a phase lock status check on the acquisition board to obtain the phase lock status of the acquisition board; when the phase lock mode meets the preset phase lock mode requirement, performing a power-on status check on the acquisition board to obtain the power-on status of the acquisition board; when the power-on mode meets the preset power-on mode requirement, performing a channel enable status check on the acquisition board to obtain the channel enable status of the acquisition board; when the channel enable mode meets the preset channel enable mode requirement, determining that the acquisition board can work normally.

[0065] Accordingly, please refer to Figure 5 The present invention provides an intra-board synchronization device without digital functions based on RFSoC, which is applicable to an acquisition board containing multiple data channels; the device includes: The self-check initialization module 510 is used to initialize the delays of several data channels in the acquisition board when the acquisition board is operating normally.

[0066] The delay test module 520 is used to perform delay tests on a number of data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay for each data channel.

[0067] The synchronization correction module 530 is used to perform synchronization correction on the queue delay when there is a difference between the queue delays of each data channel, so as to obtain synchronization delay boundaries of several data channels.

[0068] The delay optimization module 540 is used to perform delay synchronization optimization on a plurality of data channels based on the synchronization delay boundary, so that the plurality of data channels can achieve synchronous signal acquisition.

[0069] In some optional implementations, the delay testing module 520 includes: The clock calibration unit is used to perform clock calibration on several data channels according to the synchronous pulse clock to obtain a delay test clock.

[0070] The time determination unit is used to determine the measurement start time according to the delay synchronization clock.

[0071] The delay measurement unit is used to measure the delay of any data channel among the multiple data channels according to the delay test clock and the measurement start time, so as to obtain the queue delay of any data channel.

[0072] In some optional implementations, in the delay test module 520 , the synchronous pulse clock is a continuously output periodic signal, and clock calibration is performed after the synchronous pulse clock is received by several data channels and a preset capture condition is satisfied.

[0073] In some optional implementations, the synchronization correction module 530 includes: The delay boundary screening unit is used to perform delay boundary screening on the queue delay and take the queue delay that meets the preset delay boundary condition as the optimized delay boundary.

[0074] The redundant delay compensation unit is used to perform redundant delay compensation on the optimized delay boundary to obtain a synchronous delay boundary.

[0075] In some optional implementations, in the synchronization correction module 530 , the preset delay boundary condition is that the queue delay is the maximum value among all queue delays.

[0076] In some optional implementations, the delay optimization module 540 includes: The synchronization configuration unit is used to use the delayed synchronization clock as a reference clock and synchronize the synchronization delay boundary to multiple data channels, so that the multiple data channels start synchronous collection after the synchronization delay boundary.

[0077] In some optional implementations, the self-test initialization module 510 includes: The board status checking unit is used to check the status of the acquisition board.

[0078] The working status judgment unit is used to judge whether the acquisition board is working normally based on the result of the status check.

[0079] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0080] The intra-board synchronization device without digital functions based on RFSoC in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0081] An embodiment of the present application provides an acquisition board without digital functions based on RFSoC, which performs intra-board synchronization using any of the methods described in the above embodiments.

[0082] Reference Figure 6 As shown, the acquisition board provided in this embodiment is designed with a synchronous clock tree based on a single clock chip. The synchronous clock tree includes a clock chip, a PL MMCM divider, a radio frequency clock chip and an RFDC IP core. The RFDC IP core contains multiple data channels, represented by ADC Tiles. All data channels operate in the same working mode and are configured with the same working parameters. Among them, the clock chip serves as the basis of the synchronous clock tree, is used to generate a homologous clock signal, and sends it to multiple modules on the acquisition board, providing a synchronous clock basis for each of the multiple modules. It can be understood that a single clock chip outputs a clock signal in a unified manner, reduces the clock drift and error between multiple clock signals, and improves the timing consistency between clock signals. In addition, the single clock chip also simplifies the hardware design on the acquisition board, reduces the complexity of the module, and improves the hardware stability and ease of use of the acquisition board.

[0083] The PL MMCM divider is used to divide the clock signal output by the clock chip to generate the ADC parallel data output clock AXIS_clock and the back-end signal processing clock USER_clock to control the output and processing of the acquisition signal and ensure the synchronization between different acquisition signals in the above process. The PL MMCM divider also includes clock frequency conversion, clock phase control, clock division and multiplication, and clock synchronization. It can be understood that the acquisition signal is synchronously output to the RFSoCFPGA processing chip on the acquisition board to perform synchronous signal processing on the acquisition signal. For example, the frequency of the ADC parallel data output clock AXIS_clock can be 250MHz, and the frequency of the back-end signal processing clock USER_clock can be 350MHz.

[0084] The RF clock chip is used to receive the clock signal sent by the clock chip, obtain the synchronous sampling clock based on the clock signal and send it synchronously to the RFDC IP core, providing the data channel with a synchronous clock basis during the signal acquisition process, so that the data channel can perform synchronous signal acquisition. After receiving the clock signal sent by the clock chip, the RF clock chip performs a clock operation on the clock signal to obtain a synchronous sampling clock for sending to the RFDC IP core. When the frequency of the synchronous sampling clock is outside the clock frequency range corresponding to the clock chip, the clock chip cannot directly generate a synchronous sampling clock for the RFDC IP core. It is necessary to perform a clock operation on the clock signal through the RF clock chip to generate a synchronous sampling clock that meets actual needs. For example, the clock operation can be clock multiplication or clock phase adjustment.

[0085] The RFDC IP core receives synchronous acquisition signals from the RF clock chip and internally distributes the synchronous sampling clock to multiple data channels, enabling all data channels to perform synchronous signal acquisition based on the synchronous sampling clock. A data channel can be an analog-to-digital converter (ADC) channel, which converts the analog signal obtained through signal acquisition into a digital signal for further processing and analysis.

[0086] In some embodiments, the RFDC IP core may have only a single input, which can be the input of the first of multiple data channels. After receiving an external input signal, the first channel distributes the input signal to other data channels within the RFDC IP core to operate according to the input signal. It is understood that at this time, the first channel serves as the reference channel for all data channels and is active during subsequent synchronization processing and synchronous acquisition. The other data channels are synchronized with the first channel, effectively improving the synchronization between data channels. In addition, the single input also reduces the hardware resources required to set up the RFDC IP core, reduces the complexity of the module connection design on the acquisition board, and improves the integration of the acquisition board.

[0087] Between the above modules, the output of the clock chip is connected to the input of the RF clock chip. The output of the RF clock chip and the output of the clock chip are respectively connected to the input of the RFDC IP core. The input of the PL MMCM divider is connected to the output of the clock chip. Based on the connection with the RF clock chip, the RFDC IP core receives the synchronous sampling clock from the RF clock chip. Based on the connection with the clock chip, it receives the synchronous pulse clock AMS_SYSREF and the delayed synchronous clock PL_SYSREF from the clock chip. For example, the frequency of the synchronous sampling clock can be 4 GHz, the frequency of the synchronous pulse clock AMS_SYSREF can be 10 MHz, and the frequency of the delayed synchronous clock PL_SYSREF can be 10 MHz.

[0088] Before the data channels begin synchronous signal acquisition, the RFDC IP core receives the synchronization pulse clock AMS_SYSREF and the delay synchronization clock PL_SYSREF, and uses them as reference clocks. The data channels are synchronized internally based on the synchronization pulse clock AMS_SYSREF and the delay synchronization clock PL_SYSREF, optimizing the data channel delay synchronization based on the resulting synchronization delay boundary. Furthermore, the data channels are pulse-triggered and synchronized based on the synchronization pulse clock AMS_SYSREF, eliminating delay and phase errors between different data channels. This allows multiple data channels to be aligned in timing and improves synchronization consistency across all data channels. It should be noted that both the synchronization pulse clock AMS_SYSREF and the delay synchronization clock PL_SYSREF are generated by the clock chip, have the same clock frequency, and have a constant phase difference.

[0089] In some embodiments, the process of pulse triggered synchronization includes: turning off the reference signal receiver of each data channel and stopping receiving the synchronous pulse clock AMS_SYSREF; calling the API function to perform initial phase setting and application configuration update on each data channel, and setting the mixing trigger source of each data channel to the synchronous pulse clock AMS_SYSREF; turning on the reference signal receiver of each data channel so that each data channel synchronously receives the synchronous pulse clock AMS_SYSREF; capturing multiple cycles of the synchronous pulse clock AMS_SYSREF, using the pulse signal of the synchronous pulse clock AMS_SYSREF in each cycle as a trigger signal, and performing phase synchronization on each data channel to align the phase of each data channel; turning off the reference signal receiver of each data channel after the above-mentioned multiple cycles of the synchronous pulse clock AMS_SYSREF, and stopping receiving the synchronous pulse clock AMS_SYSREF to lock the phase setting of each data channel to ensure phase synchronization between the data channels.

[0090] An embodiment of the present application also provides a phased array radio telescope, comprising an acquisition board according to any one of the above embodiments.

[0091] See also Figure 7 , Figure 71 is a structural diagram of a computer device provided by an embodiment of the present application. As shown in the figure, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. The various components are connected to each other using different buses for communication and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to an interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0092] The processor 10 may be a central processing unit, a network processor, or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic, or any combination thereof.

[0093] The memory 20 stores instructions that can be executed by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0094] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and application programs required for at least one function; the data storage area may store data created based on the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely located relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0095] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0096] The computer device further includes a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0097] The embodiments of the present application also provide a computer-readable storage medium. The above-mentioned method according to the embodiment of the present application can be implemented in hardware, firmware, or implemented as a computer code that can be recorded in a storage medium, or implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and downloaded through a network and will be stored in a local storage medium, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method shown in the above embodiment is implemented.

[0098] An embodiment of the present application provides a computer program product, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform a method according to any embodiment of the present application.

[0099] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

[0100] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0101] For the convenience of description, the above devices are described as being divided into various units according to their functions. Of course, when implementing this application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0102] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0103] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

[0104] The foregoing is merely an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

[0105] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A method for on-board synchronization without digital functions based on RFSoC, characterized in that: Applicable to an acquisition board including several data channels; the method includes: When the acquisition board is operating normally, initializing the delays of the plurality of data channels in the acquisition board; Performing a delay test on the plurality of data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay of each data channel; When there is a difference between the queue delays of each of the data channels, synchronously correcting the queue delays to obtain synchronization delay boundaries of the plurality of data channels; Delay synchronization optimization is performed on the plurality of data channels based on the synchronization delay boundary, so that the plurality of data channels can achieve synchronous signal acquisition.

2. The method according to claim 1, characterized in that The delay test is performed on the plurality of data channels using the synchronous pulse clock and the delayed synchronous clock to obtain the queue delay of each data channel, including: Performing clock calibration on the plurality of data channels according to the synchronous pulse clock to obtain a delay test clock; Determining a measurement start time according to the delay synchronization clock; Delay measurement is performed on any data channel among the plurality of data channels according to the delay test clock and the measurement start time to obtain the queue delay of the any data channel.

3. The method according to claim 2, characterized in that The synchronous pulse clock is a periodic signal that is output continuously. The clock calibration is performed after the process of receiving the synchronous pulse clock by the plurality of data channels satisfies a preset capture condition.

4. The method according to claim 1, wherein The synchronously correcting the queue delay to obtain the synchronization delay boundaries of the plurality of data channels includes: Performing delay boundary screening on the queue delay, and taking the queue delay that meets the preset delay boundary condition as the optimized delay boundary; Redundant delay compensation is performed on the optimized delay boundary to obtain the synchronous delay boundary.

5. The method according to claim 4, characterized in that The preset delay boundary condition is that the queue delay is the maximum value among all queue delays.

6. The method according to claim 1, characterized in that The performing delay synchronization optimization on the plurality of data channels based on the synchronization delay boundary includes: The time-delay synchronization clock is used as a reference clock, and the synchronization delay boundary is synchronously configured to the plurality of data channels, so that the plurality of data channels start synchronous collection after the synchronization delay boundary.

7. The method according to claim 1, characterized in that Use the following methods to check whether the acquisition board is working properly: Performing status check on the acquisition board; Based on the result of the status check, it is determined whether the acquisition board is operating normally.

8. An intra-board synchronization device without digital functions based on RFSoC, characterized in that: Applicable to an acquisition board containing several data channels; the device includes: A self-check initialization module is used to initialize the delays of the plurality of data channels in the acquisition board when the acquisition board is working normally; A delay test module is used to perform a delay test on the plurality of data channels using a synchronous pulse clock and a delayed synchronous clock to obtain a queue delay of each data channel; a synchronization correction module, configured to perform synchronization correction on the queue delays of the data channels when there are differences between the queue delays of the data channels, so as to obtain synchronization delay boundaries of the data channels; The delay optimization module is used to perform delay synchronization optimization on the multiple data channels based on the synchronization delay boundary, so that the multiple data channels can achieve synchronous signal acquisition.

9. An acquisition board without digital functions based on RFSoC, characterized in that: Intra-board synchronization is performed by the method according to any one of claims 1 to 7.

10. A phased array radio telescope, characterized in that: Including the acquisition board described in claim 9.

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