Chip layout method and device, computer equipment and readable storage medium

Abstract

The invention relates to a chip layout method and device, computer equipment and a readable storage medium. The layout method comprises the following steps: obtaining size information of a plurality of chips; placing the chip with at least two placement forms in a target layout area in the layout frame; dividing a first region and a second region which have the largest area difference and are respectively attached to the adjacent edges of the chip in the remaining region of the target layout region after the chip is placed; taking the first area and the second area as new target layout areas, selecting a chip with the highest size matching degree with the first area and the second area from the remaining unplaced chips, and placing the selected chip in the new target layout areas; circulating the region division operation until the layout is completed and / or no space is left, so as to form a layout scheme set of the chips according to different placement forms of all the chips; and calculating the arrangement uniformity of the chips in each layout scheme, and selecting an optimal solution for output. According to the chip layout method, the chip layout compactness is improved, and waste of arrangement space is avoided.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a chip layout method and apparatus, a computer device, and a readable storage medium. Background Art

[0002] In the semiconductor manufacturing field, the Shuttle service (multi-project wafer sharing tapeout) significantly reduces R&D costs and improves tapeout efficiency by integrating chips (dies) designed by different customers into the same wafer frame. However, with the evolution of process nodes and the increase in design complexity, the traditional floorplan method of manually arranging multi-sized dies faces significant technical bottlenecks.

[0003] The first is the issue of space utilization and layout efficiency. Due to the large differences in the size, shape, and functional modules of different dies, engineers need to manually adjust their layout positions within the frame to adapt to the physical limitations of the manufacturing equipment. However, manual layout is difficult to efficiently coordinate multiple objective constraints (such as area utilization, signal integrity, heat dissipation, etc.), which often leads to two inefficient scenarios: one is insufficient layout space: the die density in some areas is too high, exceeding the process tolerance, and repeated iterative adjustments are required; the other is waste of space resources: there are a large number of unused blank areas in the frame, which reduces the output efficiency of a single tape-out, such as Figure 1 , which is a schematic diagram of the arrangement structure of the existing chip in the existing layout framework, including the existing chip a and the existing layout framework b.

[0004] Secondly, there are issues with manufacturing uniformity and electrical consistency. Artificial die placement can easily lead to macroscopic non-uniformities in die distribution (such as density gradients and center-edge clustering), which in turn trigger two types of key manufacturing defects: the loading effect. During processes like etching and chemical mechanical polishing (CMP), differences in pattern density in local areas can cause fluctuations in material removal rates, resulting in critical dimension (CD) deviations and impacting device performance consistency. The second is topology issues: the relative positions of dies or asymmetric placement of interconnect structures can exacerbate circuit topology effects such as signal crosstalk and clock skew, significantly reducing yield, especially in high-frequency or high-precision analog circuits.

[0005] The high cost of manual optimization is also a significant issue. The existing process relies on engineers' experience and multiple rounds of trial-and-error adjustments, requiring hundreds of hours of design rule checking (DRC), electrical simulation, and process feedback verification. As advanced processes increasingly demand increasingly stringent layout accuracy, traditional methods struggle to balance efficiency and quality, becoming a bottleneck hindering the large-scale adoption of Shuttle services. Summary of the Invention

[0006] Based on this, it is necessary to provide a chip layout method and device, computer equipment and readable storage medium that can improve chip layout efficiency, avoid waste of layout space and avoid load effects and topological problems in response to the above technical problems.

[0007] To achieve the above objectives, the present application provides a chip layout method, comprising the following steps:

[0008] Get the size information of multiple chips;

[0009] Placing the chip in a target layout area, wherein the target layout area is an area in a layout frame and the chip has at least two placement forms in the target layout area;

[0010] According to the edge of the chip already placed in the target layout area, a first area and a second area having the largest area difference are divided in the remaining area of ​​the target layout area, wherein the first area and the second area are respectively aligned with adjacent edges of the already placed chip;

[0011] Taking the first area and the second area as the new target layout areas, selecting the chips with the highest size matching with the first area and the second area from the remaining unplaced chips, and placing the chips with the highest size matching in the first area and the second area respectively;

[0012] Returning to the step of dividing the remaining area of ​​the target layout area into the first area and the second area having the largest area difference based on the edges of the chips already placed in the target layout area, the process continues until all the chips are laid out and / or there is no remaining placement space in the layout frame, thereby forming a layout solution set for the multiple chips based on the different placement forms of all the chips;

[0013] Calculating the arrangement uniformity of the chips in each of the layout schemes;

[0014] The layout solution with the best arrangement uniformity is selected as the final layout result output.

[0015] In one embodiment, the size information includes the length and width of each chip, and before placing the chip in the target layout area, the method further includes:

[0016] Based on the acquired lengths and widths of the chips, the plurality of chips are sorted according to a preset rule to form a preset sequence;

[0017] According to the preset sequence, the chip with the largest size is obtained, wherein the first chip is placed in a first target layout area, the first chip is the chip with the largest size, and the first target layout area is the layout frame.

[0018] In one embodiment, the preset rule includes: firstly sorting the chips in descending order according to their lengths, and if the lengths are equal, sorting them in descending order according to their widths.

[0019] In one embodiment, the size information includes the length and width of each chip, and selecting the chip with the highest size matching with the first area and the second area from the remaining unplaced chips includes:

[0020] Calculating a first ratio of the length of the remaining unplaced chips to the length of the first region and a second ratio of the width of the remaining unplaced chips to the width of the first region;

[0021] calculating a third ratio of the length of the remaining unplaced chips to the length of the second region and a fourth ratio of the width of the remaining unplaced chips to the width of the second region;

[0022] Determining the chip having the highest matching degree with the first region according to the first ratio and the second ratio;

[0023] The chip having the highest matching degree with the second region is determined according to the third ratio and the fourth ratio.

[0024] In one embodiment, the placement of the chip in the target layout area includes a first placement and a second placement that are perpendicular to each other.

[0025] In one embodiment, selecting the chips with the highest size matching degree with the first area and the second area from the remaining unplaced chips, and placing the chips with the highest size matching degree in the first area and the second area respectively, includes:

[0026] Placing the chip with the highest matching degree in the target layout area according to the first placement method or the second placement method;

[0027] When the chip with the highest matching degree cannot be placed in the target layout area in both the first placement mode and the second placement mode, the current layout plan is ended, and the placement of the chip is restarted in the layout framework to form a new layout plan.

[0028] In one embodiment, the calculating the arrangement uniformity of the chips in each of the layout schemes includes:

[0029] Obtaining a coordinate set of center points of all the chips arranged in the layout frame;

[0030] Calculating the minimum distance between each chip and the nearest adjacent chip;

[0031] The standard deviation or variance of all the minimum spacings is calculated as the arrangement uniformity.

[0032] In another aspect, the present application provides a chip layout device, comprising:

[0033] An information acquisition module, used to obtain size information of multiple chips;

[0034] A chip placement module is used to place the chip in a target layout area, wherein the target layout area is an area in the layout frame and the chip has at least two placement forms in the target layout area;

[0035] an area division module, configured to divide the remaining area of ​​the target layout area into the first area and the second area having the largest area difference according to the edge of the chip already placed in the target layout area, wherein the first area and the second area respectively align with adjacent edges of the already placed chip;

[0036] a matching module, configured to use the first area and the second area as new target layout areas, select the chips with the highest size matching with the first area and the second area from the remaining unplaced chips, and place the chips with the highest size matching in the first area and the second area respectively;

[0037] a loop control module, configured to repeatedly trigger the chip placement module, the area division module, and the matching module, and return to the step of dividing the remaining area of ​​the target layout area into a first area and a second area having the largest area difference based on the edges of the chips already placed in the target layout area, until all the chips are laid out and / or there is no remaining placement space in the layout framework, thereby forming a layout solution set for the plurality of chips based on the different placement forms of all the chips;

[0038] An information processing module, configured to calculate the arrangement uniformity of the chips in each of the layout schemes;

[0039] A decision module is used to select the layout solution with the best arrangement uniformity as the final layout result output.

[0040] On the other hand, the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

[0041] On the other hand, the present application also provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of any of the above-described methods when the computer program is executed by a processor.

[0042] The above-mentioned chip layout method and device, computer equipment and readable storage medium dynamically divide the remaining area of ​​the target layout area into areas with the largest area difference according to the edges of the chips already placed in the target layout area, providing a size selection basis for subsequent chip matching, and when the chips are placed, the chip filling is carried out according to the principle of the best match between the chip size and the size of the divided area, so that each chip placement is based on the current optimal choice, further reducing the spatial fragmentation rate, improving the overall layout compactness, avoiding layout space waste, and being able to flexibly adapt to a variety of chip specifications. In addition, by calculating the chip arrangement uniformity in each layout scheme and selecting the layout scheme with the best arrangement uniformity as the final layout result, the most uniform chip arrangement combination is obtained, making the chip distribution more balanced, helping to reduce local heat concentration or signal interference, improving the heat dissipation efficiency and electrical performance of chip components, reducing packaging costs, and at the same time shortening the interconnection distance between chips, improving signal transmission speed, avoiding load effects and topology problems, and being particularly suitable for high-density integration scenarios of multi-size heterogeneous chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of the arrangement structure of existing chips in an existing layout framework provided in the prior art;

[0045] Figure 2 FIG. 1 is a flow chart of a chip layout method provided in one embodiment.

[0046] Figure 3 A schematic diagram of a result of arranging the first chip in a layout framework according to a chip layout method provided in one embodiment;

[0047] Figure 4 A schematic diagram of a result of three chips being arranged in a layout framework according to a chip layout method provided in one embodiment;

[0048] Figure 5 A schematic diagram of the arrangement structure of chips in a layout framework in a chip layout method provided in one embodiment;

[0049] Figure 6 In one embodiment, Figure 5 Schematic diagram of the structure of the center point of the chip.

[0050] Description of reference numerals:

[0051] a-existing chip, b-existing layout framework, 1-chip, 2-target layout area, 21-first area, 22-second area, 3-layout framework, 4-center point. DETAILED DESCRIPTION

[0052] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0053] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0054] It will be understood that the terms "first," "second," etc. used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element.

[0055] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0056] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intervening element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc., if there is transmission of electrical signals or data between the connected objects.

[0057] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Furthermore, the term "and / or" as used in this specification includes any and all combinations of the relevant listed items.

[0058] In one embodiment, Figure 2 As shown, a chip layout method is provided, comprising the following steps:

[0059] Step S1: Obtaining size information of multiple chips 1;

[0060] Step S2: placing the chip 1 in the target layout area 2, where the target layout area 2 is an area within the layout frame 3 and the chip 1 has at least two placement forms in the target layout area 2;

[0061] Step S3: Based on the edge of the chip 1 already placed in the target layout area 2, a first area 21 and a second area 22 having the largest area difference are divided in the remaining area of ​​the target layout area 2, wherein the first area 21 and the second area 22 are respectively aligned with the adjacent edges of the already placed chip 1;

[0062] Step S4: The first area 21 and the second area 22 after the placement of the chip 1 are used as new target layout areas 2, and the chip 1 with the highest size matching with the first area 21 and the second area 22 is selected from the remaining unplaced chips 1, and the chip 1 with the highest size matching is placed in the first area 21 and the second area 22 respectively;

[0063] Step S5: Returning to the step of dividing the remaining area of ​​the target layout area 2 into a first area 21 and a second area 22 with the largest area difference based on the edges of the chips 1 already placed in the target layout area 2, this step continues until all chips 1 are laid out and / or there is no remaining placement space in the layout frame 3, thereby forming a set of layout solutions for multiple chips 1 based on the different placement forms of all chips 1;

[0064] Step S6: Calculating the arrangement uniformity of the chips 1 in each layout scheme;

[0065] Step S7: Select the layout solution with the best arrangement uniformity as the final layout result output.

[0066] The above-mentioned chip layout method dynamically divides the remaining area of ​​the target layout area 2 into areas with different characteristics with the largest area difference based on the edges of the chip 1 already placed in the target layout area 2, providing a size selection basis for the subsequent chip 1 matching. When the chip 1 is placed, the chip filling is carried out according to the principle of the best match between the chip 1 size and the divided area size, so that each placement of the chip 1 is based on the current optimal choice, further reducing the spatial fragmentation rate, improving the overall layout compactness, avoiding layout space waste, and being able to flexibly adapt to a variety of chip specifications. In addition, by calculating the arrangement uniformity of the chip 1 in each layout scheme and selecting the layout scheme with the best arrangement uniformity as the final layout result, the most uniform arrangement of the chip 1 is obtained, making the chip distribution more balanced, helping to reduce local heat concentration or signal interference, improving the heat dissipation efficiency and electrical performance of the chip components, reducing packaging costs, and shortening the interconnection distance between chips, improving the signal transmission speed, avoiding load effects and topology problems, and being particularly suitable for high-density integration scenarios of multi-size heterogeneous chips.

[0067] Specifically, execute step S1 to step S2 to obtain size information of multiple chips 1; place the chips 1 in the target layout area 2, which is the area in the layout frame 3 and the chips 1 have at least two placement forms in the target layout area 2.

[0068] For example, in the actual process, by integrating chips 1 (Die) designed by different customers into the same layout framework 3, R&D costs can be reduced and tape-out efficiency can be improved.

[0069] Exemplarily, the sizes of different chips 1 are as different as possible, but there are also cases where the sizes of chips 1 are the same.

[0070] Exemplarily, the chip 1 is rectangular in shape. In order to place the chip 1 in the target layout area 2 , the target layout area 2 is a rectangular area in the layout frame 3 .

[0071] In one embodiment, the size information includes the length and width of each chip 1 , and before placing the chip 1 in the target layout area 2 , further includes:

[0072] Based on the acquired length and width of the chip 1, the plurality of chips 1 are sorted according to a preset rule to form a preset sequence;

[0073] According to the preset sequence, the chip 1 with the largest size is obtained.

[0074] The first chip 1 is placed in the first target layout area 2 , the first chip 1 is the largest chip 1 , and the first target layout area 2 is the layout frame 3 .

[0075] In one embodiment, the preset rules include: first sorting the chips 1 in descending order by length, and if the lengths are equal, then sorting them in descending order by width. That is, the first chip 1 is preferably the chip 1 with the largest length. If the lengths are equal, then the chip 1 with the largest width is selected as the first chip 1.

[0076] For example, the two adjacent edges of the first chip 1 placed align with the two adjacent edges of the layout frame 3, allowing the first chip 1 to occupy the majority of the layout frame 3's space. This prevents smaller chips 1 from occupying the core area and leaving corners unused. Prioritizing the placement of the largest chips 1 prevents them from being forced to split or reorient due to insufficient space later, thus reducing the number of global layout backtracking attempts.

[0077] Furthermore, the clear sorting rules for multiple chips 1 simplify the chip 1 selection logic, avoiding the need to traverse all remaining chips 1 to calculate the optimal solution for each placement, thus reducing the algorithm's time complexity. Furthermore, the sorted chip 1 queue can form an adaptive pattern with the size of the subsequently dynamically divided regions, with large matching large and small matching small. This improves the efficiency of matching regions with chips 1, reduces the number of repeated attempts, optimizes space utilization, and reduces fragmentation.

[0078] Specifically, see Figure 3 , execute step S3, and divide the remaining area of ​​the target layout area 2 into a first area 21 and a second area 22 with the largest area difference according to the edge of the chip 1 placed in the target layout area 2, wherein the first area 21 and the second area 22 are respectively aligned with the adjacent edges of the placed chip 1.

[0079] For example, Figure 3 As shown, the first area 21 and the second area 22 with the largest area difference are divided in the remaining area of ​​the target layout area 2 in a manner including vertical division and horizontal division, thereby achieving regular division of the first area 21 and the second area 22.

[0080] The remaining area of ​​the target layout area 2 is divided into a first area 21 and a second area 22 with the largest area difference, including:

[0081] The remaining area of ​​the target layout area 2 adjacent to the placed chip 1 is divided vertically and horizontally along the width direction and the length direction respectively;

[0082] The area difference of all divided regions is calculated, and the divided region with the largest area difference is selected as the required solution. At the same time, it is necessary to ensure that the two divided regions are respectively aligned with the two adjacent edges of the chip 1 to obtain the first region 21 and the second region 22.

[0083] Exemplarily, an edge of one of the first area 21 and the second area 22 completely overlaps with an edge of the previously placed chip 1 , and an edge of the other area partially overlaps with an edge of the previously placed chip 1 .

[0084] Specifically, see Figure 4 , execute step S4, take the first area 21 and the second area 22 as new target layout areas 2, select the chip 1 with the highest size matching with the first area 21 and the second area 22 from the remaining unplaced chips 1, and place the chip 1 with the highest size matching in the first area 21 and the second area 22 respectively.

[0085] In one embodiment, Figure 4 As shown, the chips with the highest size matching degree with the first area 21 and the second area 22 are respectively selected from the remaining unplaced chips 1, where the highest size matching degree means that the size of the chip 1 is closest to the size in the first area 21 or the second area 22.

[0086] Therefore, when dividing the remaining area of ​​the target layout area 2 into the first area 21 and the second area 22 with the largest area difference, the process also includes recording and obtaining information on the length and width of the first area 21 and the second area 22 .

[0087] In one embodiment, the size information includes the length and width of each chip 1 , and selecting the chip 1 with the highest size matching with the first area 21 and the second area 22 from the remaining unplaced chips 1 includes:

[0088] Calculating a first ratio of the length of the remaining unplaced chips 1 to the length of the first region 21 and a second ratio of the width of the remaining unplaced chips 1 to the width of the first region 21;

[0089] Calculating a third ratio of the length of the remaining unplaced chips 1 to the length of the second region 22 and a fourth ratio of the width of the remaining unplaced chips 1 to the width of the second region 22;

[0090] Determine the chip 1 having the highest matching degree with the first region 21 according to the first ratio and the second ratio;

[0091] According to the third ratio and the fourth ratio, the chip 1 having the highest matching degree with the second region 22 is determined.

[0092] For example, based on the first and second ratios, determining the chip 1 with the highest degree of match for the first region 21 includes comparing the product of the first and second ratios obtained for each remaining chip 1 and selecting the chip with the smallest value as the chip 1 with the highest degree of match for the first region 21. Based on the third and fourth ratios, determining the chip 1 with the highest degree of match for the second region 22 includes comparing the product of the third and fourth ratios obtained for each remaining chip 1 and selecting the chip with the smallest value as the chip 1 with the highest degree of match for the second region 22. In other words, by using the dual constraints of length and width, it is possible to ensure that the size of the chip 1 is highly compatible with the region shape, reducing spatial fragmentation.

[0093] In another embodiment, selecting the chips 1 with the highest size matching with the first area 21 and the second area 22 from the remaining unplaced chips 1 includes:

[0094] Compare the area of ​​the remaining unplaced chips 1 with the area of ​​the first region 21 , and select the chip 1 with the closest area as the chip 1 with the highest size matching with the first region 21 ;

[0095] The area of ​​the remaining unplaced chips 1 is compared with the area of ​​the second region 22, and the chip 1 with the closest area is selected as the chip 1 with the highest size matching degree with the second region 22. That is, the comparison is based on the area, which is simple and improves the matching efficiency.

[0096] In one embodiment, the placement of chip 1 in the target layout area 2 includes a first placement method and a second placement method, and the chip in the first placement method and the chip 1 in the second placement method are perpendicular to each other. For example, the long side of chip 1 is aligned with the longer side of the divided area, and the short side of chip 1 is aligned with the shorter side of the divided area; or when the longer side of chip 1 is smaller than the shorter side of the divided area, the chip 1 is rotated 90 degrees, and the longer side of chip 1 is aligned with the shorter side of the divided area, and the short side of chip 1 is aligned with the shorter side of the divided area. That is, the chip 1 is allowed to adapt to the area in a 90-degree rotation. When the chip 1 cannot be fully placed according to the current placement direction, the chip 1 can also be rotated 90 degrees. By adjusting the length and width of the chip 1 through rotation, it can adapt to more irregular areas and reduce the probability of re-placement of the chip 1.

[0097] Exemplarily, selecting the chip 1 with the highest size matching degree with the first area 21 and the second area 22 from the remaining unplaced chips 1, and placing the chip 1 with the highest size matching degree in the first area 21 and the second area 22 respectively, includes:

[0098] Place the chip 1 with the highest matching degree in the target layout area 2 according to the first placement method or the second placement method;

[0099] If the chip 1 with the highest matching degree cannot be placed in the target layout area 2 using either the first or second placement method, the current layout plan is terminated and chip 1 placement is restarted in the target layout area 2 to form a new layout plan. This means that by resetting the layout frame 3 and restarting the placement of the first chip 1 in the layout frame 3, a more optimal chip 1 arrangement and combination can be explored.

[0100] Specifically, see Figure 5 , execute step S5 and return to the step of dividing the remaining area of ​​the target layout area 2 into a first area 21 and a second area 22 with the largest area difference according to the edges of the chips 1 already placed in the target layout area 2, until all chips 1 are laid out and / or there is no remaining placement space in the layout framework, so as to form a layout solution set for multiple chips 1 according to the different placement forms of all chips 1.

[0101] Exemplarily, the first area 21 and the second area 22 after the chip 1 is placed are used as the new target layout area 2. When the above area division and chip matching and placement operations are repeated, the above edge division principle and size matching principle are also followed, which will not be repeated here.

[0102] For example, Figure 5 As shown, until all chips 1 are laid out and / or there is no remaining placement space in the layout frame 3, the required layout requirements can be met.

[0103] For example, when there are n chips 1 and n is greater than or equal to 2, n chips 1 have 2 n A layout scheme.

[0104] Specifically, see Figure 6 , execute step S6 to step S7, calculate the arrangement uniformity of chip 1 in each layout scheme; select the layout scheme with the best arrangement uniformity as the final layout result output.

[0105] In one embodiment, Figure 6 As shown, calculating the arrangement uniformity of chip 1 in each layout scheme includes:

[0106] Obtain the coordinate set of the center points 4 of all chips 1 arranged in the layout frame 3; take the center point 4 of each chip 1 to generate a set of points, such as ;

[0107] Calculate the minimum distance between each chip 1 and the nearest chip 1; each point There is only one nearest neighbor , that is, the immediate distance between them is , calculate the minimum spacing for each point: ,(in It is away nearest point);

[0108] Calculate the standard deviation or variance of all the minimum spacings to obtain the uniformity of the arrangement. Calculate the standard deviation based on all the minimum spacings obtained to obtain the uniformity of the arrangement. Calculate the average value of the minimum spacing of all points to be , calculate the square of the difference between the minimum distance of each point and the mean , then the standard deviation of chip 1 arrangement is ,in, is the number of chip 1.

[0109] Therefore, quantifying the arrangement uniformity by the standard deviation of the minimum spacing provides a mathematically rigorous and computationally efficient evaluation standard for the layout of the chip 1, which is an effective means to balance space utilization and performance reliability.

[0110] It should be understood that although Figure 2 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0111] In one embodiment, the present application further provides a chip layout device, comprising: an information acquisition module, a chip placement module, an area division module, a matching module, a loop control module, an information processing module and a decision module, wherein the information acquisition module is used to obtain size information of multiple chips 1; the chip placement module is used to place the chip 1 in the target layout area 2, the target layout area 2 is the area in the layout frame 3 and the chip 1 has at least two placement forms in the target layout area 2; the area division module is used to divide the remaining area of ​​the target layout area 2 into a first area 21 and a second area 22 with the largest area difference according to the edge of the chip 1 placed in the target layout area 2, wherein the first area 21 and the second area 22 are respectively aligned with the adjacent edges of the placed chip 1; the matching module is used to use the first area 21 and the second area 22 as new target layouts. In the local area 2, the chip 1 with the highest size matching with the first area 21 and the second area 22 is selected from the remaining unplaced chips 1, and the chip 1 with the highest size matching is placed in the first area 21 and the second area 22 respectively; the loop control module is used to repeatedly trigger the chip placement module, the area division module and the matching module, and return to the step of dividing the first area 21 and the second area 22 with the largest area difference in the remaining area of ​​the target layout area 2 according to the edge of the chip 1 placed in the target layout area 2, until all chips 1 are laid out and / or there is no remaining placement space in the layout framework 3, so as to form a layout scheme set of multiple chips 1 according to the different placement forms of all chips 1; the information processing module is used to calculate the arrangement uniformity of the chips 1 in each layout scheme; the decision module is used to select the layout scheme with the best arrangement uniformity as the final layout result output.

[0112] In one embodiment, the size information includes the length and width of each chip 1, and the information processing module is further configured to:

[0113] Based on the acquired length and width of the chip 1 , the multiple chips 1 are sorted according to a preset rule to form a preset sequence, and the chip 1 with the largest size is obtained according to the preset sequence.

[0114] For the specific definition of the chip layout device, please refer to the definition of the chip layout method above, which will not be repeated here. The various modules in the above-mentioned chip layout device can be implemented in whole or in part by software, hardware and their combination. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0115] In one embodiment, the present application further provides a computer device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above-mentioned method embodiments when executing the computer program.

[0116] In one embodiment, the present application further provides a computer-readable storage medium having a computer program stored thereon, which implements the steps in the above-mentioned method embodiments when the computer program is executed by a processor.

[0117] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media used in the embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile memory may include read-only memory (ROM), magnetic tape, floppy disk, flash memory, or optical storage. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0118] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0119] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0120] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art could make various modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A chip layout method, characterized in that: The steps include: Get the size information of multiple chips; Placing the chip in a target layout area, wherein the target layout area is an area in a layout frame and the chip has at least two placement forms in the target layout area; According to the edge of the chip already placed in the target layout area, a first area and a second area having the largest area difference are divided in the remaining area of ​​the target layout area, wherein the first area and the second area are respectively aligned with adjacent edges of the already placed chip; Taking the first area and the second area as the new target layout areas, selecting the chips with the highest size matching with the first area and the second area from the remaining unplaced chips, and placing the chips with the highest size matching in the first area and the second area respectively; Returning to the step of dividing the remaining area of ​​the target layout area into the first area and the second area having the largest area difference based on the edges of the chips already placed in the target layout area, the process continues until all the chips are laid out and / or there is no remaining placement space in the layout frame, thereby forming a layout solution set for the multiple chips based on the different placement forms of all the chips; Calculating the arrangement uniformity of the chips in each of the layout schemes; The layout solution with the best arrangement uniformity is selected as the final layout result output.

2. The chip layout method according to claim 1, wherein: The size information includes the length and width of each chip. Before placing the chip in the target layout area, the method further includes: Based on the acquired lengths and widths of the chips, the plurality of chips are sorted according to a preset rule to form a preset sequence; According to the preset sequence, the chip with the largest size is obtained, wherein the first chip is placed in a first target layout area, the first chip is the chip with the largest size, and the first target layout area is the layout frame.

3. The chip layout method according to claim 2, wherein: The preset rules include: firstly sorting the chips in descending order according to their lengths, and if the lengths are equal, sorting them in descending order according to their widths.

4. The chip layout method according to claim 1, wherein: The size information includes the length and width of each chip, and selecting the chip with the highest size matching degree with the first area and the second area from the remaining unplaced chips includes: Calculating a first ratio of the length of the remaining unplaced chips to the length of the first region and a second ratio of the width of the remaining unplaced chips to the width of the first region; calculating a third ratio of the length of the remaining unplaced chips to the length of the second region and a fourth ratio of the width of the remaining unplaced chips to the width of the second region; Determining the chip having the highest matching degree with the first region according to the first ratio and the second ratio; The chip having the highest matching degree with the second region is determined according to the third ratio and the fourth ratio.

5. The chip layout method according to claim 1, wherein: The placement forms of the chips in the target layout area include a first placement form and a second placement form, and the chips in the first placement form and the chips in the second placement form are perpendicular to each other.

6. The chip layout method according to claim 5, wherein: The step of selecting the chips having the highest size matching degree with the first area and the second area from the remaining chips that have not been placed, and placing the chips having the highest size matching degree in the first area and the second area respectively, includes: Placing the chip with the highest matching degree in the target layout area according to the first placement method or the second placement method; When the chip with the highest matching degree cannot be placed in the target layout area in both the first placement manner and the second placement manner, the current layout plan is ended, and the placement of the chip is restarted in the layout framework to form a new layout plan.

7. The chip layout method according to claim 1, wherein: Calculating the arrangement uniformity of the chips in each of the layout schemes includes: Obtaining a coordinate set of center points of all the chips arranged in the layout frame; Calculating the minimum distance between each chip and the nearest adjacent chip; The standard deviation or variance of all the minimum spacings is calculated as the arrangement uniformity.

8. A chip layout device, characterized in that: include: An information acquisition module, used to obtain size information of multiple chips; A chip placement module is used to place the chip in a target layout area, wherein the target layout area is an area in the layout frame and the chip has at least two placement forms in the target layout area; an area division module, configured to divide the remaining area of ​​the target layout area into a first area and a second area with the largest area difference according to the edge of the chip already placed in the target layout area, wherein the first area and the second area respectively coincide with adjacent edges of the already placed chip; a matching module, configured to use the first area and the second area as new target layout areas, select the chips with the highest size matching with the first area and the second area from the remaining unplaced chips, and place the chips with the highest size matching in the first area and the second area respectively; a loop control module, configured to repeatedly trigger the chip placement module, the area division module, and the matching module, and return to the step of dividing the first area and the second area having the largest area difference in the remaining area of ​​the target layout area based on the edges of the chips already placed in the target layout area, until all the chips are laid out and / or there is no remaining placement space in the layout framework, thereby forming a layout solution set for the plurality of chips based on the different placement forms of all the chips; An information processing module, configured to calculate the arrangement uniformity of the chips in each of the layout schemes; A decision module is used to select the layout solution with the best arrangement uniformity as the final layout result output.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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