Multi-pass programming in memory devices

Abstract

Example memory devices, systems, and methods for multi-pass programming in memory devices are disclosed. An example method includes generating hierarchy indicator data based on first data, where the first data is to be stored in a memory device based on a first program operation and a second program operation. A program operation is performed to store hierarchy indicator data in a first cell of a memory cell array of a memory device. A first program operation is performed to store first data in a second cell of a memory cell array of a memory device.

Description

Technical Field

[0001] The present disclosure relates to memory devices, systems, and methods for multi-pass programming in memory devices. Background Art

[0002] Memory devices, such as NAND flash memory devices, can store more than a single bit of information in each memory cell in multiple levels to increase storage capacity and reduce cost per bit. Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. Flash memory can perform various operations, such as read, program (write), and erase operations. Multi-pass programming in a memory device involves multiple programming operations to improve the efficiency of the process of storing multiple bits in the memory cells of the memory device. Summary of the Invention

[0003] The present disclosure relates to memory devices, systems, and methods for multi-pass programming in memory devices.

[0004] Certain aspects of the subject matter described herein can be implemented as a method. The method includes generating level indicator data based on first data, wherein the first data is stored in a memory device based on a first programming operation and a second programming operation. The programming operation is performed to store the level indicator data in a first cell of a memory cell array of the memory device. The first programming operation is performed to store the first data in a second cell of the memory cell array of the memory device.

[0005] The method may include one or more of the following features.

[0006] In some implementations, before performing the programming operation to store the level indicator data in the first cell, the level indicator data is stored in one or more internal latches of a page buffer of the memory device.

[0007] In some implementations, the first data is stored in one or more internal latches of a page buffer of the memory device before performing the programming operation to store the level indicator data in the first cell and before performing the first programming operation to store the first data in the second cell.

[0008] In some embodiments, generating the level indicator data based on the first data includes generating the level indicator data based on parity information of the first data.

[0009] In some implementations, performing a program operation includes performing a program operation to store the level indicator data in a single-level cell (SLC) mode.

[0010] In some embodiments, after performing the first programming operation, the level indicator data is read from the memory cell array, the first data is retrieved by reading the first data from the memory cell array, second data is generated based on the level indicator data and the retrieved first data, and the second programming operation is performed to store the second data in the memory cell array of the memory device.

[0011] In some embodiments, retrieving the first data by reading the first data from the memory cell array includes performing a first read operation of the second cell using a first read voltage set to generate third data, and performing a second read operation of the second cell using a second read voltage set to generate fourth data, and generating the second data based on the level indicator data and the retrieved first data includes generating the second data based on the level indicator data, the third data, and the fourth data.

[0012] In some implementations, the first cell and the second cell are coupled to a same bit line of the memory cell array.

[0013] In some implementations, the level indicator data and the first data are programmed into different pages of the same block of the memory cell array.

[0014] In some implementations, the level indicator data and the first data are programmed into different blocks of the same plane of the memory cell array.

[0015] Certain aspects of the subject matter described herein can be implemented as a memory device including a memory cell array and peripheral circuitry coupled to the memory cell array and configured to perform operations including: generating tier indicator data based on first data, wherein the first data is to be stored in the memory device based on first programming operations and second programming operations; performing a programming operation to store the tier indicator data in a first cell of the memory cell array of the memory device; and performing the first programming operation to store the first data in a second cell of the memory cell array of the memory device.

[0016] The memory device may include one or more of the following features.

[0017] In some implementations, before performing the programming operation to store the level indicator data in the first cell, the level indicator data is stored in one or more internal latches of a page buffer of the memory device.

[0018] In some implementations, the first data is stored in one or more internal latches of a page buffer of the memory device before performing the programming operation to store the level indicator data in the first cell and before performing the first programming operation to store the first data in the second cell.

[0019] In some embodiments, generating the level indicator data based on the first data includes generating the level indicator data based on parity information of the first data.

[0020] In some implementations, the first cell and the second cell are coupled to a same bit line of the memory cell array.

[0021] In some implementations, the level indicator data and the first data are programmed into different pages of the same block of the memory cell array.

[0022] In some implementations, the level indicator data and the first data are programmed into different blocks of the same plane of the memory cell array.

[0023] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system includes a memory device and a controller coupled to the memory device and configured to send one or more signals to the memory device to initiate an operation. The memory device includes a memory cell array and peripheral circuitry coupled to the memory cell array and configured to perform an operation, the operation comprising: generating tier indicator data based on first data, wherein the first data is to be stored in the memory device based on first programming operations and second programming operations; performing a programming operation to store the tier indicator data in a first cell of the memory cell array of the memory device; and performing the first programming operation to store the first data in a second cell of the memory cell array of the memory device.

[0024] The memory system may include one or more of the following features.

[0025] In some embodiments, the controller is configured to perform one or more operations, including: sending a first signal to a memory device to initiate a programming operation to store the level indicator data and initiating a first programming operation to store the first data; sending a second signal to the memory device to initiate a read operation to read second data from the memory device, wherein the second data is generated by the memory device using the level indicator data and the first data; and sending a third signal to the memory device to initiate the second programming operation to store the second data.

[0026] In some embodiments, the controller further includes a decoder and an encoder, and one or more operations further include: after sending the second signal to the memory device to initiate the read operation of reading the second data, receiving the second data from the memory device; decoding the second data using the decoder; and encoding the decoded second data into fifth data using the encoder, wherein sending the third signal to the memory device to initiate the second programming operation of storing the second data includes: sending the third signal to the memory device to initiate the programming operation of storing the fifth data in the memory device.

[0027] The details of these and other aspects and embodiments of the present disclosure are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the present disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A block diagram of an example system having a memory device according to some aspects of the present disclosure is shown.

[0029] Figure 2 An example memory device including some example peripheral circuits and a memory cell array according to some aspects of the present disclosure is shown.

[0030] Figure 3 A detailed block diagram illustrating an example structure of a page buffer according to aspects of the present disclosure.

[0031] Figure 4 An example process for coarse programming N pages of data corresponding to a piece of N-bit data is shown according to aspects of the present disclosure.

[0032] Figure 5 An example process for reconstructing N pages of data using stored level indicator data and coarsely programmed N pages of data is shown in accordance with aspects of the present disclosure.

[0033] Figure 6A 4-bit piece of data is shown according to some aspects of the present disclosure.

[0034] Figure 7 Example read voltages when reading L- and L+ are shown according to aspects of the present disclosure.

[0035] Figure 8 Examples of DL, L-, L+, and regenerated LP data are shown according to some aspects of the present disclosure.

[0036] Figure 9 An example workflow for performing a two-pass programming operation for N pages of data according to aspects of the present disclosure is shown.

[0037] Figure 10 An example of a flowchart of a method for multi-pass programming in a memory device according to some aspects of the present disclosure is shown.

[0038] Like reference numbers and designations throughout the various drawings indicate like elements. DETAILED DESCRIPTION

[0039] The present specification relates to memory devices, systems, and methods for multi-pass programming in memory devices. In some cases, multi-pass programming can be used to store multi-bit information in a memory cell of a memory device. For example, to store N bits of information in a memory cell, a coarse programming operation can be performed to roughly store the N bits of data, followed by a fine programming operation to accurately store the N bits of data. The fine programming operation requires access to the N bits of data. The disclosed methods and systems can regenerate the N bits of data after the coarse programming operation without caching the N bits of data before the fine programming operation. The disclosed methods generate level indicator data corresponding to the N bits of data during the coarse programming operation, and use the level indicator data and data read back from the coarse programming data in the memory device to regenerate the N bits of data for the fine programming operation.

[0040] Embodiments of the present disclosure may provide one or more of the following technical advantages. For example, in order to store multi-bit information in a memory cell, data is not cached between two programming passes during a multi-pass programming operation. Therefore, the write buffer (system cache) is idle during each subsequent programming pass in the multi-pass programming operation. Therefore, storage resources can be saved. In addition, embodiments of the present disclosure are fully compatible with existing flash memory hardware and firmware for multi-pass programming. In addition, the disclosed method can handle power loss conditions in memory devices at a reduced storage cost. The disclosed method also has the benefit of not increasing the margin error of existing read operations.

[0041] Figure 1A block diagram of an example system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system on a chip (SoC), such as an application processor (AP). Host 108 may be configured to send data to or receive data from memory device 104.

[0042] Memory device 104 can be any memory device disclosed in the present disclosure. According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in a high duty cycle environment such as an SSD or embedded MultiMediaCard (eMMC), which is used as a data storage device and enterprise storage array for mobile devices (e.g., smartphones, tablets, laptops, etc.). Memory controller 106 can be configured to control operations of memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions related to data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction code (ECC) associated with data read from or written to the memory device 104. Any other suitable functions may also be performed by the memory controller 106, such as formatting the memory device 104.

[0043] The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial-ATA protocol, a Parallel-ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, etc.

[0044] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of terminal electronic products. In one example, the memory controller 106 and a single memory device 104 can be integrated into a memory card, which can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCMicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card can also include a memory card that connects the memory card to a host (for example, Figure 1 In another example, the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD, which may also include a memory card connector that connects the SSD to a host (e.g., Figure 1 In some embodiments, the storage capacity and / or operating speed of the SSD is greater than the storage capacity and / or operating speed of the memory card.

[0045] In some embodiments, the memory cells in the memory device 104 are single-level cells (SLCs) that have two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell is a multi-level cell (MLC) that is capable of storing more than a single bit of data in more than four storage states. For example, the MLC can store two bits per cell, three bits per cell (also known as a triple-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to assume a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels relative to the erased state by writing one of the three possible nominal storage values ​​into the cell. A fourth nominal storage value can be used for the erased state.

[0046] Figure 2 An example memory device 104 including some example peripheral circuits and a memory cell array 202 according to some aspects of the present disclosure is shown. The example peripheral circuits may include any suitable analog, digital, and mixed-signal circuits for facilitating the operation of the memory cell array 202 by applying a voltage signal and / or a current signal to each target memory cell in the memory cell array 202 and sensing a voltage signal and / or a current signal from each target memory cell in the memory cell array 202. Figure 2 As shown in , example peripheral circuits may include page buffers / sense amplifiers 204, column decoders / bit line drivers 206, row decoders / word line drivers 208, voltage generators 210, control logic 212, registers 214, interfaces 216, and data buses 218. In some examples, Figure 2 Additional peripheral circuits not shown.

[0047] The page buffer / sense amplifier 204 can be configured to read data from the memory cell array 202 and program (write) data to the memory cell array 202 according to control signals from the control logic 212. In one example, the page buffer / sense amplifier 204 can store a page of programming data (write data) to be programmed into a page of the memory cell array 202. In another example, the page buffer / sense amplifier 204 can perform a program verification operation to ensure that the data has been properly programmed into the memory cells of the memory cell array 202. In yet another example, the page buffer / sense amplifier 204 can also sense a low-power signal from a bit line representing a data bit stored in a memory cell during a read operation and amplify the small voltage swing to a recognizable logic level. The column decoder / bit line driver 206 can be configured to be controlled by the control logic 212 and select one or more NAND memory strings by applying a bit line voltage generated from the voltage generator 210.

[0048] The row decoder / word line driver 208 can be configured to be controlled by the control logic 212 and to select / deselect blocks of the memory cell array 202 and to select / deselect word lines of the blocks of the memory cell array 202. The row decoder / word line driver 208 can be further configured to drive the word lines using word line voltages generated from the voltage generator 210. In some embodiments, the row decoder / word line driver 208 can also select / deselect and drive source select gate (SSG) lines and drain select gate (DSG) lines. The row decoder / word line driver 208 can be configured to apply a read voltage to the selected word line in a read operation on a memory cell coupled to the selected word line.

[0049] Voltage generator 210 may be configured to be controlled by control logic 212 and generate word line voltages (eg, read voltage, program voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to memory cell array 202 .

[0050] The control logic 212 may be coupled to each of the peripheral circuits described above and configured to control the operation of each peripheral circuit. The registers 214 may be coupled to the control logic 212 and include a status register, a command register, and an address register for storing status information, a command operation code (opcode), and a command address for controlling the operation of each peripheral circuit. The status registers of the registers 214 may include one or more registers configured to store open block information indicating one or more open blocks in all blocks in the memory cell array 202, such as an automatic dynamic start voltage (ADSV) list. In some embodiments, the open block information also indicates the last programmed page of each open block.

[0051] The interface 216 may be coupled to the control logic 212 and act as a control buffer to transmit data from a host (eg, Figure 1 The interface 216 may also be coupled to the column decoder / bit line driver 206 via a data bus 218 and may function as a data input / output (I / O) interface and a data buffer to buffer and relay data to and from the memory cell array 202.

[0052] In some embodiments, during a programming operation, the page buffer / sense amplifier 204 may include a storage module (e.g., a latch) for temporarily storing a piece of N-bit data (e.g., in the form of a Gray code) received from the data bus 218 in a first pass (not the last programming pass, e.g., a coarse programming pass) of a multi-pass programming operation and providing the piece of N-bit data to a corresponding target memory cell. Before a second pass (the last programming pass, e.g., a fine programming pass) after the first pass, during a read operation, the page buffer / sense amplifier 204 may be configured to read one or more (M) bits of the piece of N-bit data based on the corresponding intermediate level to which the target memory cell is programmed in the first pass, and also receive a read request from a memory controller (e.g., Figure 1 106) receives the remaining (NM) bits of the N-bit stripe of data. The page buffer / sense amplifier 204 can then be configured to combine the read bits and the received bits into a corresponding stripe of N-bit data and provide the corresponding stripe of N-bit data to the target memory cell in a second pass. Therefore, in these embodiments, it is necessary to receive the remaining (NM) bits of the N-bit stripe of data from the memory controller.

[0053] Figure 3Detailed block diagram illustrating an example structure of a page buffer (e.g., page buffer / sense amplifier 204) according to some aspects of the present disclosure. In some embodiments, Figure 3 The page buffer in the embodiment includes a plurality of page buffer circuits 302, each of which is coupled to a corresponding one of the bit lines 316. In other words, each page buffer circuit 302 can be coupled to a corresponding column of memory cells via a corresponding bit line 316 and is configured to temporarily store an N-bit data set for programming a corresponding selected memory cell in a programming operation. All page buffer circuits 302 in the page buffer can together temporarily store an entire current data page (e.g., Q N-bit data sets) for programming a selected row of memory cells coupled to a selected word line in a programming operation. As described above, in some embodiments, each page buffer circuit 302 is further configured to pre-process a corresponding portion of user data received from the data bus 218 and convert it into a corresponding N-bit data set based on a preset Gray code. The corresponding N-bit data set can include N portions of page data (e.g., N bits from the current data page). For example, for a TLC where N=3, each page buffer circuit 302 can be configured to temporarily store a corresponding set of eight 3-bit sets of the current data page, where the corresponding set corresponds to one of eight levels.

[0054] In some embodiments, each page buffer circuit 302 may include a plurality of non-dynamic memory cells and a bias circuit 304. The plurality of non-dynamic memory cells may include N-1 data storage cells (D1, ..., D N-1 )306, a cache storage unit (DC) 308, a bias level storage unit (DL) 310 and a sense storage unit (DS) 312.

[0055] It should be understood that each non-dynamic memory cell (such as data storage cell 306, cache storage cell 308, bias level storage cell 310, and sense storage cell 312) can be any circuit having two stable states for storing a single data bit, such as a latch or a flip-flop. In some embodiments, each of data storage cell 306, cache storage cell 308, bias level storage cell 310, and sense storage cell 312 can include a latch. For example, for a TLC memory device, page buffer circuit 302 can have a 4-latch configuration, including one cache latch, one data latch, one 3-bias level (3BL) latch, and one sense latch. In another example, for a QLC memory device, page buffer circuit 302 can have a 5-latch configuration, including one cache latch, two data latches, one 3-bias level latch, and one sense latch.

[0056] During a current programming operation for programming a selected row of memory cells based on a current data page, each of the N-1 data storage units 306 can be configured to store a corresponding portion of a page of data from an N-bit data set (e.g., a corresponding bit from the corresponding N bits of the current data page). Thus, the N-1 data storage units 306 can store N-1 portions of a page of data from an N-bit data set (e.g., an N-1 bit from the corresponding N bits of the current data page).

[0057] According to some embodiments, in order to reduce the number of non-dynamic memory cells and the size of the page buffer circuit 302, the number of cache memory cells 308 is limited to one, i.e., a single cache memory cell 308, which can store only a single data bit at a time. In some cases, the number of data storage cells in each page buffer circuit 302 can be at least the same as the number of bits in the N-bit data set used to program the corresponding selected memory cell, i.e., N data storage cells, because a single cache memory cell is dedicated to caching data for the next data page. In some other cases, Figure 3 The individual cache memory cells 308 in the page buffer circuit 302 can also be configured to store one of the corresponding N bits from the current data page. That is, according to some embodiments, the cache memory cell 308 is configured to sequentially store one of the corresponding N bits from the current data page and each of the corresponding N bits from the next data page. In other words, the cache memory cell 308 can function as both a data storage cell and a cache memory cell in a time-division manner, replacing one of the data storage cells 306 in each page buffer circuit 302. Additionally, the bias level storage cell 310 can be configured to store another of the corresponding N bits from the current data page.

[0058] In some embodiments, another memory cell in each page buffer circuit 302 for storing non-data page information is configured to sequentially store the non-data page information and one of the N bits of the next data page, thereby enabling all N-1 bits of the next data page to be cached during the current programming operation to avoid a data loading window. That is, the page buffer circuit 302 may include multi-purpose memory cells that can store non-data page information and cache the data of the next data page in a time-division manner. For example, the sense memory cell (DS) 312 or the bias level memory cell (DL) 310 may be configured to store non-data page information, i.e., any information other than the data bits in the data page.

[0059] For example, the sense storage unit (DS) 312 can be configured to store information indicating whether the current operation performed by the page buffer / sense amplifier 204 is a read operation or a program operation. The bias level storage unit (DL) 310 (e.g., a 3-bias level storage unit) can be configured to store bias information for the corresponding bit line 316 coupled to the page buffer circuit 302. In some embodiments, the bias level storage unit 310 can be a multipurpose storage unit that functions as both a bias level storage unit and a data storage unit in a time-division manner. The bias circuit 304 can be coupled to the corresponding bit line 316 and configured to apply a bit line voltage to the corresponding selected memory cell coupled to the corresponding bit line 316 during a programming operation. Depending on whether the corresponding selected memory cell passes verification at a corresponding level according to the N-bit data used to program the selected memory cell, for example, a high voltage level and a low voltage level can be used as bias levels to determine the bit line voltage to be applied to the corresponding bit line 316 in the next programming operation. In some embodiments, to optimize the threshold voltage distribution, for example, to expand the read margin between adjacent levels and reduce the width of each level, a medium voltage level is also used as a bias level to determine the bit line voltage in the next programming operation. That is, one of three voltage levels, such as high, medium, and low (referred to herein as three bias levels), can be used as a bias level to determine the bit line voltage applied to the corresponding bit line 316 in the next programming operation. In some embodiments, the bias level is non-data page information stored in the bias level storage unit 310.

[0060] It should be understood that although bias level memory cell 310 is described herein as an example of a multi-purpose memory cell, any suitable non-data page memory cell in page buffer circuit 302 (e.g., sense memory cell 312 or Figure 3 Any other non-data page memory cells not shown in FIG302 may be used as multi-purpose memory cells in some examples without adding additional memory cells to page buffer circuit 302 .

[0061] In some implementations, control logic 212 can be configured to determine the type of operation to be performed on page buffer circuit 302 .

[0062] Figure 4 A method for performing a comparison with an N-bit data having 2 bits is shown according to some aspects of the present disclosure. N In some embodiments, the coarse programming of the N pages of data is the first pass (not the last pass) of a two-pass programming operation of the N pages of data to store the N pages of data in a memory cell array (e.g., Figure 2 In the memory cell array 202).

[0063] At 402, a peripheral circuit set (e.g., Figure 2 ) caches N pages of data in the internal data latches of the page buffer (e.g., Figure 3 D1, ..., D in the page buffer 302 N-1 and DC latch).

[0064] At 404, the peripheral circuit set generates a piece of level indicator data for 1 page corresponding to N pages of data (ie, a piece of N-bit data). Figure 6 A 4-bit piece of data (having 16 values ​​and in the form of Gray code) according to some aspects of the present disclosure is shown. For each of the 16 values, a level indicator DL ​​is generated as a parity check of the corresponding 4-bit binary value (i.e., LP, MP, UP, and XP). As an example, for Figure 6 The LV0 value in (1, 1, 1, 1) and the level indicator DL ​​are 0, which is the parity of (1, 1, 1, 1). In some embodiments, the level indicator data of 1 page can be temporarily stored in the internal latch of the page buffer (e.g., Figure 3 A bias level storage unit (DL) 310 configured to store 3BL bias information is provided in the embodiment of the present invention.

[0065] At 406 , the set of peripheral circuits performs single-level cell (SLC) programming (eg, a program operation) of the 1-page stripe level indicator data to store the stripe level indicator data in a memory cell (eg, a first cell) having a predefined address in the memory cell array.

[0066] At 408, the set of peripheral circuits performs multi-level cell (e.g., QLC (if N=4)) based coarse programming (e.g., a first programming operation) on the N pages of data to store the N pages of data in memory cells (e.g., second cells) of the memory cell array. In some embodiments, the stripe level indicator data can be stored in the same plane to be used to store the N pages of data, but can be stored in a different block from the block to be used to store the N pages of data. In some cases, the stripe level indicator data can be stored in the same block to store the N pages of data, but can be stored in a different page from the page to be used to store the N pages of data. In some cases, the stripe level indicator data and the N pages of data can be stored in memory cells coupled to the same word line or the same bit line.

[0067] Figure 5An example process 500 for reconstructing N pages of data using stored level indicator data and coarsely programmed N pages of data according to some aspects of the present disclosure is shown. In some embodiments, after reconstructing the N pages of data, the peripheral circuit set can perform fine programming (e.g., a second programming operation) on the reconstructed N pages of data (e.g., second data). The fine programming of the reconstructed N pages of data can be a second pass (e.g., a final programming pass) after the first pass of the two-pass programming operation of the N pages of data to store the N pages of data in the memory cell array. With the N pages of data reconstructed using the stored level indicator data and the coarsely programmed N pages of data, the peripheral circuit set does not need to obtain the N pages of data from the controller 106 after coarse programming the N pages of data and before fine programming the N pages of data. Therefore, storage resources at the controller 106 can be conserved.

[0068] At 502, a set of peripheral circuits performs an operation on a piece of level indicator data DL (eg, Figure 8 An SLC read of a level indicator data DL) in the .

[0069] At 504, the peripheral circuit set performs a first read operation based on a multi-level cell (e.g., based on QLC (if N=4)) to read N pages of coarsely programmed data as L- (e.g., third data) from the memory cell array. In some embodiments, given a Gray code set representing a piece of N-bit data corresponding to N pages of data, in order to read 2 bits corresponding to the piece of N-bit data during the first read operation, N The peripheral circuit set sets the read voltage to be equal to 2 N A first value (eg, a first set of read voltages) is determined as the center of a threshold voltage distribution of an (n-1)th value among the n values.

[0070] At 506, the peripheral circuit set performs a second read operation based on a multi-level cell (e.g., based on QLC (if N=4)) to read the coarsely programmed N pages of data as L+ (e.g., fourth data) from the memory cell array. In some embodiments, given a Gray code set representing a piece of N-bit data corresponding to N pages of data, in order to read the 2 bits corresponding to the piece of N-bit data during the second read operation, N The peripheral circuit set sets the read voltage to be equal to 2 N A second value (eg, a second set of read voltages) is determined as the center of the threshold voltage distribution for the nth value among the values.

[0071] Figure 7 Example read voltages when reading L- and L+ described in 504 and 506 above are shown according to some aspects of the present disclosure. Figure 7 Used to set the read voltage to read L- and L+ in order to reconstruct Figure 6 LP data shown in . For example, in order to perform a first read operation to read the third value (i.e., LV2) of the 16 values ​​of a piece of 4-bit data, the peripheral circuit set sets the read voltage R2- to the center of the threshold voltage distribution of the second value (i.e., LV1) of the 16 values. As another example, in order to perform a second read operation to read the third value (i.e., LV2) of the 16 values ​​of the piece of 4-bit data, the peripheral circuit set sets the read voltage R2+ to the center of the threshold voltage distribution of the third value (i.e., LV2) of the 16 values. The read voltages can be similarly set for R8-, R8+, R14-, and R14+, as shown in FIG. Figure 7 shown.

[0072] Return to Figure 5 At 508 , the peripheral circuit set regenerates N pages of data by combining a piece of level indicator data DL read at 502 , L− read at 504 , and L+ read at 506 by performing a logic operation ˜DL&L−+DL&L+.

[0073] Figure 8 Examples of DL, L-, L+, and regenerated LP data are shown according to some aspects of the present disclosure. Figure 6 The original LP data among the four pages of data (LP, MP, UP, and XP) is shown in FIG. As described above at 508 , the peripheral circuit set obtains the regenerated LP data by performing the logic operation ˜DL&L−+DL&L+. Figure 8 Shown Figure 8 The regenerated LP data in the last column of Figure 6 In some embodiments, the LP data in Figure 8 The MP, UP and XP data are regenerated in a manner similar to that shown in FIG for regenerating the LP data. When regenerating each of the MP, UP and XP data, the corresponding L- and L+ can be Figure 8 The L- and L+ shown in are different and may be derived from the Gray code associated with one piece of N-bit data for LP, MP, UP, and XP data (e.g., Figure 6 The logic operations used to regenerate each of the MP, UP, and XP data may be the same or different from the logic operations described above for the LP data.

[0074] Figure 9An example workflow for performing a two-pass programming operation for N pages of data according to some aspects of the present disclosure is shown. At 910, the controller 106 loads the N pages of data from the write buffer (system cache) 902 into the scrambler 904 in preparation for the first programming pass (e.g., coarse programming). The scrambled N pages of data then pass through the encoder 908 for low-density parity check (LDPC).

[0075] At 912, the memory device 104, for example, Figure 4 404 , generates level indicator data based on the encoded N pages of data from the encoder 908 , and then performs SLC-based programming of the level indicator data to store the level indicator data in the memory device 104 . Next, the memory device 104 performs a first programming pass (e.g., coarse programming) on ​​the encoded N pages of data from the encoder 908 to store the encoded N pages of data in the memory device 104 .

[0076] At 914, the memory device 104 may regenerate the N pages of data, e.g., according to 502 to 508, by internally pre-reading and combining the level indicator data stored in the memory device 104 and the coarsely programmed N pages of data stored in the memory device 104, in preparation for a second programming pass (e.g., fine programming) of the N pages of data.

[0077] The regenerated N pages of data then pass through the decoder 906, the scrambler 904, and the encoder 908 in the controller 106. At 916, the memory device 104 performs a second programming pass (e.g., fine programming) on ​​the encoded regenerated N pages of data from the encoder 908 to store the encoded regenerated N pages of data in the memory device 104 as encoded N pages of data.

[0078] Figure 10 An example of a flow chart of a method for multi-pass programming in a memory device according to some aspects of the present disclosure is shown. At 1002, peripheral circuitry of a memory device generates level indicator data based on first data to be stored in the memory device based on a first programming operation and a second programming operation.

[0079] At 1004 , the peripheral circuitry performs a program operation to store level indicator data in a first cell of a memory cell array of a memory device.

[0080] At 1006 , the peripheral circuit performs a first program operation to store first data in a second cell of a memory cell array of the memory device.

[0081] At 1008, the peripheral circuitry reads the level indicator data from the memory cell array.

[0082] At 1010 , the peripheral circuit retrieves the first data by reading the first data from the memory cell array.

[0083] At 1012 , the peripheral circuit generates second data based on the level indicator data and the retrieved first data.

[0084] At 1014 , the peripheral circuit performs a second program operation to store second data in a memory cell array of the memory device.

[0085] Although this specification contains many specific implementation details, these should not be interpreted as limitations on the scope of the claims, but rather as descriptions of features specific to particular implementations. Certain features described in this specification in the context of separate implementations may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented in multiple implementations separately or in any subcombination. Furthermore, although previously described features may be described as functioning in certain combinations and even initially claimed as such, in some cases, one or more features from the claimed combination may be deleted from the combination, and the claimed combination may be directed to a subcombination or a variant of the subcombination.

[0086] As used in this disclosure, the terms "a", "an" or "the" are intended to include one or more than one, unless the context clearly dictates otherwise. Unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the expressions or terms used in this disclosure (unless otherwise defined) are for descriptive purposes only and not for limiting purposes. The use of any section headings is intended to aid reading of the document and should not be construed as limiting; information associated with a section heading may appear within or outside that particular section.

[0087] As used in this disclosure, the terms "about" or "approximately" can allow for a degree of variability in a value or range, for example, within 10%, within 5%, or within 1% of the stated value or limit of the stated range.

[0088] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0089] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly stated as range limits, but also all individual values ​​or subranges encompassed within the range, as if each value and subrange were explicitly stated. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3%, and 4%) and subranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) within the indicated range. Unless otherwise indicated, the statement "X to Y" has the same meaning as "about X to about Y." Similarly, unless otherwise indicated, the statement "X, Y, or Z" has the same meaning as "about X, about Y, or about Z."

[0090] Specific embodiments of the subject matter have been described. It will be apparent to those skilled in the art that other embodiments, variations, and permutations of the described embodiments are within the scope of the appended claims. Although some operations are described in a particular order in the drawings or claims, it is not necessary to perform these operations in the particular order shown or in a sequential order to achieve the desired results, or it is not necessary to perform all of the operations shown (some operations may be considered optional). In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and are performed where deemed appropriate.

[0091] Furthermore, the various system modules and components in the previously described embodiments need not be separated or integrated in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0092] Therefore, the exemplary embodiments described above do not define or constrain the present disclosure. Other changes, substitutions, and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A method comprising: generating tier indicator data based on first data, wherein the first data is to be stored in a memory device based on a first programming operation and a second programming operation; performing a program operation to store the level indicator data in a first cell of a memory cell array of the memory device; and The first programming operation is performed to store the first data in a second cell of the memory cell array of the memory device.

2. The method according to claim 1, wherein The method further comprises: Prior to performing the programming operation to store the level indicator data in the first cell, the level indicator data is stored in one or more internal latches of a page buffer of the memory device.

3. The method according to claim 2, wherein: The method further comprises: The first data is stored in the one or more internal latches of the page buffer of the memory device before performing the programming operation to store the level indicator data in the first cell and before performing the first programming operation to store the first data in the second cell.

4. The method according to any one of claims 1 to 3, wherein Generating the level indicator data based on the first data includes generating the level indicator data based on parity information of the first data.

5. The method according to any one of claims 1 to 4, wherein Performing the program operation includes performing the program operation to store the level indicator data in a single-level cell (SLC) mode.

6. The method according to any one of claims 1 to 5, wherein After performing the first programming operation, the method further includes: reading the level indicator data from the memory cell array; retrieving the first data by reading the first data from the memory cell array; generating second data based on the level indicator data and the retrieved first data; and The second programming operation is performed to store the second data in the memory cell array of the memory device.

7. The method according to claim 6, wherein: Retrieving the first data by reading the first data from the memory cell array includes: performing a first read operation of the second cell using a first set of read voltages to generate third data; and A second read operation of the second cell is performed using a second set of read voltages to generate fourth data, and wherein generating the second data based on the level indicator data and the retrieved first data includes generating the second data based on the level indicator data, the third data, and the fourth data.

8. The method according to any one of claims 1 to 7, wherein The first cell and the second cell are coupled to a same bit line of the memory cell array.

9. The method according to any one of claims 1 to 8, wherein The level indicator data and the first data are programmed into different pages of the same block of the memory cell array.

10. The method according to any one of claims 1 to 9, wherein The level indicator data and the first data are programmed into different blocks of a same plane of the memory cell array.

11. A memory device comprising: memory cell array; as well as a peripheral circuit coupled to the memory cell array and configured to perform operations comprising: generating tier indicator data based on first data, wherein the first data is to be stored in the memory device based on a first programming operation and a second programming operation; performing a program operation to store the level indicator data in a first cell of the memory cell array of the memory device; and The first programming operation is performed to store the first data in a second cell of the memory cell array of the memory device.

12. The memory device according to claim 11, wherein The operations further include: Prior to performing the programming operation to store the level indicator data, the level indicator data is stored in one or more internal latches of a page buffer of the memory device.

13. The memory device according to claim 12, wherein: The operations further include: The first data is stored in the one or more internal latches of the page buffer of the memory device before performing the programming operation to store the level indicator data in the first cell and before performing the first programming operation to store the first data in the second cell.

14. The memory device according to any one of claims 11 to 13, wherein: Generating the level indicator data based on the first data includes generating the level indicator data based on parity information of the first data.

15. The memory device according to any one of claims 11 to 14, wherein: The first cell and the second cell are coupled to a same bit line of the memory cell array.

16. The memory device according to any one of claims 11 to 15, wherein: The level indicator data and the first data are programmed into different pages of the same block of the memory cell array.

17. The memory device according to any one of claims 11 to 16, wherein: The level indicator data and the first data are programmed into different blocks of a same plane of the memory cell array.

18. A memory system comprising: A memory device, the memory device comprising: a memory cell array; and a peripheral circuit coupled to the memory cell array and configured to perform operations comprising: generating tier indicator data based on first data, wherein the first data is to be stored in the memory device based on a first programming operation and a second programming operation; performing a program operation to store the level indicator data in a first cell of the memory cell array of the memory device; and performing the first programming operation to store the first data in a second cell of the memory cell array of the memory device; and A controller is coupled to the memory device and configured to send one or more signals to the memory device to initiate the operation.

19. The memory system of claim 18, wherein: The controller is configured to perform one or more operations, the one or more operations comprising: sending a first signal to the memory device to initiate the programming operation to store the level indicator data and to initiate the first programming operation to store the first data; sending a second signal to the memory device to initiate a read operation of reading second data from the memory device, wherein the memory device generates the second data using the level indicator data and the first data; and A third signal is sent to the memory device to initiate the second programming operation to store the second data.

20. The memory system of claim 19, wherein: The controller further includes a decoder and an encoder, and the one or more operations further include: receiving the second data from the memory device after sending the second signal to the memory device to initiate the read operation of reading the second data; decoding the second data using the decoder; and The decoded second data is encoded into fifth data using the encoder, wherein sending the third signal to the memory device to initiate the second programming operation to store the second data includes: sending the third signal to the memory device to initiate a programming operation to store the fifth data in the memory device.

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