Memory device including dummy memory blocks

Abstract

A memory device includes a memory cell structure including a plurality of memory blocks, where the plurality of memory blocks includes at least one dummy memory block and a plurality of main memory blocks, each of the plurality of main memory blocks includes a string group of a first type, and each of the plurality of main memory blocks includes a string group of a second type. The at least one dummy memory block includes a string group of a first type and a string group of a second type, the string group of the first type including a plurality of first vertical channels connected to a first string select line and connected to a bit line, and the string group of the second type including a plurality of second vertical channels connected to a second string select line and connected to a bit line. The plurality of second vertical channels are connected to the second string select line and are not connected to the bit line.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2024-0043670 filed on March 29, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory, and more particularly, to a memory device including a dummy memory block. Background Art

[0003] Semiconductor memories are divided into volatile memories, such as SRAM and DRAM, in which stored data is lost when power is interrupted; and non-volatile memories, such as flash memory, PRAM, MRAM, RRAM, and FRAM, which retain stored data even when power is interrupted.

[0004] With the recent increase in the number of multifunctional information and communication devices, large-capacity and highly integrated memory devices are required. To achieve high integration, vertical memory devices comprising memory cells arranged vertically in a three-dimensional space have been proposed. As the scale of memory devices decreases and their structures change due to their high integration, various previously unknown problems have been discovered. These newly discovered problems may damage the strings included in the memory devices and may also damage the data stored in the memory devices. Summary of the Invention

[0005] The inventive concept provides a memory device that is reduced in size and includes a dummy memory block.

[0006] According to one aspect of the inventive concept, a memory device is provided, including a memory cell structure, the memory cell structure including a plurality of memory blocks, wherein the plurality of memory blocks include a first dummy memory block and a plurality of main memory blocks, each of the plurality of main memory blocks includes a first type of string group, the first dummy memory block includes a first type of string group and a second type of string group, the first type of string group includes a plurality of first vertical channels, the plurality of first vertical channels are connected to a first string selection line and to a bit line, and the second type of string group includes a plurality of second vertical channels, the plurality of second vertical channels are connected to a second string selection line and are not connected to the bit line (e.g., do not have a signal path to the bit line and / or cannot be connected to the bit line).

[0007] According to another aspect of the inventive concept, a memory device is provided, including a memory cell structure, the memory cell structure including a plurality of memory blocks, wherein the plurality of memory blocks include a first dummy memory block, a plurality of main memory blocks, and a second dummy memory block, the first dummy memory block being arranged on a first side of the plurality of main memory blocks, and the second dummy memory block being arranged on a second side of the plurality of main memory blocks, the second side facing the first side in a first direction, the first dummy memory block being a single memory block including a first type of string group and a second type of string group, the second dummy memory block being a single memory block including a first type of string group and a second type of string group, each of the plurality of main memory blocks including a first type of string group, the first type of string group including a plurality of vertical channels connected to a first string selection line and to a bit line, and the second type of string group including a plurality of second vertical channels connected to a second string selection line and not connected to the bit line (e.g., not having a signal path to the bit line and / or being unable to connect to the bit line).

[0008] According to another aspect of the inventive concept, a memory device is provided, including a memory cell structure including a plurality of memory blocks, wherein the plurality of memory blocks include a first dummy memory block and a plurality of main memory blocks, each of the plurality of main memory blocks includes a plurality of first vertical channels connected to bit lines, and the first dummy memory block includes a plurality of first vertical channels connected to the bit lines and a plurality of second vertical channels not connected to the bit lines (e.g., having no signal paths to the bit lines and / or being unable to be connected to the bit lines), and data is stored in a memory cell included in each of the plurality of first vertical channels of the first dummy memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory device according to an embodiment;

[0011] Figure 2 It shows Figure 1 A detailed block diagram of a memory cell array;

[0012] Figure 3 is used to describe Figure 2 Graph of the string group;

[0013] Figure 4A According to the embodiment Figure 2 Equivalent circuit diagram of the main memory block;

[0014] Figure 4B According to the embodiment Figure 2 An equivalent circuit diagram of a virtual memory block;

[0015] Figure 5A is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of a storage device;

[0016] Figure 5B It is along Figure 5A A cross-sectional view taken along line AA';

[0017] Figure 5C It is along Figure 5A A cross-sectional view taken along line BB';

[0018] Figure 5D It is along Figure 5A A cross-sectional view taken along line D-D';

[0019] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A detailed block diagram of a memory cell array;

[0020] Figure 7 is used to describe Figure 6 Graph of the string group;

[0021] Figure 8A is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of a storage device;

[0022] Figure 8B It is along Figure 8A A cross-sectional view taken along line EE';

[0023] 9A to 9D According to some embodiments Figure 8A A cross-sectional view taken along line EE';

[0024] Figure 10 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A detailed block diagram of a memory cell array;

[0025] Figure 11 is a flowchart illustrating an operating method of a memory device according to an embodiment;

[0026] Figure 12A is a timing diagram of voltages applied to lines by a memory device during a pre-program operation and an erase operation according to an embodiment;

[0027] Figure 12B is a timing diagram of voltages applied to lines by a memory device during a pre-program operation and an erase operation according to an embodiment;

[0028] Figure 12C is a timing diagram of voltages applied to lines by a memory device during a pre-program operation and an erase operation according to an embodiment;

[0029] Figure 13A It shows Figure 1 a circuit diagram of a first dummy memory block among a plurality of memory blocks included in a memory cell array;

[0030] Figure 13B It shows Figure 13A A vertical cross-sectional view of a first cell string in the cell strings;

[0031] Figure 13C It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0032] Figure 13D It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0033] Figure 14A It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0034] Figure 14B It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0035] Figure 14C It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0036] Figure 14D It shows Figure 1 A timing diagram of a pre-programming operation of a memory device;

[0037] Figure 15A It shows Figure 1 a circuit diagram of a second dummy memory block among a plurality of memory blocks included in a memory cell array;

[0038] Figure 15B It shows Figure 15A A vertical cross-sectional view of a first cell string in the cell strings;

[0039] Figure 15C is a flowchart illustrating an operating method of a memory device according to an embodiment;

[0040] Figure 15D It shows Figure 1 A timing diagram of a first pre-programming operation of a memory device;

[0041] Figure 15E It shows Figure 1 A timing diagram of a second pre-programming operation of a memory device;

[0042] Figure 16 is a block diagram illustrating a solid state drive (SSD) system to which a memory device according to an embodiment is applied; and

[0043] Figure 17 is a cross-sectional view of a memory device having a B-VNAND structure according to an embodiment. DETAILED DESCRIPTION

[0044] Hereinafter, the embodiments will be described clearly and in detail so that those skilled in the art can easily implement the inventive concept.

[0045] Figure 1 is a block diagram illustrating a memory device 100 according to an embodiment.

[0046] refer to Figure 1 , the memory device 100 may include an input / output circuit 110, a control logic circuit 120, a memory cell array 130, a page buffer circuit 140, a voltage generator 150, and a row decoder 160. Figure 1 Although not shown, the memory device 100 may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

[0047] The control logic circuit 120 may generally control various operations of the memory device 100. The control logic circuit 120 may output various control signals in response to a command CMD and / or an address ADDR from the input / output circuit 110. For example, the control logic circuit 120 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0048] The memory cell array 130 may include a plurality of memory blocks, and each of the plurality of memory blocks may include a plurality of memory cells. The memory cell array 130 may be connected to the page buffer circuit 140 via the bit lines BL, and may be connected to the row decoder 160 via the word lines WL, the string select lines SSL, and the ground select lines GSL.

[0049] In an embodiment, memory cell array 130 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include multiple cell strings. Each cell string may include memory cells connected to word lines WL stacked vertically on a substrate. U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are all incorporated herein by reference. In an embodiment, memory cell array 130 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include multiple cell strings arranged in rows and columns.

[0050] In an embodiment, the plurality of memory blocks may include a plurality of main memory blocks and at least one dummy memory block. The main memory block may refer to a block including only memory cells capable of storing data, and the dummy memory block may refer to a single memory block including memory cells that cannot store data (e.g., erased cells of a nonvolatile memory).

[0051] In an embodiment, a main memory block may include memory cells storing data. All cell strings included in the main memory block may be connected to a bit line BL. All memory cells included in the main memory block may be connected to a bit line BL.

[0052] In an embodiment, a dummy memory block may include both memory cells that store data and memory cells that do not store data within a single memory block (e.g., erased cells of a nonvolatile memory). A first portion of the cell strings included in the dummy memory block may be connected to a bit line BL. A second portion of the cell strings included in the dummy memory block may not be connected to a bit line BL. A first portion of the memory cells included in the dummy memory block may be connected to a bit line BL. A second portion of the memory cells included in the dummy memory block may not be connected to a bit line BL. For example, a first portion of the memory cells in the dummy memory block may be capable of storing data by being connected to a bit line BL, while a second portion of the memory cells in the dummy memory block may not be configured to store data.

[0053] For example, the presence of memory cells in a dummy memory block that do not have a signal path to any bit lines BL (i.e., cannot be connected to any bit lines BL) and / or are incapable of storing data can address process issues by providing physical distance. In another example, as semiconductor processing technology advances, the distance required to alleviate such process issues may decrease, and therefore fewer dummy memory cells may be required. Therefore, in some embodiments, a dummy memory block can include a combination of memory cells capable of storing data (e.g., connected to bit lines BL) and memory cells not configured to store data (e.g., do not have a signal path to any bit lines BL).

[0054] In another embodiment, the dummy memory block may include only memory cells that do not store data. All cell strings included in the dummy memory block may not be connected to the bit lines BL. All memory cells included in the dummy memory block may not be connected to the bit lines BL.

[0055] The page buffer circuit 140 may include a plurality of page buffers. The page buffer circuit 140 may be connected to the memory cell array 130 via bit lines BL. The plurality of page buffers of the page buffer circuit 140 may be connected to the memory cells via the plurality of bit lines BL, respectively. The page buffer circuit 140 may select at least one bit line BL from the bit lines BL in response to a column address Y-ADDR. The page buffer circuit 140 may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a programming operation, the page buffer circuit 140 may apply a bit line voltage corresponding to the data to be programmed via the selected bit line BL. During a read operation, the page buffer circuit 140 may detect the current or voltage of the selected bit line BL to detect the data stored in the memory cell.

[0056] The voltage generator 150 can generate various types of voltages for performing program, read and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 150 can generate a program voltage, a pre-program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as the word line voltage VWL.

[0057] The row decoder 160 may select one of the plurality of word lines WL in response to the row address X-ADDR and may select one of the plurality of string select lines SSL. For example, during a program operation, the row decoder 160 may apply a program voltage and a program verification voltage to the selected word line WL, and may apply a read voltage to the selected word line WL during a read operation.

[0058] The cell string may be damaged due to repeated erase operations. Specifically, repeated erase operations on memory cells that have not been programmed may damage the memory cells. To prevent such damage to the cell string due to the erase operation, in an embodiment, the memory device 100 may perform a pre-programming operation. For example, the memory device 100 may perform a pre-programming operation on the memory cells before performing the erase operation.

[0059] In an embodiment, the row decoder 160 may perform a pre-program operation and an erase operation. The row decoder 160 may perform a pre-program operation by applying a program voltage or a pre-program voltage. The row decoder 160 may perform an erase operation by applying an erase voltage.

[0060] In an embodiment, the memory device 100 may perform a pre-program operation and an erase operation on a dummy memory block. For example, the row decoder 160 may perform a pre-program operation on the dummy memory block. The row decoder 160 may perform an erase operation on the dummy memory block.

[0061] For example, row decoder 160 may apply a program voltage or a pre-program voltage to word line WL to perform such a pre-programming operation. The program voltage may increase the threshold voltage of the memory cell to be programmed. For example, row decoder 160 may apply a pre-program voltage VPGM to word line WL connected to each string group of the second type T2 in the dummy memory block for which the pre-programming operation is to be performed. Memory device 100 may apply the pre-program voltage VPGM to word line WL connected to the second channel structure CS2.

[0062] The memory device 100 may apply a pass voltage VPASS to the ground selection line GSL connected to each string group of the second type T2. The pass voltage VPASS may be a voltage for turning on the ground selection transistor. The memory device 100 may apply a ground voltage VSS or a ground voltage GND to the common source line CSL connected to each string group of the second type T2. Figure 11 and 12A to 12C A detailed description of the pre-programming operation is given.

[0063] As described above, the memory device 100 according to an embodiment may include multiple main memory blocks and at least one dummy memory block. For example, the memory cell array 130 (or cell area) (or memory cell structure) may include multiple main memory blocks and at least one dummy memory block. The cell strings included in at least one string group included in the dummy memory block may be electrically connected to bit lines. Therefore, data can be stored in some memory cells of the dummy memory block. For example, the memory device 100 may replace some dummy memory blocks with spare blocks and use these spare blocks. Therefore, compared to other memory devices with fewer active memory cells, the disclosed memory device 100 can provide improvements, such as reducing chip size or increasing storage space.

[0064] According to an embodiment, the memory device 100 can perform a pre-programming operation on a cell string that is not connected to a bit line (e.g., does not have a signal path to a bit line and / or cannot be connected to a bit line) and is included in a dummy memory block. In this example, to perform the pre-programming operation and / or apply a ground voltage to the cell strings in the dummy memory block that are not connected to a bit line (e.g., does not have a signal path to a bit line and / or cannot be connected to a bit line), the memory device 100 can apply a pass voltage to a ground select line connected to such cell strings that are not connected to a bit line and are included in the dummy memory block, and apply a ground voltage to a common source line connected to the cell strings that are not connected to a bit line and are included in the dummy memory block. Therefore, damage to the cell strings caused by repeated erase operations can be prevented.

[0065] Hereinafter, for the sake of convenience of description, terms such as "memory cell array", "memory cell structure" and "cell region" may be used interchangeably. Depending on the context of the embodiment, these terms may have the same meaning or different meanings, and the meaning of each term will be understood according to the context of the embodiment to be described.

[0066] Figure 2 It shows Figure 1 Detailed block diagram of the memory cell array 130.

[0067] refer to Figure 1 and Figure 2 , the memory cell array 130 may include a plurality of memory blocks. The memory cell array 130 may include a dummy memory block BLKd and a main memory block BLKm. For example, the memory cell array 130 may include at least one dummy memory block BLKd and a plurality of main memory blocks BLKm.

[0068] The dummy memory block BLKd may include multiple channel structures CS (or channel holes) (or cell strings). For example, the channel structures may be channel pillars, also referred to as vertical channels. The dummy memory block BLKd may include multiple string groups SG. A string group SG may represent string cells or channel structures connected to the same string select line SSL.

[0069] For example, the dummy memory block BLKd may include a first string group SG1 to a fourth string group SG4. The plurality of channel structures CS included in the dummy memory block BLKd may be divided into a plurality of string groups. For example, the plurality of channel structures CS included in the dummy memory block BLKd may be divided into a first string group SG1 to a fourth string group SG4. For example, Figure 2 Although four string groups SG1 to SG4 are shown in the embodiment of FIG, the scope of the present inventive concept is not limited thereto, and the number of string groups may be increased or decreased according to implementation methods.

[0070] In an example, the string groups within each memory block (e.g., the first to fourth string groups SG1 to SG4) can be spaced apart at a constant distance or pitch. The spacing between adjacent memory blocks (e.g., the spacing between adjacent main memory blocks BLKm or the spacing between a dummy memory block BLKd and an adjacent main memory block BLKm) can exceed the spacing between string groups within a single memory block (e.g., the spacing between the first to fourth string groups SG1 to SG4). Alternatively or additionally, the spacing between a dummy memory block BLKd and an immediately adjacent string group of an adjacent main memory block BLKm can exceed the spacing between string groups within a single memory block. For example, the spacing between the string group SG4 shown at the bottom of the dummy memory block BLKd and the immediately adjacent string group SG1 shown at the top of the main memory block BLKm can exceed the spacing between the first to fourth string groups SG1 to SG4 within the dummy memory block BLKd.

[0071] The first string group SG1 of the dummy memory block BLKd may include a cell string or a channel structure CS connected to a first string selection line SSL1. The second string group SG2 of the dummy memory block BLKd may include a channel structure CS connected to a second string selection line SSL2. The third string group SG3 of the dummy memory block BLKd may include a channel structure CS connected to a third string selection line SSL3. The fourth string group SG4 of the dummy memory block BLKd may include a channel structure CS connected to a fourth string selection line SSL4.

[0072] The main memory block BLKm may include a plurality of channel structures CS. The main memory block BLKm may include a plurality of string groups. The main memory block BLKm may include a first string group SG1 to a fourth string group SG4. The plurality of channel structures CS included in the main memory block BLKm may be divided into a plurality of string groups. For example, the plurality of channel structures CS included in the main memory block BLKm may be divided into a first string group SG1 to a fourth string group SG4. For example, Figure 2 Although four string groups SG1 to SG4 are shown in the embodiment of FIG, the scope of the present inventive concept is not limited thereto, and the number of string groups may be increased or decreased according to implementation methods.

[0073] The first string group SG1 of the main memory block BLKm may include a cell string or a channel structure CS connected to a first string selection line SSL1. The second string group SG2 of the main memory block BLKm may include a channel structure CS connected to a second string selection line SSL2. The third string group SG3 of the main memory block BLKm may include a channel structure CS connected to a third string selection line SSL3. The fourth string group SG4 of the main memory block BLKm may include a channel structure CS connected to a fourth string selection line SSL4.

[0074] The channel structure CS may include a first channel structure (e.g., a channel pillar or a vertical channel) CS1 and a second channel structure (e.g., a channel pillar or a vertical channel) CS2. The first channel structure CS1 may indicate a channel structure CS connected to a bit line BL. The second channel structure CS2 may indicate a channel structure CS not connected to a bit line BL (e.g., not having a signal path to a bit line BL and / or not being able to connect to a bit line BL). For example, the second channel structure CS2 may be a dummy structure.

[0075] The first channel structure CS1 may be connected to the bit lines BL. For example, the first channel structure CS1 may be connected to the first to fourth bit lines BL1 to BL4. Figure 2 In the embodiment shown in FIG. 1 , four bit lines BL1 to BL4 are shown, but the scope of the present inventive concept is not limited thereto, and the number of bit lines may be increased or decreased depending on the implementation method. Some of the first channel structures CS1 may be connected to the first bit line BL1, and other of the first channel structures CS1 may be connected to the second bit line BL2. Some of the first channel structures CS1 may be connected to the third bit line BL3, and other of the first channel structures CS1 may be connected to the fourth bit line BL4. The second channel structure CS2 may not be connected to a bit line BL.

[0076] In an embodiment, the main memory block BLKm may include only the first channel structure CS1. For example, the main memory block BLKm may include only the channel structure CS connected to the bit line. For example, the main memory block BLKm may include only the memory cells connected to the bit line BL.

[0077] In an embodiment, a dummy memory block BLKd may include both a first channel structure CS1 and a second channel structure CS2. The dummy memory block BLKd may include both a channel structure CS connected to a bit line BL and a channel structure CS not connected to the bit line BL. The dummy memory block BLKd may include both memory cells connected to the bit line BL (e.g., having a signal path to the bit line BL) and memory cells not connected to the bit line BL (e.g., not having a signal path to the bit line BL and / or being unable to connect to the bit line BL).

[0078] Each of the string groups SG1 to SG4 of each of the main memory blocks BLKm may include only the first channel structure CS1. The first string group SG1 of the dummy memory block BLKd may include the second channel structure CS2. Each channel structure CS included in the first string group SG1 of the dummy memory block BLKd may not be connected to the bit line BL. The second string group SG2 of the dummy memory block BLKd may include the second channel structure CS2. Each channel structure CS included in the second string group SG2 of the dummy memory block BLKd may not be connected to the bit line BL. The third string group SG3 of the dummy memory block BLKd may include the second channel structure CS2. Each channel structure CS included in the third string group SG3 of the dummy memory block BLKd may not be connected to the bit line BL. The fourth string group SG4 of the dummy memory block BLKd may include the first channel structure CS1. Each channel structure CS included in the fourth string group SG4 of the dummy memory block BLKd may be connected to the bit line BL. Therefore, in this example, the dummy memory block BLKd may include a combination of string groups (eg, SG1 to SG3) not connected to the bit lines BL and string groups (eg, SG4) connected to the bit lines BL. In contrast, the main memory block BLKm may include only string groups connected to the bit lines BL.

[0079] Specifically, as described above, each channel structure included in at least one of the first to fourth string groups SG1 to SG4 of the dummy memory block BLKd can be connected to the bit line BL. The fourth string group SG4 of the dummy memory block BLKd can store data. Each channel structure included in the fourth string group SG4 of the dummy memory block BLKd can store data. Each memory cell included in the fourth string group SG4 of the dummy memory block BLKd can store data. The channel structures included in the first to third string groups SG1 to SG3 of the dummy memory block BLKd cannot store data. For example, the first channel structure CS1 can store data, and the second channel structure CS2 cannot store data.

[0080] Figure 3 is a description Figure 2 A table of channel structure types of string groups SG.

[0081] refer to Figure 1 、 Figure 2 、 Figure 3, the string group SG may be one of a first type T1 string group SG or a second type T2 string group SG. The string group SG may be of the first type T1 or the second type T2. The first type T1 may indicate a string group SG including a first channel structure CS1, and the second type T2 may indicate a string group SG including a second channel structure CS2. The string group SG of the first type T1 may be a string group SG including a channel structure CS connected to a bit line, and the string group SG of the second type T2 may be a string group SG including a channel structure CS not connected to a bit line.

[0082] The first string group SG1 of the dummy memory block BLKd may be the second type T2, the second string group SG2 of the dummy memory block BLKd may be the second type T2, the third string group SG3 of the dummy memory block BLKd may be the second type T2, and the fourth string group SG4 of the dummy memory block BLKd may be the first type T1.

[0083] The first string group SG1 of the main memory block BLKm may be the first type T1, the second string group SG2 of the main memory block BLKm may be the first type T1, the third string group SG3 of the main memory block BLKm may be the first type T1, and the fourth string group SG4 of the main memory block BLKm may be the first type T1.

[0084] In the dummy memory block BLKd, the string group SG adjacent to the main memory block BLKm (ie, the fourth string group SG4) may be of the first type T1. In the dummy memory block BLKd, the string group SG away from the edge of the memory cell array 130 may be of the first type T1.

[0085] Each of all first to fourth string groups SG1 to SG4 included in the main memory block BLKm may be of the first type T1. The main memory block BLKm may include only string groups SG of the first type T1. The main memory block BLKm may include only string groups SG including channel structures CS connected to bit lines.

[0086] Each of the first to fourth string groups SG1 to SG4 included in the dummy memory block BLKd may be of the first type T1 or the second type T2. The dummy memory block BLKd may include at least one string group SG of the first type T1 and a plurality of string groups SG of the second type T2. The dummy memory block BLKd may include a string group SG including a channel structure CS connected to a bit line and a string group SG including a channel structure CS not connected to a bit line.

[0087] Therefore, in this example, the string groups included in the dummy memory block BLKd may include a combination of string groups of the first type T1 and string groups of the second type T2, while all string groups included in the main memory block BLKm may be of the first type T1.

[0088] In an embodiment, the memory cells included in the string group SG of the second type T2 of the dummy memory block BLKd may be dummy memory cells that do not serve as memory cells. The memory cells included in the string group SG of the first type T1 of the dummy memory block BLKd may be the same as or similar to the memory cells included in the plurality of main memory blocks BLKm. The memory cells included in the string group SG of the first type T1 of the dummy memory block BLKd may perform the same functions as the memory cells included in the plurality of main memory blocks BLKm. The memory cells included in the string group SG of the first type T1 of the dummy memory block BLKd may store data. On the other hand, the memory cells included in the string group SG of the second type T2 of the dummy memory block BLKd cannot store data. The memory cells included in the string group SG of the second type T2 of the dummy memory block BLKd may be memory cells to which data is not written.

[0089] Figure 4A According to the embodiment Figure 2 Equivalent circuit diagram of the main memory block BLKm.

[0090] Figure 4A The main memory block BLKm shown in represents a three-dimensional (3D) memory block formed on a substrate in a 3D structure. For example, a plurality of memory cell strings included in the main memory block BLKm may be formed in a direction perpendicular to the substrate.

[0091] refer to Figure 4A The main memory block BLKm may include a plurality of memory cell strings NS11 to NS44 connected between first to fourth bit lines BL1 to BL4 and a common source line CSL. Each of the plurality of memory cell strings NS11 to NS44 may include a string selection transistor SST, a plurality of memory cells MC1, MC2, ..., and MC8, and a ground selection transistor GST. Figure 4A It is illustrated that each of the plurality of memory cell strings NS11 to NS44 includes eight memory cells MC1 , MC2 , . . . , and MC8 , but the inventive concept is not necessarily limited thereto and may include any number of memory cells.

[0092] The string selection transistor SST can be connected to the corresponding first to fourth string selection lines SSL1, SSL2, SSL3 and SSL4. A plurality of memory cells MC1, MC2, ... and MC8 can be connected to the corresponding gate lines GTL1, GTL2, ... and GTL8, respectively. The gate lines GTL1, GTL2, ... and GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ... and GTL8 can correspond to dummy word lines. The ground selection transistor GST can be connected to the corresponding ground selection lines GSL1, GSL2, GSL3 and GSL4. The string selection transistor SST can be connected to the corresponding first to fourth bit lines BL1 to BL4, and the ground selection transistor GST can be connected to the common source line CSL.

[0093] Word lines (eg, WL1 ) of the same height may be commonly connected, and ground selection lines GSL1 , GSL2 , GSL3 , and GSL4 and first to fourth string selection lines SSL1 , SSL2 , SSL3 , and SSL4 may be separated. Figure 4A The main memory block BLKm is shown connected to eight gate lines GTL1 , GTL2 , . . . , GTL8 and four bit lines BL1 , BL2 , BL3 , and BL4 , but the inventive concept is not necessarily limited thereto and may include any number of gate lines and / or bit lines.

[0094] The first string group SG1 of the main memory block BLKm may include cell strings NS11, NS12, NS13 and NS14, the second string group SG2 of the main memory block BLKm may include cell strings NS21, NS22, NS23 and NS24, the third string group SG3 of the main memory block BLKm may include cell strings NS31, NS32, NS33 and NS34, and the fourth string group SG4 of the main memory block BLKm may include cell strings NS41, NS42, NS43 and NS44.

[0095] A cell string may be an equivalent circuit diagram of a channel structure CS. A cell string may correspond to the channel structure CS. Hereinafter, for ease of description, terms such as "channel structure," "cell string," "channel pillar," and "vertical channel" may be used interchangeably. Depending on the context of the embodiment, these terms may have the same meaning or different meanings, and the meaning of each term will be understood based on the context of the embodiment to be described.

[0096] Figure 4B According to the embodiment Figure 2 Equivalent circuit diagram of the virtual memory block BLKd.

[0097] Figure 4BThe dummy memory block BLKd shown in FIG. 3 represents a 3D memory block formed on a substrate in a 3D structure. For example, a plurality of memory cell strings (also referred to as cell strings) included in the memory block BLKd may be formed in a direction perpendicular to the substrate.

[0098] refer to Figure 4B The dummy memory block BLKd may include a plurality of memory cell strings NS11 to NS44. The dummy memory block BLKd may include memory cell strings NS11 to NS33 connected to a common source line GSL. The dummy memory block BLKd may include memory cell strings NS41 to NS44 connected between the common source line GSL and first to fourth bit lines BL1 to BL4. Each of the plurality of memory cell strings NS11 to NS44 may include a string select transistor SST, a plurality of memory cells MC1, MC2, ..., and MC8, and a ground select transistor GST. Figure 4B It is illustrated that each of the plurality of memory cell strings NS11 to NS44 includes eight memory cells MC1 , MC2 , . . . , and MC8 , but the inventive concept is not necessarily limited thereto and may include any number of memory cells.

[0099] The string selection transistor SST can be connected to the corresponding first to fourth string selection lines SSL1, SSL2, SSL3 and SSL4. A plurality of memory cells MC1, MC2, ... and MC8 can be connected to corresponding gate lines GTL1, GTL2, ... and GTL8, respectively. The gate lines GTL1, GTL2, ... and GTL8 can correspond to word lines, and some of the gate lines GTL1, GTL2, ... and GTL8 can correspond to dummy word lines. The ground selection transistor GST can be connected to the corresponding ground selection lines GSL1, GSL2, GSL3 and GSL4. The string selection transistor SST connected to the fourth string selection line SSL4 can be connected to the corresponding first to fourth bit lines BL1 to BL4. The string selection transistors SST connected to the first to fourth string selection lines SSL1 to SSL4 may not be connected to the corresponding first to fourth bit lines BL1 to BL4. The ground selection transistor GST can be connected to a common source line CSL.

[0100] Word lines (eg, WL1 ) of the same height may be commonly connected, and ground selection lines GSL1 , GSL2 , GSL3 , and GSL4 and first to fourth string selection lines SSL1 , SSL2 , SSL3 , and SSL4 may be separated. Figure 4B The dummy memory block BLKd is shown connected to eight gate lines GTL1 , GTL2 , . . . , GTL8 and four bit lines BL1 , BL2 , BL3 , and BL4 , but the inventive concept is not necessarily limited thereto and may include any number of gate lines and / or bit lines.

[0101] The first string group SG1 of the dummy memory block BLKd may include cell strings NS11, NS12, NS13 and NS14, the second string group SG2 of the dummy memory block BLKd may include cell strings NS21, NS22, NS23 and NS24, the third string group SG3 of the dummy memory block BLKd may include cell strings NS31, NS32, NS33 and NS34, and the fourth string group SG4 of the dummy memory block BLKd may include cell strings NS41, NS42, NS43 and NS44.

[0102] As described above, the cell strings NS11, NS12, NS13, and NS14 of the first string group SG1 of the dummy memory block BLKd may not be connected to the first to fourth bit lines BL1 to BL4. The cell strings NS21, NS22, NS23, and NS24 of the second string group SG2 of the dummy memory block BLKd may not be connected to the first to fourth bit lines BL1 to BL4. The cell strings NS31, NS32, NS33, and NS34 of the third string group SG3 of the dummy memory block BLKd may not be connected to the first to fourth bit lines BL1 to BL4. The cell strings NS41, NS42, NS43, and NS44 of the fourth string group SG4 of the dummy memory block BLKd may be connected to the first to fourth bit lines BL1 to BL4. In an example, the memory device 100 may store data in the cell strings NS41, NS42, NS43, and NS44 of the fourth string group SG4 of the dummy memory block BLKd.

[0103] Figure 5A is a diagram showing a method according to an embodiment of the present invention. Figure 1 1 is a plan view of a memory device 100. Figure 5B It is along Figure 5A A cross-sectional view taken along line AA'. Figure 5C It is along Figure 5A A cross-sectional view taken along line BB'. Figure 5D It is along Figure 5A A cross-sectional view taken along line D-D'.

[0104] refer to Figure 2 、 Figure 5A 、 Figure 5B 、 Figure 5C and Figure 5D, the dummy memory block BLKd can be arranged on one side of the main memory block BLKm. The dummy memory block BLKd and the plurality of main memory blocks BLKm can be arranged in the second direction D2. The string groups SG1, SG2, SG3, and SG4 can be arranged to be spaced apart from each other in the second direction D2. The string group of the first type T1 of the dummy memory block BLKd can be arranged adjacent to the plurality of main memory blocks BLKm. The string group of the first type T1 of the dummy memory block BLKd can be arranged away from the edge area of ​​the memory cell array 130. The first bit line BL1 to the fourth bit line BL4 can be arranged to be spaced apart from each other in the first direction D1. The first bit line BL1 to the fourth bit line BL4 can extend along the second direction D2.

[0105] The memory device 100 may include a plurality of memory blocks. The plurality of memory blocks may include a plurality of main memory blocks BLKm and at least one dummy memory block BLKd. In an embodiment, the dummy memory block BLKd may be provided on at least one side of the plurality of main memory blocks BLKm.

[0106] In an embodiment, a dummy memory block BLKd may be provided on both sides of a plurality of main memory blocks BLKm. The dummy memory block BLKd may be formed to have the same structure as or a similar structure to the plurality of main memory blocks BLKm. However, the dummy memory block BLKd may include a plurality of dummy memory cells that are not used as memory cells (e.g., not configured to store data and / or not configured to store any data that can be accessed by a device outside the memory device 100).

[0107] In some examples, multiple dummy memory cells may belong to a dummy cell string, e.g., a cell string that is not connected to a bit line. Such a dummy cell string may be connected to a string select line and a CSL, e.g., via appropriate string select transistors and / or ground select transistors. For example, a dummy cell string may include corresponding string select transistors and ground select transistors and may be connected to them.

[0108] The memory device 100 may include a memory cell structure (eg, a memory cell system) CST. The memory cell structure CST may include a lower wiring structure LST, a first gate stack structure GST1, a second gate stack structure GST2, a third gate stack structure GST3, a first channel structure CS1, a second channel structure CS2, a common source plate CSP, etc.

[0109] For example, the memory cell structure CST may correspond to Figure 1Memory cell array 130. The memory cell structure CST may correspond to the cell region. The memory cell structure CST may include a plurality of memory blocks. The memory cell structure CST may include a plurality of memory blocks defined between an insulating layer stack 139 that passes through the memory cell structure CST and extends along a third direction D3. The plurality of memory blocks may include a plurality of main memory blocks BLKm and at least one dummy memory block BLKd. For example, the at least one dummy memory block BLKd may be disposed on one side of the plurality of main memory blocks BLKm. In one embodiment, the first width of the insulating layer stack 139 between the main memory blocks BLKm and the dummy memory block BLKd may be greater than the second width of the insulating layer stack 139 between the plurality of main memory blocks BLKm.

[0110] The lower wiring structure (eg, lower wiring system) LST may include a first interlayer insulating layer 135, a bit line 134, a second interlayer insulating layer 133, and a first contact 132. The first interlayer insulating layer 135 may include an insulating material. In some embodiments, the first interlayer insulating layer 135 may be a multilayer including a plurality of insulating layers.

[0111] The bit line 134 may be disposed in the first interlayer insulating layer 135. The bit line 134 may extend in the second direction D2. The bit line 134 may be arranged in the first direction D1. The bit line 134 may include a conductive material.

[0112] The second interlayer insulating layer 133 may be disposed on the first interlayer insulating layer 135. The second interlayer insulating layer 133 may include an insulating material. In some embodiments, the second interlayer insulating layer 133 may be a multilayer including a plurality of insulating layers.

[0113] The first contact 132 may be disposed on the bit line 134. The first contact 132 may be disposed in the second interlayer insulating layer 133. The first contact 132 may electrically connect the bit line 134 to the first channel structure CS1. The first contact 132 may include a conductive material.

[0114] The number of the second interlayer insulating layer 133 and the first interlayer insulating layer 135 may not be limited to the number shown. In some embodiments, the number of the second interlayer insulating layer 133 and the first interlayer insulating layer 135 may be two or less, or four or more.

[0115] The first gate stack structure GST1 may be disposed on the second interlayer insulating layer 133. The second gate stack structure GST2 may be disposed on the first gate stack structure GST1. The third gate stack structure GST3 may be disposed on the second gate stack structure GST2. The number of the first to third gate stack structures GST1, GST2, and GST3 may not be limited to the number shown. In some embodiments, the number of the first to third gate stack structures GST1, GST2, and GST3 may be two or less, or four or more.

[0116] Each of the first to third gate stack structures GST1, GST2, and GST3 may include an insulating pattern IP and a conductive pattern CP that are alternately stacked on top of each other in a third direction D3. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction orthogonal to the first direction D1 and the second direction D2.

[0117] Each of the insulating patterns IP may include an insulating material. For example, each of the insulating patterns IP may include an oxide or a low-dielectric material, but is not limited thereto. Each of the conductive patterns CP may include a conductive material. For example, each of the conductive patterns CP may include at least one of a doped semiconductor, a metal, a conductive metal nitride, or a transition metal, but is not limited thereto.

[0118] The first channel structure CS1 may extend in the third direction D3 and pass through the first, second, and third gate stack structures GST1, GST2, and GST3. The first channel structure CS1 may be disposed on the second interlayer insulating layer 133 in the cell region.

[0119] The second channel structure CS2 may extend in the third direction D3 and pass through the first gate stack structure GST1, the second gate stack structure GST2, and the third gate stack structure GST3. The second channel structure CS2 may be disposed on the second interlayer insulating layer 133 in the cell region. The common source plate CSP may be disposed on the third gate stack structure GST3.

[0120] The second channel structure CS2 may be covered by the second interlayer insulating layer 133, and this portion may be referred to as a gap portion GP. The second channel structure CS2 may be covered by the gap portion GP so as not to be electrically connected to the bit line BL. No contact may be provided between the bit line BL and the second channel structure CS2.

[0121] along Figure 5A The cross-sectional view taken along the line CC′ can be Figure 5A The cross-sectional view taken along line AA′ is the same. Figure 5B (i.e., along Figure 5AThe cross-sectional view taken along line AA′ of FIG. 1 may be a cross-sectional view of the string group SG of the first type T1. Figure 5C (i.e., along Figure 5A The cross-sectional view taken along line BB′ of FIG. 1 may be a cross-sectional view of the string group SG of the second type T2.

[0122] In an embodiment, the second channel structure CS2 can be moved to one side of the memory cell array. Among the string groups of the dummy memory block BLKd, the string group close to the edge area of ​​the memory cell array 130 may be the second type T2. Among the string groups of the dummy memory block BLKd, the string group away from the edge area of ​​the memory cell array 130 may be the first type T1. Alternatively, among the string groups of the dummy memory block BLKd, the string group close to the center of the memory cell array 130 may be the first type T1. Among the string groups of the dummy memory block BLKd, the string group away from the center of the memory cell array 130 may be the second type T2. For example, the first to third string groups SG1 to SG3 of the dummy memory block BLKd may be the second type T2, and the fourth string group SG4 of the dummy memory block BLKd may be the first type T1.

[0123] In an embodiment, the memory device 100 may include a memory cell structure CST including a plurality of memory blocks. The plurality of memory blocks may include at least one dummy memory block BLKd and a plurality of main memory blocks BLKm. Each of the plurality of main memory blocks BLKm may include a string group of a first type T1, and the at least one dummy memory block BLKd may include a string group of a first type T1 and a string group of a second type T2. The string group of the first type T1 may include a plurality of first channel structures CS1 connected to the same string select line SSL and connected to the bit line BL. The string group of the second type T2 may include a plurality of second channel structures CS2 connected to the same string select line SSL and not connected to the bit line BL.

[0124] In an embodiment, the string group of the first type T1 of the dummy memory block BLKd of the memory device 100 can store data in the same manner as the string group of the main memory block BLKm. The memory device 100 can store data in the first channel structure CS1 of the dummy memory block BLKd. The memory device 100 can store data in the memory cells included in the string group of the first type T1 of the dummy memory block BLKd.

[0125] As described above, the first channel structure CS1 included in the string group SG of the first type T1 can be connected to the bit line BL through the first contact 132. On the other hand, the first contact 132 may not be formed in the second channel structure CS2 included in the string group SG of the second type T2. Therefore, the second channel structure CS2 may not be electrically connected to the bit line BL. The dummy memory block BLKd may include both the first channel structure CS1 and the second channel structure CS2. The memory device 100 may store data in the first channel structure CS1 of the dummy memory block BLKd. For example, the memory device 100 may store data in at least one string group SG of the dummy memory block BLKd. Therefore, the size of the disclosed memory device 100 can be reduced while maintaining the storage capacity, thereby improving the memory device 100. Alternatively, the storage space of the memory device 100 can be increased.

[0126] Figure 6 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Detailed block diagram of the memory cell array 130.

[0127] For the sake of convenience, detailed description of the above components is omitted. Figure 1 、 Figure 2 and Figure 6 , the memory cell array 130 may include a plurality of memory blocks. In an embodiment, the memory cell array 130 may include a first dummy memory block BLKd1, first to nth main memory blocks BLKm1 to BLKmn, and a second dummy memory block BLKd2.

[0128] The first dummy memory block BLKd1 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the first string selection line SSL1 and not connected to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the first dummy memory block BLKd1 may include a first channel structure CS1 connected to the fourth string selection line SSL4 and to the first to fourth bit lines BL1 to BL4.

[0129] The first main memory block BLKm1 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the first string selection line SSL1 and to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the second string selection line SSL2 and to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the third string selection line SSL3 and to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the fourth string selection line SSL4 and to the first to fourth bit lines BL1 to BL4.

[0130] The nth main memory block BLKmn may include first to fourth string groups SG1 to SG4. The first string group SG1 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a first string selection line SSL1 and to first to fourth bit lines BL1 to BL4. The second string group SG2 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a second string selection line SSL2 and to bit lines BL1, BL2, BL3, and BL4. The third string group SG3 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a third string selection line SSL3 and to first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a fourth string selection line SSL4 and to first to fourth bit lines BL1 to BL4.

[0131] The second dummy memory block BLKd2 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the second dummy memory block BLKd2 may include a first channel structure CS1 connected to the first string selection line SSL1 and to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the fourth string selection line SSL4 and not connected to the first to fourth bit lines BL1 to BL4.

[0132] In an example, the string groups within each memory block can be spaced apart at a constant distance or spacing. The spacing between adjacent memory blocks can exceed the spacing between string groups within a single memory block. Alternatively or additionally, the spacing between the immediately adjacent string groups of a dummy memory block (e.g., BLKd1 or BLKd2) and an adjacent main memory block (e.g., BLKm1 or BLKmn) can exceed the spacing between string groups within a single memory block. For example, the spacing between string group SG4 of dummy memory block BLKd1 and the immediately adjacent string group SG1 of main memory block BLKm1 can exceed the spacing between string groups SG1 to SG4. The spacing between string group SG1 of dummy memory block BLKd2 and the immediately adjacent string group SG4 of main memory block BLKmn can also exceed the spacing between string groups SG1 to SG4.

[0133] Figure 7 is a description Figure 6 A table of channel structure types of the first string group SG1 to the fourth string group SG4.

[0134] refer to Figure 1 、 Figure 6 and Figure 7 , the first string group SG1 of the first dummy memory block BLKd1 may be the second type T2, the second string group SG2 of the first dummy memory block BLKd1 may be the second type T2, the third string group SG3 of the first dummy memory block BLKd1 may be the second type T2, and the fourth string group SG4 of the first dummy memory block BLKd1 may be the first type T1.

[0135] The first string group SG1 of the first main memory block BLKm1 may be a first type T1, the second string group SG2 of the first main memory block BLKm1 may be a first type T1, the third string group SG3 of the first main memory block BLKm1 may be a first type T1, and the fourth string group SG4 of the first main memory block BLKm1 may be a first type T1.

[0136] The first string group SG1 of the nth main memory block BLKmn may be the first type T1, the second string group SG2 of the nth main memory block BLKmn may be the first type T1, the third string group SG3 of the nth main memory block BLKmn may be the first type T1, and the fourth string group SG4 of the nth main memory block BLKmn may be the first type T1.

[0137] The first string group SG1 of the second dummy memory block BLKd2 may be the first type T1, the second string group SG2 of the second dummy memory block BLKd2 may be the second type T2, the third string group SG3 of the second dummy memory block BLKd2 may be the second type T2, and the fourth string group SG4 of the second dummy memory block BLKd2 may be the second type T2.

[0138] As described above, the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may each include both a string group of the first type T1 and a string group of the second type T2. For example, the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may each include both a first channel structure CS1 and a second channel structure CS2. Each of the first to nth main memory blocks BLKm1 to BLKmn may only include a string group of the first type T1. Each of the first to nth main memory blocks BLKm1 to BLKmn may only include a first channel structure CS1.

[0139] Figure 8A is a diagram showing a method according to an embodiment of the present invention. Figure 1 1 is a plan view of a memory device 100. Figure 8B It is along Figure 8A A cross-sectional view taken along line EE'.

[0140] For the sake of convenience, detailed description of the above components is omitted. Figure 6 、 Figure 8A and Figure 8B, the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may be disposed on both sides of the main memory block BLKm. In an embodiment, the first dummy memory block BLKd1 may be disposed on a first side of the first to n-th main memory blocks BLKm1 to BLKmn, and the second dummy memory block BLKd2 may be disposed on a second side opposite to the first side of the first to n-th main memory blocks BLKm1 to BLKmn in the second direction D2.

[0141] For example, the first dummy memory block BLKd1, the first to nth main memory blocks BLKm1 to BLKmn, and the second dummy memory block BLKd2 may be arranged in the second direction D2. The nth main memory block BLKmn may be arranged on the second dummy memory block BLKd2, the (n-1)th main memory block (not shown) may be arranged on the nth main memory block BLKmn, the first main memory block BLKm1 may be arranged on the second main memory block (not shown), and the first dummy memory block BLKd1 may be arranged on the first main memory block BLKm1.

[0142] The first to fourth string groups SG1 to SG4 may be disposed to be spaced apart from each other in the second direction D2. The first to fourth bit lines BL1 to BL4 may be disposed to be spaced apart from each other in the first direction D1. The first to fourth bit lines BL1 to BL4 may extend along the second direction D2.

[0143] The memory device 100 may include a plurality of memory blocks. The plurality of memory blocks may include a plurality of main memory blocks BLKm and a first dummy memory block BLKd1 and a second dummy memory block BLKd2. In an embodiment, the dummy memory blocks BLKd may be provided on both sides of the plurality of main memory blocks BLKm. The dummy memory blocks BLKd may be formed to have the same or similar structure as the plurality of main memory blocks BLKm. However, the dummy memory blocks BLKd may include a plurality of dummy memory cells that are not used as memory cells (e.g., not configured to store data).

[0144] For example, data may be stored in memory cells included in the string group of the first type T1 (ie, the fourth string group SG4) of the first dummy memory block BLKd1. Data may be stored in memory cells included in the string group of the first type T1 (ie, the first string group SG1) of the second dummy memory block BLKd2.

[0145] The memory device 100 may include a memory cell structure CST including a lower wiring structure LST, a first gate stack structure GST1, a second gate stack structure GST2, a third gate stack structure GST3, a first channel structure CS1, a second channel structure CS2, a common source plate CSP, and the like.

[0146] The lower wiring structure LST may include a first interlayer insulating layer 135, a bit line 134, a second interlayer insulating layer 133, and a first contact 132. The first interlayer insulating layer 135 may include an insulating material. In some embodiments, the first interlayer insulating layer 135 may be a multilayer including a plurality of insulating layers.

[0147] The bit lines 134 may be disposed in the first interlayer insulating layer 135. The bit lines 134 may extend in the second direction D2. The bit lines 134 may be arranged in the first direction D1. The bit lines 134 may each include a conductive material.

[0148] The second interlayer insulating layer 133 may be disposed on the first interlayer insulating layer 135. The second interlayer insulating layer 133 may include an insulating material. In some embodiments, the second interlayer insulating layer 133 may be a multilayer including a plurality of insulating layers.

[0149] The first contacts 132 may be disposed on the bit lines 134. The first contacts 132 may be disposed in the second interlayer insulating layer 133. The first contacts 132 may electrically connect the bit lines 134 to the first channel structure CS1. The first contacts 132 may each include a conductive material.

[0150] The number of the second interlayer insulating layer 133 and the first interlayer insulating layer 135 may not be limited to the number shown. In some embodiments, the number of the second interlayer insulating layer 133 and the first interlayer insulating layer 135 may be two or less, or four or more.

[0151] The first gate stack structure GST1 may be disposed on the second interlayer insulating layer 133. The second gate stack structure GST2 may be disposed on the first gate stack structure GST1. The third gate stack structure GST3 may be disposed on the second gate stack structure GST2. The number of the first to third gate stack structures GST1, GST2, and GST3 may not be limited to the number shown. In some embodiments, the number of the first to third gate stack structures GST1, GST2, and GST3 may be two or less, or four or more.

[0152] Each of the first to third gate stack structures GST1 , GST2 , and GST3 may include insulating patterns IP and conductive patterns CP, which are alternately stacked on one another in the third direction D3 .

[0153] Each of the insulating patterns IP may include an insulating material. For example, each of the insulating patterns IP may include an oxide or a low-dielectric material, but is not limited thereto. Each of the conductive patterns CP may include a conductive material. For example, each of the conductive patterns CP may include at least one of a doped semiconductor, a metal, a conductive metal nitride, or a transition metal, but is not limited thereto.

[0154] The first channel structure CS1 may extend in the third direction D3 and pass through the first, second, and third gate stack structures GST1, GST2, and GST3. The first channel structure CS1 may be disposed on the second interlayer insulating layer 133 in the cell region.

[0155] The second channel structure CS2 may extend in the third direction D3 and pass through the first gate stack structure GST1, the second gate stack structure GST2, and the third gate stack structure GST3. The second channel structure CS2 may be disposed on the second interlayer insulating layer 133 in the cell region. The common source plate CSP may be disposed on the third gate stack structure GST3.

[0156] The second channel structure CS2 may be covered by the second interlayer insulating layer 133, and this portion may be referred to as a gap portion GP. The second channel structure CS2 may be covered by the gap portion GP so as not to be electrically connected to the bit line BL.

[0157] along Figure 8A The cross-sectional view taken along line AA′ can be compared with the cross-sectional view taken along line Figure 5A The cross-sectional view taken along line AA′ (ie Figure 5B ) are the same. Figure 8A The cross-sectional view taken along the line CC′ can also be compared with the cross-sectional view taken along the line CC′. Figure 5A The cross-sectional view taken along line AA′ is the same. Figure 8A The cross-sectional view taken along line BB′ can be compared with the cross-sectional view taken along line BB′. Figure 5A The cross-sectional view taken along line BB′ (i.e. Figure 5C ) are the same. Figure 8A The cross-sectional view taken along line FF′ can also be compared with the cross-sectional view taken along line FF′. Figure 5A The cross-sectional view taken along line BB′ (i.e. Figure 5C ) are the same. Figure 8A The cross-sectional view taken along the line GG′ can be compared with the cross-sectional view taken along the line GG′. Figure 5A The cross-sectional view taken along line AA′ (ie Figure 5B )same.

[0158] In an embodiment, the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may be disposed at the outermost portion of the memory cell array 130. The first dummy memory block BLKd1 and the second dummy memory block BLKd2 may be disposed at an edge region of the memory cell array 130. The memory blocks may be sequentially disposed along the second direction D2. The first dummy memory block BLKd1, the first to nth main memory blocks BLKm1 to BLKmn, and the second dummy memory block BLKd2 may be sequentially disposed along the second direction D2.

[0159] In an embodiment, the string group of the first type T1 of the first dummy memory block BLKd1 (i.e., the fourth string group SG4) may be disposed adjacent to the first to nth main memory blocks BLKm1 to BLKmn. The string group of the first type T1 of the second dummy memory block BLKd2 (i.e., the first string group SG1) may be disposed adjacent to the first to nth main memory blocks BLKm1 to BLKmn.

[0160] In an embodiment, the string group types of the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may have a mirror-image structure relative to the center of the memory cell array 130. For example, the channel structures of the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may be formed symmetrically relative to the center of the memory cell array 130. For example, only the fourth string group SG4 of the first dummy memory block BLKd1 may be of the first type T1, and only the first string group SG1 of the second dummy memory block BLKd2 may be of the first type T1. The second channel structure CS2 may be provided in an outer portion (or edge region) of the memory cell array 130, thereby improving the reliability of the memory cells.

[0161] As described above, the first channel structure CS1 included in the string group SG of the first type T1 may be connected to the bit line BL through the first contact 132. On the other hand, the first contact 132 may not be formed in the second channel structure CS2 included in the string group SG of the second type T2. Therefore, the second channel structure CS2 may not be electrically connected to the bit line BL.

[0162] 9A to 9D According to some embodiments Figure 8A A cross-sectional view taken along line EE'.

[0163] The lower wiring structure LST may include a first interlayer insulating layer 135 , a bit line 134 , a second interlayer insulating layer 133 , a third interlayer insulating layer 137 , a first contact 132 , and a second contact 138 .

[0164] The first interlayer insulating layer 135 may include an insulating material. In some embodiments, the first interlayer insulating layer 135 may be a multilayer structure including a plurality of insulating layers. The bit lines 134 may be disposed in the first interlayer insulating layer 135. The bit lines 134 may extend in the second direction D2. The bit lines 134 may be arranged in the first direction D1. The bit lines 134 may include a conductive material.

[0165] The second interlayer insulating layer 133 may be disposed on the first interlayer insulating layer 135. The second interlayer insulating layer 133 may include an insulating material. In some embodiments, the second interlayer insulating layer 133 may be a multilayer including a plurality of insulating layers.

[0166] The first contacts 132 may be disposed on the bit lines 134. The first contacts 132 may be disposed in the second interlayer insulating layer 133. The first contacts 132 may electrically connect the bit lines 134 and the second contacts 138. The first contacts 132 may each include a conductive material.

[0167] The third interlayer insulating layer 137 may be disposed on the second interlayer insulating layer 133. The third interlayer insulating layer 137 may include an insulating material. In some embodiments, the third interlayer insulating layer 137 may be a multilayer including a plurality of insulating layers.

[0168] The second contacts 138 may be disposed on the first contacts 132. The second contacts 138 may be disposed in the third interlayer insulating layer 137. The second contacts 138 may electrically connect the first contacts 132 to the first channel structure CS1. The second contacts 138 may each include a conductive material.

[0169] The first gate stack structure GST1 may be disposed on the third interlayer insulating layer 137. The second gate stack structure GST2 may be disposed on the first gate stack structure GST1. The third gate stack structure GST3 may be disposed on the second gate stack structure GST2.

[0170] refer to Figure 9A , the first contact 132 and the second contact 138 may not be formed in the second channel structure CS2. Therefore, the second channel structure CS2 may not be electrically connected to the bit line BL. The second channel structure CS2 may be covered by the second interlayer insulating layer 133 and the third interlayer insulating layer 137, and this portion may be referred to as a gap portion GP. The second channel structure CS2 may be covered by the gap portion GP and thus not electrically connected to the bit line BL.

[0171] For example, the memory device 100 may include a memory cell structure CST, and the memory cell structure CST may include a lower wiring structure LST, a gate stack structure GST, a first channel structure CS1, a first contact 132, a second contact 138, and a second channel structure CS2. The lower wiring structure LST may include a first interlayer insulating layer 135, a second interlayer insulating layer 133, and a third interlayer insulating layer 137, on which a bit line 134 is disposed. The gate stack structure GST may be disposed on the lower wiring structure LST and include conductive patterns CP and insulating patterns IP alternately stacked on top of each other. The first channel structure CS1 may pass through the gate stack structure GST. The second channel structure CS2 may pass through the gate stack structure GST. The first contact 132 may electrically connect the bit line 134 to the second contact 138. The first contact 132 may be disposed in the second interlayer insulating layer 133. The second contact 138 may electrically connect the first contact 132 to the first channel structure CS1. The second contact 138 may be disposed in the third interlayer insulating layer 137. No contact may be provided between the bit line 134 and the second channel structure CS2 .

[0172] refer to Figure 9B , the first contact 132 may not be formed in the second channel structure CS2. Therefore, the second channel structure CS2 may not be electrically connected to the bit line BL. The second channel structure CS2 may be covered by the second interlayer insulating layer 133, and this portion may be referred to as a gap portion GP. The second channel structure CS2 may be covered by the gap portion GP and thus not electrically connected to the bit line BL.

[0173] For example, the memory device 100 may include a memory cell structure CST, and the memory cell structure CST may include a lower wiring structure LST, a gate stack structure GST, a first channel structure CS1, a first contact 132, a second contact 138, and a second channel structure CS2. The lower wiring structure LST may include a first interlayer insulating layer 135, a second interlayer insulating layer 133, and a third interlayer insulating layer 137, on which a bit line 134 is disposed. The gate stack structure GST may be disposed on the lower wiring structure LST and include conductive patterns CP and insulating patterns IP alternately stacked on top of each other. The first channel structure CS1 may pass through the gate stack structure GST. The second channel structure CS2 may pass through the gate stack structure GST. The first contact 132 may electrically connect the bit line 134 to the second contact 138. The first contact 132 may be disposed in the second interlayer insulating layer 133. The second contact 138 may electrically connect the first contact 132 to the first channel structure CS1. The second contact 138 may be disposed in the third interlayer insulating layer 137. The second contact 138 may be connected to the second channel structure CS2. The second contact 138 may be provided in the third interlayer insulating layer 137. No contact may be provided between the second contact 138 and the bit line 134 corresponding to the second channel structure CS2.

[0174] refer to Figure 9C , the second contact 138 may not be formed in the second channel structure CS2. Therefore, the second channel structure CS2 may not be electrically connected to the bit line BL. The second channel structure CS2 may be covered by the third interlayer insulating layer 137, and this portion may be referred to as a gap portion GP. The second channel structure CS2 may be covered by the gap portion GP and thus not electrically connected to the bit line BL.

[0175] For example, the memory device 100 may include a memory cell structure CST, and the memory cell structure CST may include a lower wiring structure LST, a gate stack structure GST, a first channel structure CS1, a first contact 132, a second contact 138, and a second channel structure CS2. The lower wiring structure LST may include a first interlayer insulating layer 135, a second interlayer insulating layer 133, and a third interlayer insulating layer 137, on which a bit line 134 is disposed. The gate stack structure GST may be disposed on the lower wiring structure LST and include conductive patterns CP and insulating patterns IP alternately stacked on top of each other. The first channel structure CS1 may pass through the gate stack structure GST. The second channel structure CS2 may pass through the gate stack structure GST. The first contact 132 may electrically connect the bit line 134 to the second contact 138. The first contact 132 may be disposed in the second interlayer insulating layer 133. The second contact 138 may electrically connect the first contact 132 to the first channel structure CS1. The second contact 138 may be disposed in the third interlayer insulating layer 137. The first contact 132 may be connected to a bit line corresponding to the second channel structure CS2. The first contact 132 may be disposed in the second interlayer insulating layer 133. No contact may be disposed between the first contact 132 and the second channel structure CS2.

[0176] refer to Figure 9D , first contact 132 and second contact 138 may be formed in second channel structure CS2. Second channel structure CS2 may be electrically connected to first contact 132 through second contact 138. However, in first interlayer insulating layer 135, bit line 134 may not extend to second channel structure CS2. First contact 132 connected to second contact 138 of second channel structure CS2 may not be connected to bit line 134. For example, first contact 132 on second channel structure CS2 may not be connected to bit line 134. First contact 132 on second channel structure CS2 may be covered by a portion of first interlayer insulating layer 135, and this portion may be referred to as gap portion GP. Second channel structure CS2 may be covered by gap portion GP and thus not electrically connected to bit line BL.

[0177] In an embodiment, the string group types of the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may have a mirror-image structure relative to the center of the memory cell array 130. For example, the channel structures of the first dummy memory block BLKd1 and the second dummy memory block BLKd2 may be formed symmetrically relative to the center of the memory cell array 130. For example, only the fourth string group SG4 of the first dummy memory block BLKd1 may be of the first type T1, and only the first string group SG1 of the second dummy memory block BLKd2 may be of the first type T1. The second channel structure CS2 may be provided in an outer portion (or edge region) of the memory cell array 130, thereby improving the reliability of the memory cells.

[0178] Figure 10 is a diagram showing a method according to an embodiment of the present invention. Figure 1 Detailed block diagram of the memory cell array 130.

[0179] For the sake of convenience, detailed description of the above components is omitted. Figure 1 、 Figure 2 and Figure 10 , the memory cell array 130 may include a plurality of memory blocks. In an embodiment, the memory cell array 130 may include a first dummy memory block BLKd1, a second dummy memory block BLKd2, first to nth main memory blocks BLKm1 to BLKmn, a third dummy memory block BLKd3, and a fourth dummy memory block BLKd4.

[0180] In an embodiment, the main memory block BLKm may include only the first channel structure CS1. The main memory block BLKm may include only the channel structure CS connected to the bit line BL. For example, the main memory block BLKm may include only memory cells connected to the bit line BL.

[0181] In an embodiment, a dummy memory block BLKd may include both a first channel structure CS1 and a second channel structure CS2. The dummy memory block BLKd may include both a channel structure CS connected to a bit line BL and a channel structure CS not connected to the bit line BL. The dummy memory block BLKd may include both memory cells connected to a bit line BL and memory cells not connected to the bit line BL.

[0182] In an embodiment, the dummy memory block BLKd may include only the second channel structure CS2. The dummy memory block BLKd may include only the channel structure CS not connected to the bit line BL. For example, the dummy memory block BLKd may include only memory cells not connected to the bit line BL.

[0183] The first dummy memory block BLKd1 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the first string selection line SSL1 and not connected to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the first dummy memory block BLKd1 may include a second channel structure CS2 connected to the fourth string selection line SSL4 and not connected to the first to fourth bit lines BL1 to BL4.

[0184] The second dummy memory block BLKd2 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the first string selection line SSL1 and not connected to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the second dummy memory block BLKd2 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the second dummy memory block BLKd2 may include a first channel structure CS1 connected to the fourth string selection line SSL4 and to the first to fourth bit lines BL1 to BL4.

[0185] The first main memory block BLKm1 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the first string selection line SSL1 and to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the second string selection line SSL2 and to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the third string selection line SSL3 and to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the first main memory block BLKm1 may include a first channel structure CS1 connected to the fourth string selection line SSL4 and to the first to fourth bit lines BL1 to BL4.

[0186] The nth main memory block BLKmn may include first to fourth string groups SG1 to SG4. The first string group SG1 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a first string selection line SSL1 and to first to fourth bit lines BL1 to BL4. The second string group SG2 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a second string selection line SSL2 and to first to fourth bit lines BL1 to BL4. The third string group SG3 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a third string selection line SSL3 and to bit lines BL1, BL2, BL3, and BL4. The fourth string group SG4 of the nth main memory block BLKmn may include a first channel structure CS1 connected to a fourth string selection line SSL4 and to first to fourth bit lines BL1 to BL4.

[0187] The third dummy memory block BLKd3 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the third dummy memory block BLKd3 may include a first channel structure CS1 connected to the first string selection line SSL1 and to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the third dummy memory block BLKd3 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the third dummy memory block BLKd3 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the third dummy memory block BLKd3 may include a second channel structure CS2 connected to the fourth string selection line SSL4 and not connected to the first to fourth bit lines BL1 to BL4.

[0188] The fourth dummy memory block BLKd4 may include first to fourth string groups SG1 to SG4. The first string group SG1 of the fourth dummy memory block BLKd4 may include a second channel structure CS2 connected to the first string selection line SSL1 and not connected to the first to fourth bit lines BL1 to BL4. The second string group SG2 of the fourth dummy memory block BLKd4 may include a second channel structure CS2 connected to the second string selection line SSL2 and not connected to the first to fourth bit lines BL1 to BL4. The third string group SG3 of the fourth dummy memory block BLKd4 may include a second channel structure CS2 connected to the third string selection line SSL3 and not connected to the first to fourth bit lines BL1 to BL4. The fourth string group SG4 of the fourth dummy memory block BLKd4 may include a second channel structure CS2 connected to the fourth string selection line SSL4 and not connected to the first to fourth bit lines BL1 to BL4.

[0189] In other words, the first string group SG1 of the first dummy memory block BLKd1 may be the second type T2, the second string group SG2 of the first dummy memory block BLKd1 may be the second type T2, the third string group SG3 of the first dummy memory block BLKd1 may be the second type T2, and the fourth string group SG4 of the first dummy memory block BLKd1 may be the second type T2.

[0190] The first string group SG1 of the second dummy memory block BLKd2 may be the second type T2, the second string group SG2 of the second dummy memory block BLKd2 may be the second type T2, the third string group SG3 of the second dummy memory block BLKd2 may be the second type T2, and the fourth string group SG4 of the second dummy memory block BLKd2 may be the first type T1.

[0191] The first string group SG1 of the first main memory block BLKm1 may be a first type T1, the second string group SG2 of the first main memory block BLKm1 may be a first type T1, the third string group SG3 of the first main memory block BLKm1 may be a first type T1, and the fourth string group SG4 of the first main memory block BLKm1 may be a first type T1.

[0192] The first string group SG1 of the nth main memory block BLKmn may be the first type T1, the second string group SG2 of the nth main memory block BLKmn may be the first type T1, the third string group SG3 of the nth main memory block BLKmn may be the first type T1, and the fourth string group SG4 of the nth main memory block BLKmn may be the first type T1.

[0193] The first string group SG1 of the third dummy memory block BLKd3 may be the first type T1, the second string group SG2 of the third dummy memory block BLKd3 may be the second type T2, the third string group SG3 of the third dummy memory block BLKd3 may be the second type T2, and the fourth string group SG4 of the third dummy memory block BLKd3 may be the second type T2.

[0194] The first string group SG1 of the fourth dummy memory block BLKd4 may be the second type T2, the second string group SG2 of the third dummy memory block BLKd3 may be the second type T2, the third string group SG3 of the third dummy memory block BLKd3 may be the second type T2, and the fourth string group SG4 of the third dummy memory block BLKd3 may be the second type T2.

[0195] Among the string groups SG1 to SG4 of the first to fourth dummy memory blocks BLKd1 to BLKd4, the string groups SG adjacent to the first to nth main memory blocks BLKm1 to BLKmn (i.e., the fourth string group SG4 of the second to fourth dummy memory blocks BLKd2 and the first string group SG1 of the third dummy memory block BLKd3) may be of the first type T1. Among the first to fourth dummy memory blocks BLKd1 to BLKd4, the string groups farther from the edge of the memory cell array 130 may be of the first type T1. In some examples, the string groups closer to the edge of the memory cell array 130 may be of the second type T2, thereby providing distance to mitigate process issues.

[0196] Each of all first to fourth string groups SG1 to SG4 included in the main memory block BLKm may be of the first type T1. The main memory block BLKm may include only string groups of the first type T1. The main memory block BLKm may include only string groups including a channel structure CS connected to a bit line.

[0197] As described above, the first dummy memory block BLKd1 and the fourth dummy memory block BLKd4 may include only the second channel structure CS2. The second dummy memory block BLKd2 and the third dummy memory block BLKd3 may include both the first channel structure SC1 and the second channel structure CS2. Each of the first to nth main memory blocks BLKm1 to BLKmn may include only the first channel structure SC1.

[0198] Figure 11 is a flowchart illustrating an operating method of the memory device 100 according to an embodiment.

[0199] refer to Figure 1 and Figure 11 In order to perform a pre-program operation, the memory device 100 may apply a pre-program voltage VPGM to a word line WL of the second type T2 string group connected to the dummy memory block BLKd, apply a pass voltage VPASS to a ground select line GSL of the second type T2 string group connected to the dummy memory block BLKd, and apply a ground voltage VSS to a common source line CSL of the second type T2 string group connected to the dummy memory block BLKd.

[0200] In operation S110, the memory device 100 may perform a pre-programming operation. The memory device 100 may perform a pre-programming operation on a string group of the second type T2 in the string group of the dummy memory block BLKd. For example, the memory device 100 may perform a pre-programming operation on the first string group SG1 to the third string group SG3 in the string groups SG1 to SG4 of the dummy memory block BLKd. The memory device 100 may perform a pre-programming operation on each cell structure included in the string group of the second type T2. The memory device 100 may perform a pre-programming operation on the second channel structure CS2. Therefore, the threshold voltage distribution of the cells included in the second channel structure CS2 may move in an increasing direction.

[0201] In an embodiment, the cell structure included in the string group of the first type T1 included in the dummy memory block BLKd may also be preprogrammed. However, the present invention is not limited thereto. In an embodiment, only the cell structure included in the string group of the second type T2 included in the dummy memory block BLKd may be preprogrammed, and the cell structure included in the string group of the first type T1 included in the dummy memory block BLKd may not be preprogrammed.

[0202] In operation S120, the memory device 100 may perform an erase operation. The memory device 100 may perform an erase operation on each string group of the second type T2 for which pre-programming is performed. For example, the memory device 100 may perform an erase operation on the dummy memory block BLKd. The memory device 100 may perform an erase operation on the second channel structure CS2 of the dummy memory block BLKd. Therefore, the data stored in the string group of the first type T1 included in the dummy memory block BLKd may be erased.

[0203] In one embodiment, the memory device 100 may perform operation S120 after performing operation S110. In another embodiment, the memory device 100 may perform operation S110 after performing operation S120. When operation S110 is performed after operation S120, in operation S110, only the string group of the second type T2 of the dummy memory block BLKd may be preprogrammed, and the string group of the first type T1 of the dummy memory block BLKd may not be preprogrammed.

[0204] As described above, the memory device 100 may perform a pre-program operation of applying a pre-program voltage VPGM to the dummy memory block BLKd. The memory device 100 may perform an erase operation of applying an erase voltage to the dummy memory block BLKd. The memory device 100 according to the present invention may perform the pre-program operation S110 on the string group of the second type T2 before or after the erase operation S120, thereby preventing damage to the cell string due to repeated erase operations performed on the string group of the second type T2.

[0205] Figure 12A is a timing diagram of voltages applied to lines by the memory device 100 during a pre-program operation and an erase operation according to an embodiment. Figure 12B is used to describe Figure 11 1 is a timing diagram of operations S110 and S120.

[0206] refer to Figure 12A ,In a pre-programming operation, a memory device (e.g. Figure 1 100) can apply a pre-program voltage VPGM to a word line WL connected to each string group of the second type T2 of the dummy memory block BLKd for which a pre-program operation is to be performed. For example, the row decoder 160 can apply the pre-program voltage VPGM to a selected word line connected to the second channel structure CS2 of the dummy memory block BLKd. The row decoder 160 can apply a pass voltage VPASS to unselected word lines connected to the second channel structure CS2 of the dummy memory block BLKd.

[0207] The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL connected to each string group of the second type T2 of the dummy memory block BLKd. For example, the row decoder 160 may apply a pass voltage VPASS to a ground selection line GSL connected to the second channel structure CS2 of the dummy memory block BLKd.

[0208] The memory device 100 may apply a ground voltage VSS to a common source line CSL connected to each string group of the second type T2. For example, the row decoder 160 may apply the ground voltage VSS to a common source line CSL connected to the second channel structure CS2 of the dummy memory block BLKd. The row decoder 160 may apply the ground voltage VSS to a common source line CSL connected to the second channel structure CS2 of the dummy memory block BLKd that is not connected to the bit line BL. When the memory device 100 performs a pre-programming operation, the substrate may maintain the ground voltage VSS.

[0209] The period during which the pre-programming voltage VPGM is applied to the word line WL and the period during which the pass voltage VPASS is applied to the ground select line GSL may overlap. For example, at a first time t1 when the pre-programming voltage VPGM is applied to the word line WL, the pass voltage VPASS may be applied to the ground select line GSL. Furthermore, at a second time t2 when the word line WL floats at the pre-programming voltage VPGM, the ground select line GSL may float at the pass voltage VPASS. In embodiments, the period during which the pre-programming voltage VPGM is applied to the word line WL and the period during which the pass voltage VPASS is applied to the ground select line GSL may overlap.

[0210] Furthermore, the period during which the pre-programming voltage VPGM is applied to the word line WL and the period during which the ground voltage VSS is applied to the common source line CSL may overlap. For example, at a first time t1 when the pre-programming voltage VPGM is applied to the word line WL, the ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2 when the word line WL floats at the pre-programming voltage VPGM, the common source line CSL may float at the ground voltage VSS. In embodiments, the period during which the pre-programming voltage VPGM is applied to the word line WL and the period during which the ground voltage VSS is applied to the common source line CSL may overlap.

[0211] Since the memory cells formed in the second channel structure CS2 are not connected to the bit lines BL, the memory cells cannot be programmed by applying a voltage to the bit lines BL. Therefore, the memory device 100 according to the embodiment may apply the ground voltage VSS to the common source line CSL, the pass voltage VPASS to the ground selection line GSL, and the pre-programming voltage VPGM to the word lines WL, thereby pre-programming the memory cells formed in the second channel structure CS2.

[0212] When the pass voltage VPASS is applied to the ground select line GSL, the ground select transistor GST can be turned on, and the ground voltage VSS can be applied to the source of the memory cells of the cell strings included in each string group of the second type T2. Even if the bit line voltage is not applied because the bit line BL is not connected to the cell strings included in the string group of the second type T2, the ground voltage VSS can be applied to the common source line CSL and the pass voltage VPASS can be applied to the ground select line GSL. Therefore, the cells included in the second channel structure CS2 can be pre-programmed. In this case, the ground voltage VSS can be applied to the substrate. However, the present invention is not limited to this. The memory device 100 can apply the pass voltage VPASS to the ground select line GSL connected to the string corresponding to the second channel structure CS2 of the dummy memory block BLKd, and apply a voltage other than the ground voltage VSS to the common source line CSL.

[0213] During an erase operation, the memory device 100 may apply a word line erase voltage VWERS to the word line WL of the dummy memory block BLKd, a ground erase voltage VGERS to the ground select line GSL of the dummy memory block BLKd, and an erase voltage VERS to the common source line CSL of the dummy memory block BLKd. In this case, the word line erase voltage VWERS may be the ground voltage VSS, or may have a level close to the ground voltage VSS. The ground erase voltage VGERS may have a value that is a certain level lower than the erase voltage VERS. For example, based on the level of the erase voltage VERS applied to the common source line CSL, the memory device 100 may apply the ground erase voltage VGERS to the ground select line GSL. When the memory device 100 performs an erase operation, the erase voltage VERS may also be applied to the substrate.

[0214] As described above, the memory device 100 can perform a pre-program operation and an erase operation on the string group of the second type T2 of the dummy memory block. Therefore, the memory device 100 having improved reliability is provided.

[0215] Figure 12B and Figure 12C is according to an embodiment in a pre-program operation and an erase operation (e.g., Figure 11 1 and 2. FIG. 1 is a timing diagram of voltages applied to the line by the memory device 100 during operations S110 and S120 of FIG.

[0216] refer to Figure 12BFor example, from first time t1 to second time t2, the voltage applied to word line WL at first time t1 may be increased from off voltage VOFF or ground voltage VSS to pre-program voltage VPGM. At first time t1, pass voltage VPASS may be applied to ground select line GSL. At first time t1, ground voltage VSS may be applied to common source line CSL. Furthermore, at second time t2, word line WL may be floated. At second time t2, ground select line GSL may be floated. At second time t2, common source line CSL may be floated.

[0217] refer to Figure 12C For example, at a first time t1, a pre-program voltage VPGM may be applied to the word line WL. From the first time t1 to a second time t2, the voltage applied to the word line WL may be increased from the ground voltage VSS or the off voltage VOFF to the pre-program voltage VPGM. The voltage applied to the word line WL may be decreased from the pre-program voltage VPGM to the second voltage V2 from the second time t2 to a third time t3. At the first time t1, a pass voltage VPASS may be applied to the ground select line GSL. At the first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a third time t3, the word line WL may be floated. At the third time t3, the ground select line GSL may be floated. At the third time t3, the common source line CSL may be floated.

[0218] refer to Figure 12A During the pre-programming period, the voltage applied to the word line WL may be maintained at the pre-programming voltage VPGM. Figure 12B , the voltage applied to the word line WL can be increased during the pre-programming period. Figure 12C , the voltage applied to the word line WL may be reduced during the pre-program period. For example, the pre-program period may refer to a period during which the pre-program voltage VPGM is applied to the word line WL to perform a pre-program operation.

[0219] Figure 13A It shows Figure 1 1 is a circuit diagram of a first dummy memory block BLKd1 among a plurality of memory blocks included in the memory cell array 130. Figure 13B It shows Figure 13A FIG. 4 is a vertical cross-sectional view of a first cell string NS11 among the cell strings of FIG.

[0220] In order to simplify and facilitate the description of the drawings, refer to Figure 13A and Figure 13B The first dummy memory block BLKd1 and the first cell string NS11 are described, but the scope of the present inventive concept is not limited thereto, and other dummy memory blocks or other cell strings may also have the same configuration as the reference numerals. Figure 13A and Figure 13BThe first dummy memory block BLKd1 is described to have a similar structure to the first cell string NS11 .

[0221] refer to Figure 13A and Figure 13B , a first dummy memory block BLKd1 may be formed on a substrate (not shown). The first dummy memory block BLKd1 may include a plurality of cell strings NS11, NS12, NS21, and NS22 vertically stacked on the substrate. Each of the plurality of cell strings NS11, NS12, NS21, and NS22 may be arranged along a first direction D1 and a second direction D2.

[0222] Cell strings located in the same column among the plurality of cell strings NS11, NS12, NS21, and NS22 may be connected to the same bit line. For example, cell strings NS11 and NS21 may be connected to a first bit line BL1, and cell strings NS12 and NS22 may be connected to a second bit line BL2. Each of the plurality of cell strings NS11, NS12, NS21, and NS22 may include a plurality of cell transistors. Each of the plurality of cell transistors may be a charge trap flash (CTF) memory cell, but the scope of the present inventive concept is not limited in this respect. The plurality of cell transistors may be stacked in a third direction D3 perpendicular to a plane formed by the first direction D1 and the second direction D2 (e.g., a semiconductor substrate (not shown)).

[0223] Hereinafter, for convenience of description, the structure and configuration of the cell strings are described with respect to the first cell string NS11 , and each of the other cell strings NS12 , NS21 , and NS22 may have a similar structure to the first cell string NS11 , and detailed descriptions thereof are omitted.

[0224] A plurality of cell transistors may be connected in series between a first bit line BL1 and a common source line CSL. For example, the plurality of cell transistors may include a string select transistor SST, first to thirteenth memory cells MC1 to MC13, and a ground select transistor GST. The string select transistor SST may be disposed or connected between the thirteenth memory cell MC13 and the first bit line BL1. The ground select transistor GST may be disposed or connected between the first memory cell MC1 and the common source line CSL.

[0225] First to thirteenth memory cells MC1 to MC13 may be connected in series between string select lines SSL1 and SSL2 and a ground select line GSL. Memory cells located at the same height in each of the plurality of cell strings NS11, NS12, NS21, and NS22 may share the same word line. For example, the first memory cell MC1 in each of the plurality of cell strings NS11, NS12, NS21, and NS22 may be located at the same height from a substrate (not shown) and may share a first word line WL1. The second memory cell MC2 in each of the plurality of cell strings NS11, NS12, NS21, and NS22 may be located at the same height from a substrate (not shown) and may share a second word line WL2. Similarly, the third to thirteenth memory cells MC3 to MC13 in each of the plurality of cell strings NS11, NS12, NS21, and NS22 may be located at the same height from a substrate (not shown) and may share a third to thirteenth word line WL3 to WL13, respectively.

[0226] Among the string selection transistors SST of each of the plurality of cell strings NS11, NS12, NS21, and NS22, the string selection transistors located in the same row and at the same height may be connected to the same string selection line. For example, the string selection transistors SST of the cell strings NS11 and NS12 may be connected to the string selection line SSL1, and the string selection transistors SST of the cell strings NS21 and NS22 may be connected to the string selection line SSL2.

[0227] Among the ground selection transistors GST of each of the plurality of cell strings NS11, NS12, NS21, and NS22, the ground selection transistors located in the same row and at the same height may be connected to the same ground selection line. For example, the ground selection transistors GST of cell strings NS11 and NS12 may be connected to the ground selection line GSL1, and the ground selection transistors GST of cell strings NS21 and NS22 may be connected to the ground selection line GSL2.

[0228] In an embodiment, Figure 13A The first dummy memory block BLKd1 shown in FIG is an example. The number of cell strings can be increased or decreased, and the number of rows and columns constituting the cell strings can be increased or decreased according to the number of cell strings. In addition, the first dummy memory block BLKd1 can also include dummy memory cells. The number of cell transistors of the first dummy memory block BLKd1 can be increased or decreased, and the height of the first dummy memory block BLKd1 can be increased or decreased according to the number of cell transistors. In addition, the number of lines connected to the cell transistors can be increased or decreased according to the number of cell transistors.

[0229] In an embodiment, the first dummy memory block BLKd1 may have a multi-stack structure. Figure 13A and Figure 13B As shown, the first dummy memory block BLKd1 may include a first structure ST1, a second structure ST2, and a third structure ST3. The first structure ST1 may include a ground selection transistor GST and memory cells MC1, MC2, MC3, and MC4 among the cell transistors of a plurality of cell strings NS11, NS12, NS21, and NS22. The second structure ST2 may include memory cells MC5, MC6, MC7, MC8, and MC9 among the cell transistors of a plurality of cell strings NS11, NS12, NS21, and NS22. The third structure ST3 may include memory cells MC10, MC11, MC12, MC13 among the cell transistors of a plurality of cell strings NS11, NS12, NS21, and NS22, and a string selection transistor SST.

[0230] The first structure ST1 may be formed on a substrate, and the second structure ST2 may be formed on an upper portion of the first structure ST1. The third structure ST3 may be formed on an upper portion of the second structure ST2. Figure 13B As shown, the first structure ST1 may be formed on an N-well substrate NW. In an embodiment, a peripheral circuit (eg, Figure 1 The row decoder 160, voltage generator 150, input / output circuit 110, and control logic circuit 120 (including the row decoder 160, voltage generator 150, input / output circuit 110, and control logic circuit 120) may be formed on the lower portion of the N-well substrate NW. For example, the memory device 100 may have a cell-on-peripheral (CoP) structure or a CMOS under array (CUA) structure. In this case, the substrate bonded to the strings may be N-type. However, the scope of the present inventive concept is not limited thereto, and the substrate bonded to the strings may be P-type.

[0231] The second structure ST2 may be formed on the upper portion of the first structure ST1. The third structure ST3 may be formed on the upper portion of the second structure ST2. In this case, as shown in FIG. Figure 13BAs shown, in the region A1 to which the first structure ST1 and the second structure ST2 are electrically connected, and in the region A2 to which the second structure ST2 and the third structure ST3 are electrically connected, the channel diameter may vary. For example, the channel of the first structure ST1 may be formed to pass through the ground select line GSL and the first to fourth word lines WL1, WL2, WL3, and WL4 vertically stacked on the substrate. The channel of the second structure ST2 may be formed to pass through the fifth to ninth word lines WL5, WL6, WL7, WL8, and WL9 stacked on the first structure ST1. The channel of the third structure ST3 may be formed to pass through the cross line to the thirteenth word lines WL10, WL11, WL12, and WL13 stacked on the second structure ST2, and the string select line SSL.

[0232] The channels of the first structure ST1 and the second structure ST2 may be electrically connected to each other in region A1. The channels of the second structure ST2 and the third structure ST3 may be electrically connected to each other in region A2. Figure 13B As shown, in the region A1 where the first structure ST1 and the second structure ST2 are electrically connected to each other, the channel diameter of the second structure ST2 may be smaller than the channel diameter of the first structure ST1. In the region A2 where the second structure ST2 and the third structure ST3 are electrically connected to each other, the channel diameter of the third structure ST3 may be smaller than the channel diameter of the second structure ST2.

[0233] Figure 13C It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0234] For the convenience of description, the memory device 100 is described as executing Figure 13C However, the scope of the inventive concept is not limited thereto.

[0235] Hereinafter, for ease of explanation, the pre-programming operation is described as being performed on the first dummy memory block BLKd1. However, the scope of the present inventive concept is not limited thereto. For example, the pre-programming operation may be performed on the entire first dummy memory block BLKd1, or on strings (e.g., NS11 and NS12) in the same row in the first memory block BLK1.

[0236] refer to Figure 13A 、 Figure 13B and Figure 13C , the memory device 100 may sequentially perform a pre-program operation on a plurality of structures of the first dummy memory block BLKd1. In an embodiment, the memory device 100 may perform a pre-program operation on the first structure ST1, then on the second structure ST2, and then on the third structure ST3.

[0237] During a pre-programming operation, the memory device 100 may apply a pre-programming voltage VPGM to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0238] For example, at a first time t1, a pre-program voltage VPGM may be applied to the first to fourth word lines WL1 to WL4. At a first time t1, a pass voltage VPASS may be applied to the fifth to thirteenth word lines WL5 to WL13. At a first time t1, a pass voltage VPASS may be applied to the ground select line GSL. At a first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to thirteenth word lines WL1 to WL3 may be floated. At a second time t2, the ground select line GSL may be floated. At a second time t2, the common source line CSL may be floated.

[0239] After performing a pre-programming operation on the first structure ST1, the memory device 100 may apply a pre-programming voltage VPGM to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0240] For example, at the third time t3, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the third time t3, a pre-program voltage VPGM may be applied to the fifth to ninth word lines WL5 to WL9. At the third time t3, a pass voltage VPASS may be applied to the third to thirteenth word lines WL10 to WL13. At the third time t3, a pass voltage VPASS may be applied to the ground select line GSL. At the third time t3, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the fourth time t4, the first to thirteenth word lines WL1 to WL3 may be floated. At the fourth time t4, the ground select line GSL may be floated. At the fourth time t4, the common source line CSL may be floated.

[0241] After performing a pre-programming operation on the second structure ST2, the memory device 100 may apply a pre-programming voltage VPGM to the first to thirteenth word lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply a pass voltage VPASS to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0242] For example, at the fifth time t5, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the fifth time t5, a pass voltage VPASS may be applied to the fifth to ninth word lines WL5 to WL9. At the fifth time t5, a pre-programming voltage VPGM may be applied to the first to thirteenth word lines WL10 to WL13. At the fifth time t5, a pass voltage VPASS may be applied to the ground select line GSL. At the fifth time t5, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the sixth time t6, the first to thirteenth word lines WL1 to WL3 may be floated. At the sixth time t6, the ground select line GSL may be floated. At the sixth time t6, the common source line CSL may be floated.

[0243] Figure 13D It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0244] refer to Figure 13A 、 Figure 13B and Figure 13D, the memory device 100 may simultaneously perform a pre-program operation on a plurality of structures of the first dummy memory block BLKd1. In an embodiment, the memory device 100 may perform a pre-program operation on the first and third structures ST1 and ST3 of the odd-numbered structures, and then perform a pre-program operation on the second structure ST2 of the even-numbered structure.

[0245] The memory device 100 may perform a pre-programming operation on the odd-numbered structures ST1 and ST3. The memory device 100 may apply a pre-programming voltage VPGM to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pre-programming voltage VPGM to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply a pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0246] For example, at a first time t1, a pre-program voltage VPGM may be applied to the first to fourth word lines WL1 to WL4. At a first time t1, a pass voltage VPASS may be applied to the fifth to thirteenth word lines WL5 to WL13. At a first time t1, a pre-program voltage VPGM may be applied to the ground select line GSL. At a first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to thirteenth word lines WL1 to WL3 may be floated. At a second time t2, the ground select line GSL may be floated. At a second time t2, the common source line CSL may be floated.

[0247] After performing the pre-programming operation on the odd structures ST1 and ST3, the memory device 100 may perform a pre-programming operation on the even structure ST2. The memory device 100 may apply a pre-programming voltage VPGM to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0248] For example, at the third time t3, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the third time t3, a pre-program voltage VPGM may be applied to the fifth to ninth word lines WL5 to WL9. At the third time t3, a pass voltage VPASS may be applied to the third to thirteenth word lines WL10 to WL13. At the third time t3, a pass voltage VPASS may be applied to the ground select line GSL. At the third time t3, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the fourth time t4, the first to thirteenth word lines WL1 to WL3 may be floated. At the fourth time t4, the ground select line GSL may be floated. At the fourth time t4, the common source line CSL may be floated.

[0249] Figure 14A It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0250] refer to Figure 13A 、 Figure 13B and Figure 14A , the memory device 100 can perform a pre-programming operation on all cell strings connected to the first to fourth string selection lines SSL1 to SSL4 of the first dummy memory block BLKd1. Hereinafter, it is assumed that the first dummy memory block BLKd1 also includes a cell string connected to the third string selection line SSL3 and a cell string connected to the fourth string selection line SSL4. However, it should be understood that in order to simplify and facilitate the description of the drawings, Figure 13A Only memory cells connected to the first and second string selection lines SSL1 and SSL2 are shown.

[0251] In an embodiment, the memory device 100 may simultaneously perform a pre-program operation on cell strings connected to each of the first to fourth string selection lines SSL1 to SSL4 .

[0252] The memory device 100 may apply a first voltage V1 to a first string selection line SSL1. For example, the first voltage V1 may be a selection voltage. The memory device 100 may apply a first voltage V1 to a second string selection line SSL2. The memory device 100 may apply a first voltage V1 to a third string selection line SSL3. The memory device 100 may apply a first voltage V1 to a fourth string selection line SSL4. The memory device 100 may apply a pre-programming voltage VPGM to a word line WL. The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL. The memory device 100 may apply a ground voltage VSS to a common source line CSL. When the memory device 100 performs a pre-programming operation, the substrate may maintain the ground voltage VSS.

[0253] For example, at a first time t1, a first voltage V1 may be applied to the first to fourth string selection lines SSL1 to SSL4. At the first time t1, a pre-program voltage VPGM may be applied to the word lines WL connected to the first to fourth string selection lines SSL1 to SSL4, respectively. At the first time t1, a pass voltage VPASS may be applied to the ground selection line GSL. At the first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the second time t2, the word lines WL may be floated. At the second time t2, the ground selection line GSL may be floated. At the second time t2, the common source line CSL may be floated.

[0254] Figure 14B It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0255] The memory device 100 may perform a pre-program operation on cell strings connected to the first to fourth string selection lines SSL1 to SSL4 of the first dummy memory block BLKd1. The memory device 100 may sequentially perform a pre-program operation on cell strings connected to each of the first to fourth string selection lines SSL1 to SSL4.

[0256] In an embodiment, the memory device 100 may perform a pre-program operation on a cell string connected to a first string selection line SSL1. Thereafter, the memory device 100 may perform a pre-program operation on a cell string connected to a second string selection line SSL2. Thereafter, the memory device 100 may perform a pre-program operation on a cell string connected to a third string selection line SSL3. Thereafter, the memory device 100 may perform a pre-program operation on a cell string connected to a fourth string selection line SSL4.

[0257] The memory device 100 may perform a pre-program operation on a cell string connected to a first string selection line SSL1. The memory device 100 may apply a first voltage V1 to the first string selection line SSL1. The memory device 100 may apply a ground voltage VSS to a second string selection line SSL2. The memory device 100 may apply a ground voltage VSS to a third string selection line SSL3. The memory device 100 may apply a ground voltage VSS to a fourth string selection line SSL4. The memory device 100 may apply a pre-program voltage VPGM to a word line WL. The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL. The memory device 100 may apply a ground voltage VSS to a common source line CSL. When the memory device 100 performs the pre-program operation, the substrate may maintain the ground voltage VSS.

[0258] For example, at a first time t1, a first voltage V1 may be applied to the first string selection line SSL1. At the first time t1, a ground voltage VSS may be applied to the second to fourth string selection lines SSL2 to SSL4. At the first time t1, a pre-programming voltage VPGM may be applied to the word line WL. At the first time t1, a pass voltage VPASS may be applied to the ground selection line GSL. At the first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the second time t2, the word line WL may be floated. At the second time t2, the ground selection line GSL may be floated. At the second time t2, the common source line CSL may be floated.

[0259] After the memory device 100 performs a pre-program operation on the cell strings connected to the first string selection line SSL1 , the memory device 100 may perform a pre-program operation on the cell strings connected to the second string selection line SSL2 .

[0260] The memory device 100 may apply a ground voltage VSS to a first string selection line SSL1. The memory device 100 may apply a first voltage V1 to a second string selection line SSL2. The memory device 100 may apply a ground voltage VSS to a third string selection line SSL3. The memory device 100 may apply a ground voltage VSS to a fourth string selection line SSL4. The memory device 100 may apply a pre-programming voltage VPGM to a word line WL. The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL. The memory device 100 may apply a ground voltage VSS to a common source line CSL. When the memory device 100 performs a pre-programming operation, the substrate may maintain the ground voltage VSS.

[0261] For example, at the third time t3, the ground voltage VSS may be applied to the first string selection line SSL1. At the third time t3, the first voltage V1 may be applied to the second string selection line SSL2. The ground voltage VSS may be applied to the third and fourth string selection lines SSL3 and SSL4. At the third time t3, the pre-programming voltage VPGM may be applied to the word line WL. At the third time t3, the pass voltage VPASS may be applied to the ground selection line GSL. At the third time t3, the ground voltage VSS may be applied to the common source line CSL. In addition, at the fourth time t4, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the fourth time t4, the word line WL may be floated. At the fourth time t4, the ground selection line GSL may be floated. At the fourth time t4, the common source line CSL may be floated.

[0262] After the memory device 100 performs the pre-program operation on the cell strings connected to the second string selection line SSL2 , the memory device 100 may perform the pre-program operation on the cell strings connected to the third string selection line SSL3 .

[0263] The memory device 100 may apply a ground voltage VSS to a first string selection line SSL1. The memory device 100 may apply a ground voltage VSS to a second string selection line SSL2. The memory device 100 may apply a first voltage V1 to a third string selection line SSL3. The memory device 100 may apply a ground voltage VSS to a fourth string selection line SSL4. The memory device 100 may apply a pre-programming voltage VPGM to a word line WL. The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL. The memory device 100 may apply a ground voltage VSS to a common source line CSL. When the memory device 100 performs a pre-programming operation, the substrate may maintain the ground voltage VSS.

[0264] For example, at the fifth time t5, the ground voltage VSS may be applied to the first string selection line SSL1. At the fifth time t5, the ground voltage VSS may be applied to the second string selection line SSL2. At the fifth time t5, the first voltage V1 may be applied to the third string selection line SSL3. At the fifth time t5, the ground voltage VSS may be applied to the fourth string selection line SSL4. At the fifth time t5, the pre-programming voltage VPGM may be applied to the word line WL. At the fifth time t5, the pass voltage VPASS may be applied to the ground selection line GSL. At the fifth time t5, the ground voltage VSS may be applied to the common source line CSL. In addition, at the sixth time t6, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the sixth time t6, the word line WL may be floated. At the sixth time t6, the ground selection line GSL may be floated. At the sixth time t6, the common source line CSL may be floated.

[0265] After the memory device 100 performs the pre-program operation on the cell strings connected to the third string selection line SSL3 , the memory device 100 may perform the pre-program operation on the cell strings connected to the fourth string selection line SSL4 .

[0266] The memory device 100 may apply a ground voltage VSS to a first string selection line SSL1. The memory device 100 may apply a ground voltage VSS to a second string selection line SSL2. The memory device 100 may apply a ground voltage VSS to a third string selection line SSL3. The memory device 100 may apply a first voltage V1 to a fourth string selection line SSL4. The memory device 100 may apply a pre-program voltage VPGM to a word line WL. The memory device 100 may apply a pass voltage VPASS to a ground selection line GSL. The memory device 100 may apply a ground voltage VSS to a common source line CSL. When the memory device 100 performs a pre-program operation, the substrate may maintain the ground voltage VSS.

[0267] For example, at the seventh time t7, the ground voltage VSS may be applied to the first string selection line SSL1. At the seventh time t7, the ground voltage VSS may be applied to the second string selection line SSL2. At the seventh time t7, the ground voltage VSS may be applied to the third string selection line SSL3. At the seventh time t7, the first voltage V1 may be applied to the fourth string selection line SSL4. At the seventh time t7, the pre-programming voltage VPGM may be applied to the word line WL. At the seventh time t7, the pass voltage VPASS may be applied to the ground selection line GSL. At the seventh time t7, the ground voltage VSS may be applied to the common source line CSL. In addition, at the eighth time t8, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the eighth time t8, the word line WL may be floated. At the eighth time t8, the ground selection line GSL may be floated. At the eighth time t8, the common source line CSL may be floated.

[0268] Figure 14C It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0269] The memory device 100 may perform a pre-program operation on cell strings connected to the first to fourth string selection lines SSL1 to SSL4 of the first dummy memory block BLKd1. In an embodiment, the memory device 100 may simultaneously perform a pre-program operation on cell strings connected to each of two or more string selection lines among the first to fourth string selection lines SSL1 to SSL4.

[0270] For example, the memory device 100 may perform a pre-program operation on cell strings connected to the first and second string selection lines SSL1 and SSL2 , and then perform a pre-program operation on cell strings connected to the third and fourth string selection lines SSL3 and SSL4 .

[0271] The memory device 100 can simultaneously perform a pre-programming operation on cell strings connected to a first string selection line SSL1 and a second string selection line SSL2. The memory device 100 can apply a first voltage V1 to the first string selection line SSL1. The memory device 100 can apply a first voltage V1 to the second string selection line SSL2. The memory device 100 can apply a ground voltage VSS to the third string selection line SSL3. The memory device 100 can apply a ground voltage VSS to the fourth string selection line SSL4. The memory device 100 can apply a pre-programming voltage VPGM to the word line WL. The memory device 100 can apply a pass voltage VPASS to the ground selection line GSL. The memory device 100 can apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate can maintain the ground voltage VSS.

[0272] For example, at a first time t1, a first voltage V1 may be applied to the first and second string selection lines SSL1 and SSL2. At the first time t1, a ground voltage VSS may be applied to the third and fourth string selection lines SSL3 and SSL4. At the first time t1, a pre-programming voltage VPGM may be applied to the word lines WL. At the first time t1, a pass voltage VPASS may be applied to the ground selection line GSL. At the first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the second time t2, the word lines WL connected to the first to fourth string selection lines SSL1 to SSL4 may be floated. At the second time t2, the ground selection line GSL may be floated. At the second time t2, the common source line CSL may be floated.

[0273] The memory device 100 may perform a pre-programming operation on the cell strings connected to the first and second string selection lines SSL1 and SSL2, and then may perform a pre-programming operation on the cell strings connected to the third and fourth string selection lines SSL3 and SSL4. The memory device 100 may apply a ground voltage VSS to the first string selection line SSL1. The memory device 100 may apply a ground voltage VSS to the second string selection line SSL2. The memory device 100 may apply a first voltage V1 to the third string selection line SSL3. The memory device 100 may apply a first voltage V1 to the fourth string selection line SSL4. The memory device 100 may apply a pre-programming voltage VPGM to the word line WL. The memory device 100 may apply a pass voltage VPASS to the ground selection line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0274] For example, at the third time t3, the ground voltage VSS may be applied to the first and second string selection lines SSL1 and SSL2. At the third time t3, the first voltage V1 may be applied to the third and fourth string selection lines SSL3 and SSL4. At the third time t3, the pre-program voltage VPGM may be applied to the word line WL. At the third time t3, the pass voltage VPASS may be applied to the ground selection line GSL. At the third time t3, the ground voltage VSS may be applied to the common source line CSL. Furthermore, at the fourth time t4, the first to fourth string selection lines SSL1 to SSL4 may be floated. At the fourth time t4, the word line WL may be floated. At the fourth time t4, the ground selection line GSL may be floated. At the fourth time t4, the common source line CSL may be floated.

[0275] Figure 14D It shows Figure 1 1 is a timing diagram of a pre-programming operation of the memory device 100.

[0276] The memory device 100 may perform a pre-program operation on cell strings connected to the first to fourth string selection lines SSL1 to SSL4 of the first dummy memory block BLKd1. In an embodiment, the memory device 100 may simultaneously perform a pre-program operation on cell strings connected to each of two or more string selection lines among the first to fourth string selection lines SSL1 to SSL4.

[0277] For example, the memory device 100 may perform a pre-program operation on cell strings connected to the first and second string selection lines SSL1 and SSL2 , and then perform a pre-program operation on cell strings connected to the third and fourth string selection lines SSL3 and SSL4 .

[0278] The memory device 100 may sequentially perform a pre-programming operation on a plurality of structures of cell strings connected to the first string selection line SSL1 and the second string selection line SSL2. In an embodiment, the memory device 100 may perform a pre-programming operation on the first structure ST1, then on the second structure ST2, and then on the third structure ST3.

[0279] The memory device 100 may perform a pre-programming operation on a cell string connected to a first string selection line SSL1 and a second string selection line SSL2. The memory device 100 may apply a first voltage V1 to the first string selection line SSL1. The memory device 100 may apply a first voltage V1 to the second string selection line SSL2. The memory device 100 may apply a ground voltage VSS to the third string selection line SSL3. The memory device 100 may apply a ground voltage VSS to the fourth string selection line SSL4.

[0280] For example, at the first time t1, the first voltage V1 may be applied to the first and second string selection lines SSL1 and SSL2. At the first time t1, the ground voltage VSS may be applied to the third and fourth string selection lines SSL3 and SSL4. Furthermore, at the sixth time t6, the first to fourth string selection lines SSL1 to SSL4 may be floated.

[0281] The memory device 100 may perform a pre-programming operation on the first structure ST1. The memory device 100 may apply a pre-programming voltage VPGM to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0282] For example, at a first time t1, a pre-program voltage VPGM may be applied to the first to fourth word lines WL1 to WL4. At a first time t1, a pass voltage VPASS may be applied to the fifth to thirteenth word lines WL5 to WL13. At a first time t1, a pass voltage VPASS may be applied to the ground select line GSL. At a first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to thirteenth word lines WL1 to WL3 may be floated. At a second time t2, the ground select line GSL may be floated. At a second time t2, the common source line CSL may be floated.

[0283] After performing a pre-programming operation on the first structure ST1, the memory device 100 may perform a pre-programming operation on the second structure ST2. The memory device 100 may apply a pre-programming voltage VPGM to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0284] For example, at the third time t3, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the third time t3, a pre-program voltage VPGM may be applied to the fifth to ninth word lines WL5 to WL9. At the third time t3, a pass voltage VPASS may be applied to the third to thirteenth word lines WL10 to WL13. At the third time t3, a pass voltage VPASS may be applied to the ground select line GSL. At the third time t3, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the fourth time t4, the first to thirteenth word lines WL1 to WL3 may be floated. At the fourth time t4, the ground select line GSL may be floated. At the fourth time t4, the common source line CSL may be floated.

[0285] After performing a pre-programming operation on the second structure ST2, the memory device 100 may perform a pre-programming operation on the third structure ST3. A pre-programming voltage VPGM may be applied to the first through thirteenth word lines WL10 through WL13 connected to the third structure ST3. The memory device 100 may apply a pass voltage VPASS to the first through fourth word lines WL1 through WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth through ninth word lines WL5 through WL9 connected to the second structure ST2. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. While the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0286] For example, at the fifth time t5, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the fifth time t5, a pass voltage VPASS may be applied to the fifth to ninth word lines WL5 to WL9. At the fifth time t5, a pre-programming voltage VPGM may be applied to the first to thirteenth word lines WL10 to WL13. At the fifth time t5, a pass voltage VPASS may be applied to the ground select line GSL. At the fifth time t5, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the sixth time t6, the first to thirteenth word lines WL1 to WL3 may be floated. At the sixth time t6, the ground select line GSL may be floated. At the sixth time t6, the common source line CSL may be floated.

[0287] The memory device 100 may sequentially perform a pre-program operation on a plurality of structures of cell strings connected to the first and second string selection lines SSL1 and SSL2. Thereafter, the memory device 100 may sequentially perform a pre-program operation on a plurality of structures of cell strings connected to the third and fourth string selection lines SSL3 and SSL4.

[0288] The memory device 100 may apply the ground voltage VSS to the first string selection line SSL1. The memory device 100 may apply the ground voltage VSS to the second string selection line SSL2. The memory device 100 may apply the first voltage V1 to the third string selection line SSL3. The memory device 100 may apply the first voltage V1 to the fourth string selection line SSL4.

[0289] For example, at the seventh time t7, the ground voltage VSS may be applied to the first and second string selection lines SSL1 and SSL2. At the seventh time t7, the first voltage V1 may be applied to the third and fourth string selection lines SSL3 and SSL4. Furthermore, at the twelfth time t12, the first to fourth string selection lines SSL1 to SSL4 may be floated.

[0290] The memory device 100 may perform a pre-programming operation on the first structure ST1. The memory device 100 may apply a pre-programming voltage VPGM to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0291] For example, at the seventh time t7, the pre-program voltage VPGM may be applied to the first to fourth word lines WL1 to WL4. At the seventh time t7, the pass voltage VPASS may be applied to the fifth to thirteenth word lines WL5 to WL13. At the seventh time t7, the pass voltage VPASS may be applied to the ground select line GSL. At the seventh time t7, the ground voltage VSS may be applied to the common source line CSL. Furthermore, at the eighth time t8, the first to thirteenth word lines WL1 to WL3 may be floated. At the eighth time t8, the ground select line GSL may be floated. At the eighth time t8, the common source line CSL may be floated.

[0292] After performing a pre-programming operation on the first structure ST1, the memory device 100 may perform a pre-programming operation on the second structure ST2. The memory device 100 may apply a pre-programming voltage VPGM to the fifth to ninth word lines WL5 to WL9 connected to the second structure ST2. The memory device 100 may apply a pass voltage VPASS to the first to fourth word lines WL1 to WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the cross lines WL10 to WL13 connected to the third structure ST3. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0293] For example, at the ninth time t9, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the ninth time t9, a pre-program voltage VPGM may be applied to the fifth to ninth word lines WL5 to WL9. At the ninth time t9, a pass voltage VPASS may be applied to the first to thirteenth word lines WL10 to WL13. At the ninth time t9, a pass voltage VPASS may be applied to the ground select line GSL. At the ninth time t9, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the tenth time t10, the first to thirteenth word lines WL1 to WL3 may be floated. At the tenth time t10, the ground select line GSL may be floated. At the tenth time t10, the common source line CSL may be floated.

[0294] After performing a pre-programming operation on the second structure ST2, the memory device 100 may perform a pre-programming operation on the third structure ST3. A pre-programming voltage VPGM may be applied to the first through thirteenth word lines WL10 through WL13 connected to the third structure ST3. The memory device 100 may apply a pass voltage VPASS to the first through fourth word lines WL1 through WL4 connected to the first structure ST1. The memory device 100 may apply a pass voltage VPASS to the fifth through ninth word lines WL5 through WL9 connected to the second structure ST2. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. While the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0295] For example, at the eleventh time t11, a pass voltage VPASS may be applied to the first to fourth word lines WL1 to WL4. At the eleventh time t11, a pass voltage VPASS may be applied to the fifth to ninth word lines WL5 to WL9. At the eleventh time t11, a pre-programming voltage VPGM may be applied to the first to thirteenth word lines WL10 to WL13. At the eleventh time t11, a pass voltage VPASS may be applied to the ground select line GSL. At the eleventh time t11, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at the twelfth time t12, the first to thirteenth word lines WL1 to WL3 may be floated. At the twelfth time t12, the ground select line GSL may be floated. At the twelfth time t12, the common source line CSL may be floated.

[0296] Figure 15A It shows Figure 1 1 is a circuit diagram of a second dummy memory block BLKd2 among a plurality of memory blocks included in the memory cell array 130. Figure 15B It shows Figure 15A FIG. 4 is a vertical cross-sectional view of a first cell string NS11 among the cell strings of FIG.

[0297] For the convenience of description, detailed description of the above components is omitted. Figure 15A The second dummy memory block BLKd2 is taken as an example for description, but the scope of the present inventive concept is not limited thereto. A plurality of other memory blocks included in the memory cell array 130 may each have a structure similar to that of the second dummy memory block BLKd2.

[0298] refer to Figure 15A and Figure 15B The second dummy memory block BLKd2 may include a plurality of cell strings NS11, NS12, NS21, and NS22. Each of the plurality of cell strings NS11, NS12, NS21, and NS22 may include a plurality of cell transistors. The plurality of cell transistors may be connected in series between the corresponding first bit line BL1 or second bit line BL2 and the common source line CSL.

[0299] The plurality of cell transistors may include a ground selection transistor GST, a first edge dummy memory cell EDMC1 and a second edge dummy memory cell EDMC2, a first to a fourth center dummy memory cell CDMC1, CDMC2, CDMC3 and CDMC4, a first to a seventh memory cell MC1, MC2, MC3, MC4, MC5, MC6 and MC7 and a string selection transistor SST. The ground selection transistor GST can be connected to each ground selection line GSL1 and GSL2, the first edge dummy memory cell EDMC1 and the second edge dummy memory cell EDMC2 can be connected to the first edge dummy word line EDWL1 and the second edge dummy word line EDWL2, respectively, the first to fourth center dummy memory cells CDMC1, CDMC2, CDMC3 and CDMC4 can be connected to the first to fourth center dummy word lines CDWL1, CDWL2, CDWL3 and CDWL4, the first to seventh memory cells MC1, MC2, MC3, MC4, MC5, MC6 and CM7 can be connected to the first to seventh word lines WL1, WL2, WL3, WL4, WL5, WL6 and WL7, respectively, and the string selection transistor SST can be connected to each of the first string selection line SSL1 and the second string selection line SSL2.

[0300] In an embodiment, the first edge dummy memory cell EDMC1, the first memory cell MC1, the second memory cell MC2, the first center dummy memory cell CDMC1, the second center dummy memory cell CDMC2, the third memory cell MC3, the fourth memory cell MC4, the fifth memory cell MC5, the third center dummy memory cell CDMC3, the fourth center dummy memory cell CDMC4, the sixth memory cell MC6, the seventh memory cell MC7 and the second edge dummy memory cell EDMC2 can be connected in series between the string selection transistor SST and the ground selection transistor GST.

[0301] In an embodiment, the dummy memory cells including the first and second edge dummy memory cells EDMC1 and EDMC2 and the first to fourth central dummy memory cells CDMC1 , CDMC2 , CDMC3 , and CDMC4 may be memory cells that do not store actual data.

[0302] The second dummy memory block BLKd2 may have a multi-stack structure and may include a first structure ST1, a second structure ST2, and a third structure ST3. The first structure ST1 may include a ground selection transistor GST, a first edge dummy memory cell EDMC1, a first memory cell MC1, a second memory cell MC2, and a first center dummy memory cell CDMC1. The second structure ST2 may include a second center dummy memory cell CDMC2, a third center dummy memory cell CDMC3, and third to fifth memory cells MC3 to MC5. The third structure ST3 may include a string selection transistor SST, a second edge dummy memory cell EDMC2, a sixth memory cell MC6, a seventh memory cell MC7, and a fourth center dummy memory cell CDMC2.

[0303] In an embodiment, the uppermost word line of the first structure ST1 may be the first central dummy word line CDWL1, and the lowermost word line of the second structure ST2 may be the second central dummy word line CDWL2. The uppermost word line of the second structure ST2 may be the third central dummy word line CDWL3, and the lowermost word line of the third structure ST3 may be the fourth central dummy word line CDWL4.

[0304] In other words, the first central dummy word line CDWL1 may be the word line closest to the second structure ST2 among the word lines of the first structure ST1, and the second central dummy word line CDWL2 may be the word line closest to the first structure ST1 among the word lines of the second structure ST2. The third central dummy word line CDWL3 may be the word line closest to the third structure ST3 among the word lines of the second structure ST2, and the fourth central dummy word line CDWL4 may be the word line closest to the second structure ST2 among the word lines of the third structure ST3.

[0305] like Figure 15B As shown, the channel diameter corresponding to the first central dummy word line CDWL1 can be wider than the channel diameter corresponding to the second central dummy word line CDWL2. Alternatively, the distance L1 between the first central dummy word line CDWL1 and the second central dummy word line CDWL2 can be greater than the distance L2 between the other word lines. The channel diameter corresponding to the third central dummy word line CDWL3 can be greater than the channel diameter corresponding to the fourth central dummy word line CDWL4. Alternatively, the distance L1 between the third central dummy word line CDWL3 and the fourth central dummy word line CDWL4 can be greater than the distance L2 between the other word lines. Due to these physical or structural characteristics, the first central dummy memory cell CDMC1 and the second central dummy memory cell CDMC2 connected to the first central dummy word line CDWL1 and the second central dummy word line CDWL2 may not be used to store actual data.

[0306] In the following, for ease of description, terms such as normal word line, center dummy word line, and edge dummy word line are used. A normal word line may indicate a word line connected to a memory cell for storing actual data among the memory cells included in a memory block. A dummy word line may include a center dummy word line and an edge dummy word line. A dummy word line may indicate a word line connected to a memory cell that is not used to store actual data among the memory cells included in a memory block. For example, data may not be stored in the memory cell connected to the dummy word line. Alternatively, the memory cell connected to the dummy word line may store fewer data bits than the memory cell connected to the normal word line. As described above, the center dummy word line may indicate a word line that is closest to another structure in each stacked structure. An edge dummy word line may indicate a word line connected to a memory cell that is closest to a string select transistor or a ground select transistor.

[0307] Figure 15A The second dummy memory block BLKd2 may be similar in structure to Figure 13A The first dummy memory block BLKd1 is configured by adding first and second edge dummy memory cells EDMC1 to EDMC2 and first to fourth center dummy memory cells CDMC1 to CDMC4 , and detailed descriptions thereof are omitted.

[0308] Figure 15C is a flowchart illustrating an operating method of the memory device 100 according to an embodiment. Figure 15D It shows Figure 1 1 is a timing diagram of a first pre-programming operation of the memory device 100. Figure 15E It shows Figure 1 1 is a timing diagram of a second pre-programming operation of the memory device 100.

[0309] refer to Figures 15A to 15E , the memory device 100 may perform a pre-programming operation on a dummy memory block. In an embodiment, the pre-programming operation may include a first pre-programming operation and a second pre-programming operation. The first pre-programming operation may indicate an operation of applying a pre-programming voltage only to memory cells connected to normal word lines. For example, the first pre-programming operation may indicate an operation of applying a pass voltage to a dummy word line and applying a pre-programming voltage to a normal word line. The second pre-programming operation may indicate an operation of applying a pre-programming voltage to both memory cells connected to a normal word line and memory cells connected to a dummy word line. For example, the second pre-programming operation may indicate an operation of applying a pre-programming voltage to a dummy word line and applying a pre-programming voltage to a normal word line.

[0310] In an embodiment, the memory device 100 may always preprogram memory cells connected to normal word lines before performing an erase operation on a dummy memory block. Before performing an erase operation on a dummy memory block, the memory device 100 may preprogram memory cells connected to the dummy word lines only a specific number of times. The memory device 100 may preprogram memory cells connected to a central dummy word line and edge dummy word lines only a specific number of times.

[0311] In an embodiment, the memory device 100 may perform a pre-programming operation based on a program / erase cycle. For example, when the program / erase cycle is a specific multiple, the memory device 100 may perform a second pre-programming operation, and when the program / erase cycle is not a specific multiple, the memory device 100 may perform a first pre-programming operation. For example, when the program / erase cycle is not a specific multiple, the memory device 100 may apply a program voltage to the memory cells connected to the normal word line, apply a pass voltage to the memory cells connected to the center dummy word line, and apply a pass voltage to the memory cells connected to the edge dummy word line. When the program / erase cycle is a specific multiple, the memory device 100 may apply a pre-programming voltage to the memory cells connected to the normal word line, apply a pre-programming voltage to the memory cells connected to the center dummy word line, and apply a pre-programming voltage to the memory cells connected to the edge dummy word line.

[0312] In operation S210, the memory device 100 may receive an erase command from an external memory controller. For example, the memory device 100 may receive an erase command for a dummy memory block.

[0313] In operation S220, the memory device 100 may determine whether the program / erase cycle is a specific multiple. For example, the memory device 100 may perform a modulo operation in the program / erase cycle to determine whether the result value is '0'. When the result value is '0', the memory device 100 may determine that the program / erase cycle is a specific multiple. When the result value is not '0', the memory device 100 may determine that the program / erase cycle is not a specific multiple. When the program / erase cycle is not a specific multiple, the memory device 100 may perform operation S230, and when the program / erase cycle is a specific multiple, the memory device 100 may perform operation S240.

[0314] In operation S230, the memory device 100 may perform a first pre-programming operation. In one embodiment, the memory device 100 may apply a pre-programming voltage only to memory cells connected to normal word lines, apply a pass voltage to memory cells connected to the center dummy word line, and apply a pass voltage to memory cells connected to the edge dummy word lines.

[0315] In operation S240, the memory device 100 may perform a second pre-programming operation. In one embodiment, the memory device 100 may apply a pre-programming voltage to the memory cells connected to the normal word lines, apply a pre-programming voltage to the memory cells connected to the center dummy word lines, and apply a pre-programming voltage to the memory cells connected to the edge dummy word lines.

[0316] In operation S250, the memory device 100 may update the program / erase cycle. For example, the memory device 100 may increase the program / erase cycle by "1". In operation S260, the memory device 100 may perform an erase operation. For example, the memory device 100 may perform an erase operation on the dummy memory block that has been pre-programmed.

[0317] Will refer to Figure 15D The first pre-programming operation is described in detail. The memory device 100 may perform the first pre-programming operation on the second dummy memory block BLKd2. The memory device 100 may apply a pre-programming voltage VPGM to the first to seventh word lines WL1 to WL7. The memory device 100 may apply a pass voltage VPASS to the first to fourth center dummy word lines CDWL1 to CDWL4. The memory device 100 may apply a pass voltage VPASS to the first and second edge dummy word lines EDWL1 and EDWL2. The memory device 100 may apply the pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0318] For example, at a first time t1, a pre-program voltage VPGM may be applied to the first to seventh word lines WL1 to WL7. At a first time t1, a pass voltage VPASS may be applied to the first to fourth center dummy word lines CDWL1 to CDWL4. At a first time t1, a pass voltage VPASS may be applied to the first and second edge dummy word lines EDWL1 and EDWL2. At a first time t1, a pass voltage VPASS may be applied to the ground select line GSL. At a first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at a second time t2, the first to seventh word lines WL1 to W7 may be floated. At a second time t2, the first to fourth center dummy word lines CDWL1 to CDWL4 may be floated. At a second time t2, the first and second edge dummy word lines EDWL1 and EDWL2 may be floated. At a second time t2, the ground select line GSL may be floated. At the second time t2 , the common source line CSL may float.

[0319] Will refer to Figure 15EThe second pre-programming operation is described in detail. The memory device 100 may perform the second pre-programming operation on the second dummy memory block BLKd2. The memory device 100 may apply a pre-programming voltage VPGM to the first to seventh word lines WL1 to WL7. The memory device 100 may apply a pre-programming voltage VPGM to the first to fourth center dummy word lines CDWL1 to CDWL4. The memory device 100 may apply a pre-programming voltage VPGM to the first and second edge dummy word lines EDWL1 and EDWL2. The memory device 100 may apply a pass voltage VPASS to the ground select line GSL. The memory device 100 may apply a ground voltage VSS to the common source line CSL. When the memory device 100 performs the pre-programming operation, the substrate may maintain the ground voltage VSS.

[0320] For example, at first time t1, a pre-program voltage VPGM may be applied to the first to seventh word lines WL1 to WL7. At first time t1, a pre-program voltage VPGM may be applied to the first to fourth center dummy word lines CDWL1 to CDWL4. At first time t1, a pre-program voltage VPGM may be applied to the first and second edge dummy word lines EDWL1 and EDWL2. At first time t1, a pass voltage VPASS may be applied to the ground select line GSL. At first time t1, a ground voltage VSS may be applied to the common source line CSL. Furthermore, at second time t2, the first to seventh word lines WL1 to W7 may be floated. At second time t2, the first to fourth center dummy word lines CDWL1 to CDWL4 may be floated. At second time t2, the first and second edge dummy word lines EDWL1 and EDWL2 may be floated. At second time t2, the ground select line GSL may be floated. At the second time t2 , the common source line CSL may float.

[0321] In the examples, reference 12A to 14D The described pre-programming operation can be applied to both the first pre-programming operation and the second pre-programming operation. For example, in the first pre-programming operation, the pre-programming operation can be sequentially performed on the first structure to the third structure. Alternatively, in the first pre-programming operation, the cell strings connected to the first string selection line to the fourth string selection line can sequentially perform the pre-programming operation.

[0322] Figure 16 1 is a block diagram illustrating a solid state drive (SSD) system 1000 to which a memory device according to an embodiment is applied. Figure 16 , the SSD system 1000 includes a host 1100 and an SSD 1200 .

[0323] The SSD 1200 exchanges signals SIG with the host 1100 through a signal connector 1201 and receives power PWR through a power connector 1202. The SSD 1200 includes an SSD memory controller 1210, a plurality of flash memories 1221 to 122n, an auxiliary power supply 1230, and a buffer memory 1240.

[0324] The SSD memory controller 1210 can control the plurality of flash memories 1221 to 122n in response to a signal SIG received from the host 1100. The plurality of flash memories 1221 to 122n can be operated under the control of the SSD memory controller 1210. The auxiliary power supply 1230 is connected to the host 1100 via the power connector 1202. The auxiliary power supply 1230 can receive power PWR from the host 1100 and be charged using the power PWR. When the power supply from the host 1100 is not smooth, the auxiliary power supply 1230 can provide power to the SSD 1200.

[0325] In an embodiment, each of the plurality of flash memories 1221 to 122n may include a reference Figures 1 to 12C The dummy memory block BLKd described above. The dummy memory block BLKd of each of the plurality of flash memories 1221 to 122n may include at least one string group of the first type T1, and each of the plurality of flash memories 1221 to 122n may store data in a portion of the dummy memory block BLKd. Each of the plurality of flash memories 1221 to 122n may perform a reference to the dummy memory block BLKd. Figures 1 to 12C The pre-programming operation and the erase operation described above are performed. Therefore, the size of the plurality of flash memories 1221 to 122n can be reduced, or the storage space of the plurality of flash memories 1221 to 122n can be increased. In addition, by performing the pre-programming operation, the reliability of the plurality of flash memories 1221 to 122n can be improved.

[0326] Figure 17 is a cross-sectional view of a memory device 500 having a B-VNAND structure according to an embodiment.

[0327] refer to Figure 17 , the memory device 500 may have a chip-to-chip (C2C) structure. Here, the C2C structure may mean manufacturing at least one upper chip including a cell region CELL and a lower chip including a peripheral circuit region PERI, and then connecting them to each other using a bonding method. For example, the bonding method may mean a method of electrically or physically connecting a bonding metal pattern formed on the uppermost metal layer of the upper chip and a bonding metal pattern formed on the uppermost metal layer of the lower chip. For example, when the bonding metal pattern includes copper (Cu), the bonding method may be a Cu-Cu bonding method. As another example, the bonding metal pattern may include aluminum (Al) or tungsten (W).

[0328] The memory device 500 may include at least one upper chip including a cell region. Figure 17 As shown, the memory device 500 can be implemented to include two upper chips. However, this is just an example, and the number of upper chips is not limited thereto. When the memory device 500 is implemented to include two upper chips, the memory device 500 can be manufactured by manufacturing a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI, and then connecting the first upper chip, the second upper chip, and the lower chip to each other using a bonding method. The first upper chip can be flipped over and connected to the lower chip using a bonding method, and the second upper chip can also be flipped over and connected to the first upper chip using a bonding method. In the following description, the upper and lower parts of each of the first upper chip and the second upper chip are defined relative to before the first upper chip and the second upper chip are flipped over. For example, in Figure 17 In the embodiment, the upper portion of the lower chip refers to the upper portion defined relative to the +Z axis direction, and the upper portion of each of the first upper chip and the second upper chip refers to the upper portion defined relative to the -Z axis direction. However, this is only an example, and in some examples, only one of the first upper chip and the second upper chip may be flipped and connected using a bonding method.

[0329] Each of the peripheral circuit region PERI, the first cell region CELL1, and the second cell region CELL2 of the memory device 500 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The peripheral circuit region PERI may include a first substrate 210 and a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210. An interlayer insulating layer 215 including one or more insulating layers may be provided on the plurality of circuit elements 220a, 220b, and 220c, and a plurality of metal wirings connecting the plurality of circuit elements 220a, 220b, and 220c may be provided in the interlayer insulating layer 215. For example, the plurality of metal wirings may include first metal wirings 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal wirings 240a, 240b, and 240c formed on the first metal wirings 230a, 230b, and 230c, respectively. The plurality of metal wirings may include at least one of a plurality of conductive materials. For example, the first metal wirings 230a, 230b, and 230c may include tungsten having a relatively high resistivity, and the second metal wirings 240a, 240b, and 240c may include copper having a relatively low resistivity.

[0330] While only the first metal wirings 230a, 230b, and 230c and the second metal wirings 240a, 240b, and 240c are shown and described herein, the present invention is not limited thereto, and one or more additional metal wirings may be further formed on the second metal wirings 240a, 240b, and 240c. In this case, the second metal wirings 240a, 240b, and 240c may include aluminum. In addition, at least some of the additional metal wirings formed on the second metal wirings 240a, 240b, and 240c may include copper, etc., having a resistivity lower than that of the aluminum of the second metal wirings 240a, 240b, and 240c. The interlayer insulating layer 215 may be provided on the first substrate 210 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0331] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 310 and a common source line 320. A plurality of word lines 330 (including word lines 331 to 338) may be stacked on the second substrate 310 in a direction perpendicular to the upper surface of the second substrate 310 (the Z-axis direction). String select lines and ground select lines may be disposed above and below the word lines 330, and the plurality of word lines 330 may be disposed between the string select lines and the ground select lines. Similarly, the second cell region CELL2 may include a third substrate 410 and a common source line 420. The plurality of word lines 430 (including word lines 431 to 438) may be stacked in a direction perpendicular to the upper surface of the third substrate 410 (the Z-axis direction). The second substrate 310 and the third substrate 410 may be made of various materials, for example, each substrate may be a silicon substrate, a silicon-germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first and second cell regions CELL1 and CELL2 .

[0332] In an embodiment, as shown in A1, a channel structure CH may be provided in the bitline bonding area BLBA and extend in a direction perpendicular to the upper surface of the second substrate 310 to pass through the wordline 330, the string select line, and the ground select line. The channel structure CH may include a data storage layer, a channel layer (e.g., a semiconductor layer), a buried insulating layer, etc. The channel layer may be electrically connected to the first metal wiring 350c and the second metal wiring 360c in the bitline bonding area BLBA. For example, the second metal wiring 360c may be a bitline and connected to the channel structure CH via the first metal wiring 350c. The bitline 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0333] In an embodiment, as shown in A2, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for the lower channel LCH and a process for the upper channel UCH. The lower channel LCH may extend in a direction perpendicular to the upper surface of the second substrate 310 and pass through the common source line 320 and the lower word lines 331 and 332. The lower channel LCH may include a data storage layer, a channel layer, a buried insulating layer, etc., and is connected to the upper channel UCH. The upper channel UCH may pass through the upper word lines 333 to 338. The upper channel UCH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer of the upper channel UCH may be electrically connected to the first metal wiring 350c and the second metal wiring 360c. As the channel length increases, it may be difficult to form a channel with a constant width due to process reasons. The memory device 500 according to an embodiment may include a channel with improved width uniformity by forming the lower channel LCH and the upper channel UCH in a sequential process.

[0334] As shown in A2, when the channel structure CH is formed to include a lower channel LCH and an upper channel UCH, the word lines near the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. For example, the word line 332 and the upper word line 333 forming the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines may be less than the number of pages corresponding to the memory cells connected to the normal word lines. The voltage level applied to the dummy word lines may be different from the voltage level applied to the normal word lines, and therefore, the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device 500 can be reduced.

[0335] Meanwhile, in A2, the number of lower word lines 331 and 332 passing through the lower channel LCH is smaller than the number of upper word lines 333 to 338 passing through the upper channel UCH. However, this is merely an example, and the present invention is not limited thereto. As another example, the number of lower word lines passing through the lower channel LCH may be equal to or greater than the number of upper word lines passing through the upper channel UCH. Furthermore, the structure and connection relationship of the channel structure CH provided in the first cell region CELL1 described above may be equally applicable to the channel structure CH provided in the second cell region CELL2.

[0336] In the bit line bonding area BLBA, the first through electrode THV1 may be provided in the first cell area CELL1, and the second through electrode THV2 may be provided in the second cell area CELL2. The first through electrode THV1 may pass through the common source line 320 and the plurality of word lines 330. However, this is merely an example, and the first through electrode THV1 may also pass through the second substrate 310. The first through electrode THV1 may include a conductive material. Alternatively, the first through electrode THV1 may include a conductive material surrounded by an insulating material. The second through electrode THV2 may also be provided in the same shape and structure as the first through electrode THV1.

[0337] The first through-electrode THV1 and the second through-electrode THV2 can be electrically connected to each other via a first through-metal pattern 372d and a second through-metal pattern 472d. The first through-metal pattern 372d can be formed at the lower end of the first upper chip including the first cell region CELL1, and the second through-metal pattern 472d can be formed at the upper end of the second upper chip including the second cell region CELL2. The first through-electrode THV1 can be electrically connected to the first metal wiring 350c and the second metal wiring 360c. A lower through-hole 371d can be formed between the first through-electrode THV1 and the first through-metal pattern 372d, and an upper through-hole 471d can be formed between the second through-electrode THV2 and the second through-metal pattern 472d. The first through-metal pattern 372d and the second through-metal pattern 472d can be connected to each other by a bonding method.

[0338] In addition, in the bit line bonding area BLBA, an upper metal pattern 252 may be formed on the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 392 having the same shape as the upper metal pattern 252 may be formed on the uppermost metal layer of the first cell area CELL1. The upper metal pattern 392 of the first cell area CELL1 and the upper metal pattern 252 of the peripheral circuit area PERI may be electrically connected to each other using a bonding method. In the bit line bonding area BLBA, the bit line 360c may be electrically connected to the page buffer included in the peripheral circuit area PERI. For example, some circuit elements 220c of the peripheral circuit area PERI may provide a page buffer, and the bit line 360c may be electrically connected to the circuit element 220c providing the page buffer through the upper bonding metal 370c of the first cell area CELL1 and the upper bonding metal 270c of the peripheral circuit area PERI.

[0339] In the examples, as referenced Figures 1 to 16As described above, the first channel structure in the channel structures CH of the first cell region CELL1 and the second cell region CELL2 can be electrically connected to the bit line 360c through the first metal wiring 350c. Since the first metal wiring 350c is not formed in the second channel structure in the channel structures CH of the first cell region CELL1 and the second cell region CELL2, the second channel structure may not be connected to the bit line 360c.

[0340] In the word line bonding area WLBA, the word lines 330 of the first cell region CELL1 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and may be connected to a plurality of cell contact plugs 340 (including contact plugs 341 to 347). First metal wirings 350b and second metal wirings 360b may be sequentially connected to upper portions of the cell contact plugs 340 connected to the word lines 330. The cell contact plugs 340 may be connected to the peripheral circuit region PERI in the word line bonding area WLBA via an upper bonding metal 370b of the first cell region CELL1 and an upper bonding metal 270b of the peripheral circuit region PERI.

[0341] The cell contact plug 340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 220b of the peripheral circuit region PERI may provide a row decoder, and the cell contact plug 340 may be electrically connected to the circuit element 220b providing the row decoder via the upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI. In an embodiment, the operating voltage of the circuit element 220b providing the row decoder may be different from the operating voltage of the circuit element 220c providing the page buffer. For example, the operating voltage of the circuit element 220c providing the page buffer may be greater than the operating voltage of the circuit element 220b providing the row decoder.

[0342] Similarly, in the word line bonding area WLBA, the word lines 430 of the second cell region CELL2 may extend in a second direction (X-axis direction) parallel to the upper surface of the third substrate 410 and may be connected to a plurality of cell contact plugs 440 (including contact plugs 441 to 447). The cell contact plugs 440 may be connected to the peripheral circuit region PERI through the upper metal pattern of the second cell region CELL2, the lower and upper metal patterns of the first cell region CELL1, and the cell contact plugs 348.

[0343] In the word line bonding area WLBA, an upper bonding metal 370b may be formed in the first cell region CELL1, and an upper bonding metal 270b may be formed in the peripheral circuit region PERI. The upper bonding metal 370b of the first cell region CELL1 and the upper bonding metal 270b of the peripheral circuit region PERI may be electrically connected to each other using a bonding method. The upper bonding metal 370b and the upper bonding metal 270b may include aluminum, copper, tungsten, or the like.

[0344] In the external pad bonding area PA, a lower metal pattern 371e may be formed on the lower portion of the first cell area CELL1, and an upper metal pattern 472a may be formed on the upper portion of the second cell area CELL2. The lower metal pattern 371e of the first cell area CELL1 and the upper metal pattern 472a of the second cell area CELL2 may be connected to each other in the external pad bonding area PA by using a bonding method. Similarly, an upper metal pattern 372a may be formed in the upper portion of the first cell area CELL1, and an upper metal pattern 272a may be formed in the upper portion of the peripheral circuit area PERI. The upper metal pattern 372a of the first cell area CELL1 and the upper metal pattern 272a of the peripheral circuit area PERI may be connected by using a bonding method.

[0345] Common source line contact plugs 380 and 480 may be disposed in the external pad bonding area PA. Common source line contact plugs 380 and 480 may each include a conductive material, such as a metal, a metal compound, or doped polysilicon. Common source line contact plug 380 of the first cell region CELL1 may be electrically connected to common source line 320, and common source line contact plug 480 of the second cell region CELL2 may be electrically connected to common source line 420. First metal wiring 350a and second metal wiring 360a may be sequentially stacked on common source line contact plug 380 of the first cell region CELL1, and first metal wiring 450a and second metal wiring 460a may be sequentially stacked on common source line contact plug 480 of the second cell region CELL2.

[0346] The first to third input / output pads 205, 405, and 406 may be provided on the external pad landing area PA. The lower insulating layer 201 may cover the lower surface of the first substrate 210, and the first input / output pads 205 may be formed on the lower insulating layer 201. The first input / output pads 205 may be connected to at least one of the plurality of circuit elements 220a provided in the peripheral circuit region PERI through the first input / output contact plug 203 and be separated from the first substrate 210 by the lower insulating layer 201. In addition, a side insulating layer may be provided between the first input / output contact plug 203 and the first substrate 210, and may electrically separate the first input / output contact plug 203 from the first substrate 210.

[0347] An upper insulating layer 401 covering an upper surface of the third substrate 410 may be formed on the third substrate 410. Second input / output pads 405 and / or third input / output pads 406 may be provided on the upper insulating layer 401. The second input / output pads 405 may be connected to at least one of the plurality of circuit elements 220 a provided in the peripheral circuit region PERI through second input / output contact plugs 403 and 303, and the third input / output pads 406 may be connected to at least one of the plurality of circuit elements 220 a provided in the peripheral circuit region PERI through third input / output contact plugs 404 and 304.

[0348] The third substrate 410 may not be provided in the region where the input / output contact plug is provided. For example, as shown in B, the third input / output contact plug 404 may be separated from the third substrate 410 in a direction parallel to the upper surface of the third substrate 410, may pass through the interlayer insulating layer 415 of the second cell region CELL2, and be connected to the third input / output pad 406. In this case, the third input / output contact plug 404 may be formed by various processes.

[0349] For example, as shown in B1, the third input / output contact plug 404 may extend along the third direction (Z-axis direction) and be formed to have a diameter that increases toward the upper insulating layer 401. For example, the diameter of the channel structure CH described in A1 may decrease toward the upper insulating layer 401, while the diameter of the third input / output contact plug 404 may increase toward the upper insulating layer 401. For example, the third input / output contact plug 404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0350] Furthermore, for example, as shown in B2, the third input / output contact plug 404 may extend in the third direction (Z-axis direction) and be formed to have a diameter that decreases toward the upper insulating layer 401. For example, the diameter of the third input / output contact plug 404 may decrease toward the upper insulating layer 401 like the channel structure CH. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0351] In another embodiment, the input / output contact plug may be disposed to overlap with the third substrate 410. For example, as shown in C, the second input / output contact plug 403 may pass through the interlayer insulating layer 415 of the second cell region CELL2 in the third direction (Z-axis direction) and be electrically connected to the second input / output pad 405 through the third substrate 410. In this case, the connection structure between the second input / output contact plug 403 and the second input / output pad 405 may be implemented in various ways.

[0352] For example, as shown in C1, an opening 408 may be formed through the third substrate 410, and the second input / output contact plug 403 may be directly connected to the second input / output pad 405 through the opening 408 formed in the third substrate 410. In this case, as shown in C1, the diameter of the second input / output contact plug 403 may increase toward the second input / output pad 405. However, this is merely an example, and in some examples, the diameter of the second input / output contact plug 403 may decrease toward the second input / output pad 405.

[0353] For example, as shown in C2, an opening 408 may be formed through the third substrate 410, and a contact 407 may be formed in the opening 408. One end of the contact 407 may be connected to the second input / output pad 405, and the other end of the contact 407 may be connected to the second input / output contact plug 403. Thus, the second input / output contact plug 403 may be electrically connected to the second input / output pad 405 through the contact 407 in the opening 408. In this case, as shown in C2, the diameter of the contact 407 may increase toward the second input / output pad 405, and the diameter of the second input / output contact plug 403 may decrease toward the second input / output pad 405. For example, the third input / output contact plug 404 may be formed together with the cell contact plug 440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact 407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0354] Furthermore, for example, as shown in C3, compared to C2, a barrier 409 may be further formed on the upper surface of the opening 408 of the third substrate 410. The barrier 409 may be a metal wiring formed on the same layer as the common source line 420. However, this is merely an example, and in some examples, the barrier 409 may be a metal wiring formed on the same layer as the at least one word line 430. The second input / output contact plug 403 may be electrically connected to the second input / output pad 405 via the contact 407 and the barrier 409.

[0355] At the same time, similar to the second input / output contact plug 403 and the third input / output contact plug 404 of the second cell area CELL2, the second input / output contact plug 303 and the third input / output contact plug 304 of the first cell area CELL1 can each be formed to have a diameter that decreases toward the lower metal pattern 371e or a diameter that increases toward the lower metal pattern 371e.

[0356] Meanwhile, according to some embodiments, a slit 411 may be formed in the third substrate 410. For example, the slit 411 may be formed at any position in the external pad landing area PA. For example, as shown in D, in a plan view, the slit 411 may be between the second input / output pad 405 and the cell contact plug 440. However, this is merely an example, and in some examples, the slit 411 may be formed so that the second input / output pad 405 may be between the slit 411 and the cell contact plug 440 in a plan view.

[0357] For example, as shown in D1, slits 411 may be formed through the third substrate 410. For example, slits 411 may be used to prevent the third substrate 410 from being finely split when forming the opening 408. However, this is merely an example, and in some examples, slits 411 may be formed to a depth of about 60% to about 70% of the thickness of the third substrate 410.

[0358] In addition, for example, as shown in D2, a conductive material 412 may be formed in the slit 411. The conductive material 412 may be used to discharge leakage current generated during driving of the circuit element in the external pad bonding area PA to the outside. In this case, the conductive material 412 may be connected to an external ground line.

[0359] In addition, for example, as shown in D3, an insulating material 413 may be formed in the slit 411. The insulating material 413 may be formed to electrically separate the second input / output pad 405 and the second input / output contact plug 403 provided in the external pad bonding area PA from the word line bonding area WLBA. The insulating material 413 may be formed in the slit 411 to prevent a voltage supplied through the second input / output pad 405 from affecting a metal layer on the third substrate 410 provided in the word line bonding area WLBA.

[0360] According to some embodiments, the first to third input / output pads 205, 405, and 406 may be selectively formed. For example, the memory device 500 may include only the first input / output pad 205 disposed on the upper portion of the first substrate 210, only the second input / output pad 405 disposed on the upper portion of the third substrate 410, or only the third input / output pad 406 disposed on the upper insulating layer 401.

[0361] According to some embodiments, at least one of the second substrate 310 of the first cell region CELL1 or the third substrate 410 of the second cell region CELL2 can serve as a sacrificial substrate and be completely or partially removed before or after the bonding process. Additional layers may be stacked after removing at least one of the second substrate 310 or the third substrate 410. For example, before or after the peripheral circuit region PERI and the first cell region CELL1 are bonded to each other, the second substrate 310 of the first cell region CELL1 can be removed, and an insulating layer or a conductive layer for connection can be formed to cover the upper surface of the common source line 320. Similarly, before or after the first cell region CELL1 and the second cell region CELL2 are bonded to each other, the third substrate 410 of the second cell region CELL2 can be removed, and an upper insulating layer 401 or a conductive layer for connection can be formed to cover the upper surface of the common source line 420.

[0362] According to an embodiment, the upper bonding metal 270c of the peripheral circuit region PERI may be disposed on an upper portion of the page buffer circuit region and arranged in a matrix form according to a first direction (Y-axis direction) and a second direction (X-axis direction). The page buffer circuit region may correspond to the bit line bonding area BLBA. For example, the upper bonding metal 270c may be grouped into a plurality of bonding pad groups, and each of the bonding pad groups may include upper bonding metal 270c arranged in a row along the first direction (Y-axis direction). According to an embodiment, the peripheral circuit region PERI may include a plurality of through wirings extending along the first direction (Y-axis direction). For example, each of the through wirings may be disposed between adjacent bonding pad groups.

[0363] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device comprising a memory cell structure, the memory cell structure comprising a plurality of memory blocks, wherein: The plurality of memory blocks include a first dummy memory block and a plurality of main memory blocks, Each of the plurality of main memory blocks includes a first type of string group, The first dummy memory block includes a string group of the first type and a string group of a second type, The first type string group includes a plurality of first vertical channels connected to a first string selection line and to a bit line, and The second type string group includes a plurality of second vertical channels connected to a second string selection line and not connected to a bit line.

2. The memory device according to claim 1, wherein Memory cells included in the first type of string group of the first dummy memory block are configured to store data.

3. The memory device according to claim 1, wherein The first type of string group of the first dummy memory block is disposed adjacent to the plurality of main memory blocks.

4. The memory device according to claim 1, wherein The first dummy memory block is provided at one side of the plurality of main memory blocks.

5. The memory device according to claim 1, wherein The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer in which the bit line is disposed, and a second interlayer insulating layer; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a contact electrically connecting the first vertical channel to the bit line and disposed in the second interlayer insulating layer; and A second vertical channel passes through the gate stack structure, and Wherein, no contact is provided between the bit line and the second vertical channel. The memory device according to claim 1 , wherein: The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer in which the bit lines are disposed; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a first contact electrically connecting the bit line to the second contact and disposed in the second interlayer insulating layer; the second contact electrically connecting the first contact to the first vertical channel and disposed in the third interlayer insulating layer; and A second vertical channel passes through the gate stack structure, and Wherein, no contact is provided between the bit line and the second vertical channel.

7. The memory device according to claim 1, wherein The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer in which the bit lines are disposed; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a first contact electrically connecting the bit line to the second contact and disposed in the second interlayer insulating layer; The second contact electrically connects the first contact to the first vertical channel and is disposed in the third interlayer insulating layer; a second vertical channel passing through the gate stack structure; and a third contact connected to the bit line and disposed in the second interlayer insulating layer, and Wherein, no contact member is provided between the third contact member and the second vertical channel.

8. The memory device according to claim 1, wherein The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer in which the bit lines are disposed; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a first contact electrically connecting the bit line to the second contact and disposed in the second interlayer insulating layer; The second contact electrically connects the first contact to the first vertical channel and is disposed in the third interlayer insulating layer; a second vertical channel penetrating the gate stack structure; and a third contact connected to the second vertical channel and disposed in the third interlayer insulating layer, and Wherein, no contact is provided between the third contact and the bit line.

9. The memory device according to claim 1, further comprising: a row decoder connected to the memory cell structure through word lines, string select lines, and ground select lines, The row decoder is configured to perform a pre-program operation of applying a pre-program voltage to the first dummy memory block and perform an erase operation of applying an erase voltage to the first dummy memory block.

10. The memory device according to claim 9, wherein The row decoder is configured to perform the following operations to perform the pre-programming operation: applying the pre-program voltage to a word line of the second type string group connected to the first dummy memory block, applying a pass voltage to a ground select line of the second type string group connected to the first dummy memory block, and A ground voltage is applied to a common source line of the second type string group connected to the first dummy memory block.

11. A memory device comprising a memory cell structure, the memory cell structure comprising a plurality of memory blocks, wherein: The plurality of memory blocks include a first dummy memory block, a plurality of main memory blocks, and a second dummy memory block, The first dummy memory block is disposed on a first side of the plurality of main memory blocks, and the second dummy memory block is disposed on a second side of the plurality of main memory blocks, the second side facing the first side in a first direction, The first dummy memory block includes a first type of string group and a second type of string group, The second dummy memory block includes the first type string group and the second type string group, each of the plurality of main memory blocks includes a string group of the first type, The first type string group includes a plurality of first vertical channels connected to a first string selection line and to a bit line, and The second type string group includes a plurality of second vertical channels connected to a second string selection line and not connected to a bit line.

12. The memory device according to claim 11, wherein The memory cells included in the first type of string group of the first dummy memory block are configured to store data, and Memory cells included in the first type string group of the second dummy memory block are configured to store data.

13. The memory device according to claim 11, wherein The first type of string group of the first dummy memory block is disposed adjacent to the plurality of main memory blocks, and The first type string group of the second dummy memory block is disposed adjacent to the plurality of main memory blocks.

14. The memory device according to claim 11, wherein The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer in which the bit line is disposed, and a second interlayer insulating layer; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a contact electrically connecting the first vertical channel to the bit line and disposed in the second interlayer insulating layer; and A second vertical channel passes through the gate stack structure, and wherein No contact is provided between the bit line and the second vertical channel.

15. The memory device according to claim 11, wherein The memory cell structure further includes: a lower wiring structure including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer in which the bit line is disposed, a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a first contact electrically connecting the bit line to the second contact and disposed in the second interlayer insulating layer; The second contact electrically connects the first contact to the first vertical channel and is disposed in the third interlayer insulating layer; a second vertical channel passing through the gate stack structure; and A third contact is connected to the bit line and is provided in the second interlayer insulating layer, and wherein No contact member is provided between the third contact member and the second vertical channel.

16. The memory device according to claim 11, wherein The memory cell structure further includes: a lower wiring structure comprising a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer in which the bit lines are disposed; a gate stack structure disposed on the lower wiring structure and comprising conductive patterns and insulating patterns alternately stacked on top of each other; A first vertical channel passing through the gate stack structure; a first contact electrically connecting the bit line to the second contact and disposed in the second interlayer insulating layer; The second contact electrically connects the first contact to the first vertical channel and is disposed in the third interlayer insulating layer; a second vertical channel passing through the gate stack structure; and A third contact is connected to the second vertical channel and is disposed in the third interlayer insulating layer, and wherein No contact is provided between the third contact and the bit line.

17. The memory device according to claim 11, further comprising: a row decoder connected to the memory cell structure through word lines, string select lines, and ground select lines, The row decoder is configured to perform the following operations to perform a pre-programming operation: applying a pre-program voltage to word lines connected to the second type of string group, applying a pass voltage to a ground select line connected to the second type of string group, and A ground voltage is applied to the common source line connected to the second type of strings.

18. A memory device comprising a memory cell structure, the memory cell structure comprising a plurality of memory blocks, wherein: The plurality of memory blocks include a first dummy memory block and a plurality of main memory blocks, Each of the plurality of main memory blocks includes a plurality of first vertical channels connected to bit lines, and the first dummy memory block includes: a plurality of first vertical channels connected to the bit lines; and a plurality of second vertical channels not connected to the bit lines, and Data is stored in a memory cell included in each of the plurality of first vertical channels of the first dummy memory block.

19. The memory device according to claim 18, wherein The first vertical channel of the first dummy memory block is adjacent to the plurality of main memory blocks.

20. The memory device according to claim 18, further comprising: a row decoder connected to the memory cell structure through word lines, string select lines, and ground select lines, The row decoder is configured to perform the following operations to perform a pre-programming operation: applying a pre-program voltage to word lines connected to the plurality of second vertical channels of the first dummy memory block, applying a pass voltage to ground selection lines connected to the plurality of second vertical channels of the first dummy memory block, and A ground voltage is applied to a common source line connected to the plurality of second vertical channels of the first dummy memory block.

Images