Bonding module, semiconductor structure and manufacturing method thereof, and stacking structure

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a bonding module, a semiconductor structure, a manufacturing method of the semiconductor structure and a stacking structure, and the bonding module comprises supporting layers which are arranged at intervals along a first direction; and the bonding columns are located between the adjacent supporting layers, and the bonding columns are bonded with the wafer along the surface arranged perpendicular to the first direction. The reliability of wafer bonding can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a bonding module, a semiconductor structure, a manufacturing method thereof, and a stacking structure. Background Art

[0002] With the rapid development of the semiconductor industry, wafer bonding equipment and processes are playing an increasingly important role in microelectronics manufacturing. Wafer bonding technology is a technique that tightly bonds two or more wafers together through a specific process to achieve higher performance and smaller electronic components.

[0003] Currently, wafer bonding is usually metal-to-metal bonding and dielectric layer-to-dielectric layer bonding. However, due to the difference in the materials of the metal and dielectric layers, the expansion coefficients of the two are quite different, resulting in abnormalities in the bonding interface of the wafer bonding.

[0004] Therefore, it is necessary to improve the reliability of wafer bonding. Summary of the Invention

[0005] The embodiments of the present disclosure provide a bonding module, a semiconductor structure, a manufacturing method thereof, and a stacking structure, which can at least improve the reliability of wafer bonding.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a bonding module for a wafer bonding process, comprising: support layers arranged at intervals along a first direction; bonding pillars, the bonding pillars being located between adjacent support layers, the bonding pillars being bonded to the wafer along a surface arranged perpendicular to the first direction.

[0007] In some embodiments, the method further includes: a transition layer, wherein the transition layer at least covers the sidewalls of the bonding pillar.

[0008] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a first wafer, the first wafer including: a first substrate and a first dielectric layer located on the surface of the first substrate, a plurality of first pads, the first pads located in the first dielectric layer, and the surface of the first pads is flush with the surface of the first dielectric layer; a second wafer, the second wafer including: a second substrate and a second dielectric layer located on the surface of the second substrate, a plurality of second pads, the second pads located in the second dielectric layer, and the surface of the second pads is flush with the surface of the second dielectric layer, and a second pad is at least opposite to a portion of the surface of the first pad; a plurality of bonding pillars, the bonding pillar is bonded to the first pad and the second pad correspondingly, and the material of the bonding pillar is different from the material of the first pad and the second pad.

[0009] In some embodiments, the method further includes: a transition layer, wherein the transition layer at least covers the sidewalls of the bonding pillar.

[0010] In some embodiments, the transition layer further covers a surface of the bonding pillar facing the first wafer or the second wafer.

[0011] In some embodiments, the method further includes: a second transition layer, wherein the second transition layer is located between the first pad and the bonding column, and the second transition layer is located between the second pad and the bonding column.

[0012] In some embodiments, the bonding pillar is made of copper, and the first pad and / or the second pad is made of aluminum.

[0013] In some embodiments, the method further includes: a filling layer, wherein the filling layer is located between adjacent bonding pillars.

[0014] According to some embodiments of the present disclosure, another aspect of the embodiments of the present disclosure further provides a method for manufacturing a semiconductor structure, including: providing a first wafer, the first wafer including: a first substrate and a first dielectric layer located on the surface of the first substrate, a plurality of first pads, the first pads being located in the first dielectric layer, and the surface of the first pads being flush with the surface of the first dielectric layer; forming a plurality of bonding pillars, and bonding the bonding pillars to the first pads accordingly, the material of the bonding pillars being different from the material of the first pads; providing a second wafer, the second wafer including: a second substrate and a second dielectric layer located on the surface of the second substrate, a plurality of second pads, the second pads being located in the second dielectric layer, and the surface of the second pads being flush with the surface of the second dielectric layer, and bonding the second pads to the side of the bonding pillar away from the first pad accordingly, the material of the second pad being different from the material of the bonding pillar.

[0015] In some embodiments, the method for forming the bonding column includes: forming a support layer, the support layer including a first surface and a second surface relative to each other, the first surface being located on the second surface; etching the support layer to form a plurality of mutually spaced grooves in the support layer; forming an initial transition layer, the initial transition layer covering the surface of the groove and the remaining first surface of the support layer; forming an initial bonding column, the initial bonding column covering the initial transition layer and at least filling the groove; performing a grinding process to at least remove the initial transition layer covering the first surface, and remove at least a portion of the support layer on the second surface to expose the initial transition layer, with the remaining initial bonding column serving as a bonding column.

[0016] In some embodiments, before bonding the bonding pillar to the second pad, the method further includes: forming a second transition layer on a surface of the second pad, wherein the second transition layer is at least located between the bonding pillar and the second pad.

[0017] In some embodiments, removing at least a portion of the support layer on the second surface to expose the initial transition layer further comprises: removing a portion of the initial transition layer to expose the initial bonding pillar; and leaving the remaining initial bonding pillar as a bonding pillar.

[0018] In some embodiments, before bonding the bonding column to the first pad, the method further includes: forming a second transition layer on the surfaces of the first pad and the second pad, wherein the second transition layer is located between the bonding column and the first pad and between the bonding column and the second pad.

[0019] In some embodiments, before forming the support layer, the method further includes: providing a carrier wafer, the support layer being formed on the surface of the carrier wafer, and after bonding the bonding column to the first wafer, the method further includes: debonding the bonding column from the carrier wafer.

[0020] In some embodiments, after bonding the bonding pillars to the second wafer, the method further includes: removing the support layer to form recessed holes between adjacent bonding pillars; and forming a filling layer, wherein the filling layer completely fills the recessed holes.

[0021] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a stacking structure, comprising: a plurality of semiconductor structures as described above, or a plurality of semiconductor structures formed by the manufacturing method of the semiconductor structure as described above, wherein the plurality of semiconductor structures are electrically connected through a plurality of conductive through-holes, and the conductive through-holes are located on the surface of the first wafer and / or the second wafer away from the bonding column.

[0022] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: an additional bonding module is designed, so that when different wafers are bonded, there is no need to form a dielectric layer and pads for bonding on the surface of the wafer, thereby reducing the cost of wafer bonding. At the same time, the bonding module can be manufactured in advance before wafer bonding, and the time required for wafer bonding can also be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 A schematic structural diagram of a bonding module provided in one embodiment of the present disclosure;

[0025] Figure 2 A schematic structural diagram of a semiconductor structure provided in one embodiment of the present disclosure;

[0026] Figure 3 A schematic structural diagram of another semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figure 4 A schematic diagram of a structure for forming a support layer according to an embodiment of the present disclosure;

[0028] Figure 5 An embodiment of the present disclosure provides Figure 4 A schematic diagram of a structure in which a groove is formed on the basis of

[0029] Figure 6 An embodiment of the present disclosure provides Figure 5 A schematic diagram of the structure of the initial bonding column formed on the basis of

[0030] Figure 7 An embodiment of the present disclosure provides Figure 6 A structural schematic diagram of a bonding module is formed on the basis of

[0031] Figure 8 An embodiment of the present disclosure provides Figure 7 A schematic structural diagram of bonding the bonding pillar to the first wafer and the second wafer based on the present invention;

[0032] Figure 9 An embodiment of the present disclosure provides Figure 8 Schematic diagram of the structure of removing the supporting layer on the basis of FIG;

[0033] Figure 10 An embodiment of the present disclosure provides Figure 9 A schematic diagram of a structure in which a filling layer is formed on the basis of

[0034] Figure 11 An embodiment of the present disclosure provides Figure 6Another structural schematic diagram of a bonding module is formed on the basis of

[0035] Figure 12 An embodiment of the present disclosure provides Figure 11 Another structural diagram of bonding the bonding pillar to the first wafer and the second wafer based on the present invention;

[0036] Figure 13 An embodiment of the present disclosure provides Figure 12 Another structural diagram of removing the support layer on the basis of FIG;

[0037] Figure 14 An embodiment of the present disclosure provides Figure 13 Another structural diagram of forming a filling layer on the basis of;

[0038] Figure 15 A schematic diagram of a stacking structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] As can be seen from the background technology, when different wafers are bonded, a dielectric layer and a pad are usually formed on the surface of the wafer, and then the pads of different wafers are bonded to the pads, and the dielectric layers are bonded to the dielectric layers. However, due to the large difference in materials between the pads and the dielectric layers, the pads will expand during high-temperature bonding, resulting in reduced bonding reliability between different wafers. Therefore, in related technologies, additional etching is usually performed on the pads formed on the surface of the wafer to improve the problem of reduced bonding reliability caused by pad expansion. However, such treatment will also lead to the inability to accurately control the etching process. Excessive etching will lead to gaps between the pads, reducing the reliability of bonding and electrical connections. Too little etching will also lead to the problem of reduced wafer bonding reliability due to expansion.

[0040] Based on this, the embodiment of the present disclosure provides a bonding module. When bonding different wafers, there is no need to form a dielectric layer and a pad for bonding on the surface of the wafer, thereby reducing the cost of wafer bonding. At the same time, the bonding module can be manufactured in advance before wafer bonding, and the time required for wafer bonding can be reduced. At the same time, the material of the bonding column can be adjusted according to demand so that the bonding between the bonding column and the wafer adopts low-temperature bonding, avoiding the problem of reduced reliability caused by expansion caused by different materials in the wafer.

[0041] In the description of the embodiments of the present disclosure, technical terms such as "first" and "second" are used solely to distinguish between different objects and should not be understood to indicate or imply relative importance or to implicitly specify the quantity, specific order, or primary and secondary relationship of the technical features indicated. In the description of the embodiments of the present disclosure, "plurality" means more than two, unless otherwise specifically defined.

[0042] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0043] In the description of the embodiments of the present disclosure, the term "and / or" is merely a description of an association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can represent the following three situations: A exists, A and B exist at the same time, and B exists. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0044] In the description of the embodiments of the present disclosure, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0045] In the description of the embodiments of the present disclosure, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as limiting the embodiments of the present disclosure.

[0046] In the description of the embodiments of the present disclosure, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and they can refer to internal connectivity between two components or interaction between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present disclosure based on specific circumstances.

[0047] In the accompanying drawings corresponding to the embodiments of the present disclosure, the thickness and area of ​​the layers are exaggerated for better understanding and ease of description. When describing a component (such as a layer, film, region or substrate) on another component or on the surface of another component, the component can be "directly" located on the surface of the other component, or a third component can be present between the two components. Conversely, when describing a component on the surface of another component or when another component is formed or provided on the surface of a component, it means that there is no third component between the two components. In addition, when describing a component as being "substantially" formed on another component, it means that the component is not formed on the entire surface (or front surface) of the other component, nor is it formed on a partial edge of the entire surface.

[0048] In the description of the embodiments of the present disclosure, when a component is referred to as "including" another component, unless otherwise specified, other components are not excluded, and other components may be further included. In addition, when a component such as a layer, film, region, or plate is referred to as being "on / located on" another component, it can be "directly on" the other component (i.e., located on the surface of the other component with no other components between them), or another component can be present between them. In addition, when a component such as a layer, film, region, or plate is "directly on" another component, or when a component such as a layer, film, region, or plate is located on the surface of another component, it means that no other components are located between them.

[0049] The terms used herein in the description of the various embodiments are intended only to describe the specific embodiments and are not intended to be limiting. As used in the description of the various embodiments and the appended claims, "the component" is intended to include the plural form unless the context clearly indicates otherwise. A component includes a layer, film, region, or plate.

[0050] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0051] refer to Figure 1 , Figure 1 A schematic structural diagram of a bonding module provided in one embodiment of the present disclosure.

[0052] In some embodiments, a bonding module for a wafer bonding process may include: support layers 100 arranged at intervals along a first direction X.

[0053] The bonding module may further include: bonding pillars 101 , the bonding pillars 101 being located between adjacent support layers 100 , and the bonding pillars 101 being bonded to the wafer along a surface arranged perpendicular to the first direction X.

[0054] On the one hand, the support layer 100 is used to limit the position of the bonding column 101. On the other hand, in the process of forming the bonding column 101, it can facilitate the attachment and molding of the bonding column 101 material, thereby defining the morphology of the bonding column 101. The bonding column 101 is used to bond with two wafers respectively, thereby completing the stacking and electrical connection of the two wafers.

[0055] In some embodiments, the material of the support layer 100 may be nickel, nickel-tungsten alloy, or titanium nitride, and the material of the bonding pillars 101 may be a metal material such as copper or silver. The material of the support layer 100 may be different from the material of the bonding pillars 101. After the bonding module is bonded to the two wafers, the support layer 100 will be removed. By utilizing the difference in material between the support layer 100 and the bonding pillars 101, the etching rate can be increased during the removal of the support layer 100 to completely remove it.

[0056] In some embodiments, the bonding module also includes: a transition layer 102, the transition layer 102 at least covers the side wall of the bonding column 101, and the transition layer 102 is used to separate the bonding column 101 from other structures. On the one hand, when the support layer 100 is subsequently removed, the transition layer 102 can be used to protect the bonding column 101, thereby preventing the bonding column 101 from being damaged. On the other hand, a filling layer will be formed after removing the support layer 100. The transition layer 102 can be used to separate the bonding column 101 from the filling layer to prevent the metal elements of the bonding column 101 from diffusing into the filling layer and affecting the reliability of the semiconductor structure.

[0057] In some embodiments, the transition layer 102 also covers a side surface of the bonding column 101 arranged perpendicular to the first direction X. The transition layer 102 can also be used to separate the bonding column 101 from the wafer, thereby avoiding the mutual diffusion reaction of elements caused by direct contact between the bonding column 101 and the wafer, and improving the reliability of the semiconductor structure formed after the wafer is bonded.

[0058] The embodiment of the present disclosure provides a bonding module. When bonding different wafers, it is not necessary to form a dielectric layer and a pad for bonding on the surface of the wafer, thereby reducing the cost of wafer bonding. At the same time, the bonding module can be manufactured in advance before wafer bonding, and the time required for wafer bonding can be reduced. At the same time, the material of the bonding column 101 can be adjusted according to demand so that the bonding between the bonding column 101 and the wafer can be bonded at low temperature, avoiding the problem of reduced reliability caused by mismatch of thermal expansion coefficients due to different materials during high-temperature bonding.

[0059] Another embodiment of the present disclosure further provides a semiconductor structure, which may include the bonding columns in some or all of the above-mentioned embodiments, so as to illustrate a semiconductor structure provided by another embodiment of the present disclosure in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to those in the above-mentioned embodiments can refer to the above-mentioned embodiments and will not be repeated here.

[0060] refer to Figure 2 and Figure 3 , Figure 2 A schematic diagram of a semiconductor structure provided in one embodiment of the present disclosure is shown. Figure 3 A schematic structural diagram of another semiconductor structure provided in an embodiment of the present disclosure.

[0061] In some embodiments, the semiconductor structure may include: a first wafer 203, the first wafer 203 includes: a first substrate 213 and a first dielectric layer 223 located on the surface of the first substrate 213, a plurality of first pads 233, the first pads 233 are located in the first dielectric layer 223, and the surface of the first pads 233 is flush with the surface of the first dielectric layer 223.

[0062] The semiconductor structure may further include: a second wafer 204, the second wafer 204 including: a second substrate 214 and a second dielectric layer 224 located on the surface of the second substrate 214, a plurality of second pads 234, the second pads 234 being located within the second dielectric layer 224, and the surfaces of the second pads 234 being flush with the surface of the second dielectric layer 224, and a second pad 234 being directly opposite to at least a portion of the surface of a first pad 233.

[0063] The semiconductor structure may further include: a plurality of bonding pillars 201 , wherein a bonding pillar 201 is bonded to a first pad 233 and a second pad 234 , respectively. The material of the bonding pillar 201 is different from the material of the first pad 233 and the second pad 234 .

[0064] It is understandable that in the related art, an additional dielectric layer is usually formed on the surface of the first wafer 203 and a copper pad electrically connected to the first pad 233 is formed in the dielectric layer. A dielectric layer and a copper pad electrically connected to the second pad 234 are formed on the surface of the second wafer 204. Then, a hybrid bonding method is used to bond the copper pads to the copper pads and the dielectric layers to the dielectric layers. However, this method not only leads to an additional increase in process steps, but also brings problems with bonding reliability.

[0065] The semiconductor structure provided by the embodiment of the present disclosure reduces the additional process steps of forming a dielectric layer and a copper pad on the surface of the first wafer 203 and the second wafer 204 by providing multiple bonding pillars 201 and utilizing the bonding pillars 201 to bond to the first pad 233 and the second pad 234 respectively, thereby simplifying the process. The temperature of the bonding process can also be adjusted by adjusting the materials of the first pad 233, the second pad 234 and the bonding pillars 201, changing from the original high-temperature bonding to low-temperature bonding, thereby avoiding thermal expansion problems caused by material differences.

[0066] In some embodiments, corresponding structures may be formed in the first substrate 213, such as transistors, word lines, or bit lines, etc. A first interconnect layer 243 may also be formed in the first dielectric layer 223. The first interconnect layer 243 may include one or more metal layers. The first interconnect layers 243 are electrically connected to each other through first conductive vias 253, and the first interconnect layers 243 may be electrically connected to the first pads 233 through the first conductive vias 253. The first wafer 203 also includes conductive vias 208, which provide a process basis for subsequently forming a stacked structure electrically connected to each other.

[0067] In some embodiments, the material of the bonding column 201 is copper, and the material of the first pad 233 is aluminum. When the material of the bonding column 201 is copper and the material of the first pad 233 is aluminum, the bonding between the bonding column 201 and the first pad 233 can use low-temperature bonding. Even if low-temperature bonding is used, the copper material and the aluminum material still have good bonding strength, thereby ensuring the reliability of the bonding between the bonding column 201 and the first pad 233. At the same time, due to the use of low-temperature bonding, the thermal expansion of the material between the first pad 233 and the first dielectric layer 223 is small, and there will be no warping problem caused by the large degree of thermal expansion of the material, that is, there will be no problem of reducing the bonding reliability. In addition, low-temperature bonding can reduce the impact on the internal devices of the semiconductor structure, thereby reducing the process difficulty of forming the semiconductor structure while improving the stability of the formed semiconductor structure.

[0068] Corresponding structures may also be formed in the second substrate 214, such as transistors, word lines, or bit lines. A second interconnect layer 244 may also be formed in the second dielectric layer 224. The second interconnect layer 244 may include one or more metal layers. The second interconnect layers 244 are electrically connected to each other through second conductive vias 254, and the second interconnect layers 244 may be electrically connected to the second pads 234 through the second conductive vias 254. The second wafer 204 also includes conductive vias 208, which provide a process foundation for subsequently forming a stacked structure electrically connected to each other.

[0069] In some embodiments, the material of the bonding column 201 is copper and the material of the second pad 234 is aluminum. When the material of the bonding column 201 is copper and the material of the second pad 234 is aluminum, the bonding between the bonding column 201 and the second pad 234 can use low-temperature bonding. Even if low-temperature bonding is used, the copper material and the aluminum material still have good bonding strength, thereby ensuring the reliability of the bonding between the circuit bonding column 201 and the second pad 234. At the same time, due to the use of low-temperature bonding, the thermal expansion of the material between the second pad 234 and the second dielectric layer 224 is small, and there will be no warping problem caused by the large degree of thermal expansion of the material, that is, there will be no problem of reducing the bonding reliability, thereby reducing the process difficulty of forming the semiconductor structure while improving the stability of the formed semiconductor structure.

[0070] It can be understood that when the material of the bonding column 201 is copper and the material of the first pad 233 and the second pad 234 is aluminum, additionally setting a bonding column 201 between the first pad 233 and the second pad 234 can also improve the transmission performance. In other words, the transmission performance of bonding the first pad 233 and the second pad 234 together through the bonding column 201 is better than the transmission performance of directly bonding the first pad 233 and the second pad 234.

[0071] In some embodiments, the semiconductor structure may further include: a transition layer 202, the transition layer 202 at least covering the side wall of the bonding column 201, and the transition layer 202 can separate the bonding column 201 from the remaining structures, thereby preventing the metal ions in the bonding column 201 from diffusing into other film layers of other semiconductor structures, thereby improving the stability of the semiconductor structure, and the transition layer 202 can also prevent the bonding column 201 from being oxidized, thereby avoiding the problem of decreased transmission performance and bonding strength of the bonding column 201.

[0072] refer to Figure 2 In some embodiments, the transition layer 202 further covers the surface of the bond pillar 201 facing the first wafer 203 or the second wafer 204. Taking the case where the transition layer 202 covers the surface of the bond pillar 201 facing the first wafer 203 as an example, the transition layer 202 can suppress the mutual diffusion of ions between the bond pillar 201 and the first pad 233, thereby preventing mutual contamination between the bond pillar 201 and the first pad 233. Furthermore, the transition layer 202 can further prevent oxidation of the bond pillar 201 and the first pad 233. Furthermore, the transition layer 202 can also serve as an adhesive layer between the bond pillar 201 and the first pad 233, thereby improving the bonding reliability between the bond pillar 201 and the first pad 233.

[0073] In some embodiments, the material of the transition layer 202 is tantalum or tantalum nitride, etc. Tantalum or tantalum nitride has high interface energy matching with metals such as copper or aluminum, thereby improving the bonding reliability between the bonding column 201 and the first pad 233.

[0074] In some embodiments, the transition layer 202 covers the surface of the bond pin 201 facing one of the first wafer 203 or the second wafer 204. The semiconductor structure further includes a second transition layer 205, which covers the surface of the bond pin 201 facing the other of the first wafer 203 or the second wafer 204. The second transition layer 205 can be used to separate the bond pin 201 from the other of the first wafer 203 or the second wafer 204, thereby preventing atomic interdiffusion between the bond pin 201 and the other of the first wafer 203 or the second wafer 204, thereby improving the stability of the semiconductor structure and serving as an adhesive layer to enhance bonding reliability.

[0075] In some embodiments, the length of the second transition layer 205 is greater than the width of the bonding column 201. By controlling the length of the formed second transition layer 205 to be longer, the difficulty of aligning the bonding column 201 and the second transition layer 205 can be reduced, thereby improving the stability of the semiconductor structure. It should be noted that the length and width here refer to: the length of the second transition layer 205 and the width of the bonding column 201 along the arrangement direction of the bonding column 201 in the figure.

[0076] refer to Figure 3 In some embodiments, the transition layer 202 covers the sidewalls of the bonding pillar 201. The semiconductor structure may further include a second transition layer 205, which is located between the first pad 233 and the bonding pillar 201, and between the second pad 234 and the bonding pillar 201. The second transition layer 205 prevents atomic interdiffusion between the bonding pillar 201 and the first pad 233 and the second pad 234, thereby improving the stability of the semiconductor structure. It also serves as an adhesive layer to enhance bonding reliability.

[0077] In some embodiments, the semiconductor structure may further include: a filling layer 206, the filling layer 206 being located between adjacent bonding pillars 201, and the filling layer 206 being used to fill the gap between the first wafer 203 and the second wafer 204, thereby improving the overall reliability of the semiconductor structure and avoiding the problem of decreased stability of the semiconductor structure due to factors such as gravity or air.

[0078] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the semiconductor structures in some or all of the above-mentioned embodiments. The method for manufacturing a semiconductor structure provided in another embodiment of the present disclosure will be described in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to those in the above-mentioned embodiments can refer to the above-mentioned embodiments and will not be repeated here.

[0079] refer to Figures 4 to 10 and Figures 4 to 7 and Figures 11 to 14 ,in, Figures 4 to 10 This is a schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure. Figures 4 to 7 and Figures 11 to 14 A schematic structural diagram corresponding to each step of a method for manufacturing another semiconductor structure provided by an embodiment of the present disclosure.

[0080] In some embodiments, a method for manufacturing a semiconductor structure may include: providing a first wafer 303, the first wafer 303 including: a first substrate 313 and a first dielectric layer 323 located on the surface of the first substrate 313, a plurality of first pads 333, the first pads 333 being located in the first dielectric layer 323, and the surface of the first pads 333 being flush with the surface of the first dielectric layer 323.

[0081] The method for manufacturing the semiconductor structure may further include: forming a plurality of bonding pillars 301 , and correspondingly bonding the bonding pillars 301 to the first pads 333 , wherein the material of the bonding pillars 301 is different from that of the first pads 333 .

[0082] The method for manufacturing the semiconductor structure may also include: providing a second wafer 304, the second wafer 304 including: a second substrate 314 and a second dielectric layer 324 located on the surface of the second substrate 314, a plurality of second pads 334, the second pads 334 being located in the second dielectric layer 324, and the surface of the second pads 334 being flush with the surface of the second dielectric layer 324, and the second pads 334 being bonded to a side of the bonding column 301 away from the first pad 333, and the material of the second pads 334 being different from the material of the bonding column 301.

[0083] The embodiment of the present disclosure utilizes a method of bonding the bonding column 301 to the first pad 333 and the second pad 334 respectively, thereby reducing the additional process steps of forming a dielectric layer and a copper pad on the surface of the first wafer 303 and the second wafer 304. The temperature of the bonding process can also be adjusted by adjusting the materials of the first pad 333, the second pad 334 and the bonding column 301, thereby avoiding thermal expansion problems caused by material differences.

[0084] refer to Figures 4 to 10 ,in Figure 4Schematic diagram of the structure of the support layer. Figure 5 For Figure 4 The grooves are formed on the basis of Figure 6 For Figure 5 The initial bonding column is formed on the basis of Figure 7 For Figure 6 The bonding module is formed on the basis of Figure 8 For Figure 7 The bonding module is bonded to the first wafer and the second wafer based on Figure 9 For Figure 8 Remove the support layer on the basis of Figure 10 For Figure 9 A filling layer is formed on the basis of

[0085] In some embodiments, the method for forming a bonding column 301 includes: forming a support layer 300, the support layer 300 including a first surface 310 and a second surface 320 relative to each other, the first surface 310 being located on the second surface 320; etching the support layer 300 to form a plurality of mutually spaced grooves 330 in the support layer 300; forming an initial transition layer 312, the initial transition layer 312 covering the surface of the groove 330 and the remaining first surface 310 of the support layer 300; forming an initial bonding column 311, the initial bonding column 311 covering the initial transition layer 312 and at least filling the groove 330; performing a grinding process to at least remove the initial transition layer 312 covering the first surface 310, and remove at least a portion of the support layer 300 on the second surface 320 to expose the initial transition layer 312, the remaining initial bonding column 311 serving as the bonding column 301, and the remaining initial transition layer 312 serving as the transition layer 302; the bonding column 301, the support layer 300 and the transition layer 302 together constitute a key and module.

[0086] The method of forming the support layer 300 and the groove 330 can provide a process basis for forming the transition layer 302 and the bonding column 301. The method of forming the groove 330 can define the position of the bonding column 301, which can facilitate the deposition of the transition layer 302 and the bonding column 301 materials, thereby improving the reliability of the formed transition layer 302 and the bonding column 301. At the same time, in the process of forming the transition layer 302 and the bonding column 301, the groove 330 can be filled by first depositing and then chemical mechanical polishing, thereby avoiding the existence of holes in the formed bonding column 301, thereby improving the reliability of the bonding column 301.

[0087] In some embodiments, the position of the groove 330 corresponds to the position of the first pad 333 of the first wafer 303, so that in the subsequent bonding process, the bonding column 301 can be aligned with the first pad 333. Similarly, the position of the groove 330 also corresponds to the position of the second pad 334 of the second wafer 304, so that the bonding column 301 can be aligned with the second pad 334 in the subsequent bonding process.

[0088] In some embodiments, the support layer 300 can be etched by mask etching to form a groove 330, the initial transition layer 312 can be directly deposited by deposition, and the initial bonding column 311 can be formed by deposition or electroplating, and part of the initial bonding column 311 and the initial transition layer 312 can be removed by chemical mechanical polishing.

[0089] Figure 7 After the bonding pillar 301 is formed, the bonding pillar 301, the transition layer 302 and the support layer 300 constitute a bonding module 309. Figure 8 The bonding module 309 is bonded to the first wafer 303 and the second wafer 304. Figure 9 The support layer of the bonding module 309 is removed.

[0090] In some embodiments, before bonding the bonding pillar 301 to the second pad 334, the process further includes: forming a second transition layer 305 on the surface of the second pad 334, wherein the second transition layer 305 is at least located between the bonding pillar 301 and the second pad 334. The formation of the second transition layer 305 can separate the bonding pillar 301 from the second pad 334, thereby preventing atomic interdiffusion between the bonding pillar 301 and the second pad 334, thereby improving the stability of the formed semiconductor structure and increasing the stability of the stacked structure.

[0091] refer to Figures 11 to 14 , Figure 11 For Figure 6 The bonding module is formed on the basis of Figure 12 For Figure 11 Bond the bonding module to the first wafer and the second wafer based on Figure 13 For Figure 12 Remove the support layer on the basis of Figure 14 For Figure 13 A filling layer is formed on the basis of

[0092] In some embodiments, removing at least a portion of the support layer 300 from the second surface 320 to expose the initial transition layer 312 further includes: removing a portion of the initial transition layer 312 to expose the initial bonding pillar 311; and the remaining initial bonding pillar 311 serves as the bonding pillar 301. In other words, during the process of forming the transition layer 302, the transition layer 302 is formed to cover only the sidewalls of the bonding pillar 301. It is understandable that before removing the initial transition layer 312, a portion of the support layer 300 is also etched. When etching the support layer 300, a portion of the initial transition layer 312 may be etched, resulting in a decrease in the reliability of the initial transition layer. Therefore, removing this portion of the initial transition layer 312 and forming a second transition layer can also improve the reliability of the formed semiconductor structure.

[0093] Figure 11 After the bonding pillar 301 is formed, the bonding pillar 301, the transition layer 302 and the support layer 300 constitute a bonding module 309. Figure 12 The bonding module 309 is bonded to the first wafer 303 and the second wafer 304. Figure 13 The support layer 300 of the bonding module 309 is removed to form the recessed hole 307 .

[0094] refer to Figure 12 In some embodiments, before bonding the bonding pillar 301 to the first pad 333, the process further includes forming a second transition layer 305 on the surfaces of the first pad 333 and the second pad 334. The second transition layer 305 is located between the bonding pillar 301 and the first pad 333, and between the bonding pillar 301 and the second pad 334. The second transition layer 305 prevents atomic interdiffusion between the bonding pillar 301 and the first pad 333 and the second pad 334, thereby improving the stability of the semiconductor structure and the stacked structure. The second transition layer 305 also serves as an adhesive layer to enhance bonding reliability.

[0095] In some embodiments, before forming the support layer 300, the process further includes: providing a carrier wafer, forming the support layer 300 on the surface of the carrier wafer, and after bonding the bond pillars 301 to the first wafer 303, further including: debonding the bond pillars 301 from the carrier wafer. On the one hand, using the carrier wafer as a support and forming the support layer 300 can improve the reliability of the formed support layer 300. On the other hand, using the carrier wafer can also facilitate alignment and bonding of the support layer 300 to the first wafer 303. Subsequently, by debonding the bond pillars 301 from the carrier wafer, the other sidewall of the bond pillars 301 is exposed, so that the second wafer 304 can be bonded to the surface of the bond pillars 301.

[0096] In some embodiments, when bonding the bonding column 301 to the first wafer 303, since the support layer 300 is not removed, the bonding module 309 is bonded to the first wafer 303 as a whole. After the bonding column 301 and the first pad 333 are aligned and bonded, the carrier wafer and the bonding module 309 are debonded to complete the bonding of the first wafer and the bonding column 301. Then, the second wafer is bonded to the bonding module 309, and the second pad is aligned with the bonding column 301, thereby completing the entire bonding process.

[0097] refer to Figure 13 and Figure 14 In some embodiments, after bonding the bond pillars 301 to the second wafer 304, the following steps are further performed: removing the support layer 300 to form recessed holes 307 between adjacent bond pillars 301; and forming a filling layer 306 to completely fill the recessed holes 307. It is understood that the support layer 300 is used to form the transition layer 302 and the bond pillars 301. After bonding the bonding module 309 to the second wafer 304, the support layer 300 is removed and the filling layer 306 is formed.

[0098] In some embodiments, the bonding module 309 may be directly formed and directly bonded to the first wafer 303 and the second wafer 304 without the need for a carrier wafer. Alignment marks may be formed on the bonding module 309 in advance, and the alignment marks are used to align the bonding module 309 with the first pad 333 and the second pad 334. Figure 12 As shown, after aligning and bonding the bonding module 309 with the first wafer 303 and the second wafer 304, the following steps are also included: Figure 13 As shown, the support layer 300 is removed to form the recessed hole 307, and then Figure 14 As shown, recessed hole 307 is filled with filling layer 306. By directly bonding bonding module 309 to first wafer 303 and second wafer 304, the bonding process can be simplified, reducing manufacturing costs. Furthermore, since bonding module 309 is provided separately, it can be produced separately during the semiconductor manufacturing process, allowing for better control and improvement of the performance and yield of bonding module 309, further improving the yield of bonding module 309 after bonding to first wafer 303 and second wafer 304.

[0099] In some embodiments, a separate bonding pillar 301 may be formed first, and then the bonding pillar 301 may be directly bonded to the first wafer 303 and the second wafer 304 .

[0100] It should be noted that the first interconnect layer 343, the first conductive via 353, the conductive via 308, the second interconnect layer 344 and the second conductive via 354 in the figure correspond one-to-one to the first interconnect layer 243, the first conductive via 253, the conductive via 208, the second interconnect layer 244 and the second conductive via 254 in the above embodiment. The same or corresponding parts can refer to the above content and will not be repeated here.

[0101] Another embodiment of the present disclosure further provides a stacking structure, which may include the semiconductor structure in some or all of the above-mentioned embodiments, or a semiconductor structure formed by the manufacturing method of the semiconductor structure in some or all of the above-mentioned embodiments. A stacking structure provided in another embodiment of the present disclosure will be described in conjunction with the accompanying drawings. It should be noted that the parts that are the same or corresponding to those in the above-mentioned embodiments can refer to the above-mentioned embodiments and will not be repeated here.

[0102] refer to Figure 15 , Figure 15 A schematic diagram of a stacking structure provided in one embodiment of the present disclosure.

[0103] The stacked structure may include: multiple semiconductor structures 400 as in some or all of the above embodiments, or multiple semiconductor structures 400 formed by the manufacturing method of the semiconductor structure as in some or all of the above embodiments, the multiple semiconductor structures 400 are electrically connected through multiple conductive vias 401, and the conductive vias 401 are located on the surface of the first wafer and / or the second wafer away from the bonding column.

[0104] In some embodiments, the semiconductor structure includes a conductive via 401. When connecting the semiconductor structure 400, the first substrate or the second substrate of the semiconductor structure 400 can be ground to expose the surface of the conductive via 401, thereby electrically connecting the conductive vias 401 to each other.

[0105] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and in actual applications, various changes may be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A bonding module for wafer bonding process, characterized in that: include: Support layers arranged at intervals along a first direction; The bonding pillars are located between adjacent support layers, and the bonding pillars are bonded to the wafer along surfaces arranged perpendicular to the first direction.

2. The bonding module according to claim 1, characterized in that Also includes: A transition layer at least covers the sidewalls of the bonding pillars.

3. A semiconductor structure, characterized in that include: A first wafer, comprising: a first substrate and a first dielectric layer located on a surface of the first substrate, and a plurality of first pads, wherein the first pads are located in the first dielectric layer, and a surface of the first pads is flush with a surface of the first dielectric layer; a second wafer, the second wafer comprising: a second substrate and a second dielectric layer located on a surface of the second substrate; a plurality of second pads, the second pads being located in the second dielectric layer, the surfaces of the second pads being flush with the surface of the second dielectric layer, and the second pads being directly opposite to at least a portion of the surface of the first pad; A plurality of bonding pillars are provided, wherein a bonding pillar is bonded to a first pad and a second pad correspondingly, and a material of the bonding pillar is different from a material of the first pad and the second pad.

4. The semiconductor structure according to claim 3, wherein: Also includes: A transition layer at least covers the sidewalls of the bonding pillars.

5. The semiconductor structure according to claim 4, wherein: The transition layer also covers the surface of the bonding pillar facing the first wafer or the second wafer. The semiconductor structure according to claim 4 , wherein: Also includes: A second transition layer is located between the first pad and the bonding column, and the second transition layer is located between the second pad and the bonding column.

7. The semiconductor structure according to claim 3, wherein: The bonding pillar is made of copper, and the first pad and / or the second pad is made of aluminum.

8. The semiconductor structure according to claim 3, wherein: Also includes: A filling layer is located between adjacent bonding pillars.

9. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first wafer, the first wafer comprising: a first substrate and a first dielectric layer located on a surface of the first substrate, and a plurality of first pads, wherein the first pads are located in the first dielectric layer, and the surfaces of the first pads are flush with the surface of the first dielectric layer; forming a plurality of bonding pillars, and bonding the bonding pillars to the first pads correspondingly, wherein the material of the bonding pillars is different from that of the first pads; A second wafer is provided, comprising: a second substrate and a second dielectric layer located on a surface of the second substrate; and a plurality of second pads, wherein the second pads are located within the second dielectric layer, and the surfaces of the second pads are flush with the surface of the second dielectric layer. The second pads are bonded to a side of the bonding column away from the first pad, and the material of the second pads is different from that of the bonding column.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein: The method of forming the bonding pillar includes: forming a support layer, the support layer comprising a first surface and a second surface opposite to each other, the first surface being located on the second surface; Etching the support layer to form a plurality of mutually spaced grooves in the support layer; forming an initial transition layer, wherein the initial transition layer covers the surface of the groove and the remaining first surface of the supporting layer; forming an initial bonding column, wherein the initial bonding column covers the initial transition layer and at least fills the groove; A grinding process is performed to remove at least the initial transition layer covering the first surface, and to remove at least a portion of the support layer on the second surface to expose the initial transition layer, with the initial bonding pillar remaining as a bonding pillar.

11. The method for manufacturing a semiconductor structure according to claim 10, wherein: Before bonding the bonding pillar to the second pad, the method further includes: forming a second transition layer on the surface of the second pad, wherein the second transition layer is at least located between the bonding pillar and the second pad.

12. The method for manufacturing a semiconductor structure according to claim 10, wherein: The removing of at least a portion of the support layer on the second surface to expose the initial transition layer further comprises: A portion of the initial transition layer is removed to expose the initial bonding pillar; and the remaining initial bonding pillar serves as a bonding pillar.

13. The method for manufacturing a semiconductor structure according to claim 12, wherein: Before bonding the bonding column to the first pad, the method further includes: forming a second transition layer on the surfaces of the first pad and the second pad, wherein the second transition layer is located between the bonding column and the first pad and between the bonding column and the second pad.

14. The method for manufacturing a semiconductor structure according to claim 10 or 12, wherein: Before forming the support layer, the method further includes: providing a carrier wafer, the support layer is formed on the surface of the carrier wafer, and after bonding the bonding pillar to the first wafer, the method further includes: debonding the bonding pillar from the carrier wafer.

15. The method for manufacturing a semiconductor structure according to claim 10 or 12, wherein: After bonding the bonding pillar to the second wafer, the method further includes: removing the support layer to form recessed holes between adjacent bonding pillars; A filling layer is formed, and the filling layer completely fills the concave hole.

16. A stacking structure, characterized in that: include: A plurality of semiconductor structures according to any one of claims 3 to 8, or a plurality of semiconductor structures formed by the method for manufacturing a semiconductor structure according to any one of claims 9 to 15, wherein the plurality of semiconductor structures are electrically connected through a plurality of conductive vias, and the conductive vias are located on a surface of the first wafer and / or the second wafer away from the bonding pillars.

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