A power amplifier for improving amplitude and phase distortion

Abstract

The application discloses a power amplifier for improving amplitude-phase distortion, and relates to the technical field of power amplifiers, and solves the technical problem that the prior art has limited improvement on amplitude-phase distortion of the power amplifier, and has more gain reduction, which affects the performance of the power amplifier. The power amplifier comprises a first-stage input matching circuit, a first-stage drive amplifier circuit, a first-stage interstage matching circuit, a second-stage power amplifier circuit, a second-stage output matching circuit and a linearization structure. The second-stage power amplifier circuit adopts a full-differential structure to suppress the output of a common-mode signal, and performs power output based on a class-A working state of a CASCODE structure. The linearization structure introduces a signal of third harmonic of the power amplifier into an alternating current ground through a capacitor, hinders the inflow of a fundamental wave, and adjusts the opening degree through a MOS tube. The CASCODE structure is connected with the linearization structure, amplitude-phase distortion is improved, the linearity of the circuit is improved, and the gain reduction is less.

Description

Technical Field

[0001] This invention relates to the field of power amplifier technology, and more particularly to a power amplifier that improves amplitude and phase distortion. Background Technology

[0002] Millimeter-wave technology will be applied to fifth-generation communications and future satellite communications, radar, sensors, aerospace, and defense. Among the many modules in a millimeter-wave front-end system, the power amplifier is a core module. Its linearity directly determines the quality of the transmitter's transmitted signal, its efficiency determines the transceiver's power consumption, and its output power determines the communication distance. The power amplifier is crucial to the quality of wireless communication.

[0003] In power amplifiers, the fully differential CASCODE structure (cascode structure) is a commonly used configuration. Combining the CASCODE structure with fully differential technology, it simultaneously achieves high gain, high bandwidth, high power supply rejection ratio, and good common-mode noise suppression capability. It can effectively suppress common-mode signals at the output, thereby eliminating even-order harmonics at the output and improving output power. However, the CASCODE structure has a high output impedance, and the conjugation degree between the optimal load impedance and the output impedance of the CASCODE structure is poor. This results in the maximum gain of the CASCODE structure in power amplifier design being much lower than its maximum usable gain, and the S22 matching degree (used to measure how small the reflection at the output port Port-2 is; the smaller the value, the better the matching) is very poor.

[0004] Currently, Class AB power amplifiers (a combination of Class A and Class B amplifiers, depending on the bias current and output level) are widely used in phased array chips. This type of power amplifier is typically affected by amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions, which degrade the error vector magnitude (EVM) and adjacent channel power ratio (ACPR). Because the parasitic capacitance Cgs between the gate and source of a MOSFET is affected by the gate-source overdrive voltage, for power amplifiers, as the input power gradually increases, the voltage swing at the MOSFET gate also gradually increases, affecting the position of its gate equivalent bias point. When a high-power signal is input, the change in parasitic capacitance Cgs causes nonlinear distortion in the signal output from the MOSFET drain, generating new frequency components and causing a phase change in the output signal, resulting in amplitude-to-phase signal distortion.

[0005] Existing solutions include connecting a PMOS transistor to the gate of the common-source amplifier as a variable capacitor. However, the parasitic capacitance of the PMOS transistor has limited variation, insufficient to compensate for changes in the drain-source capacitance of the MOS transistor, resulting in minimal improvement in amplitude and phase distortion. Furthermore, this approach introduces additional gain loss. Another method employs multiple-gate transistors (MGTRs) to correct amplitude and phase distortion over a wide bandwidth. In a Cascode structure, a new MOS transistor's drain is connected between the two MOS transistors on one side. The source of this new MOS transistor is connected to AC ground or a virtual ground (i.e., the source of the symmetrical MOS transistor on the other side). The source DC voltage is 0V or the same as the drain voltage. The gate of the new MOS transistor is supplied with a control voltage and is in the ON state. By using a multi-gate transistor, the input equivalent capacitance and its fluctuation in the power amplifier stage are reduced, resulting in lower amplitude and phase distortion. However, this structure leads to a gain decrease of approximately 4dB, severely impacting circuit performance, and the improvement in phase distortion is only about 2-3°. There is an urgent need for a differential CASCODE structure power amplifier that improves amplitude and phase distortion and enhances the output impedance of the CASCODE structure.

[0006] In the process of realizing this invention, the inventors discovered at least the following problems in the prior art:

[0007] Existing technical solutions offer limited improvement in amplitude and phase distortion of power amplifiers, while also resulting in a significant drop in gain, which negatively impacts the performance of the power amplifier. Summary of the Invention

[0008] The purpose of this invention is to provide a power amplifier that improves amplitude and phase distortion, thereby addressing the technical problems in existing technologies where the improvement in amplitude and phase distortion is limited, while the gain decreases significantly, affecting the performance of the power amplifier. The various technical effects of the preferred solutions among the many technical solutions provided by this invention are detailed below.

[0009] To achieve the above objectives, the present invention provides the following technical solution:

[0010] This invention provides a power amplifier with improved amplitude and phase distortion, comprising a first-stage input matching circuit, a first-stage driver amplifier circuit, a first-stage inter-stage matching circuit, a second-stage power amplifier circuit, a second-stage output matching circuit, and a linearization structure. The first-stage input matching circuit converts a single-ended input signal into a differential signal and performs impedance matching. The first-stage driver amplifier circuit is connected to the first-stage input matching circuit and employs a differential common-source amplifier structure to amplify the signal input to the first-stage input matching circuit to meet the input power requirements of the second-stage power amplifier. The first-stage inter-stage matching circuit is connected to the first-stage driver amplifier circuit. Used for interstage matching; the second-stage power amplifier circuit is connected to the first-stage interstage matching circuit, adopts a fully differential structure to suppress the common-mode signal output, and performs power output based on the Class A operating state of the CASCODE structure; the second-stage output matching circuit is connected to the second-stage power amplifier circuit, used to convert the differential signal of the second-stage output matching circuit into a single-ended signal, and perform impedance transformation for power matching; the linearization structure is connected to the second-stage power amplifier circuit, used to introduce the third harmonic signal of the power amplifier into AC ground through a capacitor, and to block the inflow of the fundamental frequency, and the linearization structure adjusts the turn-on degree through a MOS transistor.

[0011] Preferably, the linearization structure includes a first linearization structure and a second linearization structure. The first linearization structure and the second linearization structure have the same circuit structure and are respectively connected to the drain of MOS transistor M3 and the drain of MOS transistor M4 in the second-stage power amplifier circuit.

[0012] Preferably, the first linearization structure includes a MOSFET M7, a capacitor C5, a resistor R3, and a resistor R4. The source of the MOSFET M7 is connected to the drain of the MOSFET M3, the drain is connected to the first plate of the capacitor C5 and the first end of the resistor R4, the gate is connected to the first end of the resistor R3, the second plate of the capacitor C5 is grounded, the second end of the resistor R3 is connected to a voltage Vctrl, and the second end of the resistor R4 is connected to a power supply VL. The second linearization structure includes a MOSFET M8, a capacitor C6, a resistor R5, and a resistor R6. The source of the MOSFET M8 is connected to the drain of the MOSFET M4, the drain is connected to the first plate of the capacitor C6 and the first end of the resistor R6, the gate is connected to the first end of the resistor R5, the second plate of the capacitor C6 is grounded, the second end of the resistor R5 is connected to a voltage Vctrl, and the second end of the resistor R6 is connected to a power supply VL.

[0013] Preferably, when the voltage Vctrl = 0V, the linearization structure is turned off, which is the normal mode; when the voltage Vctrl > 1.4V, the MOS transistor of the linearization structure is turned on, and the linearization structure is turned on.

[0014] Preferably, the first linearization structure includes a resistor R7 and a capacitor C8, and the second linearization structure includes a resistor R8 and a capacitor C9; the first end of the resistor R7 is connected to the drain of the MOSFET M3, and the second end is connected to the first plate of the capacitor C8, and the second plate of the capacitor C8 is grounded; the first end of the resistor R8 is connected to the drain of the MOSFET M4, and the second end is connected to the first plate of the capacitor C9, and the second plate of the capacitor C9 is grounded.

[0015] Preferably, the first-stage driver amplifier circuit includes a neutralizing capacitor C1, a neutralizing capacitor C2, a MOSFET M1, and a MOSFET M2; the gate of the MOSFET M1 is connected to the first-stage input matching circuit and the first plate of the neutralizing capacitor C2, the source is grounded, and the drain is connected to the second plate of the neutralizing capacitor C1 and the first-stage interstage matching circuit; the gate of the MOSFET M2 is connected to the first-stage input matching circuit and the first plate of the neutralizing capacitor C1, the source is grounded, and the drain is connected to the second plate of the neutralizing capacitor C2 and the first-stage interstage matching circuit.

[0016] Preferably, the second-stage power amplifier circuit includes MOSFETs M3, M4, M5, and M6, neutralizing capacitors C3 and C4; the gates of MOSFETs M3 and M4 are both connected to the input signal of the first-stage interstage matching circuit, and their sources are both grounded; the drain of MOSFET M3 is connected to the source of MOSFET M5 and the first plate of neutralizing capacitor C3, the second plate of neutralizing capacitor C3 is connected to the gate of MOSFET M4, the drain of MOSFET M4 is connected to the source of MOSFET M6 and neutralizing capacitor C4, and the second plate of neutralizing capacitor C4 is connected to the gate of MOSFET M3; the gates of MOSFETs M5 and M6 are both connected to a bias voltage, and the output signals of their drains are both connected to the second-stage output matching circuit.

[0017] Preferably, the first-stage input matching circuit matches the impedance from 50 ohms to the conjugate value of the input impedance of the first-stage driver amplifier.

[0018] Preferably, the first-stage interstage matching circuit matches the conjugate value of the output impedance of the first-stage driver amplifier to the conjugate value of the input impedance of the second-stage power amplifier.

[0019] Preferably, both the first-stage input matching circuit and the second-stage output matching circuit use balun-based transformers. The first-stage input matching circuit connects the differential output port of the balun to the differential signal input terminal of the first-stage driver amplifier. The differential input port of the balun in the second-stage output matching circuit is connected to the differential signal output terminal of the second-stage power amplifier, and a capacitor C7 is connected in parallel between the single-ended output interface of the balun and the single-ended ground of the balun.

[0020] Implementing one of the above-described technical solutions of the present invention has the following advantages or beneficial effects:

[0021] In this invention, a linearization structure is connected to the CASCODE structure in the second-stage power amplifier circuit. Compared with existing power amplifiers, this significantly improves the amplitude and phase distortion when outputting large signals, thereby increasing the linearity of the circuit. At the same time, while achieving the same amplitude and phase improvement effect, the gain can decrease less than other structures such as multi-gate transistor technology, because this structure reduces the loss of the fundamental frequency, thus the gain will not decrease much. In addition, the linearization structure can significantly improve the conjugation degree between the output impedance of the CASCODE structure and the optimal load impedance, thereby improving the matching degree of circuit S22. Attached Figure Description

[0022] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings:

[0023] Figure 1 This is a circuit principle of a power amplifier for improving amplitude and phase distortion according to an embodiment of the present invention. Figure 1 ;

[0024] Figure 2 This is a circuit principle of a power amplifier for improving amplitude and phase distortion according to an embodiment of the present invention. Figure 1 Chinese V ctrl Equivalent model of linearized structure when =0V;

[0025] Figure 3 This is a circuit principle of a power amplifier for improving amplitude and phase distortion according to an embodiment of the present invention. Figure 1 Chinese V ctrl Equivalent model of linearized structure at >1.4V;

[0026] Figure 4 This is a circuit principle of a power amplifier for improving amplitude and phase distortion according to an embodiment of the present invention. Figure 2 ;

[0027] Figure 5 This is a schematic diagram of the S-parameters of the second-stage power amplifier circuit of a power amplifier for improving amplitude and phase distortion according to an embodiment of the present invention;

[0028] Figure 6 This is a graph showing the gain of a second-stage power amplifier circuit for a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention, as a function of output power at a frequency of 31 GHz.

[0029] Figure 7 This is a graph showing the relative amplitude and phase distortion as a function of output power at a frequency of 31 GHz, representing the second-stage power amplifier circuit of a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention.

[0030] Figure 8 This is a simulation gain curve as a function of frequency for a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention.

[0031] Figure 9 This is a simulation curve of S22 versus frequency for a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention.

[0032] Figure 10 This is a simulated output impedance versus frequency curve of a power amplifier with improved amplitude and phase distortion at 34 GHz, according to an embodiment of the present invention.

[0033] Figure 11 This is a simulation gain curve of a power amplifier with improved amplitude and phase distortion at 34GHz, according to an embodiment of the present invention, as a function of output power.

[0034] Figure 12 This is a simulated curve of relative amplitude and phase distortion versus output power at 34GHz for a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention.

[0035] Figure 13 This is a signal simulation curve of a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention when the linearized structure is turned off;

[0036] Figure 14 This is a signal simulation curve of a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention when the linearization structure is turned on;

[0037] Figure 15 This is a simulation curve of the relative amplitude and phase distortion as a function of frequency at the 1dB compression point of a power amplifier with improved amplitude and phase distortion according to an embodiment of the present invention. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the present invention clearer, various exemplary embodiments described below will be referenced to the accompanying drawings, which form part of the exemplary embodiments, illustrating various exemplary embodiments that may be used to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. It should be understood that they are merely examples of processes, methods, and apparatuses consistent with some aspects of the present invention disclosed as detailed in the appended claims, and other embodiments may be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and spirit of the present invention.

[0039] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," etc., indicate the orientation or positional relationship based on the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the referred element must have a specific orientation, or be constructed and operated in a specific orientation. The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. The term "multiple" means two or more. The terms "connected" and "linked" should be interpreted broadly, for example, they can be fixed connections, detachable connections, integral connections, mechanical connections, electrical connections, communication connections, direct connections, indirect connections through an intermediate medium, and can be the internal connection of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0040] To illustrate the technical solution described in this invention, specific embodiments are described below, showing only the parts related to the embodiments of this invention.

[0041] Example:

[0042] like Figure 1As shown, this invention provides a power amplifier with improved amplitude and phase distortion, including a first-stage input matching circuit T1, a first-stage driver amplifier circuit, a first-stage inter-stage matching circuit T2, a second-stage power amplifier circuit, a second-stage output matching circuit T3, and a linearization structure. It is preferably manufactured using TSMC's 65nm process. The first-stage input matching circuit converts the single-ended input signal into a differential signal and performs impedance matching to avoid energy loss caused by signal reflection. The first-stage driver amplifier circuit is connected to the first-stage input matching circuit and employs a differential common-source amplifier structure. This differential common-source amplifier structure is used to suppress the output of common-mode signals, thereby eliminating even-order harmonics at the output end and amplifying the signal input to the first-stage input matching circuit to meet the input power requirements of the second-stage power amplifier. The first-stage inter-stage matching circuit is connected to the first-stage driver amplifier circuit for inter-stage matching. The second-stage power amplifier circuit is connected to the first-stage interstage matching circuit. It adopts a fully differential structure to suppress the common-mode signal output, thereby eliminating even-order harmonics at the output. It outputs power based on the Class A operating state of the CASCODE structure. In the Class A operating state, the MOS transistor of the CASCODE structure operates in the center of its linear amplification region. Whether it is the positive or negative half-cycle of the input signal, the MOS transistor is in a saturated conduction state. There is no signal distortion due to truncation or clipping effect, resulting in small harmonic components. While obtaining higher gain and output power, it reduces the harmonic components caused by amplifier nonlinearity, thereby improving the output power. The second-stage output matching circuit is connected to the second-stage power amplifier circuit. It is used to convert the differential signal of the second-stage output matching circuit into a single-ended signal and perform impedance transformation for power matching. The linearization structure is connected to the second-stage power amplifier circuit, that is, to the CASCODE structure of the second-stage power amplifier circuit. It is used to introduce the third harmonic signal of the power amplifier to AC ground through a capacitor and block the flow of the fundamental wave, thus achieving a filtering effect. The linearization structure is adjusted by a MOSFET. The MOSFET can easily control the degree of activation by the gate bias voltage, or determine whether to activate the structure, thereby reducing the amplitude and phase distortion of the power amplifier and improving linearity. In this invention, a linearization structure is connected to the CASCODE structure in the second-stage power amplifier circuit. Compared with existing power amplifiers, this significantly improves the amplitude and phase distortion when outputting large signals, thereby increasing the linearity of the circuit. At the same time, while achieving the same amplitude and phase improvement effect, the gain can decrease less than other structures such as multi-gate transistor technology, because this structure reduces the loss of the fundamental frequency, thus the gain will not decrease much. In addition, the linearization structure can significantly improve the conjugation degree between the output impedance of the CASCODE structure and the optimal load impedance, thereby improving the matching degree of circuit S22.

[0043] As an optional implementation method, such as Figure 1As shown, the linearization structure includes a first linearization structure and a second linearization structure. The first linearization structure and the second linearization structure have the same circuit structure, that is, the number of components, component parameters, and connection relationships between components are the same. The first linearization structure and the second linearization structure are connected to the source of MOS transistor M5 and the source of MOS transistor M6 of the second-stage power amplifier circuit, respectively. That is, they are both connected to the input MOS transistor of the CASCODE structure of the second-stage power amplifier circuit. Thus, the linearization structure is located between the input MOS transistor and the output MOS transistor of the CASCODE structure.

[0044] As an optional implementation method, such as Figure 1 As shown, the first linearization structure includes a MOSFET M7, a capacitor C5, resistors R3 and R4. The source of MOSFET M7 is connected to the drain of MOSFET M3. The drain is connected to the first plate of capacitor C5 and the first terminal of resistor R4. The gate is connected to the first terminal of resistor R3. The second plate of capacitor C5 is grounded. The second terminal of resistor R3 is connected to voltage Vctrl. The second terminal of resistor R4 is connected to power supply VL. The second linearization structure includes a MOSFET M8, a capacitor C6, resistors R5 and R6. The source of MOSFET M8 is connected to the drain of MOSFET M4. The drain is connected to the first plate of capacitor C6 and the first terminal of resistor R6. The gate is connected to the first terminal of resistor R5. The second plate of capacitor C6 is grounded. The second terminal of resistor R5 is connected to voltage Vctrl. The second terminal of resistor R6 is connected to power supply VL. The first and second linear structured circuits are connected to the input MOSFETs of the second-stage power amplifier circuit's CASCODE structure via MOSFETs M7 and M8, respectively. This allows the third harmonic signal of the second-stage power amplifier circuit to be introduced to AC ground through capacitors C5 and C6, while also blocking the inflow of the fundamental frequency, thus achieving a filtering effect. The degree of linearization structure activation can be adjusted by changing the gate voltages of MOSFETs M7 and M8, thereby reducing the amplitude and phase distortion of the circuit.

[0045] As an optional implementation method, such as Figure 2 As shown (using the first linearization structure as an example), when the voltage Vctrl = 0V, the linearization structure is turned off, which is the normal mode and does not affect the circuit gain; Figure 3As shown (using the first linearization structure as an example), when the voltage Vctrl > 1.4V, the MOSFET of the linearization structure is turned on, and the linearization structure is activated. By precisely selecting the capacitance values ​​of capacitors C5 and C6, the third harmonic is allowed to flow into the AC ground through capacitors C5 and C6 without affecting the fundamental frequency, thus achieving a filtering effect. If the capacitance value is too small, the harmonic will not be filtered out, resulting in no improvement effect; if the capacitance value is too large, the fundamental frequency will pass through, severely affecting the overall gain of the circuit. As the external voltage Vctrl is gradually increased to 1.9V, the conduction current of the MOSFET in the linearization structure gradually increases. After passing through capacitors C5 and C6, the linearization improvement effect becomes more obvious, and this structure can also improve the output impedance of the CASCODE structure.

[0046] As an optional implementation method, such as Figure 4 As shown, the first linearization structure includes resistor R7 and capacitor C8, and the second linearization structure includes resistor R8 and capacitor C9. The first terminal of resistor R7 is connected to the drain of MOSFET M3, and the second terminal is connected to the first plate of capacitor C8, whose second plate is grounded. Similarly, the first terminal of resistor R8 is connected to the drain of MOSFET M4, and the second terminal is connected to the first plate of capacitor C9, whose second plate is grounded. In other words, the first terminals of both resistors R7 and R8 are connected to the input MOSFETs of the second-stage power amplifier circuit's CASCODE structure. In this case, the first and second linearization structures are simpler, achieving harmonic filtering while retaining the fundamental frequency, thus significantly saving chip area and reducing cost and power consumption.

[0047] As an optional implementation, the first-stage driver amplifier circuit includes neutralizing capacitors C1 and C2, MOSFETs M1 and M2. The gate of MOSFET M1 is connected to the first-stage input matching circuit and the first plate of neutralizing capacitor C2, its source is grounded, and its drain is connected to the second plate of neutralizing capacitor C1 and the first-stage inter-stage matching circuit. The gate of MOSFET M2 is connected to the first-stage input matching circuit and the first plate of neutralizing capacitor C1, its source is grounded, and its drain is connected to the second plate of neutralizing capacitor C2 and the first-stage inter-stage matching circuit. By adjusting the capacitance values ​​of neutralizing capacitors C1 and C2, the stability of the differential pair of the single-stage amplifier can be adjusted.

[0048] As an optional implementation, the second-stage power amplifier circuit includes MOSFETs M3, M4, M5, and M6, neutralizing capacitors C3 and C4. The gates of MOSFETs M3 and M4 are both connected to the input signal of the first-stage interstage matching circuit, and their sources are both grounded and interconnected. The drain of MOSFET M3 is connected to the source of MOSFET M5 and the first plate of neutralizing capacitor C3. The second plate of neutralizing capacitor C3 is connected to the gate of MOSFET M4. The drain of MOSFET M4 is connected to the source of MOSFET M6 and neutralizing capacitor C4. The second plate of neutralizing capacitor C4 is connected to the gate of MOSFET M3. The gates of MOSFETs M3 and M4 are respectively connected to two differential input signals of the CASCODE structure, forming the input MOSFET of the CASCODE structure. The gates of MOSFETs M5 and M6 are both connected to a bias voltage VG3, and their drain output signals are both connected to the second-stage output matching circuit. Corresponding to the two differential output signals of the CASCODE structure, this forms the output MOSFETs of the CASCODE structure. Specifically, the output MOSFETs are connected to the input inductor of the balun in the second-stage output matching circuit, and through this input inductor, to the supply voltage VDD2. In this embodiment, neutralizing capacitors C3 and C4 are used to improve circuit stability. The drain signal of the CASCODE structure's input signal MOSFET is introduced to the gate of the MOSFET at the input of the other differential signal in the CASCODE structure via the neutralizing capacitors, thus improving the stability of the second-stage power amplifier circuit.

[0049] As an optional implementation, the first-stage input matching circuit matches the impedance from 50 ohms to the conjugate value of the input impedance of the first-stage driver amplifier to reduce losses. The 50-ohm matching balances minimum loss (75 ohms) and maximum power capacity (30 ohms), ensuring reflection-free signal transmission between the signal source and power amplifier, reducing losses and distortion. The first-stage inter-stage matching circuit ( Figure 1 , Figure 4 T2 in the first stage driver amplifier matches the conjugate value of the output impedance of the first stage driver amplifier to the conjugate value of the input impedance of the second stage power amplifier. This ensures that the real parts of the impedances of the first stage driver amplifier and the second stage power amplifier are equal, while the imaginary parts are equal in size and opposite in sign. This is used to achieve interstage matching, thereby maximizing power transmission efficiency, ensuring gain flatness, and avoiding signal reflection to reduce losses.

[0050] As an optional implementation method, such as Figure 1 , Figure 4As shown, both the first-stage input matching circuit and the second-stage output matching circuit employ balun-based transformers. A balun is a balun-to-unbalanced converter, a three-port device used to convert single-ended signals (unbalanced) into differential signals (balanced). In this embodiment, the balun-based transformer is a specific implementation of the balun, namely a magnetically coupled transformer-type balun. The first-stage input matching circuit connects the differential output port of the balun to the differential signal input of the first-stage driver amplifier. Specifically, the single-ended input port of the balun is connected to the input signal, and the differential output port is connected to the gates of MOSFETs M1 and M2 of the first-stage driver amplifier. The differential input port of the balun in the second-stage output matching circuit connects to the differential signal output of the second-stage power amplifier. A capacitor C7 is connected in parallel between the single-ended output interface of the balun and the single-ended ground of the balun to achieve broadband impedance matching, i.e., impedance matching over a wide frequency range, thereby maximizing energy transfer efficiency and minimizing reflection loss.

[0051] As an optional implementation, regarding the CASCODE structure of the second-stage power amplifier circuit, the simulation results are as follows: Figures 5-7 As shown, when the linearization structure is enabled, the in-band gain of the single-stage amplifier decreases by about 2dB, while the output reflection coefficient S... 22 The relative distortion of amplitude and phase at 34 GHz will be significantly improved, as shown in the simulation results attached. Figure 7 As shown, the smaller the relative distortion, the better. Power amplifiers are prone to distortion when outputting large signals. This structure can improve the amplitude and phase distortion of a single-stage power amplifier to 0° at the 1dB compression point, and the overall amplitude before the 1dB compression point does not exceed 0.6°.

[0052] Regarding the power amplifier, the overall simulation results are as follows: Figures 8-15 As shown, when the linearization structure is in linearization mode and the external bias voltage Vctrl = 1.7V, the gain drops by 2dB. When the external bias voltage Vctrl = 1.9V, the gain drops by 2.4~3dB, and the output reflection coefficient S of the power amplifier... 22 Within the 28~34GHz operating frequency band, the impedance was reduced from -7dB to below -10dB, improving the conjugation degree of the output impedance and optimal load impedance of the CASCODE structure. The output impedance change is as follows: Figure 10 As shown. The amplitude-phase relative distortion of the power amplifier is as follows. Figure 12 , Figure 15 As shown, at 26 GHz, the amplitude-phase relative distortion at the 1dB compression point decreased from 5.9° to 1.5°, and at 34 GHz, the amplitude-phase relative distortion at the 1dB compression point decreased from 2.5° to 0°. Other frequency points also showed an improvement of approximately 4°. The large-signal simulation results of the power amplifier are as follows: Figure 13 , Figure 14As shown, at 30GHz, the normal mode P1dB (output power point with 1dB gain compression, used to describe gain compression due to saturation under single signal) is 15.9dBm, Psat (Saturation Power, representing the power value of the amplifier when it enters deep saturation at maximum output power) is 17.5dBm, and the peak PAE (Power-Added Efficiency, representing the net gain efficiency of RF output power relative to DC input power) is 21.2%; the linear mode P1dB is 15dBm, Psat is 17.2dBm, and the peak PAE is 17.5%.

[0053] The embodiment is merely a specific example and does not indicate that this is the only way to implement the present invention.

[0054] The above description is merely a preferred embodiment of the present invention. Those skilled in the art will understand that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the present invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. A power amplifier with improved amplitude and phase distortion, characterized in that, It includes a first-stage input matching circuit, a first-stage driver amplifier circuit, a first-stage inter-stage matching circuit, a second-stage power amplifier circuit, a second-stage output matching circuit, and a linearization structure; The first-stage input matching circuit converts the single-ended input signal into a differential signal and performs impedance matching. The first-stage driver amplifier circuit is connected to the first-stage input matching circuit and adopts a differential common-source amplifier structure to amplify the signal input to the first-stage input matching circuit to meet the input power requirements of the second-stage power amplifier. The first-stage inter-stage matching circuit is connected to the first-stage driver amplifier circuit for inter-stage matching. The second-stage power amplifier circuit is connected to the first-stage inter-stage matching circuit, adopts a fully differential structure to suppress the common-mode signal output, and performs power output based on the Class A operating state of the CASCODE structure. The second-stage output matching circuit is connected to the second-stage power amplifier circuit to convert the differential signal of the second-stage output matching circuit into a single-ended signal and perform impedance transformation for power matching. The linearization structure is connected to the second-stage power amplifier circuit to introduce the third harmonic signal of the power amplifier to AC ground through a capacitor and to block the inflow of the fundamental frequency. The linearization structure adjusts the turn-on degree through a MOSFET. The linearization structure includes a first linearization structure and a second linearization structure. The first linearization structure and the second linearization structure have the same circuit structure and are respectively connected to the drain of MOS transistor M3 and the drain of MOS transistor M4 in the second stage power amplifier circuit. When the voltage Vctrl = 0V, the linearization structure is turned off, which is the normal mode; when the voltage Vctrl > 1.4V, the MOS transistor of the linearization structure is turned on, and the linearization structure is turned on.

2. The power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The first linearization structure includes a MOSFET M7, a capacitor C5, resistors R3 and R4. The source of the MOSFET M7 is connected to the drain of the MOSFET M3. The drain of the MOSFET M7 is connected to the first plate of the capacitor C5 and the first terminal of the resistor R4. The gate of the MOSFET M7 is connected to the first terminal of the resistor R3. The second plate of the capacitor C5 is grounded. The second terminal of the resistor R3 is connected to a voltage Vctrl. The second terminal of the resistor R4 is connected to a power supply V. L Connection; the second linearized structure includes a MOSFET M8, a capacitor C6, resistors R5 and R6. The source of the MOSFET M8 is connected to the drain of the MOSFET M4, the drain is connected to the first plate of the capacitor C6 and the first terminal of the resistor R6, the gate is connected to the first terminal of the resistor R5, the second plate of the capacitor C6 is grounded, the second terminal of the resistor R5 is connected to the voltage Vctrl, and the second terminal of the resistor R6 is connected to the power supply V. L connect.

3. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The first linearization structure includes a resistor R7 and a capacitor C8, and the second linearization structure includes a resistor R8 and a capacitor C9; the first end of the resistor R7 is connected to the drain of the MOSFET M3, and the second end is connected to the first plate of the capacitor C8, and the second plate of the capacitor C8 is grounded; the first end of the resistor R8 is connected to the drain of the MOSFET M4, and the second end is connected to the first plate of the capacitor C9, and the second plate of the capacitor C9 is grounded.

4. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The first-stage driver amplifier circuit includes neutralizing capacitor C1, neutralizing capacitor C2, MOSFET M1, and MOSFET M2. The gate of MOSFET M1 is connected to the first-stage input matching circuit and the first plate of neutralizing capacitor C2, the source is grounded, and the drain is connected to the second plate of neutralizing capacitor C1 and the first-stage interstage matching circuit. The gate of MOSFET M2 is connected to the first-stage input matching circuit and the first plate of neutralizing capacitor C1, the source is grounded, and the drain is connected to the second plate of neutralizing capacitor C2 and the first-stage interstage matching circuit.

5. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The second-stage power amplifier circuit includes MOSFETs M3, M4, M5, and M6, neutralizing capacitors C3 and C4. The gates of MOSFETs M3 and M4 are connected to the input signal of the first-stage interstage matching circuit, and their sources are grounded. The drain of MOSFET M3 is connected to the source of MOSFET M5 and the first plate of neutralizing capacitor C3. The second plate of neutralizing capacitor C3 is connected to the gate of MOSFET M4. The drain of MOSFET M4 is connected to the source of MOSFET M6 and neutralizing capacitor C4. The second plate of neutralizing capacitor C4 is connected to the gate of MOSFET M3. The gates of MOSFETs M5 and M6 are both connected to a bias voltage, and their drain output signals are both connected to the second-stage output matching circuit.

6. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The first-stage input matching circuit matches the impedance from 50 ohms to the conjugate value of the input impedance of the first-stage driver amplifier.

7. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, The first-stage interstage matching circuit matches the conjugate value of the output impedance of the first-stage driver amplifier to the conjugate value of the input impedance of the second-stage power amplifier.

8. A power amplifier for improving amplitude and phase distortion according to claim 1, characterized in that, Both the first-stage input matching circuit and the second-stage output matching circuit use balun-based transformers. The differential output port of the first-stage input matching circuit is connected to the differential signal input terminal of the first-stage driver amplifier. The differential input port of the balun of the second-stage output matching circuit is connected to the differential signal output terminal of the second-stage power amplifier, and a capacitor C7 is connected in parallel between the single-ended output interface of the balun and the single-ended ground of the balun.

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