An adaptive configurable hash algorithm hardware accelerator

Abstract

The application discloses a self-adaptive configurable hash algorithm hardware accelerator, and belongs to the technical field of data processing, which comprises a parameter configuration module, which is used for receiving and analyzing externally input configuration parameters; an algorithm adaptation module, which is used for selecting corresponding target processing logic from preset multiple hash algorithm processing logics according to an algorithm type parameter; a data processing module, which is used for executing hash operation on input data according to a data length parameter under the control of the target processing logic; a performance monitoring module, which is used for monitoring running performance parameters in real time, comparing the running performance parameters with performance requirement parameters, and obtaining performance comparison results; and a dynamic adjustment module, which is used for dynamically adjusting the target processing logic and operation parameters according to the performance comparison results and a preset adjustment strategy; the self-adaptive configurable hash algorithm hardware accelerator can adapt to different hash algorithm requirements, and improves the flexibility and efficiency of hash operation.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and in particular to an adaptive and configurable hash algorithm hardware accelerator. BACKGROUND

[0002] In today's information age, data security and data processing efficiency have become key issues. Hash algorithm, as an important data processing technology, is widely used in data encryption, data verification, data indexing and other fields. Common hash algorithms include MD5, SHA-1, SHA-256, SHA-512, etc. Different hash algorithms have different characteristics and application scenarios.

[0003] In order to improve the efficiency of hash operation, hardware accelerator is widely used. However, the existing hash algorithm hardware accelerator is mostly designed for one or several specific hash algorithms, lacking flexibility and adaptability. When different hash algorithms need to be processed, different hardware accelerators often need to be replaced, which not only increases the cost, but also reduces the integration and scalability of the system.

[0004] In addition, the existing hardware accelerator cannot be dynamically adjusted according to the actual running status and performance requirements during operation, resulting in low operation efficiency, resource waste or excessive power consumption in different application scenarios. For example, in scenarios with high real-time requirements, the existing accelerator may not provide fast enough operation speed; in resource-limited scenarios, the accelerator may occupy too much system resources.

[0005] Therefore, it has become a problem for those skilled in the art to develop a hardware accelerator that can adapt to different hash algorithm requirements and dynamically adjust according to the running status. SUMMARY

[0006] The purpose of the present application is to provide an adaptive and configurable hash algorithm hardware accelerator to solve the problem of poor flexibility and inability to dynamically adjust in the existing hash algorithm hardware accelerator mentioned in the background.

[0007] To achieve the above purpose, the present application provides an adaptive and configurable hash algorithm hardware accelerator, comprising:

[0008] A parameter configuration module is configured to receive external input configuration parameters and parse the configuration parameters to obtain algorithm type parameters, data length parameters and performance requirement parameters.

[0009] An algorithm adaptation module is connected to the parameter configuration module and is configured to select a corresponding target processing logic from a plurality of preset hash algorithm processing logics according to the algorithm type parameters.

[0010] The data processing module is connected with the algorithm adaptation module and is configured to perform a hash operation on the input data according to the data length parameter under the control of the target processing logic to obtain a hash result.

[0011] The performance monitoring module is connected with the data processing module and the parameter configuration module respectively and is configured to monitor a running performance parameter of the data processing module in real time, compare the running performance parameter with a performance requirement parameter, and obtain a performance comparison result.

[0012] The dynamic adjustment module is connected with the performance monitoring module, the algorithm adaptation module and the data processing module respectively and is configured to dynamically adjust the target processing logic of the algorithm adaptation module and the operation parameter of the data processing module according to the performance comparison result and a preset adjustment strategy.

[0013] Preferably, the plurality of hash algorithm processing logics preset in the algorithm adaptation module include MD5, SHA-1, SHA-256 and SHA-512 processing logics.

[0014] Preferably, the data processing module includes a data buffering unit, an operation unit and a result output unit, and specifically includes:

[0015] The data buffering unit is configured to buffer the input data.

[0016] The operation unit is connected with the data buffering unit and the algorithm adaptation module and is configured to perform a hash operation on the buffered input data under the control of the target processing logic, and specifically includes:

[0017] S1, preprocessing the input data to convert the input data of any length into fixed-length groups, including length padding and splitting the padded data stream into N bits to obtain M(0), M(1), …, M(n-1) n groups, each group being an independent unit entering the next step;

[0018] S2, splitting the group M(i) into w bits to obtain W0, W1, …, W(m-1), wherein m=N / w; generating additional message words Wm, W(m+1), …, W(t-1) through an iterative formula, wherein t is the total number of message words;

[0019] S3, performing iterative operation on the extended message words and the algorithm predefined initial hash value as the initial value of iteration, performing r rounds of iteration on each group, using the message word Wj to update the state register in each round, and accumulating the final state register and the initial hash value after the iteration of a group is completed as the initial value of the next group;

[0020] S4, accumulating the final state registers of all groups after processing In sequence, the hash result of fixed length is obtained, wherein, The number of state registers; a result output unit, connected with the operation unit, for outputting the hash result.

[0021] Preferably, the operation unit adopts a reconfigurable computing architecture, and changes the internal operation logic and data path according to the adjustment instruction of the dynamic adjustment module, including:

[0022] The time-sharing multiplexing logic of the basic operation unit realizes the switching of the logic functions of different algorithms through the configuration selector;

[0023] The mixed deployment of 64-bit adders and 32-bit adders adapts different word length algorithms through the input selector;

[0024] The full pipeline structure includes a message word expansion pipeline and a compression function pipeline, both of which realize the output of a calculation result once per clock cycle through parallel execution, wherein:

[0025] The message word expansion pipeline stores the minimum message word required for the current iteration through the register multiplexing mechanism, and dynamically updates the register content as the iteration progresses;

[0026] The compression function pipeline shortens the critical path by precomputing intermediate variables, and supports the multiplexing of the iteration logic of multiple hash algorithms.

[0027] Preferably, it further includes a power management module for adjusting the power supply voltage and current of each power consumption module according to the instruction of the dynamic adjustment module.

[0028] Preferably, the running performance parameters include operation speed, resource occupancy rate and power consumption.

[0029] Preferably, the preset adjustment strategy includes:

[0030] When the operation speed in the running performance parameter is lower than the corresponding speed threshold in the performance requirement parameter, the dynamic adjustment module controls the algorithm adaptation module to switch to the hash algorithm processing logic with high operation speed, and controls the data processing module to increase the operation frequency;

[0031] When the resource occupancy rate in the running performance parameter is higher than the corresponding resource threshold in the performance requirement parameter, the dynamic adjustment module controls the algorithm adaptation module to switch to the hash algorithm processing logic with low resource occupancy, and controls the data processing module to reduce the number of parallel operations;

[0032] When the power consumption in the running performance parameter is higher than the corresponding power consumption threshold in the performance requirement parameter, the dynamic adjustment module reduces the core power supply voltage through the power management module, and controls the operation unit to enable the low power consumption mode.

[0033] Preferably, the parameter configuration module supports configuration through an OpenCL API, including: asynchronous calculation control between a host and an FPGA device, data filling being completed on the CPU side, and message word expansion and compression functions being executed on the FPGA side.

[0034] Hierarchical allocation of global memory and local memory, grouped data being stored in the global memory and intermediate variables being stored in the local memory.

[0035] Preferably, the parameter configuration module is further configured to receive externally input algorithm custom parameters, and the algorithm adaptation module generates new hash algorithm processing logic according to the algorithm custom parameters, at this time, the custom parameters satisfy the reconfigurable architecture constraints: word length w∈{32bit, 64bit}, group length N=512bit or 1024bit, iteration round number r≤128, and the logic function call operation unit supports the basic operation.

[0036] Therefore, the adaptive and configurable hash algorithm hardware accelerator has the following beneficial effects:

[0037] (1) The algorithm adaptation module can select the corresponding target processing logic from the preset multiple hash algorithm processing logics, and also supports generating new hash algorithm processing logic according to the algorithm custom parameters, which can adapt to different hash algorithm requirements without replacing the hardware accelerator, thereby improving the flexibility and scalability of the system;

[0038] (2) The performance monitoring module monitors the running performance parameters of the accelerator in real time, and the dynamic adjustment module dynamically adjusts the running state of the accelerator according to the performance comparison result and the preset adjustment strategy, so that the accelerator can maintain good performance in different application scenarios, and the problems of low operation efficiency, resource waste or high power consumption are avoided;

[0039] (3) The operation unit in the data processing module adopts a reconfigurable computing architecture, which can change the internal operation logic and data path as needed, and further improves the efficiency of hash operation in cooperation with the adjustment of the dynamic adjustment module;

[0040] (4) Not only can it support common hash algorithms, but also can adapt to custom hash algorithms, and can be widely applied to various fields requiring hash operation such as data encryption, data verification, data indexing, etc.

[0041] The technical solutions of the present application will be further described in detail below with reference to the drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0042] Fig. 1 FIG. 1 is a structural schematic diagram of an adaptive and configurable hash algorithm hardware accelerator according to the present application;

[0043] Fig. 2 Asynchronous computing schematic diagram of host end and device end of an embodiment of the present application. DETAILED DESCRIPTION

[0044] The following detailed description of embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application claimed, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0045] Please refer to Figs. 1-2 An adaptive configurable hash algorithm hardware accelerator comprises:

[0046] A parameter configuration module is configured to receive externally input configuration parameters, and parse the configuration parameters to obtain algorithm type parameters, data length parameters and performance requirement parameters;

[0047] An algorithm adaptation module is connected to the parameter configuration module, and is configured to select a corresponding target processing logic from a plurality of preset hash algorithm processing logics according to the algorithm type parameters;

[0048] A data processing module is connected to the algorithm adaptation module, and is configured to execute a hash operation on input data according to the data length parameters under the control of the target processing logic, to obtain a hash result;

[0049] A performance monitoring module is connected to the data processing module and the parameter configuration module, and is configured to monitor running performance parameters of the data processing module in real time, and compare the running performance parameters with the performance requirement parameters to obtain a performance comparison result;

[0050] A dynamic adjustment module is connected to the performance monitoring module, the algorithm adaptation module and the data processing module, and is configured to dynamically adjust the target processing logic of the algorithm adaptation module and the operation parameters of the data processing module according to the performance comparison result and a preset adjustment strategy;

[0051] A power management module is configured to adjust the supply voltage and current of each power module according to the instructions of the dynamic adjustment module.

[0052] To verify the adaptive configuration capability, algorithm switching efficiency and core function correctness of the accelerator in multiple scenarios, the following experimental environment is simulated:

[0053] Hardware: Intel Stratix10 GX2800 FPGA (logic resource 550k ALUT), Intel Xeon E5-2650 CPU, 16GB DDR4 memory, PCIe 3.0 interface;

[0054] Software: Intel OpenCL SDK (version 20.1), C++ test framework, power consumption monitoring tool (Tektronix PA3000);

[0055] Test data: 1 GB random plaintext data (divided into 1000 1 MB blocks).

[0056] The experimental procedure is as follows:

[0057] Step 1: initialization configuration

[0058] Input initial parameters through the parameter configuration module:

[0059] Algorithm type parameter: preferentially enable SHA-256;

[0060] Performance requirement parameter: speed ≥ 300 MHash / s, resource occupancy rate ≤ 50%, power consumption ≤ 20 W;

[0061] Enable OpenCL API configuration: CPU is responsible for data preprocessing (padding), FPGA is responsible for message expansion and compression iteration.

[0062] The accelerator automatically loads the SHA-256 processing logic, and the operation unit initializes the reconfigurable architecture (8 64-bit adders and 16 32-bit register groups are enabled).

[0063] Step 2: basic performance verification (preset algorithm)

[0064] Input 1 GB plaintext data, trigger the data processing module to execute the following process:

[0065] S1, preprocessing: CPU pads the data to 512-bit groups (a total of 2 million groups), and transmits them to the FPGA global memory through PCIe;

[0066] S2, message expansion: FPGA splits the group into 16 32-bit message words, and generates 64 expanded message words (W 0- W 63 ) through the iteration formula;

[0067] S3, iteration operation: starting from the initial hash value (0x6a09e667...), perform 64 rounds of compression iteration, and update 8 state registers each round;

[0068] S4, result generation: cascade the final state registers to output a 256-bit hash value.

[0069] Performance monitoring module records:

[0070] Operation speed: 372 MHash / s (satisfies the requirement of ≥ 300 MHash / s);

[0071] Resource occupation: 42% (ALUT usage 231k / 550k);

[0072] Power consumption: 15W (≤20W requirement).

[0073] Step 3: Dynamic adjustment verification (resource shortage scenario)

[0074] New test task: Enable both SHA-256 and SHA-1 algorithms (dual algorithm parallel), and the performance monitoring module detects that the resource occupation rate rises to 65% (exceeding the 50% threshold).

[0075] Dynamic adjustment module triggers strategy:

[0076] Control algorithm adaptation module switches to "resource optimization mode", SHA-256 and SHA-1 share 4 64-bit adders;

[0077] Operation unit closes 2-way parallel pipeline, reduces register group to 12.

[0078] Re-execute 1GB data processing, results:

[0079] Resource occupation rate drops to 48% (meets requirements);

[0080] Operation speed: SHA-256 is 280MHash / s, SHA-1 is 210MHash / s (still meets the actual scene requirements).

[0081] Step 4: Algorithm switching verification (real-time scenario)

[0082] Simulation scenario: switch from "SHA-256" to "custom algorithm" (parameters: 32-bit word length, 64 rounds of iteration, logic function ).

[0083] Switching process:

[0084] Parameter configuration module receives custom parameters, algorithm adaptation module generates new processing logic (180ms); dynamic adjustment module reconfigures operation unit: switch adder word length to 32 bits, update logic function selector; execute custom algorithm processing, results:

[0085] The first group of data processing after switching takes 2.3ms (including reconfiguration delay);

[0086] Hash value correctness: consistent with software simulation results (verify core logic correct).

[0087] Step 5: Low power verification

[0088] Manually set performance requirement parameters: power consumption ≤10W (simulate embedded scenario).

[0089] The dynamic adjustment module reduces the FPGA core voltage from 1.0V to 0.8V and the operation frequency from 370MHz to 200MHz through the power management module.

[0090] SHA-256 operation is performed, and the result is:

[0091] Power consumption: 9.2W (satisfies the requirement);

[0092] Operation speed: 205MHash / s (sacrifice part of performance to obtain low power consumption).

[0093] According to the above verification data, it is shown that the accelerator can correctly perform the hash operation of the preset algorithm and the self-defined algorithm, the result is consistent with the theoretical value, in the scene of resource shortage and low power consumption, the parameter self-adaption is realized through the dynamic adjustment model, the diversified performance requirements are met, the algorithm switching time is less than or equal to 200ms, the real-time scene demand is supported, and the effectiveness and practicability of the scheme are verified.

[0094] Therefore, the adaptive and configurable hash algorithm hardware accelerator is adopted, the problems in the prior art are effectively solved through the reasonable module design and the dynamic adjustment mechanism, and the scheme has remarkable creativity and practicability.

[0095] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application but not to limit it, although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that: the technical solutions of the present application can still be modified or replaced by the equivalent, and these modifications or equivalent replacements cannot make the modified technical solutions deviate from the spirit and scope of the technical solutions of the present application.

Claims

1. An adaptive configurable hash algorithm hardware accelerator, comprising: The application relates to a hash algorithm processing method and device. The application comprises the following: A parameter configuration module is used for receiving externally input configuration parameters, and the configuration parameters are parsed to obtain algorithm type parameters, data length parameters and performance requirement parameters; An algorithm adaptation module is connected with the parameter configuration module, and is used for selecting corresponding target processing logic from preset multiple hash algorithm processing logics according to the algorithm type parameters; A data processing module is connected with the algorithm adaptation module, and is used for executing hash operation on input data according to the data length parameters under the control of the target processing logic to obtain a hash result; A performance monitoring module is connected with the data processing module and the parameter configuration module, and is used for monitoring the running performance parameters of the data processing module in real time, comparing the running performance parameters with the performance requirement parameters, and obtaining a performance comparison result; A dynamic adjustment module is connected with the performance monitoring module, the algorithm adaptation module and the data processing module, and is used for dynamically adjusting the target processing logic of the algorithm adaptation module and the operation parameters of the data processing module according to the performance comparison result and a preset adjustment strategy; The data processing module comprises a data cache unit, an operation unit and a result output unit, and specifically comprises the following: The data cache unit is used for caching input data; The operation unit is connected with the data cache unit and the algorithm adaptation module, and is used for performing hash operation on the cached input data under the control of the target processing logic, and specifically comprises the following: S1, preprocessing input data, converting input data of any length into fixed-length groups, including length padding, and splitting the padded data stream into M(0), M(1), …, M(n-1) n groups, each group serving as an independent unit to enter the next step; S3, add the extended message word to the initial hash value predefined by the algorithm As an iterative initial value, perform r rounds of iteration on each packet, update the state register using the message word Wj in each round, and after one packet iteration is completed, add the final state register to the initial hash value as the initial value of the next packet. S4, final state register after all packet processing is complete concatenated in order, resulting in a fixed length hash result, wherein, is the number of state registers; S2, splitting the group M(i) into W0, W1, …, W(m-1), wherein m=N / w; generating additional message words Wm, W(m+1), …, W(t-1) through an iteration formula, wherein t is the total number of message words; The result output unit is connected with the operation unit and is used for outputting a hash result; The operation unit adopts a reconfigurable computing architecture, and changes internal operation logic and data paths according to adjustment instructions of the dynamic adjustment module, and comprises the following: Time-sharing multiplexing logic of a basic operation unit, which realizes logical function switching of different algorithms through a configuration selector; Mixed deployment of 64-bit adders and 32-bit adders, which adapts different word length algorithms through an input selector; A full pipeline structure, including a message word expansion pipeline and a compression function pipeline, which realizes output of a calculation result once per clock cycle through parallel execution, wherein: The message word expansion pipeline stores the minimum message words required for the current iteration through a register multiplexing mechanism, and dynamically updates the register content with iteration advancement; The compression function pipeline adopts a pre-computed intermediate variable to shorten a critical path, and supports iteration logic multiplexing of multiple hash algorithms. The parameter configuration module is further configured to receive externally input algorithm customized parameters, and the algorithm adaptation module generates new hash algorithm processing logic according to the algorithm customized parameters, at this time, the customized parameters satisfy the reconfigurable architecture constraints: word length w∈{32bit, 64bit}, packet length N=512bit or 1024bit, iteration round number r≤128, and the basic operation supported by the logic function calling operation unit.

2. The self-adapting configurable hash algorithm hardware accelerator of claim 1, wherein: The preset multiple hash algorithm processing logics in the algorithm adaptation module include MD5, SHA-1, SHA-256 and SHA-512 processing logics.

3. The self-adapting configurable hash algorithm hardware accelerator of claim 1, wherein: The power management module is further included, and is configured to adjust the power supply voltage and current of each power consumption module according to the instruction of the dynamic adjustment module.

4. The self-adapting configurable hash algorithm hardware accelerator of claim 3, wherein: The running performance parameters include operation speed, resource occupancy and power consumption.

5. The self-adapting configurable hash algorithm hardware accelerator of claim 4, wherein, The preset adjustment strategy includes: When the operation speed in the running performance parameters is lower than the corresponding speed threshold in the performance requirement parameters, the dynamic adjustment module controls the algorithm adaptation module to switch to the hash algorithm processing logic with high operation speed, and controls the data processing module to improve the operation frequency; When the resource occupancy in the running performance parameters is higher than the corresponding resource threshold in the performance requirement parameters, the dynamic adjustment module controls the algorithm adaptation module to switch to the hash algorithm processing logic with low resource occupancy, and controls the data processing module to reduce the number of parallel operations; When the power consumption in the running performance parameters is higher than the corresponding power consumption threshold in the performance requirement parameters, the dynamic adjustment module reduces the core power supply voltage through the power management module, and controls the operation unit to enable the low power consumption mode.

6. The self-adapting configurable hash algorithm hardware accelerator of claim 1, wherein, The parameter configuration module supports configuration through the OpenCL API, including: Asynchronous calculation control between the host side and the FPGA device side, data filling is completed at the CPU side, and the message word expansion and compression function is executed at the FPGA side; Layered allocation of the global memory and the local memory, and grouping data is stored in the global memory and intermediate variables are stored in the local memory.

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