Semiconductor device, manufacturing method thereof and electronic equipment
By forming the bit line on the back of the substrate and introducing the air gap, the problem of difficulty in manufacturing the bit line is solved, the performance and production efficiency of the semiconductor device are improved, and the process flow is simplified.
Patent Information
- Application Number
- CN202410379832.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-29
- Publication Date
- 2025-09-30
AI Technical Summary
In semiconductor device manufacturing, bit lines are difficult to fabricate, which affects device performance and production efficiency.
The method of forming bit lines on the back side of the substrate is adopted. By forming a recessed trench on the second surface of the substrate and depositing the bit lines therein, the difficulty of manufacturing the bit lines is reduced, and air gaps are introduced between adjacent bit lines to reduce coupling capacitance.
The difficulty of manufacturing the bit line is reduced, the performance and production efficiency of the semiconductor device are improved, and the process flow is simplified.
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Figure CN120730728A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing accordingly, so that slight differences in process production may affect device performance.
[0003] To minimize product costs, people hope to create as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention
[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.
[0005] Embodiments of the present application provide a semiconductor device, a manufacturing method thereof, and an electronic device. The manufacturing method reduces the difficulty of manufacturing bit lines.
[0006] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:
[0007] providing a first substrate having a first surface and a second surface;
[0008] forming a plurality of transistors distributed in an array on the first surface, the transistors comprising a semiconductor pillar extending in a direction perpendicular to the first substrate and a gate electrode at least partially surrounding the semiconductor pillar, the semiconductor pillar comprising a first end surface away from the second surface and a second end surface close to the second surface;
[0009] Processing the second surface of the first substrate to expose at least the second end surface of the semiconductor pillar;
[0010] A plurality of bit lines are formed on the second surface of the first substrate, parallel to the first surface of the first substrate and extending along the column direction. Each bit line corresponds to a column of the transistors, and the bit line contacts the second end surface of each semiconductor column of the corresponding column of the transistors.
[0011] In some embodiments, forming a plurality of bit lines on the second surface of the first substrate that are parallel to the first surface of the first substrate and extend along a column direction includes:
[0012] forming a plurality of first trenches on the second surface that are recessed toward the first surface of the first substrate, wherein each of the first trenches exposes a second end surface of each semiconductor column of a column of transistors;
[0013] A bit line is formed in each of the first trenches, and the bit line contacts the semiconductor pillars of a column of transistors exposed by the first trenches.
[0014] In some embodiments, forming a plurality of transistors distributed in an array on the first surface includes:
[0015] The first surface of the first substrate is etched to form a plurality of semiconductor pillars spaced apart from each other in row and column directions and extending in a direction perpendicular to the first surface of the first substrate, wherein any adjacent semiconductor pillars are spaced apart by a first insulating layer.
[0016] In some embodiments, processing the second surface of the first substrate to expose at least the second end surface of the semiconductor pillar includes:
[0017] The second surface of the first substrate is subjected to chemical mechanical polishing or etching to expose the second end faces of the semiconductor pillars and the first insulating layer, and the semiconductor pillars are insulated from each other by the first insulating layer.
[0018] In some embodiments, forming a plurality of first trenches on the second surface that are recessed toward the first surface of the first substrate, wherein each of the first trenches exposes the second end surface of each semiconductor pillar of a column of transistors, includes:
[0019] The exposed second end faces of the semiconductor pillars and the first insulating layer are etched on the second surface of the first substrate to form a plurality of first trenches that are recessed toward the first surface of the first substrate and extend along a column direction within the first surface of the first substrate, wherein the bottom wall of each of the first trenches exposes the second end faces of a column of semiconductor pillars and the first insulating layer between adjacent semiconductor pillars.
[0020] In some embodiments, the manufacturing method further comprises: etching the first insulating layer between two adjacent columns of semiconductor pillars on the second surface of the first substrate to form a second trench between two adjacent bit lines on the second surface;
[0021] A first insulating layer including an air gap is formed in the second trench.
[0022] In some embodiments, after forming the first trench and before forming a bit line in the first trench to contact the semiconductor pillar, the manufacturing method further includes:
[0023] A second insulating layer is formed on the sidewalls of the first trench, and the bottom wall of the first trench exposes the second end surface of the semiconductor column; the bit line is formed in the first trench including the second insulating layer.
[0024] In some embodiments, etching the first insulating layer between two adjacent columns of semiconductor pillars on the second surface of the first substrate to form a second trench between two adjacent bit lines on the second surface includes:
[0025] The first insulating layer between two adjacent rows of semiconductor pillars is etched on the second surface of the first substrate to expose the second insulating layer on the sidewalls of the first trench, thereby forming the second trench.
[0026] In some embodiments, before forming the bit line in the first trench, the manufacturing method further includes:
[0027] Germanium and phosphorus are sequentially used in the first trench to perform ion doping on the second end surface of the semiconductor column exposed by the first trench.
[0028] An embodiment of the present application provides a semiconductor device, including:
[0029] A plurality of transistors distributed in an array, each transistor comprising a semiconductor column and a gate electrode at least partially surrounding the semiconductor column; the semiconductor column comprising a first end surface and a second end surface;
[0030] a plurality of bit lines, each bit line corresponding to a column of the transistors, the bit line being in contact with the second end surface of the semiconductor column of the corresponding column of the transistors;
[0031] A first insulating layer is disposed between any adjacent semiconductor pillars.
[0032] In some embodiments, the semiconductor device further includes:
[0033] A plurality of first trenches extend along a column direction, wherein bottom walls of the first trenches expose the second end surfaces of a column of the semiconductor pillars, and the bit lines are located in the first trenches and contact the second end surfaces of the column of the semiconductor pillars.
[0034] In some embodiments, the semiconductor device further includes:
[0035] A plurality of second trenches extending along a column direction, wherein the second trenches are located between any two adjacent first trenches; the second trenches are filled with a first insulating layer, and the first insulating layer in the second trenches contains air gaps.
[0036] In some embodiments, the semiconductor pillar is made of silicon, and the second end surface of the semiconductor pillar contains a doping material, wherein the doping material includes germanium and phosphorus.
[0037] In some embodiments, the material of the bit line comprises metal.An embodiment of the present application further provides an electronic device comprising the semiconductor device.
[0038] In the manufacturing method of the embodiment of the present application, the bit line is formed on the back side of the substrate, which reduces the difficulty of manufacturing the bit line and improves the performance of the semiconductor device.
[0039] Other features and advantages of the present application will be described in the following description, and in part will become more apparent from the description, or understood by practicing the present application. Other advantages of the present application can be realized and obtained by the solutions described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.
[0041] Figure 1 A process flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;
[0042] Figure 2 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a transistor;
[0043] Figure 3 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after combining a first substrate with a second substrate;
[0044] Figure 4 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after the second end surface of the semiconductor pillar is exposed;
[0045] Figure 5 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a first trench;
[0046] Figure 6 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer in a first trench;
[0047] Figure 7 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application when ion doping is performed on an end face of a semiconductor pillar;
[0048] Figure 8A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a first trench is filled with a metal conductive layer;
[0049] Figure 9 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a bit line;
[0050] Figure 10 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after the adhesion barrier layer is flush with the bit line;
[0051] Figure 11 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer on a top surface of a bit line;
[0052] Figure 12 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after etching away a first insulating layer between two adjacent bit lines;
[0053] Figure 13 This is a schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a first insulating layer containing air gaps.
[0054] The meanings of the various symbols in the accompanying drawings are:
[0055] 11-first insulating layer; 12-second insulating layer; 13-first trench; 15-second trench; 14-air gap; 20-transistor; 21-semiconductor pillar; 211-first end surface; 212-second end surface; 22-gate electrode; 31-adhesion barrier layer; 32-metal conductive layer; 40-first substrate; 41-first surface; 42-second surface; 50-capacitor; 60-second substrate. DETAILED DESCRIPTION
[0056] To make the purpose, technical solutions and advantages of this application more clear, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless there is a conflict, the embodiments and features in the embodiments of this application can be combined with each other in any way.
[0057] The embodiments of the present application are not necessarily limited to the dimensions shown in the drawings. The shapes and sizes of the components in the drawings are preferred embodiments and may also be other shapes and sizes. In addition, the drawings schematically illustrate ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.
[0058] The sizes and proportions of the various film layers or components in the drawings of this application can be used as a reference in actual processes and are exemplary embodiments of the present invention. However, these are not intended to be limiting. For example, the aspect ratio of the semiconductor pillars, the thickness of the various film layers, and the spacing between them can be adjusted based on actual needs.
[0059] The ordinal numbers such as “first” and “second” in this application are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
[0060] In this application, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation on this application. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in the disclosure are not limited and may be appropriately replaced according to the circumstances.
[0061] In this application, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.
[0062] In this application, a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this application, the channel region refers to the region through which current primarily flows.
[0063] In this application, the first electrode may be a drain electrode and the second electrode may be a source electrode, or vice versa. In cases where transistors with opposite polarities are used or the direction of current changes during circuit operation, the functions of the "source electrode" and "drain electrode" may be interchanged. Therefore, in this application, unless otherwise specified, the terms "source electrode" and "drain electrode" may be interchanged.
[0064] In this application, "electrical connection" or "connection" includes situations where components are connected together through an element with some electrical function, such as electrical signal connection (coupling connection, such as coupled to), or physical direct connection. There is no particular limitation on the "element with some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.
[0065] In this application, "parallel" means approximately parallel or nearly parallel. For example, the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes the angle of greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular. For example, the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes the angle of greater than 85° and less than 95°.
[0066] In this application, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."
[0067] The substrate in the embodiment of the present application can be a supporting structure, such as a silicon substrate, or a supporting structure on which other film layers or functions or circuits are already distributed. The device involved in the inventive structure of the embodiment of the present application is arranged on the main surface of the supporting structure.
[0068] In this application, the term "separated distribution" can be understood as a separate, independent distribution. Separation can be achieved by physical structural disconnection or electrical disconnection. For example, the semiconductor layer between the active channels of two transistors is modified to achieve insulation to achieve electrical separation between the two channels.
[0069] An embodiment of the present application provides a method for manufacturing a semiconductor device. Figure 1 FIG. 1 is a process flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application. Figure 1 As shown, the manufacturing method includes:
[0070] S10: providing a first substrate, wherein the first substrate has a first surface and a second surface;
[0071] S20: forming a plurality of transistors distributed in an array on the first surface, the transistors comprising a semiconductor pillar extending in a direction perpendicular to the first substrate and a gate electrode at least partially surrounding a sidewall of the semiconductor pillar, the semiconductor pillar comprising a first end surface away from the second surface and a second end surface close to the second surface, the sidewall of the semiconductor pillar being between the first end surface and the second end surface;
[0072] S30: performing processing on the second surface of the first substrate to expose at least the second end surface of the semiconductor pillar;
[0073] S40: forming a plurality of first trenches on the second surface that are recessed toward the first surface, each of the first trenches exposing a second end surface of a column of semiconductor pillars;
[0074] S50: forming a bit line in the first trench so as to contact a column of the semiconductor pillars.
[0075] The above step S40 is not necessary. For example, after step S30 is formed, a bit line can be directly formed on the second surface without digging a groove or trench.
[0076] The manufacturing method of the present invention can be used in the process flow of manufacturing semiconductor devices with vertical channel transistors (VCTs). The manufacturing method of the present invention can form the transistors first and then the bit lines, which can reduce the difficulty of manufacturing the bit lines and improve the contact performance between the bit lines and the transistors.
[0077] The row and column directions described herein correspond to the row and column directions of transistors arranged in an array, and both the row and column directions are parallel to the first surface or the second surface of the first substrate. A column of transistors includes a column of semiconductor pillars, and accordingly, the semiconductor pillars of the array-arranged transistors are also arranged in an array.
[0078] In some embodiments, forming a plurality of transistors distributed in an array on the first surface includes:
[0079] A plurality of semiconductor pillars are formed on the first surface of the first substrate. The semiconductor pillars are spaced apart from each other in row and column directions and extend in a direction perpendicular to the first surface of the first substrate. Sidewalls of adjacent semiconductor pillars are spaced apart by a first insulating layer.
[0080] The method further comprises forming a plurality of first trenches on the second surface that are recessed toward the first surface, wherein each of the first trenches exposes the second end surface of a column of semiconductor pillars, comprising:
[0081] The exposed second end surfaces of the semiconductor pillars and the first insulating layer are etched on the second surface of the first substrate to form a plurality of first trenches extending along a column direction.
[0082] In some embodiments, the manufacturing method further comprises: etching the first insulating layer between two adjacent columns of semiconductor pillars on the second surface of the first substrate to form a second trench between two adjacent bit lines on the second surface;
[0083] A first insulating layer including an air gap is formed in the second trench.
[0084] The manufacturing method of the embodiment of the present application introduces an air gap in the first insulating layer between two adjacent bit lines, which can reduce the coupling capacitance between the two adjacent bit lines and has a simple process flow.
[0085] In some embodiments, after forming the first trench and before forming a bit line in contact with the semiconductor pillar in the first trench, the manufacturing method further includes: forming a second insulating layer on the sidewall of the first trench to expose the second end surface of the semiconductor pillar at the bottom wall of the first trench; and the bit line is formed in the first trench including the second insulating layer.
[0086] In some embodiments, the manufacturing method further includes: before forming the bit line in the first trench, sequentially ion-doping the exposed second end surface of the semiconductor pillar in the first trench with germanium and phosphorus.
[0087] In some embodiments, the manufacturing method further includes: after forming the transistor, forming a capacitor connected to the transistor on a side of the transistor away from the first substrate.
[0088] The technical solution of the embodiment of the present application is further explained below through the manufacturing process of the semiconductor device of the exemplary embodiment. The "patterned etching" mentioned in this embodiment includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching, and stripping the photoresist, which is a mature preparation process in the relevant technology. The "photolithography" process mentioned in this embodiment includes coating a film layer, mask exposure and development, which is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here.
[0089] Figure 2 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a transistor and before forming a bit line; Figure 3 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after combining a first substrate with a second substrate; Figure 4 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after the second end surface of the semiconductor pillar is exposed; Figure 5A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a first trench; Figure 6 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer in a first trench; Figure 7 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application when ion doping is performed on an end face of a semiconductor pillar; Figure 8 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after a first trench is filled with a metal conductive layer; Figure 9 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a bit line; Figure 10 A schematic longitudinal cross-sectional view in a vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after the adhesion barrier layer is flush with the bit line; Figure 11 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after depositing a second insulating layer on a top surface of a bit line; Figure 12 A schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after etching away a first insulating layer between two adjacent bit lines; Figure 13 This is a schematic longitudinal cross-sectional view in the vertical direction of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application after forming a first insulating layer containing air gaps.
[0090] like Figures 2 to 13 As shown, in an exemplary embodiment, the method for manufacturing the semiconductor device may include the following processes.
[0091] S10: The first substrate 40 has a first surface 41 and a second surface 42; a transistor 20 is formed on the first surface 41, such as Figure 2 shown.
[0092] For example, step S10 may include: providing an initial substrate, patterning the initial substrate to form a Figure 2The first substrate 40 shown has a first surface 41 and a second surface 42; a plurality of transistors 20 are formed on the first surface 41 of the first substrate 40, which are spaced apart and distributed in an array along the row direction and the column direction, and the transistor 20 includes a semiconductor column 21 extending in a direction perpendicular to the first substrate 40 and a gate electrode 22 at least partially surrounding the semiconductor column 21, and a gate insulating layer (not shown in the figure) is provided between the semiconductor column 21 and the gate electrode 22, and the semiconductor column 21 includes a first end face 211 away from the second surface 42 and a second end face 212 close to the second surface 42; two adjacent transistors 20 are separated by a first insulating layer 11, and this step S10 can be understood as the side walls of the semiconductor columns of the two adjacent transistors are insulated by the first insulating layer. In this step S10, the first substrate connects the semiconductor columns.
[0093] Exemplarily, the initial substrate is an initial silicon substrate, the first substrate 40 can be a silicon substrate, and spacing grooves extending along the row direction and the column direction can be etched on one side of the silicon substrate, and the spacing grooves separate the initial silicon substrate into multiple semiconductor pillars 21, and the substrate area outside the semiconductor pillars is the first substrate, which includes two main surfaces, namely the first surface and the second surface.
[0094] Exemplarily, the trenches in the row and column directions are connected and have the same depth. The first insulating layer 11 is filled in the spacing trenches in the row and column directions, and the first insulating layer 11 surrounds the sidewalls of the semiconductor pillars and completely fills the trenches in the row and column directions.
[0095] The row direction and the column direction are both horizontal directions. For example, the row direction is parallel to the first substrate, the column direction is parallel to the first substrate, and the row direction and the column direction are perpendicular to each other.
[0096] Exemplarily, the material forming the first insulating layer may be a low-K dielectric material, ie, a dielectric material with a dielectric constant K<3.9, including but not limited to silicon oxides, such as silicon dioxide (SiO2) or other silicon-containing film layers.
[0097] S20: forming a capacitor 50 connected to the transistor 20 on a side of the transistor 20 away from the first substrate 40 . For example, the capacitor 50 may be connected to the first end surface 211 of the transistor 20 and stacked vertically with the transistor 20 on the first surface 41 of the first substrate 40 .
[0098] After the first substrate 40 provided with the transistor 20 and the capacitor 50 is inverted, the side provided with the capacitor is bonded to the second substrate 60, and the second surface 42 of the first substrate 40 is exposed and the patterning process is continued, such as Figure 3 shown.
[0099] S30: Process the second surface 42 of the first substrate 40 to expose the second end surface 212 of the semiconductor pillar 21 and the first insulating layer 11. At this time, the semiconductor pillars are not connected to each other by the substrate, but are isolated from each other by the first insulating layer. Figure 4 The processing of the second surface 42 of the first substrate 40 may be a thinning process of the first substrate, wherein the thinning process includes finally removing the substrate or retaining a portion of the substrate;
[0100] In the embodiment where the substrate is finally removed, it can be understood that the semiconductor pillar is located in the hole of the first insulating layer, and the semiconductor pillar passes through the first insulating layer on a side close to the second end surface of the semiconductor pillar.
[0101] Exemplarily, step S30 may include:
[0102] A chemical mechanical polishing (CMP) process or an etching process is used to remove a certain thickness of the second surface 42 of the first substrate 40 or remove the entire first substrate until the second end surface 212 of the semiconductor pillar 21 is exposed.
[0103] It should be noted that the formation of semiconductor columns on the first substrate can be understood as the first substrate and the semiconductor columns being two parts. The semiconductor columns are multiple semiconductor columns perpendicular to the initial first substrate formed by etching the initial first substrate. The part of the initial first substrate except for the semiconductor columns is the first substrate below the semiconductor columns. The first substrate connects the semiconductor columns, and the connection area on the semiconductor column is the second end face of the semiconductor column.
[0104] S40: etching back (etching toward the first surface) the second end surface 212 of the semiconductor pillar 21 and the first insulating layer 11 between two adjacent transistors 20 in the column direction to form a first trench 13 extending along the column direction. Figure 5 shown.
[0105] S50: Depositing a second insulating layer 12 on the inner wall (including the side wall and the bottom wall) of the first trench 13, such as Figure 6 shown.
[0106] In some embodiments of the present application, the material of the second insulating layer may be any one or more of silicon oxide (e.g., SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and silicon carbonitride (SiCN), and the material of the second insulating layer is different from that of the first insulating layer, so that when one of the first insulating layer and the second insulating layer is subsequently etched away, the first insulating layer and the second insulating layer may have different etching rates, thereby removing the desired insulating layer. For example, in this embodiment, the material of the first insulating layer may be silicon oxide, and the material of the second insulating layer may be silicon nitride.
[0107] S60: removing the second insulating layer 12 on the bottom wall of the first trench 13 to expose the second end surface 212 of the semiconductor column 21; performing ion doping on the exposed second end surface 212 of the semiconductor column 21, such as Figure 7 shown.
[0108] In some embodiments of the present application, the semiconductor pillar 21 may be a portion of an initial silicon substrate, and may be a silicon pillar;
[0109] The ion doping in step S60 may include doping with germanium (Ge) and phosphorus (P), for example, doping germanium (Ge) and phosphorus (P) in sequence. Germanium can amorphize the end faces of the silicon pillars of the single crystal silicon, so that when phosphorus is subsequently implanted, the phosphorus element is doped as much as possible on the surface of the silicon pillars.
[0110] S70: depositing an adhesion barrier layer 31 and a metal conductive layer 32 on the bottom wall of the first trench 13 and the surface of the first insulating layer 11 in sequence, wherein the adhesion barrier layer 31 and the metal conductive layer 32 together constitute the bit line BL, and the metal conductive layer 32 fills the first trench 13; planarizing the metal conductive layer 32 by a chemical mechanical polishing (CMP) process until the adhesion barrier layer 31 is exposed. At this time, the adhesion barrier layers 31 in each first trench are connected and are different regions of the same film layer, such as Figure 8 shown.
[0111] The adhesion barrier layer can prevent the metal in the metal conductive layer from reacting with the silicon pillar, and can also prevent the metal in the metal conductive layer from being oxidized by the oxygen-containing film layer (for example, the oxygen-containing first insulating layer, etc.), so it can also be called an anti-oxidation layer. The adhesion barrier layer can also enhance the adhesion between the metal conductive layer and the silicon pillar, thereby improving the bonding strength between the metal conductive layer and the silicon pillar. In some embodiments of the present application, the adhesion barrier layer can be a single layer or a multi-layer structure. For example, when the material of the bit line is tungsten, the adhesion barrier layer can be a double-layer structure formed by Ti and TiN; when the material of the bit line is copper, the adhesion barrier layer can include a double-layer structure formed by tantalum (Ta) and tantalum nitride (TaN). And TiN or TaN is in contact with the metal conductive layer.
[0112] S80: Using the adhesion barrier layer as an etching barrier layer, a portion of the metal conductive layer 32 in the first trench 13 is etched back and removed. Figure 9 shown.
[0113] S90: Etching the adhesion barrier layer 31 to remove the adhesion barrier layer 31 on the surface of the first insulating layer 11, and the adhesion barrier layer 31 in the first trench 13 is flush with the bit line, thereby obtaining a bit line BL located in the first trench 13. The sidewalls of the bit line BL are covered by the second insulating layer 12 on the sidewalls of the first trench 13, and the top surface of the bit line BL is exposed. Figure 10 shown.
[0114] S100: depositing a second insulating layer 12 in the first trench 13, and planarizing the second insulating layer 12 by a CMP process until the surface of the first insulating layer 11 between the first trenches is exposed. In this step, the top surface of the bit line BL (the side away from the bottom wall of the first trench) is covered by the second insulating layer 12. Figure 11 shown.
[0115] S110: etching and removing the first insulating layer 11 between two adjacent bit lines BL to form a second trench 15 between two adjacent bit lines BL on the second surface. The second trench 15 exposes the second insulating layer 12 on the sidewalls of the bit lines BL. Figure 12 shown.
[0116] For example, in step S80 , the first insulating layer 11 may be etched until the remaining first insulating layer 11 is flush with the semiconductor pillar 21 .
[0117] S120: Deposit the first insulating layer 11 filling the second trench 15 between two adjacent bit lines BL and covering the second insulating layer 12, and introduce an air gap 14 during the deposition of the first insulating layer 11. The air gap 14 can be achieved by rapid deposition, and the structure formed is as follows: Figure 13 shown.
[0118] An embodiment of the present application provides a semiconductor device, comprising: a plurality of transistors distributed in an array, the transistors comprising a semiconductor pillar and a gate electrode at least partially surrounding the semiconductor pillar; the semiconductor pillar comprising a first end face and a second end face; a plurality of bit lines stacked with the semiconductor pillars and connected to the second end faces of the semiconductor pillars; a first insulating layer being disposed between any adjacent semiconductor pillars.
[0119] In some embodiments, the semiconductor device further includes a plurality of first trenches extending along a column direction, the bottom walls of the first trenches exposing the second end surfaces of a column of semiconductor pillars, and the bit lines are located in the first trenches and in contact with the second end surfaces of a column of semiconductor pillars.
[0120] In some embodiments, the semiconductor device further includes a plurality of second trenches extending along a column direction, wherein the second trenches are located between any two adjacent first trenches; and the second trenches are filled with a first insulating layer containing air gaps.
[0121] In some embodiments, the semiconductor pillar is made of silicon, and the second end surface of the semiconductor pillar contains a doping material, wherein the doping material includes germanium and phosphorus.
[0122] In some embodiments, the bit line includes at least one film layer, which can be a metal layer or a metal nitride, for example, a tungsten metal layer, or a stack of a TiN layer and a tungsten metal layer. The TiN layer acts as an adhesion barrier.
[0123] like Figure 13 As shown, the semiconductor device includes: a plurality of transistors 20 and a plurality of bit lines BL;
[0124] Multiple transistors 20 are distributed in an array, each transistor including a semiconductor pillar 21 extending in a vertical direction and a gate electrode 22 at least partially surrounding the semiconductor pillar 21, with a gate insulating layer (not shown) between the semiconductor pillar 21 and the gate electrode 22, and a sidewall of the semiconductor pillar 21, a first end surface 211, and a second end surface 212;
[0125] A plurality of bit lines BL are located below the semiconductor pillars and contact the second end surfaces 212 ; the plurality of bit lines BL extend along a column direction; and each bit line BL contacts the second end surfaces 212 of a column of semiconductor pillars 21 .
[0126] Figure 13 The material of the semiconductor pillar 21 shown is silicon (single crystal silicon) or includes single crystal silicon. The semiconductor pillar 21 is formed by etching the first substrate 40 .
[0127] In some embodiments, such as Figure 13As shown, the semiconductor device further includes a plurality of first trenches 13 extending along a column direction on the second surface 42 , the bottom walls of the first trenches 13 exposing the second end faces 212 of a column of semiconductor pillars 21 , and the bit lines BL are located in the first trenches 13 and in contact with the second end faces 212 of a column of semiconductor pillars 21 .
[0128] In some embodiments, such as Figure 13 As shown, the semiconductor device further includes a plurality of second trenches 15 extending along a column direction on the second surface 42 ; the second trenches 15 are filled with a first insulating layer 11 containing air gaps 14 .
[0129] In some embodiments, such as Figure 13 As shown, a second insulating layer 12 is provided between at least a portion of the sidewall of the bit line BL and the first insulating layer 11 including the air gap 14 .
[0130] In some embodiments, the semiconductor pillar 21 is made of silicon, and one end of the semiconductor pillar 21 connected to the bit line BL contains a doping material; the doping material includes germanium, and may also include phosphorus, etc.
[0131] In some embodiments, the second end surfaces of the semiconductor pillars of a column of transistors spaced apart along the column direction are connected to the same bit line. It can be understood that multiple columns of transistors correspond one-to-one to multiple bit lines, and each bit line contacts the second end surfaces of each semiconductor pillar of the corresponding column of transistors.
[0132] In some embodiments, the bit line is connected to the second end surface of each semiconductor pillar of a corresponding column of transistors and does not contact the sidewall of the semiconductor pillar.
[0133] In some embodiments, such as Figure 13 As shown, the semiconductor device includes a memory cell, which includes the transistor and may further include a capacitor 50 .
[0134] In some embodiments, the transistor may be an access transistor, and the memory cell may further include other components, such as a capacitor in a 1T1C memory cell, or a read transistor and a storage node in a 2T0C memory cell.
[0135] In some embodiments, the transistor may be a vertical channel transistor (VCT), and the transistor may further include a gate electrode at least partially surrounding the semiconductor pillar.
[0136] In some embodiments, the semiconductor column includes a source electrode region, a channel region, and a drain electrode region in sequence, and the gate electrode surrounds the channel region.
[0137] Surrounding can be understood as partial surrounding or full surrounding. In some embodiments, the surrounding can be full surrounding, that is, the side wall of the semiconductor column located in the channel region is completely surrounded by the gate electrode, and the cross-section of the gate electrode after surrounding is a closed ring. The cross-section is intercepted along the horizontal direction. In some embodiments, the surrounding can be partial surrounding, that is, a part of the side wall of the semiconductor column located in the channel region is surrounded by the gate electrode, and the cross-section of the gate electrode after surrounding is not closed, but presents a ring shape. For example, a ring with an opening or two independent semiconductor layers. For example, the opposite side surfaces of the semiconductor column located in the channel region are surrounded by the gate electrode, and the cross-section of the gate electrode is a ring with two openings.
[0138] In some embodiments, the semiconductor device may further include a word line (WL) connected to the gate electrode of the transistor.
[0139] In some embodiments, gate electrodes of a row of transistors spaced apart along the row direction are connected to the same word line.
[0140] An embodiment of the present application further provides an electronic device, comprising a semiconductor device manufactured by the manufacturing method as described above, or comprising the semiconductor device as described above.
[0141] In some embodiments of the present application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.
[0142] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: include: providing a first substrate having a first surface and a second surface; forming a plurality of transistors distributed in an array on the first surface, the transistors comprising a semiconductor pillar extending in a direction perpendicular to the first substrate and a gate electrode at least partially surrounding the semiconductor pillar, the semiconductor pillar comprising a first end surface away from the second surface and a second end surface close to the second surface; Processing the second surface of the first substrate to expose at least the second end surface of the semiconductor pillar; A plurality of bit lines are formed on the second surface of the first substrate, parallel to the first surface of the first substrate and extending along the column direction. Each bit line corresponds to a column of the transistors, and the bit line contacts the second end surface of each semiconductor column of the corresponding column of the transistors.
2. The manufacturing method according to claim 1, characterized in that The method further comprises forming a plurality of bit lines on the second surface of the first substrate that are parallel to the first surface of the first substrate and extend along a column direction, comprising: forming a plurality of first trenches on the second surface that are recessed toward the first surface of the first substrate, wherein each of the first trenches exposes a second end surface of each semiconductor column of a column of transistors; A bit line is formed in each of the first trenches, and the bit line contacts the semiconductor pillars of a column of transistors exposed by the first trenches.
3. The manufacturing method according to claim 1, characterized in that The forming of a plurality of transistors distributed in an array on the first surface includes: The first surface of the first substrate is etched to form a plurality of semiconductor pillars spaced apart from each other in row and column directions and extending in a direction perpendicular to the first surface of the first substrate, wherein any adjacent semiconductor pillars are spaced apart by a first insulating layer.
4. The manufacturing method according to claim 2, characterized in that The processing of the second surface of the first substrate to expose at least the second end surface of the semiconductor pillar comprises: The second surface of the first substrate is subjected to chemical mechanical polishing or etching to expose the second end faces of the semiconductor pillars and the first insulating layer, wherein the semiconductor pillars are insulated from each other by the first insulating layer.
5. The manufacturing method according to claim 4, characterized in that The method further comprises forming a plurality of first trenches on the second surface that are recessed toward the first surface of the first substrate, wherein each of the first trenches exposes the second end surface of each semiconductor column of a column of transistors, comprising: The exposed second end faces of the semiconductor pillars and the first insulating layer are etched on the second surface of the first substrate to form a plurality of first trenches that are recessed toward the first surface of the first substrate and extend along a column direction within the first surface of the first substrate, wherein the bottom wall of each of the first trenches exposes the second end faces of a column of semiconductor pillars and the first insulating layer between adjacent semiconductor pillars.
6. The manufacturing method according to claim 5, characterized in that Also includes: Etching the first insulating layer between two adjacent rows of semiconductor pillars on the second surface of the first substrate to form a second trench between two adjacent bit lines on the second surface; A first insulating layer including an air gap is formed in the second trench.
7. The manufacturing method according to claim 6, characterized in that After forming the first trench and before forming a bit line in contact with the semiconductor pillar in the first trench, the method further includes: A second insulating layer is formed on the sidewalls of the first trench, and the bottom wall of the first trench exposes the second end surface of the semiconductor column; the bit line is formed in the first trench including the second insulating layer.
8. The manufacturing method according to claim 7, characterized in that The etching of the first insulating layer between two adjacent columns of semiconductor pillars on the second surface of the first substrate to form a second trench between two adjacent bit lines on the second surface includes: The first insulating layer between two adjacent rows of semiconductor pillars is etched on the second surface of the first substrate to expose the second insulating layer on the sidewalls of the first trench, thereby forming the second trench.
9. The manufacturing method according to claim 2, characterized in that: Before forming the bit line in the first trench, the method further includes: Germanium and phosphorus are sequentially used in the first trench to perform ion doping on the second end surface of the semiconductor column exposed by the first trench.
10. A semiconductor device, characterized in that: include: A plurality of transistors distributed in an array, each transistor comprising a semiconductor column and a gate electrode at least partially surrounding the semiconductor column; the semiconductor column comprising a first end surface and a second end surface; a plurality of bit lines, each bit line corresponding to a column of the transistors, the bit line being in contact with the second end surface of each semiconductor pillar of the corresponding column of the transistors; A first insulating layer is disposed between any adjacent semiconductor pillars.
11. The semiconductor device according to claim 10, wherein: Also includes: A plurality of first trenches extend along a column direction, wherein bottom walls of the first trenches expose the second end surfaces of a column of the semiconductor pillars, and the bit lines are located in the first trenches and contact the second end surfaces of the column of the semiconductor pillars.
12. The semiconductor device according to claim 11, wherein Also includes: a plurality of second grooves extending along a column direction, wherein the second grooves are located between any two adjacent first grooves; The second trench is filled with a first insulating layer, and the first insulating layer in the second trench contains an air gap.
13. The semiconductor device according to any one of claims 10 to 12, characterized in that The semiconductor pillar is made of silicon. The second end surface of the semiconductor pillar contains a doping material, and the doping material includes germanium and phosphorus.
14. The semiconductor device according to any one of claims 10 to 12, wherein: The material of the bit line includes metal.
15. An electronic device, characterized in that: A semiconductor device comprising any one of claims 10 to 14.