Semiconductor structure, forming method thereof and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure, a forming method thereof and electronic equipment. The forming method of the semiconductor structure comprises the following steps: providing a substrate; the substrate comprises an array area, and the array area comprises a plurality of active columns which are arranged in the first direction and the second direction and extend in the third direction; the active column comprises a channel structure, and an initial drain electrode and an initial source electrode which are located on the two sides of the channel structure in the third direction; etching a part of the initial drain electrode in the active column along the back surface of the substrate to form a first etching groove; the back surface is the surface of one side where the initial drain electrode is located; forming a first doping structure in the first etching groove; the first doped structure and the remaining initial drain form a drain in the active column.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and is related to, but not limited to, a semiconductor structure and a method for forming the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the layout density of 2D memory chips has reached its limit. Through stacked array transistor (SAT) and wafer-on-wafer (WOW) technology, the performance and cost of logic chip and memory chip architecture can be greatly improved.

[0003] In the related art, before forming the buried bit line in the memory chip, the active pillar needs to be ion doped and annealed to form the source and drain doping regions; however, on the one hand, when the active pillar is doped, the doped ions have a tail, that is, the ions extend to the area that does not need to be doped, thereby introducing defects; on the other hand, during annealing, amorphous silicon needs to be deposited on the surface of the active pillar for protection, and ammonia is passed through the process when depositing the amorphous silicon, so that there is a hydrogen-containing interface layer between the interface of the active pillar and the amorphous silicon, which makes it difficult to conduct heat from the hydrogen-containing interface layer, causing the active pillar to easily expand and protrude in volume after absorbing heat, thereby squeezing and breaking the formed bit line. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, the method comprising:

[0006] Providing a substrate; the substrate includes an array region, the array region includes a plurality of active pillars arranged along a first direction and a second direction and extending along a third direction; the active pillars include a channel structure, and an initial drain and an initial source located on both sides of the channel structure along the third direction;

[0007] Etching a portion of the initial drain electrode in the active pillar along the back surface of the substrate to form a first etched groove; the back surface is the surface on the side where the initial drain electrode is located;

[0008] forming a first doping structure in the first etched groove; the first doping structure and the remaining initial drain constitute the drain in the active pillar;

[0009] The first direction and the second direction intersect and are parallel to the plane where the base is located; and the third direction is perpendicular to the plane where the base is located.

[0010] In some embodiments, the first etched groove is connected to the back side of the substrate; and a first doping structure is formed in the first etched groove, including:

[0011] forming an initial first doping structure in the first etched groove and the exposed back surface of the substrate;

[0012] The initial first doping structure located on the back side of the substrate is removed, and the remaining initial first doping structure located in the first etched groove constitutes the first doping structure.

[0013] In some embodiments, forming an initial first doping structure in the first etched groove and the exposed surface of the substrate includes:

[0014] Performing deposition and doping treatments simultaneously on the first etched groove and the exposed back surface of the substrate to form a first doping material layer;

[0015] The first doping material layer is melted and recrystallized to form the initial first doping structure.

[0016] In some embodiments, the first doping material layer is made of amorphous silicon with predetermined ion doping.

[0017] In some embodiments, the base further includes a peripheral region, the peripheral region including a substrate, and a nitride layer and a metal layer sequentially located on a front surface of the substrate;

[0018] While forming the first doping structure, a reflective layer is formed on the back side of the substrate; the front side is a surface along the third direction opposite to the back side.

[0019] In some embodiments, before forming the first etched groove, the method further includes:

[0020] performing heavy doping on a portion of the initial source electrode along the front surface of the substrate to form a second doping structure; or

[0021] Etching a portion of the initial source electrode along the front surface of the substrate to form a second etched groove, and forming the second doping structure in the second etched groove;

[0022] The front side is a surface opposite to the back side; the second doping structure and the remaining initial source constitute the source in the active column.

[0023] In some embodiments, the second etched groove is connected to the front surface of the substrate; and forming the second doping structure in the second etched groove includes:

[0024] Performing deposition and doping treatments simultaneously on the second etched groove and the exposed front surface of the substrate to form a second doping material layer;

[0025] melting and recrystallizing the second doping material layer to form an initial second doping structure;

[0026] The initial second doping structure located on the front surface of the substrate is removed, and the remaining initial second doping structure located in the second etched groove constitutes the second doping structure.

[0027] In some embodiments, the method further comprises:

[0028] The initial drain and the initial source in the active column are lightly doped; wherein the ion concentration injected by the light doping is lower than the ion concentration in the first doping structure and the second doping structure.

[0029] In some embodiments, the method further comprises:

[0030] forming a gate structure located on the surface of the channel structure; the gate structure includes a gate dielectric layer and a gate metal layer, and a plurality of the gate metal layers arranged along the first direction are interconnected to form a word line;

[0031] A capacitor structure is formed, which extends along the third direction and is connected to a surface of the source electrode away from the channel structure.

[0032] In some embodiments, the method further comprises:

[0033] A bit line structure is formed, which extends along the second direction and is connected to a surface of the drain electrode away from the channel structure.

[0034] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0035] A substrate; the substrate includes an array region, the array region includes a plurality of active pillars arranged along a first direction and a second direction and extending along a third direction; the active pillar includes a channel structure, and a drain and a source located on both sides of the channel structure along the third direction;

[0036] The first direction and the second direction intersect and are parallel to the plane where the base is located; and the third direction is perpendicular to the plane where the base is located.

[0037] In some embodiments, the drain includes an initial drain and a first doping structure located on a surface of the initial drain away from the channel structure; the ion concentration in the initial drain is less than the ion concentration in the first doping structure;

[0038] The source includes an initial source and a second doping structure located on a surface of the initial source away from the channel structure; the ion concentration in the initial source is lower than the ion concentration in the second doping structure.

[0039] In some embodiments, the substrate further comprises:

[0040] a peripheral region, the peripheral region including a substrate, a nitride layer and a metal layer sequentially located on a front surface of the substrate, and a reflective layer located on a back surface of the substrate;

[0041] The back surface is the surface on the side where the drain is located; and the front surface is the surface along the third direction relative to the back surface.

[0042] In some embodiments, the semiconductor structure further comprises:

[0043] a gate structure located on the surface of the channel structure; the gate structure comprising a gate dielectric layer and a gate metal layer, wherein a plurality of the gate metal layers arranged along the first direction are interconnected to form a word line;

[0044] a capacitor structure extending along the third direction and connected to a surface of the source electrode away from the channel structure;

[0045] The bit line structure extends along the second direction and is connected to a surface of the drain electrode away from the channel structure.

[0046] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising a processing device; and a memory device electrically connected to the processing device, wherein the memory device comprises a semiconductor structure as described in any one of the above embodiments.

[0047] An embodiment of the present disclosure provides a semiconductor structure, a method for forming the same, and an electronic device; wherein the method for forming the semiconductor structure comprises: providing a substrate; the substrate comprises an array area, the array area comprises a plurality of active pillars arranged along a first direction and a second direction and extending along a third direction; the active pillar comprises a channel structure, and an initial drain and an initial source located on both sides of the channel structure along the third direction; along the back side of the substrate, a portion of the initial drain in the active pillar is etched to form a first etched groove; the back side is the surface on the side where the initial drain is located; in the first etched groove, a first doping structure is formed; the first doping structure and the remaining initial drain constitute the drain in the active pillar.

[0048] Here, the first doping structure is formed in the first etched groove after the first etched groove is formed; that is, the first doping structure is formed in the first etched groove by doping while deposition. This prevents the ions in the first doping structure from producing a tailing effect, thereby preventing defects from being introduced into other areas, resulting in better performance of the semiconductor structure. Furthermore, the introduction of ammonia gas is avoided during the formation of the first doping structure, thereby eliminating a hydrogen-containing interface layer between the bit line and the first doping structure (i.e., the active pillar). This allows for even heat diffusion and prevents localized stress from causing bit line breakage. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0050] Figure 1 It is a structural schematic diagram of a semiconductor structure in the related art;

[0051] Figure 2 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0052] Figures 3 to 14 A schematic diagram of a structure during the formation of a semiconductor structure provided by an embodiment of the present disclosure;

[0053] Figure 15 A schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0054] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0055] In the following description, numerous details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0056] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0057] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0058] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] Currently, in the SAT WoW vertical channel process, the steps for forming the memory chip 10 are as follows: Figure 1 The active pillars 11, word lines 12 and capacitor structures 13 shown are located in the substrate; the memory chip 10 is then flipped over, and ions are injected into the active pillars 11 on the back side of the memory chip (the upper surface along the Z-axis direction in the figure) and activated by heat treatment to form source-drain doped regions; finally, bit lines (not shown) are formed on the surface of the source-drain doped regions.

[0060] However, on the one hand, when the active pillar 11 is doped, the doped ions have a tail, that is, the ions extend to the area where doping is not required, thereby introducing defects; on the other hand, during heat treatment, amorphous silicon needs to be deposited on the surface of the active pillar for protection, and when amorphous silicon is deposited by processes such as Chemical Vapor Deposition (CVD), ammonia is passed through the process, so that there is a hydrogen-containing interface layer between the active pillar 11 and the amorphous silicon, thereby generating a Marangoni capillary effect, making it difficult to conduct heat from the hydrogen-containing interface layer, and then making the active pillar easy to expand and protrude in volume after absorbing heat, and ultimately causing the bit line to be squeezed and broken.

[0061] Furthermore, during the heat treatment process, even with conventional RTA (seconds) to Flash annealing (milliseconds), crystallization of the dielectric material (e.g., HK material) in the capacitor structure 13 cannot be avoided, thereby increasing leakage in the capacitor structure 13. Furthermore, due to differences in heat absorption between the metal film layers of different patterns in the array region and the peripheral region of the memory chip 10, localized thermal stress can be excessive, leading to delamination and damage of the metal film layer.

[0062] Based on this, the embodiments of the present disclosure provide a semiconductor structure and a method for forming the same, and an electronic device. The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0063] Before introducing the embodiments of the present disclosure, let's first define the three directions that may be used in describing a three-dimensional structure in the following embodiments. These three directions may include a first (X-axis), a second (Y-axis), and a third (Z-axis). The third direction may be a direction perpendicular to the plane in which the semiconductor structure resides. The X-axis and Y-axis directions are two perpendicular directions on the plane in which the semiconductor structure resides, where the X-axis direction is the direction in which the word lines extend.

[0064] The present disclosure provides a method for forming a semiconductor structure 100. Figure 2 A schematic flow chart of a method for forming a semiconductor structure 100 according to an embodiment of the present disclosure is shown in FIG. Figure 2 As shown, the method for forming the semiconductor structure 100 includes the following steps:

[0065] Step S110, providing a substrate; the substrate includes an array area, the array area includes a plurality of active pillars arranged along the X-axis direction and the Y-axis direction and extending along the Z-axis direction; the active pillars include a channel structure, and an initial drain and an initial source located on both sides of the channel structure along the Z-axis direction.

[0066] Here, the array region is used to form a memory array of a semiconductor structure, such as a DRAM array composed of transistors, bit line structures, and capacitor structures.

[0067] In the disclosed embodiment, the material of the active pillar may be a semiconductor material such as silicon, germanium, or a metal oxide material such as indium gallium zinc oxide (IGZO) or indium tin oxide (ITO).

[0068] In the disclosed embodiments, the active pillars extend along the Z-axis, meaning they form vertical transistors. This allows for a higher density of memory cells, reducing the size of the memory cells while increasing their storage density. Furthermore, the regions where the initial drain and source electrodes are located are also where the subsequently formed source and drain electrodes are located.

[0069] Step S120 , etching a portion of the initial drain in the active pillar along the back surface of the substrate to form a first etched groove; the back surface is the surface on the side where the initial drain is located.

[0070] The etching process in the embodiments of the present disclosure includes but is not limited to: dry etching, wet etching and a combination thereof.

[0071] Step S130 , forming a first doping structure in the first etched groove; the first doping structure and the remaining initial drain constitute the drain in the active pillar.

[0072] Furthermore, the first doping structure can be P-type doped or N-type doped according to the type of transistor constructed; for example, in a P-type metal oxide semiconductor (P-Metal-Oxide-Semiconductor, PMOS), the first doping structure can be doped with Group III elements such as boron, gallium, and indium; for example, in an N-type metal oxide semiconductor (N-Metal-Oxide-Semiconductor, NMOS), the first doping structure can be doped with Group V elements such as phosphorus, antimony, and arsenic.

[0073] The semiconductor structure involved in the embodiments of the present disclosure is at least a portion of a final device structure that will be used in subsequent manufacturing processes. Here, the final device may be a memory, such as a DRAM (Dynamic Random Access Memory), or other memory chips or processing chips that include DRAM memory cells.

[0074] In the disclosed embodiment, the first doping structure is formed in the first etched groove after the first etched groove is formed; that is, the first doping structure is formed in the first etched groove by a deposition-as-doping method. As a result, the ions in the first doping structure do not produce a tailing effect, thereby not introducing defects in other areas, resulting in better performance of the semiconductor structure. Furthermore, the introduction of ammonia gas can be avoided during the formation of the first doping structure, thereby eliminating a hydrogen-containing interface layer between the bit line and the first doping structure (i.e., the active pillar). This allows heat to diffuse evenly, preventing localized stress from causing bit line breakage.

[0075] Figures 3 to 14 This is a schematic diagram of the structure of the semiconductor structure during the formation process provided by the embodiment of the present disclosure. Figures 3 to 14 The formation process of the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0076] First, execute step S110 to provide Figure 3 The substrate 110 is shown; the substrate 110 includes an array area A, the array area A includes a plurality of active pillars 111 arranged along the X-axis direction and the Y-axis direction and extending along the Z-axis direction; the active pillar 111 includes a channel structure 1111, and an initial drain 1112 and an initial source 1113 located on both sides of the channel structure 1111 along the Z-axis direction.

[0077] In the embodiment of the present disclosure, first, the following is provided: Figure 3 The substrate 112 is shown; the substrate 112 may be a silicon substrate, or may include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), etc.

[0078] Here, the substrate 112 includes an array area A and a peripheral area (not shown); wherein the array area is used to form a storage array of a semiconductor structure, such as a DRAM array composed of transistors, bit line structures and capacitor structures; the peripheral area is used to form peripheral circuits, such as word line drivers, sense amplifiers and other structures.

[0079] In the embodiment of the present disclosure, an initial active layer (not shown) can be formed on the surface of the array region A in the substrate 112. The initial active layer is then etched to form a plurality of active pillars 111 arranged along the X-axis and the Y-axis and extending along the Z-axis. In other embodiments, the active pillars 111 can also be formed by etching the substrate 112.

[0080] In some embodiments, the method for forming the semiconductor structure 100 further includes: performing a light doping process on the initial drain 1112 and the initial source 1113 in the active pillar 111 .

[0081] During implementation, ion implantation can be performed directly on the initial drain 1112 and the initial source 1113 in the active column 111; alternatively, after forming the initial active layer, ion implantation can be performed on the bottom and top of the initial active layer along the Z-axis direction (i.e., the area where the initial drain 1112 and the initial source 1113 are located); in the embodiment of the present disclosure, the order of light doping treatment is not limited.

[0082] Among them, ion implantation can be achieved through processes such as thermal diffusion and plasma doping. The energy and dose used in the ion implantation process and the type of implanted ions can be determined according to the type of transistor to be formed. For example, the ions implanted in PMOS can be group III elements such as boron, gallium, and indium; the ions implanted in NMOS can be group V elements such as phosphorus, antimony, and arsenic.

[0083] In the embodiment of the present disclosure, by lightly doping the initial drain 1112 and the initial source 1113 , leakage of the semiconductor structure can be reduced, thereby increasing the threshold voltage of the transistor and further improving the performance of the semiconductor structure.

[0084] In some embodiments, after forming the active pillar 111, the method for forming the semiconductor structure 100 further includes: forming a substrate on the surface of the channel structure 1111. Figure 3 The gate structure 113 shown includes a gate dielectric layer 1131 and a gate metal layer 1132 . A plurality of gate metal layers 1132 arranged along the X-axis are interconnected to form word lines.

[0085] In the embodiment of the present disclosure, the material of the gate dielectric layer 1131 can be silicon oxide or other suitable materials; the material of the gate metal layer 1132 can be any material with good conductive properties, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

[0086] The deposition processes involved in the embodiments of the present disclosure include but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD) and their combinations.

[0087] In the disclosed embodiment, the active pillar 111 and the corresponding gate structure 113 can form a transistor. The gate structure 113 can control the conductivity of the channel structure 1111, thereby allowing current to flow between a subsequently formed source, the channel structure 1111, and a subsequently formed drain, controlled by the gate structure 113.

[0088] In the embodiment of the present disclosure, after forming the gate structure 113, the method for forming the semiconductor structure further includes forming a first isolation structure 114 located on the surface of the gate structure 113 (i.e., between the initial source electrodes 1113). The material of the first isolation structure 114 can be silicon oxide, silicon nitride, or silicon oxynitride.

[0089] In some embodiments, the method for forming a semiconductor structure further includes: heavily doping the initial source 1113 to form a second doping structure 140; the second doping structure 140 and the remaining initial source 1113 constitute a source 141; in implementation, the second doping structure 140 can be formed by the following two methods:

[0090] The first method is to perform heavy doping on a portion of the initial source 1113 along the front surface of the substrate 110 to form a second doping structure 140 .

[0091] In the embodiment of the present disclosure, the front surface of the substrate 110 refers to the surface on the side of the initial source 1113 , and the back surface of the substrate 110 refers to the surface on the side of the initial drain 1112 .

[0092] When implementing, please refer to Figure 4 Ions are implanted into the surface of the initial source 1113 exposed by the active pillar 111, wherein the depth of the ion implantation is less than the dimension of the initial source 1113 along the Z-axis. The ion implantation can be achieved through processes such as thermal diffusion and plasma doping. The energy and dose used in the ion implantation process, as well as the type of implanted ions, can be determined based on the type of transistor to be formed. Specifically, the second doped structure 140 can have the same type of doping as the initial source 1113, and the ion doping concentration in the second doped structure 140 is greater than the ion doping concentration in the initial source 1113.

[0093] Here, after the ion implantation, a high-temperature annealing process may be further included, so as to repair the lattice damage caused by the ion implantation and activate the ion-implanted elements.

[0094] The second method is to etch a portion of the initial source 1113 along the front surface of the substrate 110 to form a second etched groove 121, and form a second doping structure 140 in the second etched groove 121. Here, the second method includes the following steps S11 and S13.

[0095] Step S11, please refer to Figure 5 , etching part of the initial source 1113 to form a second etched groove 121; wherein the second etched groove 121 is connected to the front surface of the substrate 110, and the depth of the second etched groove 121 is smaller than the size of the initial source 1113 along the Z-axis direction.

[0096] Step S12, please refer to Figure 6 Deposition and doping are performed simultaneously on the second etched groove 121 and the exposed front surface of the substrate 110 to form a second doping material layer; the second doping material layer is melted and recrystallized to form an initial second doping structure 140a. The initial second doping structure 140a completely covers the front surface of the substrate.

[0097] In the embodiment of the present disclosure, the second doping material layer is made of amorphous silicon doped with predetermined ions. The predetermined ions are of the same type as the ions doped in the initial source 1113 , and the concentration of the predetermined ions is greater than the concentration of the ions doped in the initial source 1113 .

[0098] Here, deposition and doping can be performed simultaneously through the furnace tube process to form a second doping material layer, so that the preset ions are only located in the second doping material layer. That is to say, compared with doping by ion implantation, doping through the furnace tube process can avoid the tailing effect of the preset ions, thereby improving the performance of the semiconductor structure.

[0099] In addition, since hydrogen-containing gas is not used in the furnace tube process, no hydrogen-containing interface layer is generated, so that the subsequently formed source electrode 141 (ie, active pillar) has good thermal conductivity and reduces the generation of thermal stress.

[0100] In the disclosed embodiment, the second doping material layer can be melted and recrystallized by pulse laser annealing (PLA); wherein, the pulse laser annealing can be nanosecond (ns) level annealing using a 532 nanometer (nm) ultrashort pulse nanosecond laser; here, the nanosecond level ultrashort pulse laser instantly generates a high temperature of about 1400 to 1600°C, with an absorption depth of about 50 to 100 nm, and the temperature decreases step by step from the surface layer, the time is short and the depth is controllable.

[0101] Specifically, pulsed laser annealing is performed by providing pulsed laser light from a laser, and setting a suitable delay between pulses to allow heat to diffuse to the desired depth, thereby completely melting the second doping material layer and eliminating voids. The energy density of pulsed laser annealing is 0.01 to 0.5 J / cm 2 The pulse is 10ns to 1000ns, the delay time is 1ns to 1000ns, and the wavelength is 193nm to 980nm; for example, the wavelength is 532nm. The laser crystal includes but is not limited to YAG crystal.

[0102] The second doping material layer (eg, amorphous silicon) is instantaneously melted by pulsed laser annealing, thereby activating the doped elements in the initial second doping structure 140 a and reducing the generation of lattice defects.

[0103] Step S13, please refer to Figure 7 , the initial second doping structure 140 a located on the front surface of the substrate 110 is removed, and the remaining initial second doping structure 140 a located in the second etched groove 121 constitutes the second doping structure 140 .

[0104] In the embodiment of the present disclosure, the initial second doping structure 140 a may be etched by chemical mechanical polishing (CMP), dry etching technology, or wet etching technology until the front surface of the substrate 110 (ie, the first isolation structure 114 ) is exposed.

[0105] In some embodiments, please refer to Figure 8 After forming the source electrode 141, the method for forming the semiconductor structure further includes forming a capacitor structure 150 extending along the Z-axis direction and connected to the surface of the source electrode 141 on a side away from the channel structure 1111. Here, forming the capacitor structure 150 includes the following steps S21 and S23.

[0106] Step S21, please continue to refer to Figure 8 , forming a support structure 160 and a second isolation structure 115 located between the support structures 160.

[0107] In the disclosed embodiment, support structure 160 and second isolation structure 115 are used to support the subsequently formed capacitor structure, preventing the capacitor structure from collapsing and improving the stability of the formed semiconductor structure. Furthermore, they can isolate adjacent capacitor structures and reduce leakage current. Support structure 160 can be made of silicon nitride or silicon carbonitride; second isolation structure 115 can be made of silicon oxide, silicon nitride, or silicon oxynitride.

[0108] Step S22, please continue to refer to Figure 8 , the support structure 160 and the second isolation structure 115 are etched to form a plurality of third etched grooves (not shown) arranged along the X-axis direction and the Y-axis direction and extending along the Z-axis direction; each third etched groove exposes the surface of the corresponding source 141.

[0109] In step S23, a lower electrode, a dielectric layer, and an upper electrode are sequentially formed in the third etched groove; the lower electrode, the dielectric layer, and the upper electrode together constitute the capacitor structure 150. The materials of the lower electrode and the upper electrode may include metal nitride or metal silicide, for example, titanium nitride. The material of the dielectric layer may include a high-K dielectric material, for example, one or any combination of lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiOx), or zirconium oxide (ZrO2).

[0110] In the embodiment of the present disclosure, after forming the capacitor structure 150, the method for forming the semiconductor structure further includes connecting a carrier wafer 170 to the surface of the capacitor structure 150, and Figure 8 The structure shown is flipped so that the back of the substrate faces upward, forming a Figure 9 The structure shown.

[0111] In this disclosure, please refer to Figure 10 The substrate 112 may be etched by chemical mechanical polishing (CMP), dry etching technology, or wet etching technology until the initial drain 1112 is exposed.

[0112] Next, step S120 is performed to etch a portion of the initial drain 1112 in the active pillar 111 along the back surface of the substrate 110 to form a first etched groove 120 ; the back surface is the surface on the side where the initial drain 1112 is located.

[0113] In this disclosure, please refer to Figure 11 , a portion of the initial drain 1112 is etched to form a first etched groove 120; wherein the first etched groove 120 is connected to the back side of the substrate 110, and the depth of the first etched groove 120 is smaller than the size of the initial drain 1112 along the Z-axis direction.

[0114] Finally, step S130 is performed to form a first doping structure 130 in the first etched groove 120 ; the first doping structure 130 and the remaining initial drain 1112 constitute a drain 131 in the active pillar 111 .

[0115] In some embodiments, step S130 includes: step S131 and step S132.

[0116] Step S131, please refer to Figure 12 An initial first doping structure 130 a is formed in the first etched groove 120 and the exposed back surface of the substrate 110 .

[0117] During implementation, deposition and doping are simultaneously performed on the first etched groove 120 and the exposed back surface of the substrate 110 to form a first doping material layer (not shown). The first doping material layer is melted and recrystallized to form an initial first doping structure 130a. The initial first doping structure 130a completely covers the back surface of the substrate.

[0118] In the embodiment of the present disclosure, the first doping material layer is made of amorphous silicon doped with predetermined ions. The predetermined ions are of the same type as the ions doped in the initial drain 1112 , and the concentration of the predetermined ions is greater than the concentration of the ions doped in the initial drain 1112 .

[0119] Here, deposition and doping can be performed simultaneously through the furnace tube process to form a first doping material layer, so that the preset ions are only located in the first doping material layer. That is to say, compared with doping by ion implantation, doping through the furnace tube process can avoid the tailing effect of the preset ions, thereby avoiding the introduction of defects in areas where doping is not required, and improving the performance of the semiconductor structure.

[0120] In addition, since hydrogen-containing gas is not used in the furnace tube process, no hydrogen-containing interface layer is generated, so that the subsequently formed drain 131 (ie, active pillar) has good thermal conductivity and reduces the generation of thermal stress.

[0121] In the disclosed embodiment, the first doping material layer can be melt-recrystallized by pulsed laser annealing. The pulsed laser annealing can be performed using a 532 nanometer (nm) ultrashort pulse nanosecond laser at the nanosecond (ns) level. Here, the nanosecond ultrashort pulse laser instantly generates a high temperature of approximately 1400-1600°C, with an absorption depth of approximately 50-100 nm. The temperature decreases gradually from the surface layer, with a short duration and controllable depth.

[0122] Specifically, pulsed laser annealing is performed by providing pulsed laser light from a laser, and setting a suitable delay between pulses to allow heat to diffuse to the desired depth, thereby completely melting the first doped material layer and eliminating voids. The energy density of pulsed laser annealing is 0.01 to 0.5 J / cm 2 The pulse is 10ns to 1000ns, the delay time is 1ns to 1000ns, and the wavelength is 193nm to 980nm; for example, the wavelength is 532nm. The laser crystal includes but is not limited to YAG crystal.

[0123] Here, pulsed laser annealing is used to instantaneously melt the first doping material layer (e.g., amorphous silicon), thereby activating the doped elements in the initial first doping structure 130a while reducing the generation of lattice defects. Furthermore, compared to the annealing step in conventional processes, the pulsed laser annealing in the disclosed embodiment not only improves the laser energy absorption rate, thereby increasing the doping activation rate, but also reduces heat transfer to the capacitor structure 150, preventing crystallization of the dielectric layer in the capacitor structure, resulting in a higher yield rate for the semiconductor structure.

[0124] Step S131, please refer to Figure 13 , the initial first doping structure 130 a located on the back side of the substrate 110 is removed, and the remaining initial first doping structure 130 a located in the first etched groove 120 constitutes the first doping structure 130 .

[0125] In the embodiment of the present disclosure, the initial first doping structure 130 a may be etched by chemical mechanical polishing, dry etching technology, or wet etching technology until the back side of the substrate 110 is exposed.

[0126] In some embodiments, please refer to Figure 14 The base 110 further includes a peripheral region B, which includes a substrate 112, and a nitride layer 181 and a metal layer 182 sequentially located on the front side of the substrate 112; while forming the first doping structure 130, a reflective layer 182 is formed on the back side of the substrate.

[0127] In the disclosed embodiment, metal layer 182 may constitute metal wiring located in peripheral region B; nitride layer 181 is used to isolate metal layer 182 from substrate 112 to prevent leakage or short circuits; metal layer 182 may be made of tungsten. It is understood that the front surface of substrate 112 is the front surface of base 110, i.e., nitride layer 181 and metal layer 182 are located on the same side as capacitor structure 150.

[0128] In the embodiment of the present disclosure, a reflective layer 182 is formed on the back side of the substrate while the first doping structure 130 is formed; that is, the reflective layer 182 and the first doping structure 130 are formed through the same step, so that the material of the reflective layer 182 can also be amorphous silicon with preset ion doping.

[0129] In the embodiment of the present disclosure, the thickness of the reflective layer 182 is within a range of 10 to 150 nm or other thicknesses with relatively high periodic absorption rates. Since the extinction coefficient of amorphous silicon is 0.764, the surface laser absorption rate can be increased by providing the reflective layer 182, thereby reducing damage to the substrate surface material and the amount of laser absorption by the metal layer 182, thereby preventing the metal layer 182 from peeling off during the annealing process. In addition, in the peripheral region B, the stack composed of the reflective layer 182, the substrate 112, and the nitride layer 181 can enhance the reflection of the laser and further reduce the amount of laser absorption by the metal layer 182 below the stack, thereby achieving the goal of activating the source and drain doping ions and solving the problem of stress deformation and shedding caused by the high heat absorption of the metal layer 182. In other embodiments, the reflective layer 182 can also be made of other suitable materials, such as silicon nitride.

[0130] In related art, due to the different pattern densities in array region A and peripheral region B, active pillars in array region A are prone to protrusion defects, while metal layer 182 in peripheral region B experiences transient high-temperature expansion and contraction upon cooling, causing shedding. In the disclosed embodiments, the provision of reflective layer 182 and first doped structure 130 (i.e., amorphous silicon with predetermined ion doping) enhances laser energy absorption and heat conduction after cooling, while reducing laser energy to prevent surface damage caused by excessive heat accumulation, thereby reducing shedding damage caused by excessive local thermal stress.

[0131] In some embodiments, after forming the drain 131 , the method for forming the semiconductor structure further includes forming a bit line structure (not shown) extending along the Y-axis direction and connected to a surface of the drain 131 away from the channel structure 1111 .

[0132] In the embodiment of the present disclosure, the material of the bit line structure includes: tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium nitride (TiN), polysilicon or any combination thereof.

[0133] In the embodiment of the present disclosure, the method for forming the semiconductor structure further includes: removing the carrier wafer 170 ; specifically, the carrier wafer 170 may be removed after the semiconductor structure 100 is bonded to another chip (eg, a logic chip).

[0134] In summary, in the embodiment of the present disclosure, amorphous silicon with preset ion doping (e.g., P-type doped amorphous silicon) is deposited on the back side of the substrate through a furnace tube process; thus, when forming the first doping structure 130 in the drain 131, the tailing effect of the doped ions in the first doping structure 130 can be avoided. The amorphous silicon is melted and recrystallized by pulsed laser annealing; thus, a laser provides pulsed laser light, and a suitable delay is set between the pulsed laser light to allow the heat to diffuse to the expected depth, so that the amorphous silicon in the channel is completely melted to eliminate voids. The energy density of ultrashort pulse annealing is 0.01 to 0.5 J / cm2 , the pulse is 10ns~1000ns, the delay time is 1ns~1000ns, the wavelength includes but is not limited to 532nm, the optional range is 193nm~980nm, and the laser crystal includes but is not limited to YAG crystal.

[0135] In addition, the present disclosure also provides a semiconductor structure 100, please refer to Figure 13 The semiconductor structure 100 includes: a substrate 110; the substrate 110 includes an array area A, the array area A includes a plurality of active pillars 111 arranged along the X-axis direction and the Y-axis direction and extending along the Z-axis direction; the active pillar 111 includes a channel structure 1111, and a drain 131 and a source 141 located on both sides of the channel structure 1111 along the Z-axis direction.

[0136] In some embodiments, please refer to Figure 13 The drain 131 includes an initial drain 1112 and a first doping structure 130 located on the surface of the initial drain 1112 away from the channel structure 1111; the ion concentration in the initial drain 1112 is less than the ion concentration in the first doping structure 130; the source 141 includes an initial source 1113 and a second doping structure 140 located on the surface of the initial source 1113 away from the channel structure 1111; the ion concentration in the initial source 1113 is less than the ion concentration in the second doping structure 140.

[0137] In the disclosed embodiment, the first doping structure 130 and the second doping structure 140 are made of amorphous silicon with predetermined ion doping. The drain 131 (i.e., the initial drain 1112 and the first doping structure 130) and the source 141 (i.e., the initial source 1113 and the second doping structure 140) can be doped with Group III elements such as boron, gallium, and indium. Alternatively, the drain 131 and the source 141 can be doped with Group V elements such as phosphorus, antimony, and arsenic.

[0138] In the embodiment of the present disclosure, since the ions in the first doping structure do not produce a tailing effect during the formation of the first doping structure, that is, the ions do not extend to areas that do not require doping, defects are not introduced in other areas, resulting in better performance of the semiconductor structure.

[0139] In some embodiments, please refer to Figure 13 The semiconductor structure 100 further includes: a gate structure 113 located on the surface of the channel structure 1111; the gate structure 113 includes a gate dielectric layer 1131 and a gate metal layer 1132, and a plurality of gate metal layers 1132 arranged along the X-axis direction are interconnected to form a word line.

[0140] In the disclosed embodiment, the active pillar 111 and the corresponding gate structure 113 can form a transistor. The gate structure 113 can control the conductivity of the channel structure 1111, thereby allowing current to flow between a subsequently formed source, the channel structure 1111, and a subsequently formed drain, controlled by the gate structure 113.

[0141] In some embodiments, please refer to Figure 13 The semiconductor structure 100 further includes a capacitor structure 150 extending along the Z-axis and connected to the surface of the source 141 on a side away from the channel structure 1111. The support structure 160 and the second isolation structure 115 are disposed outside the capacitor structure to support the capacitor structure 150 and prevent collapse of the capacitor structure 150, thereby improving the stability of the formed semiconductor structure.

[0142] In some embodiments, please refer to Figure 13 The semiconductor structure 100 further includes: forming a first isolation structure 114 located on the surface of the gate structure (ie, between the initial source electrodes 1113 ) for isolating adjacent active pillars 111 .

[0143] In some embodiments, please refer to Figure 13 The semiconductor structure 100 further includes a bit line structure (not shown) extending along the Y-axis direction and connected to the surface of the drain 131 away from the channel structure 1111 .

[0144] In some embodiments, please refer to Figure 14 The base 110 also includes: a peripheral area B, the peripheral area B includes a substrate 112, a nitride layer 181 and a metal layer 182 located on the front side of the substrate 112, and a reflective layer 183 located on the back side of the substrate; wherein the back side is the surface on the side where the drain 131 is located; the front side is the surface opposite to the back side along the Z-axis direction.

[0145] In the embodiment of the present disclosure, the thickness of the reflective layer 182 is within a range of 10 to 150 nm or other thicknesses with a relatively high periodic absorption rate. Since the extinction coefficient of amorphous silicon is 0.764, the reflective layer 182 can be provided to increase the surface laser absorption rate during the formation of the semiconductor structure, thereby reducing damage to the substrate surface material and the amount of laser absorption by the metal layer 182, thereby preventing the metal layer 182 from peeling off during the annealing process. In addition, in the peripheral region B, the stack composed of the reflective layer 182, the substrate 112, and the nitride layer 181 can enhance the reflection of the laser and further reduce the amount of laser absorption by the metal layer 182 below the stack; thereby achieving the goal of activating the source and drain doping ions and solving the problem of stress deformation and shedding caused by the high heat absorption of the metal layer 182.

[0146] The semiconductor structure provided in the embodiment of the present disclosure is similar to the formation method of the semiconductor structure provided in the above embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above embodiment for understanding, and no further details will be given here.

[0147] The present disclosure also provides an electronic device, Figure 15 A schematic diagram of the structure of an electronic device 200 provided in an embodiment of the present disclosure is shown in FIG. Figure 15 As shown, the electronic device 200 includes: a processor 210; and any semiconductor structure 100 in the above embodiments; wherein the memory is coupled to the processor.

[0148] In some embodiments, electronic devices include but are not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0149] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0150] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-target manner. The structural embodiments described above are merely illustrative. For example, the division of units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other. The features disclosed in the several method or structural embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0151] The above are only some embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: The method comprises: Providing a substrate; the substrate includes an array region, the array region includes a plurality of active pillars arranged along a first direction and a second direction and extending along a third direction; the active pillars include a channel structure, and an initial drain and an initial source located on both sides of the channel structure along the third direction; Etching a portion of the initial drain electrode in the active pillar along the back surface of the substrate to form a first etched groove; the back surface is the surface on the side where the initial drain electrode is located; forming a first doping structure in the first etched groove; the first doping structure and the remaining initial drain constitute the drain in the active pillar; The first direction and the second direction intersect and are parallel to the plane where the base is located; and the third direction is perpendicular to the plane where the base is located.

2. The forming method according to claim 1, wherein: The first etched groove is connected to the back side of the substrate; a first doping structure is formed in the first etched groove, including: forming an initial first doping structure in the first etched groove and the exposed back surface of the substrate; The initial first doping structure located on the back side of the substrate is removed, and the remaining initial first doping structure located in the first etched groove constitutes the first doping structure.

3. The forming method according to claim 2, wherein: An initial first doping structure is formed in the first etched groove and the exposed surface of the substrate, comprising: Performing deposition and doping treatments simultaneously on the first etched groove and the exposed back surface of the substrate to form a first doping material layer; The first doping material layer is melted and recrystallized to form the initial first doping structure.

4. The forming method according to claim 3, wherein: The material of the first doping material layer is amorphous silicon with preset ion doping.

5. The forming method according to any one of claims 1 to 4, characterized in that: The base further includes a peripheral region, the peripheral region including a substrate, and a nitride layer and a metal layer sequentially located on a front surface of the substrate; While forming the first doping structure, a reflective layer is formed on the back side of the substrate; the front side is a surface along the third direction opposite to the back side.

6. The forming method according to claim 1, wherein: Before forming the first etched groove, the method further includes: performing heavy doping on a portion of the initial source electrode along the front surface of the substrate to form a second doping structure; or Etching a portion of the initial source electrode along the front surface of the substrate to form a second etched groove, and forming the second doping structure in the second etched groove; The front side is a surface opposite to the back side; the second doping structure and the remaining initial source constitute the source in the active column.

7. The forming method according to claim 6, wherein: The second etched groove is connected to the front surface of the substrate; and the second doping structure is formed in the second etched groove, comprising: Performing deposition and doping treatments simultaneously on the second etched groove and the exposed front surface of the substrate to form a second doping material layer; melting and recrystallizing the second doping material layer to form an initial second doping structure; The initial second doping structure located on the front surface of the substrate is removed, and the remaining initial second doping structure located in the second etched groove constitutes the second doping structure.

8. The forming method according to claim 6, wherein: The method further comprises: The initial drain and the initial source in the active column are lightly doped; wherein the ion concentration injected by the light doping is lower than the ion concentration in the first doping structure and the second doping structure.

9. The forming method according to claim 6, wherein: The method further comprises: forming a gate structure located on the surface of the channel structure; the gate structure includes a gate dielectric layer and a gate metal layer, and a plurality of the gate metal layers arranged along the first direction are interconnected to form a word line; A capacitor structure is formed, which extends along the third direction and is connected to a surface of the source electrode away from the channel structure.

10. The forming method according to claim 1, wherein: The method further comprises: A bit line structure is formed, which extends along the second direction and is connected to a surface of the drain electrode away from the channel structure.

11. A semiconductor structure, characterized in that The semiconductor structure comprises: A substrate; the substrate includes an array region, the array region includes a plurality of active pillars arranged along a first direction and a second direction and extending along a third direction; the active pillar includes a channel structure, and a drain and a source located on both sides of the channel structure along the third direction; The first direction and the second direction intersect and are parallel to the plane where the base is located; and the third direction is perpendicular to the plane where the base is located.

12. The structure according to claim 11, characterized in that The drain includes an initial drain and a first doping structure located on a surface of the initial drain away from the channel structure; the ion concentration in the initial drain is lower than the ion concentration in the first doping structure; The source includes an initial source and a second doping structure located on a surface of the initial source away from the channel structure; the ion concentration in the initial source is lower than the ion concentration in the second doping structure.

13. The structure according to claim 11, characterized in that The substrate further comprises: a peripheral region, the peripheral region including a substrate, a nitride layer and a metal layer sequentially located on a front surface of the substrate, and a reflective layer located on a back surface of the substrate; The back surface is the surface on the side where the drain is located; and the front surface is the surface along the third direction relative to the back surface.

14. The structure according to claim 11, characterized in that The semiconductor structure further comprises: a gate structure located on the surface of the channel structure; the gate structure comprising a gate dielectric layer and a gate metal layer, wherein a plurality of the gate metal layers arranged along the first direction are interconnected to form a word line; a capacitor structure extending along the third direction and connected to a surface of the source electrode away from the channel structure; The bit line structure extends along the second direction and is connected to a surface of the drain electrode away from the channel structure.

15. An electronic device, characterized in that: A device comprising a processing device; and a memory device electrically connected to the processing device, wherein the memory device comprises the semiconductor structure according to any one of claims 11 to 14.

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