Formation method of semiconductor structure and semiconductor structure

Abstract

The invention provides a semiconductor structure forming method and a semiconductor structure, and relates to the technical field of semiconductors. The forming method comprises the steps that a laminated structure is formed on a substrate, the laminated structure comprises a plurality of active column sets, a first gap is formed between every two adjacent active column sets, each active column set comprises a plurality of active columns, a second gap is formed between every two adjacent active columns, the active columns extend in the third direction and comprise channel regions, and the laminated structure exposes the outer surfaces of the channel regions; forming a first passivation layer covering the outer surface of the channel region and filling the second gap; the first passivation layer is thinned in the first direction, continuously distributed second passivation layers are formed, and a third gap is formed between every two adjacent second passivation layers; forming a first isolation layer filling the third gap; removing the second passivation layer to form a plurality of word line accommodating grooves; and filling a conductive material layer in the word line accommodating groove to form a word line structure. The method at least can eliminate size relevance in different directions in the word line structure forming process.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in computers and other electronic devices. It is composed of multiple memory cells, each of which usually includes a transistor and a capacitor. The gate of the transistor is electrically connected to the word line structure, the source is electrically connected to the bit line structure, and the drain is electrically connected to the capacitor. The voltage on the word line structure can control the opening and closing of the transistor, so that the data information stored in the capacitor can be read or written into the capacitor through the bit line structure.

[0003] Currently, due to the increasing demand for miniaturization of memory structures such as DRAM, vertical wordline structures can no longer meet the requirements of memory miniaturization and performance. Therefore, the wordline structure of three-dimensional memory has shifted from a vertical structure to a horizontal structure. However, in the existing manufacturing process of horizontal wordline structures, in order to ensure the continuity of the wordline structure in the horizontal direction, the wordline structure needs to have a certain thickness in the vertical direction. This makes the formation process of the wordline structure dependent on the space available between active pillars in the device. Moreover, the thickness of the wordline structure is relatively thick, which cannot meet the requirements of device miniaturization and performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0005] In view of this, a method for forming a semiconductor structure and a semiconductor structure are provided. The horizontal word line structure formed by this method can reduce the dependence on space, and the formed word line structure is thinner, meeting the device miniaturization requirements on the basis of ensuring the electrical performance of the device.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] providing a substrate;

[0009] forming a stacked structure on the substrate, the stacked structure comprising a plurality of active pillar groups spaced apart along a first direction, with a first gap between two adjacent active pillar groups; the active pillar group comprising a plurality of active pillars spaced apart along a second direction, with a second gap between two adjacent active pillars in the second direction; the active pillars extending along a third direction, the active pillars comprising a channel region, the stacked structure exposing an outer surface of the channel region, wherein the first direction is a direction perpendicular to the surface of the substrate, the second direction and the third direction are directions parallel to the surface of the substrate, and the second direction and the third direction intersect;

[0010] forming a first passivation layer, wherein the first passivation layer covers an outer surface of the channel region and fills the second gap;

[0011] Thinning the first passivation layer in the first direction, where the thinned first passivation layer is a second passivation layer, the second passivation layers are continuously distributed along the second direction, and a third gap exists between two adjacent second passivation layers in the first direction;

[0012] forming a first isolation layer, wherein the first isolation layer fills the third gap;

[0013] removing the second passivation layer to form a plurality of word line accommodating grooves;

[0014] A conductive material layer is filled in the word line receiving groove to form a word line structure.

[0015] In an exemplary embodiment of the present disclosure, after forming a plurality of word line accommodating grooves, the method further includes:

[0016] The outer surface of the channel region is trimmed by an etching process so as to make the outer surface of the channel region have a smooth transition.

[0017] In an exemplary embodiment of the present disclosure, before filling the word line receiving groove with a conductive material layer, the method further includes:

[0018] forming an oxide layer surrounding the outer surface of each of the channel regions, wherein a first gap exists between two adjacent oxide layers in the second direction;

[0019] Filling the word line receiving groove with a conductive material layer, further comprising:

[0020] The conductive material layer fills the first gap to form the word line structure distributed continuously in the second direction.

[0021] In an exemplary embodiment of the present disclosure, before forming the first passivation layer, the method further includes:

[0022] forming an insulating layer surrounding the outer surface of the channel region, wherein a second gap exists between two adjacent insulating layers in the first direction, and a third gap exists between two adjacent insulating layers in the second direction;

[0023] forming a first passivation layer, comprising:

[0024] The first passivation layer fills the second gap and the third gap.

[0025] In an exemplary embodiment of the present disclosure, after removing the second passivation layer, the method further includes:

[0026] The insulating layer is removed to expose the outer surface of the channel region.

[0027] In an exemplary embodiment of the present disclosure, forming a stacked structure on the substrate includes:

[0028] forming a first intermediate stacked structure on the surface of the substrate, wherein the first intermediate stacked structure comprises a first semiconductor layer and a second semiconductor layer alternately arranged in sequence along the first direction;

[0029] Etching the first intermediate stacked structure along the first direction and from the first intermediate stacked structure toward the substrate to form a plurality of first openings penetrating the first intermediate stacked structure, wherein the first openings extend along the third direction to form a plurality of initial active pillars in the first semiconductor layer, wherein the initial active pillars have initial channel regions;

[0030] A second isolation layer is filled in the first opening to form a second intermediate stacked structure.

[0031] In an exemplary embodiment of the present disclosure, it further includes:

[0032] The second semiconductor layer in the second intermediate stacked structure is removed to form a plurality of the initial active pillars arranged at intervals along the first direction.

[0033] In an exemplary embodiment of the present disclosure, it further includes:

[0034] trimming the initial active pillar to reduce the thickness of the initial channel region in the first direction to form the channel region of the active pillar;

[0035] After forming the channel region of the active pillar, the method includes:

[0036] The second isolation layer is removed to expose the outer surface of the channel region of each active pillar.

[0037] In an exemplary embodiment of the present disclosure, the width of the first gap is greater than the width of the second gap; and the width of the third gap is 30% to 70% of the width of the first gap.

[0038] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising:

[0039] substrate;

[0040] A stacked structure comprising a plurality of active pillar groups spaced apart along a first direction on the substrate, the active pillar groups comprising a plurality of active pillars spaced apart along a second direction, the active pillars extending along a third direction, and the active pillars including channel regions; wherein the first direction is a direction perpendicular to a surface of the substrate, the second direction and the third direction are directions parallel to the surface of the substrate, and the second direction and the third direction intersect;

[0041] a plurality of word line structures, the word line structures being connected to the active pillar groups correspondingly, the word line structures extending along the second direction, and the word line structures continuously covering outer surfaces of the plurality of channel regions within the active pillar groups;

[0042] a first isolation layer, located between two adjacent word line structures;

[0043] Half of the width of the word line structure between two adjacent active pillars along the second direction is greater than the thickness of the word line structure between the active pillar and the first isolation layer along the first direction.

[0044] The present disclosure provides a method for forming a semiconductor structure. The method comprises forming a first passivation layer on the outer surface of a channel region within a stacked structure, thinning the first passivation layer in a first direction, and then forming a second passivation layer. A first isolation layer is then filled between the second passivation layers to isolate two adjacent second passivation layers via the first isolation layer. The second passivation layer is then removed to form a wordline accommodating groove around the periphery of the channel region. A conductive material layer is then filled into the wordline accommodating groove to form a horizontal wordline structure that is continuously distributed and covers multiple channel regions. The wordline structure formed by this method uses the first isolation layer to separate the spaces between adjacent active pillar groups, thereby forming wordline accommodating grooves. While ensuring the continuous distribution of the wordline structure in the second (horizontal) direction, the wordline structure is thinner in the first (vertical) direction. This eliminates the dimensional correlation between the second (horizontal) and first (vertical) directions during the wordline structure formation process, thereby overcoming the wordline structure's dependence on the space between the active pillar groups, meeting device miniaturization requirements, and improving device performance.

[0045] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0047] Figure 1 The present invention is a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure.

[0048] Figure 2 Schematic diagram of the structure of a first intermediate stacked structure in an exemplary embodiment of the present disclosure.

[0049] Figure 3 FIG. 1 is a schematic structural diagram of forming a first opening in a first intermediate stacked structure in an exemplary embodiment of the present disclosure.

[0050] Figure 4 Schematic diagram of the structure of a second isolation layer in an exemplary embodiment of the present disclosure.

[0051] Figure 5 Schematic diagram of the structure of an initial active pillar in an exemplary embodiment of the present disclosure.

[0052] Figure 6 It is a structural cross-sectional view of a channel region of an active pillar in an exemplary embodiment of the present disclosure.

[0053] Figure 7 This is a schematic structural diagram of an insulating layer covering a channel region in an exemplary embodiment of the present disclosure.

[0054] Figure 8 Schematic diagram of the structure of a first passivation layer in an exemplary embodiment of the present disclosure.

[0055] Figure 9 Schematic diagram of the structure of another first passivation layer in an exemplary embodiment of the present disclosure.

[0056] Figure 10 Schematic diagram of the structure of a first passivation layer and a second passivation layer in an exemplary embodiment of the present disclosure.

[0057] Figure 11 Schematic diagram of the structure of a first isolation layer in an exemplary embodiment of the present disclosure.

[0058] Figure 12This is a schematic diagram of the structure after removing the second passivation layer in an exemplary embodiment of the present disclosure.

[0059] Figure 13 This is a schematic diagram of a structure after removing the insulating layer in an exemplary embodiment of the present disclosure.

[0060] Figure 14 4 is a cross-sectional view of a structure of a trimmed channel region in an exemplary embodiment of the present disclosure.

[0061] Figure 15 Schematic diagram of the structure of an oxide layer in an exemplary embodiment of the present disclosure.

[0062] Figure 16 Schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0063] The description of the accompanying drawings is as follows:

[0064] 100, substrate; 200, stacked structure; 210, first intermediate stacked structure; 220, second intermediate stacked structure; 201, active pillar group; 215, active pillar; 2151, channel region; 211, first semiconductor layer; 212, second semiconductor layer; 213, first opening; 214, initial active pillar; 410, first passivation layer; 420, second passivation layer; 501, first isolation layer; 502, second isolation layer; 610, oxide layer; 620, insulating layer; 701, word line accommodating groove; 710, conductive material layer; 720, word line structure; 800, sharp corner; A1, first gap; A2, second gap; A3, third gap; a1, first gap; a2, second gap; a3, third gap; X, first direction; Y, second direction; Z, third direction. DETAILED DESCRIPTION

[0065] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0066] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0067] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0068] In related technologies, three-dimensional memories are widely used due to their integration and miniaturization characteristics, and horizontal word line structures have lower resistance and more optimized electrical performance than vertical word line structures and are therefore used in three-dimensional memories.

[0069] Currently, in the process of forming a horizontal wordline structure, conductive material is usually directly deposited on the outer surfaces of multiple exposed channel regions to form the wordline structure. However, in order to ensure the continuous distribution of the wordline structure in the horizontal direction, the conductive material needs to fill the gap between two adjacent channel regions in the horizontal direction. Due to the synchronization of the process, the width of the wordline structure in the horizontal direction is correlated with its thickness in the vertical direction. That is, the thickness of the wordline structure in the vertical direction is determined by the width of the wordline structure in the horizontal direction. This causes the wordline structure to rely on the space between the channel regions in the vertical direction. Moreover, the wordline structure formed by this method is relatively thick and cannot meet the miniaturization and performance requirements of the device.

[0070] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as Figure 1 As shown, the forming method includes: steps S10 to S70.

[0071] Wherein, step S10: providing a substrate;

[0072] Step S20: forming a stacked structure on a substrate, the stacked structure comprising a plurality of active pillar groups spaced apart along a first direction, a first gap between two adjacent active pillar groups, the active pillar groups comprising a plurality of active pillars spaced apart along a second direction, a second gap between two adjacent active pillars in the second direction, the active pillars extending along a third direction, the active pillars including a channel region, the stacked structure exposing an outer surface of the channel region, wherein the first direction is a direction perpendicular to the surface of the substrate, the second direction and the third direction are directions parallel to the surface of the substrate, and the second direction and the third direction intersect;

[0073] Step S30: forming a first passivation layer, wherein the first passivation layer covers the outer surface of the channel region and fills the second gap;

[0074] Step S40: thinning the first passivation layer in the first direction, the thinned first passivation layer being a second passivation layer, the second passivation layer being continuously distributed along the second direction, and a third gap being provided between two adjacent second passivation layers in the first direction;

[0075] Step S50: forming a first isolation layer, wherein the first isolation layer fills the third gap;

[0076] Step S60: removing the second passivation layer to form a plurality of word line accommodating grooves;

[0077] Step S70 : filling the word line receiving groove with a conductive material layer to form a word line structure.

[0078] The present disclosure provides a method for forming a semiconductor structure. The method forms a first passivation layer on the outer surface of the channel region in the stacked structure, and forms a second passivation layer after thinning the first passivation layer in a first direction, fills a first isolation layer between the second passivation layers, isolates two adjacent second passivation layers by the first isolation layer, and then removes the second passivation layer to form a word line accommodating groove on the periphery of the channel region. Subsequently, a conductive material layer is filled in the word line accommodating groove to form a horizontal word line structure that is continuously distributed and covers multiple channel regions. The word line structure formed by the formation method is used to separate adjacent word line structures by filling the first isolation layer between the second passivation layers. The space between the source pillar groups forms a word line accommodating groove, and the width of the word line accommodating groove in the first direction is equal to the thickness of the word line structure in the first direction, thereby ensuring that the word line structure is continuously distributed in the second direction (horizontally). Due to the setting of the word line accommodating groove, the thickness of the word line structure in the first direction (vertical) is thinner, and the thickness of the word line structure in the first direction is not restricted by its width in the second direction during the formation process of the word line structure, that is, the dimensional correlation between the second direction and the first direction during the formation process of the word line structure is eliminated, thereby overcoming the dependence of the word line structure on the space between the active pillar groups, meeting the miniaturization requirements of the device, and improving the performance of the device.

[0079] It should be noted that in the embodiments provided in this disclosure, Figures 2 to 16 As shown, the first direction X is a direction perpendicular to the surface of the substrate 100, and the first direction X can be understood as the vertical direction in the embodiment of the present disclosure; the second direction Y is a direction parallel to the surface of the substrate 100 and intersects with the first direction X, and the second direction Y can be understood as the horizontal direction in the embodiment of the present disclosure; the third direction Z is a direction parallel to the surface of the substrate 100 and intersects with the first direction X and the second direction Y, respectively. The first direction X, the second direction Y, and the third direction Z will not be repeated in the following embodiments. However, it should be understood that the above three directions do not form a specific limitation on the actual structural layout and formation process of the device. When the relative position of the device changes, the above three directions will also change adaptively, and the present disclosure does not impose specific limitations.

[0080] The following is a detailed description of the various steps of the method for forming a semiconductor structure provided by the embodiment of the present disclosure with reference to the accompanying drawings:

[0081] In the embodiments provided in the present disclosure, Figures 2 to 16 As shown, in step S10 , a substrate 100 is provided.

[0082] The substrate 100 may be a semiconductor substrate, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, an SOI (Silicon On Insulator), or a GOI (Germanium On Insulator). In some embodiments, the semiconductor substrate may also be a substrate comprising other elemental semiconductors or compound semiconductors, for example, silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs). The substrate 100 may be selected based on the actual design requirements of the semiconductor structure and is not specifically limited in this disclosure.

[0083] The cross-sectional shape of the substrate 100 can be one of a variety of shapes, such as square, rectangular, circular, or triangular. The specific shape of the substrate 100 can be selected based on the actual design requirements of the device and is not specifically limited in this disclosure. However, it should be noted that regardless of the shape of the substrate 100, it does not affect the preparation process of the semiconductor structure disclosed herein.

[0084] In the embodiments provided in the present disclosure, Figure 6 As shown, in step S20 , a stacked structure 200 is formed on a substrate 100 .

[0085] In which, the stacked structure 200 includes a plurality of active column groups 201 arranged at intervals along a first direction X, and two adjacent active column groups 201 have a first gap A1. The active column group 201 includes a plurality of active columns 215 arranged at intervals along a second direction Y, and two adjacent active columns 215 have a second gap A2 in the second direction Y. The active columns 215 extend along a third direction Z, and the active columns 215 include a channel region 2151. The stacked structure 200 exposes the outer surface of the channel region 2151.

[0086] In some embodiments, the width of the first gap A1 may be greater than the width of the second gap A2 to provide sufficient space for subsequently forming the word line structures 720 distributed continuously in the second direction Y.

[0087] In some embodiments, a stacked structure 200 is formed on a substrate 100 , and the method includes steps S201 to S203 .

[0088] Among them, Figure 2 As shown, in step S201, a first intermediate stacked structure 210 is formed on the surface of the substrate 100. The first intermediate stacked structure 210 includes first semiconductor layers 211 and second semiconductor layers 212 alternately arranged in sequence along a first direction X; Figure 3 As shown, in step S202, the first intermediate stacked structure 210 is etched along the first direction X and in the direction from the first intermediate stacked structure 210 to the substrate 100 to form a plurality of first openings 213 penetrating the first intermediate stacked structure 210. The first openings 213 extend along the third direction Z to form a plurality of initial active pillars 214 in the first semiconductor layer 211. The initial active pillars 214 have initial channel regions 2151. Figure 4 As shown, in step S203 , a second isolation layer 502 is filled in the first opening 213 to form a second intermediate stacked structure 220 .

[0089] The first semiconductor layer 211 may be a silicon film layer, and the second semiconductor layer 212 may be an epitaxial layer. For example, the second semiconductor layer 212 may be a silicon germanium film layer. To facilitate the subsequent formation of the active pillars 215, the thickness of the first semiconductor layer 211 in the first direction X may be greater than the thickness of the second semiconductor layer in the first direction X.

[0090] In order to form active pillars 215 in the first semiconductor layer 211, a plurality of spaced-apart first openings 213 may be formed in the first intermediate stacked structure 210. The first openings 213 separate the first semiconductor layer 211 into a plurality of initial active pillars 214, and a second isolation layer 502 is filled in each first opening 213. The second isolation layer 502 is used to isolate two adjacent initial active pillars 214 in the second direction Y.

[0091] The second isolation layer 502 can be formed of a material having isolation and insulation functions such as silicon oxide and silicon nitride. It can be filled in the first opening 213 by one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), thermal oxidation (Thermal Oxidation), and sol-gel (Sol-Gel). The material and formation process of the second isolation layer 502 can be selected according to the actual process design, and this disclosure does not make specific limitations.

[0092] In some embodiments, as Figure 5 As shown, after forming the second intermediate stacked structure 220, the method further includes removing the second semiconductor layer 212 within the second intermediate stacked structure 220 to form a plurality of initial active pillars 214 spaced apart along the first direction X. Removing the second semiconductor layer 212 may be performed using one or more methods selected from the group consisting of wet etching, dry etching, and selective vapor phase etching. After removing the second semiconductor layer 212, the upper and lower surfaces of the first semiconductor layer 211 may be exposed in the first direction X, forming a plurality of initial active pillars 214 spaced apart in the first direction X, thereby providing a structural foundation for the subsequent formation of active pillars 215.

[0093] In some embodiments, as Figure 6 As shown, after forming a plurality of initial active pillars 214 spaced apart along the first direction X, the method further includes trimming the initial active pillars 214 to reduce the thickness of the initial channel region in the first direction X to form the channel region 2151 of the active pillars 215. After forming the channel region 2151 of the active pillars 215, the method further includes removing the second isolation layer 502 to expose the outer surface of the channel region 2151 of each active pillar 215.

[0094] In the stacked structure 200 provided by the present disclosure, in the first direction X, the distance between two adjacent active pillars 215 can be the sum of the thickness of the second semiconductor layer 212 in the first direction X and the thinned thickness of the first semiconductor layer 211 in the first direction X; in the second direction Y, the distance between two adjacent active pillars 215 can be the opening size of the first opening 213 in the second direction Y. Of course, in the process of removing the second isolation layer 502 and thinning the first semiconductor layer 211, due to process limitations, the distance between two adjacent active pillars 215 in the second direction Y will increase. It should be understood that this increased distance is within the allowable range of process error and does not affect the formation method provided by the present disclosure, and can be understood to be within the protection scope of the present disclosure.

[0095] In the embodiments provided in the present disclosure, Figure 8 As shown, in step S30 , a first passivation layer 410 is formed. The first passivation layer 410 covers the outer surface of the channel region 2151 and fills the second gap A2 .

[0096] like Figure 7 As shown, before forming the first passivation layer 410, the method further includes forming an insulating layer 620 surrounding the outer surface of the channel region 2151. A second gap a2 is defined between two adjacent insulating layers 620 in the first direction X, and the width of the second gap a2 is smaller than the width of the first gap A1. A third gap a3 is defined between two adjacent insulating layers 620 in the second direction Y, and the width of the third gap a3 is smaller than the width of the second gap A2. The insulating layer 620 is coated on the outer surface of the channel region 2151 to protect the outer surface of the channel region 2151 from damage during subsequent processing, thereby ensuring the integrity of the channel region 2151.

[0097] The insulating layer 620 can be formed of materials such as silicon oxide, and can be deposited on the outer surface of the channel region 2151 using one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the insulating layer 620 can be 1nm to 50nm. The material, thickness and formation process of the insulating layer 620 can be selected according to the space between adjacent channel regions 2151 and the subsequent process design requirements, and this disclosure does not make specific limitations.

[0098] like Figure 8 As shown, after forming the insulating layer 620 on the outer surface of the channel region 2151 , the method further includes: filling the second gap a2 and the third gap a3 with the first passivation layer 410 .

[0099] The first passivation layer 410 may be made of a material such as silicon nitride. Furthermore, in order to reduce the adverse effects on the insulating layer 620 during the subsequent thinning of the first passivation layer 410, the first passivation layer 410 needs to be formed of a material different from that of the insulating layer 620. For example, the insulating layer 620 may be made of silicon oxide, and the first passivation layer 410 may be made of silicon nitride. The first passivation layer 410 may be deposited on the outer surface of the insulating layer 620 using one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The formation process of the first passivation layer 410 may be selected based on actual process design requirements and is not specifically limited in this disclosure.

[0100] In the embodiments provided in the present disclosure, Figure 10 As shown, in step S40, the first passivation layer 410 is thinned in the first direction X. The thinned first passivation layer 410 is the second passivation layer 420. The second passivation layer 420 is continuously distributed along the second direction Y, and a third gap A3 is formed between two adjacent second passivation layers 420 in the first direction X.

[0101] In step S30, the first passivation layer 410 covers the outer surface of the channel region 2151 and fills the second gap A2. When the first passivation layer 410 fills the second gap A2, the first passivation layer 410 is simultaneously formed in the first gap A1. The thickness of the first passivation layer 410 in the first gap A1 (in the first direction X) is determined by the width of the thickness of the first passivation layer 410 in the second gap A2 (in the second direction Y), that is, the first passivation layer 410 is formed in the first gap A1 and the second gap A2 using a one-step process.

[0102] In some embodiments, as Figure 8 As shown, in the first direction X, there may be a gap between the first passivation layers 410 coated on the outer surfaces of two adjacent channel regions 2151. In some embodiments, as shown in FIG. Figure 9 As shown, in the first direction X, the first passivation layers 410 coated on the outer surfaces of two adjacent channel regions 2151 can be connected as a whole. In order to facilitate the subsequent thinning process of the first passivation layer 410, a certain gap is usually left between the first passivation layers 410 coated on the outer surfaces of two adjacent channel regions 2151 in the first direction X.

[0103] The first passivation layer 410 may be thinned in the first direction X by etching back the first passivation layer 410 to reduce the thickness of the first passivation layer 410 in the first direction X. In the present disclosure, thinning the first passivation layer 410 may mean thinning the first passivation layer 410 located on both the upper and lower surfaces of the channel region 2151 in the first direction X at the same time, and the thinned thicknesses may be equal or substantially equal, so as to facilitate uniformity of the subsequently formed word line structure 720 and improve the electrical performance of the subsequently formed word line structure 720.

[0104] like Figure 10 As shown, the thinned first passivation layer 410 becomes the second passivation layer 420. The second passivation layer 420 is continuously distributed along the second direction Y, and a third gap A3 is formed between two adjacent second passivation layers 420 in the first direction X. To meet the thickness requirement of the subsequent word line structure 720 in the first direction X, the width of the third gap A3 can be 30% to 70% of the width of the first gap A1. For example, the width of the third gap A3 can be 30%, 40%, 50%, 60%, or 70% of the width of the first gap A1. This third gap A3 ensures that the thickness of the subsequently formed word line structure 720 in the first direction X is relatively thin, and can also enable the word line structure 720 to continuously cover the outer surface of the channel region 2151 in the second direction Y.

[0105] In the embodiments provided in the present disclosure, Figure 11 As shown, in step S50 , a first isolation layer 501 is formed, and the first isolation layer 501 fills the third gap A3 .

[0106] The first isolation layer 501 can be made of a material such as silicon oxide. To facilitate the subsequent removal of the second passivation layer 420, the first isolation layer 501 and the second passivation layer 420 can be made of different materials. For example, when the second passivation layer 420 is silicon nitride, the first isolation layer 501 can be made of silicon oxide. Filling the third gap A3 with the first isolation layer 501 can isolate two adjacent second passivation layers 420 in the first direction X, providing a structural foundation for the subsequent formation of the word line accommodating trench 701.

[0107] In the embodiments provided in the present disclosure, Figure 12 As shown, in step S60 , the second passivation layer 420 is removed to form a plurality of word line receiving grooves 701 .

[0108] In some embodiments, the second passivation layer 420 may be removed by wet etching, dry etching, or a combination of the two.

[0109] like Figure 13As shown, after removing the second passivation layer 420, the method further includes removing the insulating layer 620 to expose the outer surface of the channel region 2151. By removing the second passivation layer 420 and the insulating layer 620, word line accommodating grooves 701 can be formed between the outer surface of the channel region 2151 and the first isolation layer 501. The word line accommodating grooves 701 surround the outer surfaces of multiple channel regions 2151 in the second direction Y and are continuously distributed in the second direction Y. The word line accommodating grooves 701 can be used to define the shape and size of the subsequent word line structure 720, ensuring the integrity, continuity, and functionality of the word line structure 720.

[0110] In some embodiments, half of the width of the word line receiving groove 701 between two adjacent active pillars 215 along the second direction Y is greater than the width of the word line receiving groove 701 between the active pillar 215 and the first isolation layer 501 along the first direction X.

[0111] In some embodiments, as Figure 14 As shown, after forming the word line accommodating groove 701, the method further includes: trimming the outer surface of the channel region 2151 using an etching process to achieve a smooth transition on the outer surface of the channel region 2151. During the etching process such as removing the insulating layer 620, the outer surface of the channel region 2151 is affected by the etching gas or etching solution, which may produce sharp corners 800 around the channel region 2151 or a concave-convex structure on the surface of the channel region 2151. In particular, the sharp corners 800 may cause leakage current in subsequent devices, seriously affecting the electrical performance of the devices. In order to prevent the morphology of the outer surface of the channel region 2151 from adversely affecting the device performance, after removing the insulating layer 620, the outer surface of the channel region 2151 is trimmed using an etching process to achieve a smooth transition on the outer surface of the channel region 2151, thereby improving the performance of the device.

[0112] In the embodiments provided in the present disclosure, Figure 16 As shown, in step S70 , a conductive material layer 710 is filled in the word line receiving groove 701 to form a word line structure 720 .

[0113] In some embodiments, as Figure 15 As shown, before filling the word line receiving groove 701 with a conductive material, the method further includes: forming an oxide layer 610 surrounding the outer surface of each channel region 2151 , and in the second direction Y, a first gap a1 is formed between two adjacent oxide layers 610 .

[0114] The oxide layer 610 can be made of one or more materials such as silicon nitride, silicon oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, and hafnium silicate. The material of the oxide layer 610 needs to be selected based on the interface characteristics of the device and the material of the channel region 2151, and is not specifically limited in this disclosure. In some embodiments, considering the difficulty and cost of the manufacturing process, as well as the characteristics of the oxide layer 610, the oxide layer 610 can be made of silicon nitride.

[0115] The oxide layer 610 can be formed by one or more methods such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD) or electron beam evaporation (E-beam Evaporation). In order to improve the convenience of process preparation, the oxide layer 610 covering the outer surface of the plurality of channel regions 2151 can be formed by a one-step process. The thickness of the oxide layer 610 can be 3nm to 20nm. The specific thickness, material and formation process of the oxide layer 610 can be selected according to the actual design requirements of the device, and the present disclosure does not make specific limitations.

[0116] In the present disclosure, the oxide layer 610 is coated on the outer surface of the channel region 2151, which can achieve gate insulation, electric field regulation, threshold voltage control and other functions, thereby improving the reliability of the device.

[0117] In the second direction Y, a first gap a1 is required between two adjacent oxide layers 610 . When the word line structure 720 is subsequently formed, the word line structure 720 fills the first gap a1 to ensure the continuity of the word line structure 720 in the second direction Y.

[0118] like Figure 16 As shown, after forming the oxide layer 610 on the outer surface of the channel region 2151 , the method further includes: filling the first gap a1 with a conductive material layer 710 to form a continuously distributed word line structure 720 in the second direction Y.

[0119] In some embodiments, half of the width of the word line structure 720 between two adjacent active pillars 215 along the second direction Y is greater than the thickness of the word line structure 720 between the active pillar 215 and the first isolation layer 501 along the first direction X, so as to form a word line structure 720 with a thinner thickness in the first direction X (vertical). On the one hand, this can reduce the size of the device and improve the integration of the device; on the other hand, it can reduce the RC delay and optimize the performance of the device.

[0120] Among them, the conductive material layer 710 may include materials such as titanium nitride, which can adopt one or more methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD). The material and formation process of the conductive material layer 710 can be selected according to actual process requirements, and this disclosure does not make specific limitations.

[0121] The method for forming a semiconductor structure provided by the present disclosure forms a horizontal wordline structure 720 that covers multiple channel regions 2151 and is continuously distributed in the second direction Y (horizontal) by filling a conductive material layer 710 within a wordline receiving groove 701. The thickness of the wordline structure 720 in the first direction X (vertical) is less than its width in the second direction Y (horizontal), which can significantly reduce the thickness of the wordline structure 720, thereby reducing RC delay and improving the performance of the wordline structure 720. In addition, during the formation process of the wordline structure 720, the thickness of the wordline structure 720 in the first direction X is not limited by its width in the second direction Y, eliminating the correlation between the horizontal and vertical dimensions in the wordline structure 720 formation process and the spatial dependence of the formation of the wordline structure 720. This reduces the restriction on the width of the active pillar 215 in the second direction Y, increases the adjustable threshold of the device, improves the gate control capability of the device, and thus improves the overall functionality of the device.

[0122] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0123] The present disclosure provides a semiconductor structure that can be manufactured using the formation method provided in any of the above embodiments, such as Figure 16 As shown, the semiconductor structure includes: a substrate 100 , a stacked structure 200 , a plurality of word line structures 720 and a first isolation layer 501 .

[0124] In which, the stacked structure 200 includes a plurality of active pillar groups 201 arranged on the substrate 100 at intervals along a first direction X, the active pillar groups 201 include a plurality of active pillars 215 arranged at intervals along a second direction Y, the active pillars 215 extend along a third direction Z, and the active pillars 215 include channel regions 2151; a word line structure 720 is correspondingly connected to the active pillar groups 201, the word line structure 720 extends along the second direction Y, and the word line structure 720 continuously covers the outer surface of the plurality of channel regions 2151 within the active pillar groups 201; a first isolation layer 501 is located between two adjacent word line structures 720; half of the width of the word line structure 720 between two adjacent active pillars 215 along the second direction Y is greater than the thickness of the word line structure 720 between the active pillars 215 and the first isolation layer 501 along the first direction X.

[0125] The semiconductor structure provided by the present disclosure has a horizontal word line structure 720. The thickness of the word line structure 720 between the active pillar 215 and the first isolation layer 501 along the first direction X (vertical) is less than half the width of the word line structure 720 between two adjacent active pillars 215 along the second direction Y (horizontal). The thickness of the word line structure 720 in the vertical direction is reduced, thereby improving the electrical performance of the word line structure 720 and further improving the overall performance of the device.

[0126] Among them, in addition to the channel region 2151, the active column 215 may also include a first source and drain region and a second source and drain region (not shown in the figure). The first source and drain region, the channel region 2151 and the second source and drain region can be arranged in sequence along the third direction Z. The first source and drain region and the second source and drain region can be formed by doping the first semiconductor layer 211. For example, the first semiconductor layer 211 can be doped with P-type or N-type to form the first source and drain region and the second source and drain region. The specific doping type can be selected according to the type requirements of the device, and the present disclosure does not make specific restrictions. Among them, the first source and drain region can be used as a source or a drain, and the second source and drain region can be used as a drain or a source. After the active column 215 is electrically connected to other devices through the first source and drain region and the second source and drain region, data can be read and written through control signals. For example, the first source and drain region can be connected to the bit line structure in the device, and the second source and drain region can be connected to the capacitor structure in the device to realize functions such as data control, transmission and storage. The present disclosure does not make specific statements or limitations on the bit line structure, capacitor structure and other structures within the device. It should be understood that the bit line structure, capacitor structure and other structures are all semiconductor structures available in the art, and can be electrically connected to the semiconductor structure provided by the present disclosure to achieve signal control, data reading and other functions of the device.

[0127] The other specific structures within the semiconductor structure provided by the present disclosure are as described in the above-mentioned formation method and will not be repeated here. The semiconductor structure provided by the present disclosure can be applied to one of 3D DRAM, 3D NAND Flash, 3D RRAM, 3D MRAM, etc., and the present disclosure does not make specific limitations.

[0128] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a stacked structure on the substrate, the stacked structure comprising a plurality of active pillar groups spaced apart along a first direction, with a first gap between two adjacent active pillar groups; the active pillar group comprising a plurality of active pillars spaced apart along a second direction, with a second gap between two adjacent active pillars in the second direction; the active pillars extending along a third direction, the active pillars comprising a channel region, the stacked structure exposing an outer surface of the channel region, wherein the first direction is a direction perpendicular to the surface of the substrate, the second direction and the third direction are directions parallel to the surface of the substrate, and the second direction and the third direction intersect; forming a first passivation layer, wherein the first passivation layer covers an outer surface of the channel region and fills the second gap; Thinning the first passivation layer in the first direction, where the thinned first passivation layer is a second passivation layer, the second passivation layers are continuously distributed along the second direction, and a third gap exists between two adjacent second passivation layers in the first direction; forming a first isolation layer, wherein the first isolation layer fills the third gap; removing the second passivation layer to form a plurality of word line accommodating grooves; A conductive material layer is filled in the word line receiving groove to form a word line structure.

2. The method for forming a semiconductor structure according to claim 1, wherein: After forming a plurality of word line accommodating grooves, the method further includes: The outer surface of the channel region is trimmed by an etching process so as to make the outer surface of the channel region have a smooth transition.

3. The method for forming a semiconductor structure according to claim 1, wherein: Before filling the conductive material layer in the word line receiving groove, the method further includes: forming an oxide layer surrounding the outer surface of each of the channel regions, wherein a first gap exists between two adjacent oxide layers in the second direction; Filling the word line receiving groove with a conductive material layer, further comprising: The conductive material layer fills the first gap to form the word line structure distributed continuously in the second direction.

4. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the first passivation layer, the method further includes: forming an insulating layer surrounding the outer surface of the channel region, wherein a second gap exists between two adjacent insulating layers in the first direction, and a third gap exists between two adjacent insulating layers in the second direction; forming a first passivation layer, comprising: The first passivation layer fills the second gap and the third gap.

5. The method for forming a semiconductor structure according to claim 4, wherein: After removing the second passivation layer, the method further includes: The insulating layer is removed to expose the outer surface of the channel region.

6. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a stacked structure on the substrate comprises: forming a first intermediate stacked structure on the surface of the substrate, wherein the first intermediate stacked structure comprises a first semiconductor layer and a second semiconductor layer alternately arranged in sequence along the first direction; Etching the first intermediate stacked structure along the first direction and from the first intermediate stacked structure toward the substrate to form a plurality of first openings penetrating the first intermediate stacked structure, wherein the first openings extend along the third direction to form a plurality of initial active pillars in the first semiconductor layer, wherein the initial active pillars have initial channel regions; A second isolation layer is filled in the first opening to form a second intermediate stacked structure.

7. The method for forming a semiconductor structure according to claim 6, wherein: Also includes: The second semiconductor layer in the second intermediate stacked structure is removed to form a plurality of the initial active pillars arranged at intervals along the first direction.

8. The method for forming a semiconductor structure according to claim 7, wherein: Also includes: trimming the initial active pillar to reduce the thickness of the initial channel region in the first direction to form the channel region of the active pillar; After forming the channel region of the active pillar, the method includes: The second isolation layer is removed to expose the outer surface of the channel region of each active pillar.

9. The method for forming a semiconductor structure according to any one of claims 1 to 8, wherein: The width of the first gap is greater than that of the second gap; and the width of the third gap is 30% to 70% of the width of the first gap.

10. A semiconductor structure, characterized in that include: substrate; A stacked structure comprising a plurality of active pillar groups spaced apart along a first direction on the substrate, the active pillar groups comprising a plurality of active pillars spaced apart along a second direction, the active pillars extending along a third direction, and the active pillars including channel regions; wherein the first direction is a direction perpendicular to a surface of the substrate, the second direction and the third direction are directions parallel to the surface of the substrate, and the second direction and the third direction intersect; a plurality of word line structures, the word line structures being connected to the active pillar groups correspondingly, the word line structures extending along the second direction, and the word line structures continuously covering outer surfaces of the plurality of channel regions within the active pillar groups; a first isolation layer, located between two adjacent word line structures; Half of the width of the word line structure between two adjacent active pillars along the second direction is greater than the thickness of the word line structure between the active pillar and the first isolation layer along the first direction.

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