Laminated structure, semiconductor device and preparation process thereof

Abstract

The invention provides a laminated structure, a semiconductor device and a preparation process thereof, and relates to the technical field of semiconductors. The laminated structure comprises supporting layers and sacrificial layers which are alternately stacked from bottom to top, in the supporting layers, one at the bottom is a bottom supporting layer, and the rest are upper supporting layers; the area where the laminated structure is located comprises a first area and a second area, and the total layer thickness of the upper supporting layer in the first area is larger than the total layer thickness of the upper supporting layer in the second area. The laminated structure is applied to the semiconductor device, the thickness of the supporting layer in the second region of the laminated structure is reduced, the overall etching rate of the through holes etched in the second region can be improved, the depth load effect caused by the fact that the pattern density formed in the first region of the laminated structure is smaller than that of the through holes in the second region is balanced, and the reliability of the semiconductor device is improved. On the basis of reducing the etching damage to the substrate, the connectivity of the through holes of the first region and the second region is ensured, so that the rejection rate of the semiconductor device is reduced, and the yield of finished products is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a stacked structure, a semiconductor device and a preparation process thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device widely used in computer systems, servers, and embedded systems. With the continuous iterative development of DRAM technology, the structural integration of its related products continues to improve.

[0003] As an important structure in DRAM, the capacitor structure specifically includes a stacked structure formed by alternating multiple supporting layers and sacrificial layers. The stacked structure includes an array area, a peripheral area, and a junction area located therebetween. Capacitor tubes are arranged in both the array area and the junction area, and the pattern density of the capacitor tubes in the array area is less than that in the junction area.

[0004] During the process of etching to form capacitor holes, the depth loading effect is caused by the difference in pattern density of the capacitor holes in the array area and the junction area, resulting in the capacitor holes in the array area reaching the bottom of the stacked structure before the capacitor holes in the junction area. If etching is stopped at this time, the capacitor holes in the junction area will be in a closed bottom state and the subsequently formed capacitor tube will be in an open circuit state; if etching is continued until the capacitor holes in the junction area reach the bottom of the stacked structure, etching damage will be caused to the substrate at the bottom of the capacitor holes in the array area; both situations will cause the semiconductor device to be scrapped and reduce the yield of the finished product. Summary of the Invention

[0005] The purpose of the present invention is to provide a semiconductor device and its preparation process to solve the technical problem in the related art that during the process of etching to form capacitor holes, the bottom of the capacitor hole is easily not penetrated or the etching damages the substrate, resulting in the scrapping of the semiconductor device and reducing the yield of the finished product.

[0006] To solve the above problems, the present invention provides a laminated structure comprising support layers and sacrificial layers alternately stacked from bottom to top, wherein the one at the bottom of the support layers is a bottom support layer and the others are upper support layers;

[0007] The region where the stacked structure is located includes a first region and a second region, and the total thickness of the upper supporting layer in the first region is greater than the total thickness of the upper supporting layer in the second region.

[0008] Optionally, in each of the upper supporting layers, the thickness of the second region is smaller than the thickness of the first region.

[0009] Optionally, the thickness of the second region of the upper supporting layer is 20%-30% smaller than the thickness of the first region.

[0010] Optionally, among the upper supporting layers, the one located at the top is the top supporting layer and the rest are middle supporting layers. The second region of at least one of the middle supporting layers is recessed relative to the first region to form a first groove, and the first groove is filled with a filling sacrificial layer, and the filling sacrificial layer is an oxide layer not doped with ions.

[0011] Optionally, among the upper supporting layers, the one located at the top is a top supporting layer, and the bottom surface of the second region of the top supporting layer is recessed upward relative to the first region to form a second groove;

[0012] The sacrificial layer adjacent to and below the top supporting layer is a top sacrificial layer. The top sacrificial layer includes a flat layer portion and a raised layer portion partially protruding upward. The raised layer portion is filled in the second groove.

[0013] Optionally, the stacked structure includes a first supporting layer, a first sacrificial layer, a second supporting layer, a second sacrificial layer, and a third supporting layer stacked in sequence from bottom to top, wherein the second region of the second supporting layer is recessed relative to the first region to form a first groove, the first groove is filled with a filling sacrificial layer, and the filling sacrificial layer is an oxide layer not doped with ions;

[0014] The bottom surface of the second region of the third supporting layer is recessed upward relative to the first region to form a second groove. The second sacrificial layer includes a flat layer portion and a partially upwardly protruding raised layer portion. The raised layer portion is filled in the second groove.

[0015] Optionally, the stacked structure includes an array region, a peripheral region, and a boundary region therebetween, wherein the array region serves as the first region;

[0016] The boundary area serves as the second region; or, the boundary area and a local area of ​​the peripheral area adjacent to the boundary area serve as the second region; or, the boundary area and the peripheral area serve as the second region.

[0017] The present invention also provides a semiconductor device comprising a substrate and the above-mentioned stacked structure, wherein the stacked structure is formed on the substrate, and the stacked structure is formed with a plurality of through holes extending downward to the surface of the substrate, wherein the graphic density of the through holes in the first region is less than the graphic density of the through holes in the second region.

[0018] The present invention also provides a process for preparing a laminated structure, which is used to prepare the above-mentioned laminated structure. The process comprises:

[0019] forming a first supporting layer, a first sacrificial layer, and a patterned filling sacrificial layer in sequence on the substrate, wherein the filling sacrificial layer covers the second region of the first sacrificial layer;

[0020] forming a second supporting layer covering the first sacrificial layer and the filling sacrificial layer, and reducing the thickness of the second supporting layer in the second region;

[0021] forming a second sacrificial layer on the second supporting layer, wherein the second region of the second sacrificial layer protrudes upward relative to the first region to form a raised layer portion;

[0022] A third supporting layer covering the second sacrificial layer is formed, and a chemical mechanical polishing and planarization process is performed on the third supporting layer to obtain a stacked structure.

[0023] The present invention also provides a process for preparing a semiconductor device, which is used to prepare the above-mentioned semiconductor device. The process comprises:

[0024] providing a substrate;

[0025] forming a stacked structure on the substrate, the stacked structure comprising supporting layers and sacrificial layers alternately stacked from bottom to top, wherein one of the supporting layers located at the bottom is a bottom supporting layer and the others are upper supporting layers; the stacked structure comprises a first region and a second region, wherein the total thickness of the upper supporting layer in the first region is greater than the total thickness of the upper supporting layer in the second region;

[0026] The stacked structure is patterned to form a plurality of through holes penetrating the stacked structure, wherein a pattern density of the through holes in the first region is smaller than a pattern density of the through holes in the second region.

[0027] The stacked structure provided by the present invention is applied to semiconductor devices. The upper supporting layer located at the top of the stacked structure affects the etching rate when etching through holes before the bottom supporting layer. Relative to the total thickness of all upper supporting layers in the first region, the total thickness of all upper supporting layers in the second region is thinned, and the total thickness of all sacrificial layers in the second region is thickened. On the basis of ensuring that the overall thickness of the first region and the second region in the stacked structure are uniform, the total thickness of all upper supporting layers in the second region is made smaller than the total thickness of all upper supporting layers in the first region, so as to reduce the overall etching difficulty of the second region and effectively improve the overall etching rate of etching through holes in the second region.

[0028] An array of through holes is formed by synchronously etching in the first and second regions of the stacked structure, and the pattern density of the through holes in the first region is less than that in the second region; in the process of etching to form the through holes, the etching rate of the through holes is affected by both the depth micro-loading effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer, wherein the depth micro-loading effect makes the overall etching rate of the through holes in the first region greater than the overall etching rate of the through holes in the second region, and the difference in the total thickness of the upper support layer makes the overall etching rate of the through holes in the first region less than the overall etching rate of the through holes in the second region, the latter having an influence on the etching difficulty of the through holes in the first region. The influence of the etching rate of the through holes in the first region and the second region is opposite to that of the former, thereby improving the consistency of the etching rate of the through holes formed in the first region and the second region, balancing the depth load effect caused by the formation of a through hole array with a pattern density smaller than that in the second region in the stacked structure of the semiconductor device, so that the through holes in the first region and the second region can reach the substrate surface at approximately the same time, and on the basis of reducing etching damage to the substrate and ensuring substrate performance, the penetration of the through holes in the first region and the second region is ensured, thereby ensuring the path performance of structures such as capacitors formed in the through holes later, reducing the scrap rate of semiconductor devices, and improving their finished product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in related technologies, the following briefly introduces the drawings required for use in the specific embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 A schematic diagram of a device structure in which a stacked structure is formed on a substrate in the related art;

[0031] Figure 2 A schematic diagram of a target device structure of a semiconductor device of related art;

[0032] Figure 3 A schematic diagram of an actual device structure of a semiconductor device in related technology;

[0033] Figures 4A-4I Schematic diagram of the device structure of each step in the preparation process of the stacked structure provided by the embodiment of the present invention, wherein: Figure 4I A schematic diagram of a device structure in which a stacked structure provided by an embodiment of the present invention is formed on a substrate;

[0034] Figures 5A-5E A schematic diagram of the device structure of each step of etching to form a through hole in the manufacturing process of a semiconductor device provided by an embodiment of the present invention, wherein: Figure 5EA schematic diagram of the device structure of a semiconductor device provided in an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of a process for preparing a laminated structure according to an embodiment of the present invention;

[0036] Figure 7 The figure is a schematic flow chart of a process for preparing a semiconductor device according to an embodiment of the present invention.

[0037] Description of reference numerals:

[0038] 10-stacked structure; A-first area; 11-array area; B-second area; 12-junction area; 13-peripheral area; 100-substrate; 210-bottom supporting layer; 220-first supporting layer; 300-first sacrificial layer; 400-filling sacrificial layer; 510-middle supporting layer; 511-first groove; 520-second supporting layer; 610-top sacrificial layer; 611-flat layer portion; 612-raised layer portion; 620-second sacrificial layer; 710-top supporting layer; 711-second groove; 720-third supporting layer; 810-first mask layer; 820-second mask layer; 910-groove; 920-through hole. DETAILED DESCRIPTION

[0039] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0042] Figure 1 FIG. 1 is a schematic diagram of a device structure when a stacked structure 10 is formed on a substrate 100 in the related art. Figure 2 A schematic diagram of a target device structure of a semiconductor device in related art. Figure 3 Schematic diagram of the actual device structure of a semiconductor device in related technology.

[0043] In related technologies, such as Figure 1 The stacked structure 10 shown in the perspective includes a first supporting layer 220, a first sacrificial layer 300, a second supporting layer 520, a second sacrificial layer 620 and a third supporting layer 720 stacked in sequence from bottom to top. The area where the stacked structure 10 is located includes an array area 11, a peripheral area 13 and a boundary area 12 located therebetween.

[0044] A plurality of capacitor holes (through holes 920) extending along the stacking direction and arranged in an array are formed in the array region 11 and the interface region 12 of the stacked structure 10, wherein the pattern density of the capacitor holes in the array region 11 is less than the pattern density of the capacitor holes in the interface region 12; Figure 2 As shown, under ideal conditions, the etching depths of the capacitor holes in the array region 11 and the capacitor holes in the junction region 12 are consistent, and can reach the bottom surface of the first supporting layer 220 at approximately the same time. On the basis of reducing etching damage to the substrate 100, it ensures that the path state of the capacitor tube is subsequently formed in the capacitor hole, thereby reducing the scrap rate of the semiconductor device and improving its finished product yield. However, in the process of simultaneously etching the capacitor holes in the array region 11 and the junction region 12, the pattern density of the capacitor holes in the array region 11 is less than the pattern density of the capacitor holes in the junction region 12, causing a depth loading effect. The etching rate of the capacitor holes in the array region 11 is greater than the etching rate of the capacitor holes in the junction region 12. Accordingly, as shown in FIG. Figure 3As shown, the capacitor holes in the array area 11 first reach the surface of the substrate 100. At this time, the bottom of the capacitor holes in the junction area 12 has not reached the substrate 100 and is in a closed state. If etching is stopped at this time, the capacitor tube subsequently formed in the capacitor holes in the junction area 12 is in an open circuit state, resulting in the stored charge being invalid and unable to connect with the MOS structure of the substrate 100, causing the semiconductor device to be scrapped and the yield rate of the finished product to be reduced; if etching is continued until the capacitor holes in the junction area 12 reach the bottom of the stacked structure 10, the capacitor holes in the array area 11 will cause etching damage to the substrate 100, affecting its performance, causing the semiconductor device to be scrapped and the yield rate of the finished product to be reduced.

[0045] This embodiment provides a stacked structure 10. Compared to the total thickness of the support layer 510 in the first region A, the total thickness of the support layer 510 in the second region B is reduced to balance the depth loading effect caused by the formation of a through-hole array 920 with a pattern density smaller than that in the second region B in the stacked structure 10 in the first region A of the semiconductor device. This allows the through-holes 920 in the first region A and the second region B to reach the surface of the substrate 100 approximately at the same time. On the basis of reducing etching damage to the substrate 100 and ensuring the performance of the substrate 100, the through-holes 920 in the first region A and the second region B are ensured to be continuous, thereby ensuring the path performance of structures such as capacitors formed in the through-holes 920, reducing the scrap rate of the semiconductor device and improving its finished product yield. The stacked structure 10 and the semiconductor device provided by the embodiment of the present invention will be further described in detail below with reference to the accompanying drawings.

[0046] Figure 4I Schematic diagram of a device structure when the stacked structure 10 provided by an embodiment of the present invention is formed on a substrate 100. Figure 5E A schematic diagram of the device structure of a semiconductor device provided by an embodiment of the present invention.

[0047] This embodiment provides a stacked structure 10, such as Figure 4I As shown, it includes support layers and sacrificial layers stacked alternately from bottom to top. Among the support layers, the one located at the bottom is the bottom support layer 210 and the rest are upper support layers; the area where the stacked structure 10 is located includes a first area A and a second area B, and the total layer thickness of the upper support layer in the first area A is greater than the total layer thickness of the upper support layer in the second area B.

[0048] This embodiment also provides a semiconductor device, such as Figure 5E As shown, it includes a substrate 100 and the above-mentioned stacked structure 10, the stacked structure is formed on the substrate 100, and the stacked structure 10 is formed with a plurality of through holes 920 extending downward to the surface of the substrate 100, wherein the pattern density of the through holes 920 in the first area A is less than the pattern density of the through holes 920 in the second area B.

[0049] The stacked structure 10 provided in this embodiment includes alternately stacked support layers and sacrificial layers, wherein the membrane layer located at the bottom is the support layer, and the support layer is defined as the bottom support layer 210, and the remaining support layers located above the bottom support layer 210 are defined as upper support layers; the etching difficulty of the support layer is greater than that of the sacrificial layer, and under the same etching process conditions, the etching rate of the support layer is lower than the etching rate of the sacrificial layer.

[0050] In the stacked structure 10, the upper supporting layer located above affects the etching rate when etching the through hole 920 before the bottom supporting layer 210. Relative to the total thickness of all upper supporting layers in the first area A, by thinning the total thickness of all upper supporting layers in the second area B and thickening the total thickness of all sacrificial layers in the second area B, on the basis of ensuring the overall uniformity of the thickness of the first area A and the second area B in the stacked structure 10, the total thickness of all upper supporting layers in the second area B is made smaller than the total thickness of all upper supporting layers in the first area A, so as to reduce the overall etching difficulty of the second area B and effectively improve the overall etching rate of the through hole 920 in the second area B.

[0051] When the stacked structure 10 is applied to a semiconductor device, an array of through holes 920 is simultaneously etched in the first region A and the second region B of the stacked structure 10, and the pattern density of the through holes 920 in the first region A is less than the pattern density of the through holes 920 in the second region B. In the process of etching to form the through holes 920, the etching rate of the through holes 920 is affected by both the depth micro-load effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer. The depth micro-load effect makes the overall etching rate of the through holes 920 in the first region A greater than the overall etching rate of the through holes 920 in the second region B, and the difference in the total thickness of the upper support layer makes the overall etching rate of the through holes 920 in the first region A less than the overall etching rate of the through holes 920 in the second region B. The etching rate of the through-holes 920 in the first region A and the second region B is opposite to that of the former, thereby improving the consistency of the etching rate of the through-holes 920 formed in the first region A and the second region B, balancing the depth loading effect caused by the formation of the through-hole array 920 with a pattern density smaller than that in the second region B in the first region A of the stacked structure 10 in the semiconductor device, so that the through-holes 920 in the first region A and the second region B can reach the surface of the substrate 100 at approximately the same time, and on the basis of reducing the etching damage to the substrate 100 and ensuring the performance of the substrate 100, the penetration of the through-holes 920 in the first region A and the second region B is ensured, thereby ensuring the path performance of the capacitor tube and other structures formed in the through-holes 920 later, reducing the scrap rate of the semiconductor device and improving its finished product yield.

[0052] In an embodiment of the present invention, among the upper supporting layers, the one at the top is the top supporting layer 710, and the rest are the middle supporting layers 510. The second region B of at least one middle supporting layer 510 is recessed relative to the first region A to form a first groove 511, and the first groove 511 is filled with a filling sacrificial layer 400, and the filling sacrificial layer 400 is an oxide layer not doped with ions. The number of supporting layers is greater than or equal to three. From bottom to top, the supporting layer at the bottom is the bottom supporting layer 210, the supporting layer at the top is the top supporting layer 710, and the supporting layer between the bottom supporting layer 210 and the top supporting layer 710 is the middle supporting layer 510. The second region B of at least one middle supporting layer 510 is thinned to reduce the total thickness of the upper supporting layer in the second region B. Specifically, the upper surface of the thinned middle supporting layer 510 is recessed relative to the first region A to form a first groove 511 with an opening facing upward, or the lower surface is recessed relative to the first region A to form a first groove 511 with an opening facing downward. Groove 511, an oxide layer not doped with ions is filled in the first groove 511 as a filling sacrificial layer 400, and the filling sacrificial layer 400 is a pure oxide layer. When the etching process conditions are constant, the etching rate of the filling sacrificial layer 400 is approximately a constant value, thereby improving the control of the etching rate of the filling sacrificial layer 400 and the entire second area B, and correspondingly improving the consistency of the etching rate of the through hole 920 formed in the first area A and the second area B. On the basis of reducing the etching damage to the substrate 100, the penetration of the through hole 920 formed in the first area A and the second area B is ensured, thereby ensuring the yield of the semiconductor device.

[0053] In the embodiment of the present invention, the bottom surface of the second region B of the top supporting layer 710 is recessed upward relative to the first region A to form a second groove 711. The sacrificial layer adjacent to and below the top supporting layer 710 is the top sacrificial layer 610, which includes a flat layer portion 611 and a partially upwardly protruding raised layer portion 612, which fills the second groove 711. The bottom surface of the second region B of the top supporting layer 710 is recessed relative to the first region A to form the second groove 711. While thinning the second region B of the top supporting layer 710, the flatness and consistency of the entire top surface of the top supporting layer 710 are ensured. The top sacrificial layer 610 is a unitary film layer, and its partially upwardly protruding raised layer portion 612 is provided to fill the second groove 711, ensuring the filling stability of the top supporting layer 710, thereby ensuring the support stability of the top supporting layer 710 and the entire stacked structure 10, and ensuring the formation stability of other device structures above the stacked structure 10.

[0054] In the embodiment of the present invention, the thickness of the second region B of each upper supporting layer is less than the thickness of the first region A. The thickness of the total thickness of the upper supporting layer in the second region B, which is reduced relative to the thickness of the first region A, is distributed among the upper supporting layers, and the thickness of the second region B of all upper supporting layers is thinned. On the basis of achieving the target thickness of the total thinning thickness, the thinning thickness of the second region B of each upper supporting layer is reduced to ensure the effective support of each upper supporting layer and the subsequent stability of the stacked structure 10. The situation in which the thickness thinning of the second region B of a single upper supporting layer is large, resulting in a large structural change, poor support strength of the second region B, and affecting the stability of the stacked structure 10 occurs.

[0055] In the embodiment of the present invention, the thickness of the second region B of the upper support layer is 20%-30% thinner than the thickness of the first region A. When the total thickness of the upper support layer in the second region B of the stacked structure 10 is reduced to the target thickness, the support strength of each second region B of the upper support layer is ensured, thereby ensuring the subsequent stability of the stacked structure 10.

[0056] Specifically, in the embodiment of the present invention, Figure 4I As shown, the stacked structure 10 includes a first supporting layer 220, a first sacrificial layer 300, a second supporting layer 520, a second sacrificial layer 620 and a third supporting layer 720 stacked in sequence from bottom to top, wherein the second region B of the second supporting layer 520 is recessed relative to the first region A to form a first groove 511, the first groove 511 is filled with a filling sacrificial layer 400, and the filling sacrificial layer 400 is an oxide layer not doped with ions; the bottom surface of the second region B of the third supporting layer 720 is recessed upward relative to the first region A to form a second groove 711, the second sacrificial layer 620 includes a flat layer portion 611 and a raised layer portion 612 that locally protrudes upward, and the raised layer portion 612 is filled in the second groove 711.

[0057] The first supporting layer 220 serves as the bottom supporting layer 210, the second supporting layer 520 serves as the middle supporting layer 510 in the upper supporting layer, the third supporting layer 720 serves as the top supporting layer 710 in the upper supporting layer, and the second sacrificial layer 620 serves as the top sacrificial layer 610; wherein, the first supporting layer 220, the second supporting layer 520 and the third supporting layer 720 are all nitride layers that are more difficult to etch, and the first sacrificial layer 300 and the second sacrificial layer 620 are both oxide layers that are less difficult to etch. Specifically, the first supporting layer 220 can be SiBN, the second supporting layer 520 can be SiCN, the third supporting layer 720 can be SiCN, the first sacrificial layer 300 can be BPSG, and the second sacrificial layer 620 can be TEOS.

[0058] like Figure 4IAs shown, the lower surface of the second region B of the second supporting layer 520 is concave relative to the first region A to form a first groove 511. A pure oxide layer without ions is filled in the first groove 511 as a filling sacrificial layer 400. This reduces the thickness of the second region B of the second supporting layer 520 and improves the control of the etching rate of the filling sacrificial layer 400 and the entire second region B. The lower surface of the second region B of the third supporting layer 720 is concave relative to the first region A to form a second groove 711. The raised layer portion 612 of the second sacrificial layer 620 is raised to fill the second groove 711. This reduces the thickness of the second region B of the third supporting layer 720 and ensures the support stability of the second sacrificial layer 620 for the third supporting layer 720. The second regions B of both the second supporting layer 520 and the third supporting layer 720 are thinned. While the overall thickness is reduced, the support strength of the second supporting layer 520 and the third supporting layer 720 is ensured, ensuring the stability of the stacked structure 10.

[0059] In an embodiment of the present invention, the stacked structure 10 includes an array region 11, a peripheral region 13, and a junction region 12 located therebetween, wherein the array region 11 serves as a first region A and the junction region 12 serves as a second region B. The stacked structure is applied to a capacitor structure in a semiconductor device, and the through-holes 920 formed in the array region 11 and the junction region 12 serve as capacitor holes, wherein the pattern density of the capacitor holes in the array region 11 is less than the pattern density of the capacitor holes in the junction region 12. At the same time, the total thickness of the upper support layer in the array region 11 is greater than the total thickness of the upper support layer in the junction region 12. In addition, the effect of the difference in the total thickness of the upper support layer in the array region 11 and the junction region 12 on the etching rate can balance the effect of the pattern density difference on the etching rate, thereby improving the consistency of the etching rate of the capacitor holes formed in the array region 11 and the junction region 12. On the basis of reducing etching damage to the substrate 100, the through-holes of the capacitor holes are ensured, thereby ensuring the path for the subsequent formation of the capacitor tube and ensuring the yield rate of the semiconductor device.

[0060] In the embodiment of the present invention, in addition to defining the interface region 12 as the second region B, the interface region 12 and a local area of ​​the peripheral region 13 adjacent to the interface region 12 are also defined as the second region B. Alternatively, the interface region 12 and the entire peripheral region 13 are defined as the second region B. Without affecting the film structure of the array region 11 and achieving thinning of the support layer on the interface region 12, the above configuration can increase the pattern size of the second region B, provide a wider process window, reduce processing difficulty, and improve processing accuracy when thinning the support layer in the second region B, depositing the filling sacrificial layer 400 in the second region B, and etching to form the raised layer portion 612 of the top sacrificial layer 610.

[0061] Figures 4A-4I Schematic diagram of the device structure of each step in the preparation process of the stacked structure provided by an embodiment of the present invention. Figure 6 Schematic diagram of a process for preparing a laminated structure 10 according to an embodiment of the present invention.

[0062] The embodiment of the present invention also provides a process for preparing a laminated structure 10, which is used to prepare Figure 4I The stacked structure 10 shown is as follows Figure 6 As shown, the preparation process includes:

[0063] S602 : sequentially forming a first supporting layer 220 , a first sacrificial layer 300 , and a patterned filling sacrificial layer 400 on the substrate 100 , wherein the filling sacrificial layer 400 covers the second region B of the first sacrificial layer 300 .

[0064] The substrate 100, the first supporting layer 220, the first sacrificial layer 300 and the patterned filling sacrificial layer 400 are sequentially stacked from bottom to top, wherein the first supporting layer 220 and the first sacrificial layer 300 are both non-patterned film layers with uniform thickness, and the filling sacrificial layer 400 is a film layer having an opening corresponding to the first area A; specifically, as Figure 4A As shown, a chemical vapor deposition (CVD) process may be used to sequentially deposit a first support layer 220, a second sacrificial layer 620, and a filling sacrificial layer 400, and a patterned first mask layer 810, such as a photoresist layer, may be formed on the filling sacrificial layer 400; Figure 4B As shown, the first mask layer 810 is used as a mask to etch the filling sacrificial layer 400 to pattern it, wherein the filling sacrificial layer 400 covers the second region B of the first sacrificial layer 300; Figure 4C As shown, the remaining first mask layer 810 is removed by oxidation or other processes.

[0065] S604 forms a second supporting layer 520 covering the first sacrificial layer 300 and filling the sacrificial layer 400 , and reduces the thickness of the second supporting layer 520 in the second region B.

[0066] like Figure 4D As shown, a second supporting layer 520 is deposited on the first sacrificial layer 300 and the filling sacrificial layer 400, wherein the film thickness of the second region B of the second supporting layer 520 is consistent with the film thickness of the first region A, and is recessed upward relative to the first region A to form a first groove 511, and the filling sacrificial layer 400 is filled in the first groove 511; Figure 4E As shown, a patterned second mask layer 820 is formed on the second support layer 520, wherein the second mask layer 820 covers the first area A of the second support layer 520; Figure 4FAs shown, the second mask layer 820 is used as a mask to etch and thin the second region B of the second support layer 520 to reduce the film thickness of the second region B of the second support layer 520; Figure 4G As shown, the second mask layer 820 is removed by oxidation or other processes.

[0067] S606 forms a second sacrificial layer 620 on the second supporting layer 520 , wherein the second region B of the second sacrificial layer 620 protrudes upward relative to the first region A to form a raised layer portion 612 .

[0068] Specifically, you can get the following Figure 4H The second sacrificial layer 620 shown is as follows: the second sacrificial layer 620 is deposited on the second supporting layer 520, and a patterned third mask layer is deposited on the second sacrificial layer 620, the third mask layer covering the second region B of the second sacrificial layer 620; the first region A of the second sacrificial layer 620 is etched and thinned using the third mask layer as a mask, and the third mask layer is removed, thereby obtaining the following: Figure 4H In the second sacrificial layer 620 shown, the portion of the second region B in the second sacrificial layer 620 that protrudes upward relative to the first region A serves as a raised layer portion 612 , and the remaining portion of the second sacrificial layer 620 serves as a flat layer portion 611 .

[0069] S608 : forming a third supporting layer 720 covering the second sacrificial layer 620 , and performing a chemical mechanical polishing (CMP) planarization process on the third supporting layer 720 to obtain a stacked structure 10 .

[0070] A third supporting layer 720 is deposited on the second sacrificial layer 620, and a chemical mechanical polishing and planarization process is performed on the surface of the third supporting layer 720 to planarize the surface, thereby obtaining the following: Figure 4I In the third supporting layer 720 and the stacked structure 10 shown, the second region B of the third supporting layer 720 is recessed relative to the first region A to form a second groove 711 , and the raised layer portion 612 fills the second groove 711 .

[0071] Figures 5A-5E Schematic diagram of the device structure of each step of etching to form a through hole 920 in the manufacturing process of the semiconductor device provided by an embodiment of the present invention. Figure 7 The figure is a schematic flow chart of a process for preparing a semiconductor device according to an embodiment of the present invention.

[0072] The embodiment of the present invention further provides a process for preparing a semiconductor device, for preparing the above-mentioned semiconductor device, such as Figure 7 As shown, the preparation process includes:

[0073] S702 provides a substrate 100 .

[0074] The base 100 may be a substrate or other structural layers formed on the substrate, or may include both the substrate and other structural layers formed on the substrate, wherein the substrate may provide a supporting foundation for other structural layers on the substrate.

[0075] S704 forms a stacked structure 10 on the substrate 100, and the stacked structure 10 includes supporting layers and sacrificial layers stacked alternately from bottom to top. Among the supporting layers, the one located at the bottom is the bottom supporting layer 210, and the rest are upper supporting layers; the stacked structure 10 includes a first area A and a second area B, and the total layer thickness of the upper supporting layer in the first area A is greater than the total layer thickness of the upper supporting layer in the second area B.

[0076] In the stacked structure 10, the upper supporting layer located above affects the etching rate when etching the through hole 920 before the bottom supporting layer 210. Relative to the total thickness of all upper supporting layers in the first area A, by thinning the total thickness of all upper supporting layers in the second area B and thickening the total thickness of all sacrificial layers in the second area B, on the basis of ensuring the overall uniformity of the thickness of the first area A and the second area B in the stacked structure 10, the total thickness of all upper supporting layers in the second area B is made smaller than the total thickness of all upper supporting layers in the first area A, so as to reduce the overall etching difficulty of the second area B and effectively improve the overall etching rate of the through hole 920 in the second area B.

[0077] S706: Patterning the stacked structure 10 to form a plurality of through holes 920 penetrating the stacked structure 10. The pattern density of the through holes 920 in the first region A is smaller than that in the second region B.

[0078] An array of through holes 920 is formed by synchronously etching the first region A and the second region B of the stacked structure 10, and the pattern density of the through holes 920 in the first region A is less than the pattern density of the through holes 920 in the second region B. In the process of etching to form the through holes 920, the etching rate of the through holes 920 is affected by both the depth micro-loading effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer. The depth micro-loading effect makes the overall etching rate of the through holes 920 in the first region A greater than the overall etching rate of the through holes 920 in the second region B, and the difference in the total thickness of the upper support layer makes the overall etching rate of the through holes 920 in the first region A less than the overall etching rate of the through holes 920 in the second region B. The latter has a greater impact on the etching difficulty of the first region A. The influence on the etching rate of the through hole 920 in the region A and the second region B is opposite to that of the former, thereby improving the consistency of the etching rate of the through hole 920 formed in the first region A and the second region B, balancing the depth load effect caused by the formation of the through hole 920 array with a pattern density smaller than that in the second region B in the first region A of the stacked structure 10 in the semiconductor device, so that the through holes 920 in the first region A and the second region B can reach the surface of the substrate 100 at approximately the same time, and on the basis of reducing the etching damage to the substrate 100 and ensuring the performance of the substrate 100, the penetration of the through holes 920 in the first region A and the second region B is ensured, thereby ensuring the path performance of the subsequent formation of the capacitor tube and other structures in the through hole 920, reducing the scrap rate of the semiconductor device and improving its finished product yield.

[0079] Specific to Figure 4I The steps of etching the stacked structure 10 to form the through hole 920 are as follows: Figure 5A As shown, the third supporting layer 720 is first etched, and the pattern density of the first region A (array region 11) is less than the pattern density of the second region B (junction region 12 and peripheral region 13). When the groove 910 formed in the first region A reaches the surface of the second sacrificial layer 620, since the thickness of the second region B of the third supporting layer 720 is smaller, and the increase in etching rate due to the thinning of the thickness of the third supporting layer 720 in the second region B is greater than the decrease in etching rate due to the pattern density difference, at this time, the groove 910 formed in the second region B has extended into the second sacrificial layer 620, and the extension depth is greater than the extension depth of the groove 910 in the first region A.

[0080] like Figure 5B As shown, the second sacrificial layer 620 is continuously etched. When the groove 910 formed in the first region A reaches the surface of the second sacrificial layer 620, the groove 910 formed in the second region B has penetrated the second supporting layer 520 and extended into the filling sacrificial layer 400. Continuing, as shown in FIG. Figure 5CAs shown, the second supporting layer 520 is etched. When the groove 910 formed in the first region A reaches the surface of the first sacrificial layer 300, the groove 910 formed in the second region B has penetrated the filling sacrificial layer 400 and extended into the first sacrificial layer 300; Figure 5D As shown, the first sacrificial layer 300 is continuously etched. When the groove 910 formed in the first region A reaches the surface of the first supporting layer 220, the groove 910 formed in the second region B has extended into the first supporting layer 220. Figure 5E As shown, the first supporting layer 220 continues to be etched, wherein the thickness of the first supporting layer 220 required to be etched in the first region A is greater than that in the second region B, and the pattern density of the groove 910 in the first region A is less than that in the second region B. Accordingly, the etching rate of the groove 910 in the first region A is greater than that in the second region B. Under the dual influence of the etching layer thickness and the etching rate, the grooves 910 in the first region A and the second region B can reach the surface of the substrate 100 at the same time, forming a through hole 920 that passes through the bottom, and the etching damage to the substrate 100 is relatively small.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A laminated structure, characterized in that: It comprises supporting layers and sacrificial layers alternately stacked from bottom to top, wherein the one at the bottom of the supporting layers is a bottom supporting layer (210) and the others are upper supporting layers; The region where the laminated structure (10) is located includes a first region (A) and a second region (B), and the total thickness of the upper support layer in the first region (A) is greater than the total thickness of the upper support layer in the second region (B).

2. The laminated structure according to claim 1, wherein: In each of the upper supporting layers, the thickness of the second region (B) is smaller than the thickness of the first region (A).

3. The laminated structure according to claim 2, wherein: The thickness of the second region (B) of the upper supporting layer is 20%-30% smaller than the thickness of the first region (A).

4. The laminated structure according to claim 1, wherein: Among the upper supporting layers, the one located at the top is a top supporting layer (710), and the rest are middle supporting layers (510); the second region (B) of at least one of the middle supporting layers (510) is recessed relative to the first region (A) to form a first groove (511); and the first groove (511) is filled with a filling sacrificial layer (400), and the filling sacrificial layer (400) is an oxide layer not doped with ions.

5. The laminated structure according to claim 1, wherein: Among the upper supporting layers, the one located at the top is a top supporting layer (710), and the bottom surface of the second region (B) of the top supporting layer (710) is recessed upward relative to the first region (A) to form a second groove (711); The sacrificial layer adjacent to the top supporting layer (710) is a top sacrificial layer (610), and the top sacrificial layer (610) includes a flat layer portion (611) and a raised layer portion (612) that partially protrudes upward, and the raised layer portion (612) is filled in the second groove (711).

6. The laminated structure according to claim 1, wherein: The stacked structure (10) comprises a first supporting layer (220), a first sacrificial layer (300), a second supporting layer (520), a second sacrificial layer (620), and a third supporting layer (720) stacked in sequence from bottom to top, wherein the second region (B) of the second supporting layer (520) is recessed relative to the first region (A) to form a first groove (511), the first groove (511) is filled with a filling sacrificial layer (400), and the filling sacrificial layer (400) is an oxide layer not doped with ions; The bottom surface of the second region (B) of the third supporting layer (720) is recessed upward relative to the first region (A) to form a second groove (711); the second sacrificial layer (620) includes a flat layer portion (611) and a raised layer portion (612) that partially protrudes upward; the raised layer portion (612) is filled in the second groove (711).

7. The laminated structure according to any one of claims 1 to 6, characterized in that: The stacked structure (10) comprises an array region (11), a peripheral region (13), and a boundary region (12) located therebetween, wherein the array region (11) serves as the first region (A); The boundary area (12) serves as the second region (B); or, the boundary area (12) and a local area of ​​the peripheral area (13) adjacent to the boundary area (12) serve as the second region (B); or, the boundary area (12) and the peripheral area (13) serve as the second region (B).

8. A semiconductor device, characterized in that: The invention comprises a substrate (100) and a laminated structure (10) according to any one of claims 1 to 7, wherein the laminated structure (10) is formed on the substrate (100), and the laminated structure (10) is formed with a plurality of through holes (920) extending downward to the surface of the substrate (100), wherein the pattern density of the through holes (920) in the first area (A) is less than the pattern density of the through holes (920) in the second area (B).

9. A process for preparing a laminated structure, characterized in that: For preparing the laminated structure (10) according to claim 6, the preparation process comprises: A first supporting layer (220), a first sacrificial layer (300), and a patterned filling sacrificial layer (400) are sequentially formed on a substrate (100), wherein the filling sacrificial layer (400) covers a second region (B) of the first sacrificial layer (300); forming a second supporting layer (520) covering the first sacrificial layer (300) and the filling sacrificial layer (400), and reducing the thickness of the second supporting layer (520) in the second region (B); forming a second sacrificial layer (620) on the second supporting layer (520), wherein a second region (B) of the second sacrificial layer (620) protrudes upward relative to the first region (A) to form a raised layer portion (612); A third supporting layer (720) covering the second sacrificial layer (620) is formed, and a chemical mechanical polishing and planarization process is performed on the third supporting layer (720) to obtain a stacked structure (10).

10. A process for preparing a semiconductor device, characterized in that: For preparing the semiconductor device according to claim 8, the preparation process comprises: providing a substrate (100); A stacked structure (10) is formed on the substrate (100), the stacked structure (10) comprising support layers and sacrificial layers alternately stacked from bottom to top, wherein one of the support layers located at the bottom is a bottom support layer (210) and the others are upper support layers; the stacked structure (10) comprises a first region (A) and a second region (B), the total thickness of the upper support layer in the first region (A) being greater than the total thickness of the upper support layer in the second region (B); The stacked structure (10) is patterned to form a plurality of through holes (920) penetrating the stacked structure (10), wherein a pattern density of the through holes (920) in the first region (A) is less than a pattern density of the through holes (920) in the second region (B).

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