Layered structures, semiconductor devices and their fabrication processes

Abstract

This invention provides a stacked structure, a semiconductor device, and its fabrication process, relating to the field of semiconductor technology. The stacked structure includes alternately stacked support layers and sacrificial layers from bottom to top. In the support layers, one layer at the bottom is called the bottom support layer, and the rest are upper support layers. The region where the stacked structure is located includes a first region and a second region. In the first region, the total thickness of the upper support layers is greater than the total thickness of the upper support layers in the second region. When this stacked structure is applied to a semiconductor device, the thinning of the support layer in the second region can improve the overall etching rate of vias in the second region. This balances the depth loading effect caused by the lower pattern density of vias in the first region compared to the second region. While reducing etching damage to the substrate, it ensures the connectivity of vias in the first and second regions, thereby reducing the scrap rate of the semiconductor device and improving its yield.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a stacked structure, a semiconductor device, and its fabrication process. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device widely used in computer systems, servers, and embedded systems. With the continuous iteration and development of DRAM technology, the structural integration of related products is constantly improving.

[0003] As an important structure in DRAM, the capacitor structure specifically includes a stacked structure formed by alternating stacks of multiple support layers and sacrificial layers. The stacked structure includes an array region, a peripheral region, and a boundary region located between the two. Capacitors are arranged in both the array region and the boundary region, and the pattern density of capacitors in the array region is less than that in the boundary region.

[0004] During the etching process to form capacitor vias, the difference in pattern density between the capacitor vias in the array region and the boundary region causes a depth loading effect. This results in the capacitor vias in the array region reaching the bottom of the stacked structure before the capacitor vias in the boundary region. If etching is stopped at this point, the capacitor vias in the boundary region will be in a closed state at the bottom, and the capacitors formed subsequently will be in an open circuit state. If etching continues until the capacitor vias in the boundary region reach the bottom of the stacked structure, it will cause etching damage to the substrate at the bottom of the capacitor vias in the array region. Both situations will lead to the scrapping of semiconductor devices and reduce the yield of finished products. Summary of the Invention

[0005] The purpose of this invention is to provide a semiconductor device and its fabrication process to solve the technical problem in the related art where, during the etching process to form capacitor holes, the bottom of the capacitor holes is prone to being incomplete or the substrate is damaged by etching, resulting in the scrapping of semiconductor devices and a reduction in the yield of finished products.

[0006] To address the aforementioned problems, the present invention provides a stacked structure comprising support layers and sacrificial layers stacked alternately from bottom to top, wherein one of the support layers at the bottom is a bottom support layer and the rest are upper support layers;

[0007] The region where the stacked structure is located includes a first region and a second region, wherein the total thickness of the upper support layer in the first region is greater than the total thickness of the upper support layer in the second region.

[0008] Optionally, in each of the upper support layers, the thickness of the second region is less than the thickness of the first region.

[0009] Optionally, the thickness of the second region of the upper support layer is 20%-30% smaller than the thickness of the first region.

[0010] Optionally, in the upper support layer, one of the top supports is a top support layer and the rest are middle support layers. The second region of at least one of the middle support layers is recessed relative to the first region to form a first groove, and the first groove is filled with a filling sacrificial layer, and the filling sacrificial layer is an oxide layer without ions.

[0011] Optionally, in the upper support layer, the one located at the top is the top support layer, and the bottom surface of the second region of the top support layer is recessed upward relative to the first region to form a second groove;

[0012] The sacrificial layer adjacent to the top support layer is the top sacrificial layer, which includes a flat layer and a partially upward-protruding raised layer, the raised layer filling the second groove.

[0013] Optionally, the stacked structure includes a first support layer, a first sacrificial layer, a second support layer, a second sacrificial layer and a third support layer stacked sequentially from bottom to top, wherein the second region of the second support layer is recessed relative to the first region to form a first groove, the first groove is filled with a filling sacrificial layer, and the filling sacrificial layer is an oxide layer without ions.

[0014] The bottom surface of the second region of the third support layer is recessed upward relative to the first region to form a second groove. The second sacrificial layer includes a flat layer and a partially upward-protruding raised layer, which fills the second groove.

[0015] Optionally, the stacked structure includes an array region, a peripheral region, and a boundary region between the two, wherein the array region serves as the first region;

[0016] The boundary area is designated as the second region; or, the boundary area and the peripheral area are designated as the second region, with a local area adjacent to the boundary area being the second region; or, the boundary area and the peripheral area are designated as the second region.

[0017] The present invention also provides a semiconductor device, including a substrate and the above-described stacked structure, the stacked structure being formed on the substrate, and the stacked structure having a plurality of vias extending downward to the surface of the substrate, wherein the pattern density of the vias in the first region is less than the pattern density of the vias in the second region.

[0018] The present invention also provides a process for preparing a laminated structure, the process comprising:

[0019] A first support layer, a first sacrificial layer, and a patterned fill sacrificial layer are sequentially formed on a substrate, wherein the fill sacrificial layer covers a second region of the first sacrificial layer;

[0020] A second support layer is formed to cover the first sacrificial layer and the filling sacrificial layer, and the thickness of the second support layer in the second region is reduced.

[0021] A second sacrificial layer is formed on the second support layer, wherein a second region of the second sacrificial layer protrudes upward relative to the first region to form a raised layer portion;

[0022] A third support layer is formed to cover the second sacrificial layer, and the third support layer is subjected to a chemical mechanical polishing planarization process to obtain a stacked structure.

[0023] The present invention also provides a process for fabricating a semiconductor device, for fabricating the above-mentioned semiconductor device, the process comprising:

[0024] Provide a base;

[0025] A stacked structure is formed on the substrate, the stacked structure including support layers and sacrificial layers stacked alternately from bottom to top, wherein one of the support layers at the bottom is a bottom support layer and the rest are upper support layers; the stacked structure includes a first region and a second region, wherein the total thickness of the upper support layers in the first region is greater than the total thickness of the upper support layers in the second region;

[0026] The stacked structure is patterned to form a plurality of through holes penetrating the stacked structure, wherein the pattern density of the through holes in the first region is less than the pattern density of the through holes in the second region.

[0027] The stacked structure provided by this invention is applied in semiconductor devices. In the stacked structure, the upper support layer affects the etching rate of vias before the bottom support layer. Relative to the total thickness of all upper support layers in the first region, by reducing the total thickness of all upper support layers in the second region and increasing the total thickness of all sacrificial layers in the second region, the total thickness of all upper support layers in the second region is less than that in the first region, while ensuring that the overall thickness of the first and second regions in the stacked structure is uniform. This reduces the overall etching difficulty of the second region and effectively improves the overall etching rate of vias in the second region.

[0028] In a multilayer structure, via arrays are formed simultaneously through etching in the first and second regions. The pattern density of vias in the first region is lower than that in the second region. During the etching process, the etching rate of the vias is simultaneously affected by both the depth micro-loading effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer. Specifically, the depth micro-loading effect makes the overall etching rate of vias in the first region greater than that in the second region, while the difference in the total thickness of the upper support layer makes the overall etching rate of vias in the first region less than that in the second region. The latter has a greater impact on the etching rate of vias in the first region. The etching rate of vias in the first and second regions has the opposite effect to that in the second region, thereby improving the consistency of the etching rate of vias formed in the first and second regions. This balances the depth loading effect caused by the formation of via arrays with a lower pattern density in the first region than in the second region in the stacked structure of semiconductor devices. This allows the vias in the first and second regions to reach the substrate surface approximately simultaneously. While reducing etching damage to the substrate and ensuring substrate performance, this ensures the connectivity of vias in the first and second regions, thereby ensuring the path performance of subsequent structures such as capacitors formed in the vias, reducing the scrap rate of semiconductor devices, and improving their finished product yield. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the device structure when the stacked structure of the related technology is formed on the substrate;

[0031] Figure 2 This is a schematic diagram of the target device structure for semiconductor devices in related technologies;

[0032] Figure 3 This is a schematic diagram of the actual device structure of semiconductor devices related to the technology;

[0033] Figure 4A-4I This is a schematic diagram of the device structure in each step of the fabrication process of the stacked structure provided in the embodiments of the present invention, wherein, Figure 4I This is a schematic diagram of the device structure when the stacked structure is formed on the substrate, as provided in an embodiment of the present invention;

[0034] Figures 5A-5E This is a schematic diagram of the device structure for each step of etching to form a through-hole in the fabrication process of a semiconductor device provided in an embodiment of the present invention. Figure 5EA schematic diagram of the device structure of a semiconductor device provided in an embodiment of the present invention;

[0035] Figure 6 This is a schematic flowchart of the fabrication process of the laminated structure provided in an embodiment of the present invention;

[0036] Figure 7 This is a schematic flowchart of the fabrication process of a semiconductor device according to an embodiment of the present invention.

[0037] Explanation of reference numerals in the attached figures:

[0038] 10-Layered structure; A-First region; 11-Array region; B-Second region; 12-Boundary region; 13-Outer region; 100-Substrate; 210-Bottom support layer; 220-First support layer; 300-First sacrificial layer; 400-Fill sacrificial layer; 510-Middle support layer; 511-First groove; 520-Second support layer; 610-Top sacrificial layer; 611-Planar layer; 612-Protruding layer; 620-Second sacrificial layer; 710-Top support layer; 711-Second groove; 720-Third support layer; 810-First mask layer; 820-Second mask layer; 910-Trench; 920-Through hole. Detailed Implementation

[0039] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0040] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0042] Figure 1 This is a schematic diagram of the device structure when the stacked structure 10 of the related technology is formed on the substrate 100. Figure 2 This is a schematic diagram of the target device structure for semiconductor devices in related technologies. Figure 3 This is a schematic diagram of the actual device structure of semiconductor devices related to the technology.

[0043] In related technologies, such as Figure 1 The stacked structure 10 shown in the view includes a first support layer 220, a first sacrificial layer 300, a second support layer 520, a second sacrificial layer 620 and a third support layer 720 stacked from bottom to top. The area where the stacked structure 10 is located includes an array area 11, a peripheral area 13 and a boundary area 12 located between the two.

[0044] Multiple capacitor vias (through-holes 920) extending along their stacking direction and arranged in an array are formed in the array region 11 and the boundary region 12 of the stacked structure 10, wherein the pattern density of capacitor vias in the array region 11 is less than the pattern density of capacitor vias in the boundary region 12; for example Figure 2 As shown, ideally, the etching depths of the capacitor holes in array region 11 and boundary region 12 are consistent, allowing them to reach the bottom surface of the first support layer 220 approximately simultaneously. This reduces etching damage to the substrate 100 and ensures the continuity of the capacitors formed within the capacitor holes, thereby reducing the scrap rate of semiconductor devices and improving their yield. However, during the simultaneous etching of capacitor holes in array region 11 and boundary region 12, the depth loading effect is caused by the lower pattern density of capacitor holes in array region 11 compared to boundary region 12. Consequently, the etching rate of capacitor holes in array region 11 is higher than that in boundary region 12. Figure 3As shown, the capacitor vias in the array region 11 first reach the surface of the substrate 100. At this time, the bottom of the capacitor vias in the boundary region 12 has not reached the substrate 100 and is in a closed state. If etching is stopped at this time, the capacitors formed in the capacitor vias in the boundary region 12 will be in an open circuit state, resulting in invalid stored charge and inability to connect with the MOS structure of the substrate 100, which will lead to the scrapping of the semiconductor device and a reduction in the yield of the finished product. If etching continues until the capacitor vias in the boundary region 12 reach the bottom of the stacked structure 10, the capacitor vias in the array region 11 will cause etching damage to the substrate 100, affecting its performance and leading to the scrapping of the semiconductor device and a reduction in the yield of the finished product.

[0045] This embodiment provides a stacked structure 10. Compared to the total thickness of the support layer 510 in the first region A, the total thickness of the support layer 510 in the second region B is reduced to balance the depth loading effect caused by the formation of a via 920 array with a lower pattern density in the first region A than in the second region B. This allows the vias 920 in the first and second regions A and B to reach the surface of the substrate 100 approximately simultaneously. While reducing etching damage to the substrate 100 and ensuring its performance, this also ensures the connectivity of the vias 920 in the first and second regions B, thereby ensuring the pathway performance for subsequent structures such as capacitors formed within the vias 920. This reduces the scrap rate of the semiconductor device and improves its yield. The stacked structure 10 and the semiconductor device provided in this embodiment will be further described in detail below with reference to the accompanying drawings.

[0046] Figure 4I This is a schematic diagram of the device structure when the stacked structure 10 provided in the embodiment of the present invention is formed on the substrate 100. Figure 5E This is a schematic diagram of the device structure of a semiconductor device provided in an embodiment of the present invention.

[0047] This embodiment provides a stacked structure 10, such as Figure 4I As shown, the structure includes support layers and sacrificial layers stacked alternately from bottom to top. Among the support layers, the one at the bottom is the bottom support layer 210, and the rest are upper support layers. The area where the stacked structure 10 is located includes a first region A and a second region B. The total thickness of the upper support layers in the first region A is greater than the total thickness of the upper support layers in the second region B.

[0048] This embodiment also provides a semiconductor device, such as Figure 5E As shown, the structure includes a substrate 100 and the aforementioned stacked structure 10. The stacked structure is formed on the substrate 100, and the stacked structure 10 has a plurality of through holes 920 extending downward to the surface of the substrate 100. The pattern density of the through holes 920 in the first region A is less than the pattern density of the through holes 920 in the second region B.

[0049] The stacked structure 10 provided in this embodiment includes alternately stacked support layers and sacrificial layers. The film layer at the bottom is the support layer, and this support layer is defined as the bottom support layer 210. The remaining support layers above the bottom support layer 210 are defined as the upper support layers. The etching difficulty of the support layer is greater than that of the sacrificial layer. Under the same etching process conditions, the etching rate of the support layer is less than that of the sacrificial layer.

[0050] In the stacked structure 10, the upper support layer affects the etching rate of the via 920 before the bottom support layer 210. Relative to the total thickness of all upper support layers in the first region A, by thinning the total thickness of all upper support layers in the second region B and simultaneously thickening the total thickness of all sacrificial layers in the second region B, while ensuring that the overall thickness of the first region A and the second region B in the stacked structure 10 is uniform, the total thickness of all upper support layers in the second region B is less than the total thickness of all upper support layers in the first region A, thereby reducing the overall etching difficulty of the second region B and effectively improving the overall etching rate of the via 920 in the second region B.

[0051] When the stacked structure 10 is applied to a semiconductor device, an array of vias 920 is formed simultaneously in the first region A and the second region B of the stacked structure 10. The pattern density of the vias 920 in the first region A is less than that in the second region B. During the etching process of forming the vias 920, the etching rate of the vias 920 is simultaneously affected by both the depth micro-loading effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer. Specifically, the depth micro-loading effect makes the overall etching rate of the vias 920 in the first region A greater than that in the second region B, while the difference in the total thickness of the upper support layer makes the overall etching rate of the vias 920 in the first region A less than that in the second region B. The etching rate, which has the opposite effect on the etching rate of vias 920 in the first region A and the second region B, improves the consistency of the etching rate of vias 920 formed in the first region A and the second region B. This balances the depth loading effect caused by the formation of a via 920 array with a lower pattern density in the first region A of the stacked structure 10 in the semiconductor device than in the second region B. This allows the vias 920 in the first region A and the second region B to reach the surface of the substrate 100 approximately simultaneously. While reducing etching damage to the substrate 100 and ensuring the performance of the substrate 100, this ensures the continuity of the vias 920 in the first region A and the second region B. This, in turn, ensures the path performance of subsequent structures such as capacitors formed in the vias 920, reduces the scrap rate of semiconductor devices, and improves their finished product yield.

[0052] In this embodiment of the invention, in the upper support layer, one of the top supports is a top support layer 710, and the rest are middle support layers 510. At least one middle support layer 510 has a second region B recessed relative to the first region A to form a first groove 511, and the first groove 511 is filled with a sacrificial filling layer 400, which is an oxide layer without ions. The number of support layers is greater than or equal to three. Along the bottom-up direction, the support layer at the bottom is the bottom support layer 210, the support layer at the top is the top support layer 710, and the support layer between the bottom support layer 210 and the top support layer 710 is the middle support layer 510. The second region B of at least one middle support layer 510 is thinned to reduce the total thickness of the upper support layer in the second region B. Specifically, the upper surface of the thinned middle support layer 510 is recessed relative to the first region A to form an upward-facing first groove 511, or the lower surface is recessed relative to the first region A to form a downward-facing first groove 511. The first groove 511 is filled with an oxide layer without ions as a filler sacrificial layer 400. The filler sacrificial layer 400 is a pure oxide layer. When the etching process conditions are constant, the etching rate of the filler sacrificial layer 400 is approximately constant, thereby improving the control of the etching rate of the filler sacrificial layer 400 and the entire second region B. Correspondingly, the consistency of the etching rate of the via 920 formed in the first region A and the second region B is improved. On the basis of reducing the etching damage to the substrate 100, the continuity of the via 920 formed in the first region A and the second region B is ensured, thereby ensuring the yield of semiconductor devices.

[0053] In this embodiment of the invention, the bottom surface of the second region B of the top support layer 710 is recessed upward relative to the first region A to form a second groove 711; the sacrificial layer adjacent to the bottom of the top support layer 710 is a top sacrificial layer 610, which includes a flat layer portion 611 and a partially upward-protruding protruding layer portion 612, the protruding layer portion 612 filling the second groove 711. The bottom surface of the second region B of the top support layer 710 is recessed upward relative to the first region A to form the second groove 711, which ensures the flatness and consistency of the entire top surface of the top support layer 710 while achieving the thinning of the second region B of the top support layer 710; the top sacrificial layer 610 is an integral film layer, and its partially upward-protruding protruding layer portion 612 fills the second groove 711 to ensure the filling stability of the top support layer 710, thereby ensuring the support stability of the top support layer 710 and the entire stacked structure 10, and ensuring the formation stability of other device structures above the stacked structure 10.

[0054] In this embodiment of the invention, the thickness of the second region B in each upper support layer is less than the thickness of the first region A. The reduction in the total thickness of the upper support layer in the second region B relative to the first region A is distributed across each upper support layer. The thickness of the second region B in all upper support layers is reduced. While achieving the target thickness, the reduction in the thickness of the second region B in each upper support layer is kept small to ensure the effective support function of each upper support layer and the subsequent stability of the laminated structure 10. This reduces the likelihood of a large reduction in the thickness of the second region B of a single upper support layer, leading to significant structural changes and poor support strength in the second region B, which could affect the stability of the laminated structure 10.

[0055] In this embodiment of the invention, the thickness of the second region B of the upper support layer is 20%-30% smaller than the thickness of the first region A. Based on the reduction of the total thickness of the upper support layer in the second region B of the laminated structure 10 to the target thickness, the support strength of each second region B of the upper support layer is ensured, thus ensuring the subsequent stability of the laminated structure 10.

[0056] Specifically, in the embodiments of the present invention, such as Figure 4I As shown, the stacked structure 10 includes a first support layer 220, a first sacrificial layer 300, a second support layer 520, a second sacrificial layer 620, and a third support layer 720 stacked sequentially from bottom to top. The second region B of the second support layer 520 is recessed relative to the first region A to form a first groove 511. The first groove 511 is filled with a filling sacrificial layer 400, which is an oxide layer without ions. The bottom surface of the second region B of the third support layer 720 is recessed upward relative to the first region A to form a second groove 711. The second sacrificial layer 620 includes a flat layer portion 611 and a partially upwardly protruding protruding layer portion 612, which is filled in the second groove 711.

[0057] The first support layer 220 serves as the bottom support layer 210, the second support layer 520 serves as the middle support layer 510 in the upper support layer, the third support layer 720 serves as the top support layer 710 in the upper support layer, and the second sacrificial layer 620 serves as the top sacrificial layer 610. Among them, the first support layer 220, the second support layer 520 and the third support layer 720 are all nitride layers that are difficult to etch, and the first sacrificial layer 300 and the second sacrificial layer 620 are both oxide layers that are easier to etch. Specifically, the first support layer 220 can be SiBN, the second support layer 520 can be SiCN, the third support layer 720 can be SiCN, the first sacrificial layer 300 can be BPSG, and the second sacrificial layer 620 can be TEOS.

[0058] like Figure 4IAs shown, the lower surface of the second region B of the second support layer 520 is recessed relative to the first region A to form a first groove 511. A pure oxide layer without ions is filled within the first groove 511 as a sacrificial filling layer 400. This reduces the film thickness of the second region B of the second support layer 520 and improves control over the etching rate of the sacrificial filling layer 400 and the entire second region B. Similarly, the lower surface of the second region B of the third support layer 720 is recessed relative to the first region A to form a second groove 711. The protruding portion 612 of the second sacrificial layer 620 protrudes upward to fill the second groove 711. This reduces the film thickness of the second region B of the third support layer 720 and ensures the support stability of the second sacrificial layer 620 for the third support layer 720. Both the second region B of the second support layer 520 and the third support layer 720 are thinned. This ensures the support strength of the second support layer 520 and the third support layer 720 while achieving the total thinning thickness, thus ensuring the stability of the stacked structure 10.

[0059] In this embodiment of the invention, the stacked structure 10 includes an array region 11, a peripheral region 13, and a boundary region 12 located between them. The array region 11 serves as a first region A, and the boundary region 12 serves as a second region B. The stacked structure is applied to a capacitor structure in a semiconductor device. Vias 920 formed in the array region 11 and the boundary region 12 serve as capacitor vias. The pattern density of the capacitor vias in the array region 11 is less than that in the boundary region 12. Simultaneously, the total thickness of the upper support layer in the array region 11 is greater than that in the boundary region 12. The difference in the total thickness of the upper support layer between the array region 11 and the boundary region 12 balances the effect of the pattern density difference on the etching rate, thereby improving the consistency of the etching rate for the capacitor vias formed in the array region 11 and the boundary region 12. This reduces etching damage to the substrate 100 while ensuring the continuity of the capacitor vias, thus ensuring the path for subsequent capacitor formation and guaranteeing the yield of the semiconductor device.

[0060] In this embodiment of the invention, in addition to designating the boundary region 12 as the second region B, the local areas of the boundary region 12 and the peripheral region 13 adjacent to the boundary region 12 are also designated as the second region B. Alternatively, the boundary region 12 and the entire peripheral region 13 are designated as the second region B. Without affecting the film structure of the array region 11 and achieving the thinning of the support layer on the boundary region 12, the above-mentioned configuration can increase the pattern size of the second region B. When thinning the support layer of the second region B, depositing the filling sacrificial layer 400 in the second region B, and etching the protruding layer 612 of the top sacrificial layer 610, the process window is larger, the processing difficulty is reduced, and the processing accuracy is improved.

[0061] Figure 4A-4I This is a schematic diagram of the device structure in each step of the fabrication process of the stacked structure provided in the embodiment of the present invention. Figure 6 This is a schematic flowchart of the fabrication process of the laminated structure 10 provided in an embodiment of the present invention.

[0062] This invention also provides a process for preparing a laminated structure 10, used to prepare such a laminated structure 10. Figure 4I The stacked structure 10 shown is as follows: Figure 6 As shown, the preparation process includes:

[0063] S602 A first support layer 220, a first sacrificial layer 300 and a patterned filling sacrificial layer 400 are sequentially formed on the substrate 100, wherein the filling sacrificial layer 400 covers the second region B of the first sacrificial layer 300.

[0064] A substrate 100, a first support layer 220, a first sacrificial layer 300, and a patterned filling sacrificial layer 400 are sequentially stacked from bottom to top. The first support layer 220 and the first sacrificial layer 300 are both uniformly thick, unpatterned films, and the filling sacrificial layer 400 is a film with openings corresponding to the first region A. Specifically, as shown... Figure 4A As shown, a first support layer 220, a second sacrificial layer 620, and a filler sacrificial layer 400 can be sequentially deposited using a chemical vapor deposition (CVD) process, and a patterned first mask layer 810, such as a photoresist layer, can be formed on the filler sacrificial layer 400; Figure 4B As shown, using the first mask layer 810 as a mask, the filling sacrificial layer 400 is etched to pattern it, wherein the filling sacrificial layer 400 covers the second region B of the first sacrificial layer 300; as Figure 4C As shown, the remaining first mask layer 810 is removed by processes such as oxidation.

[0065] S604 forms a second support layer 520 covering the first sacrificial layer 300 and the filling sacrificial layer 400, and thins the layer thickness of the second support layer 520 in the second region B.

[0066] like Figure 4D As shown, a second support layer 520 is deposited on the first sacrificial layer 300 and the filling sacrificial layer 400, wherein the film thickness of the second region B of the second support layer 520 is the same as the film thickness of the first region A, and it is recessed upward relative to the first region A to form a first groove 511, and the filling sacrificial layer 400 fills the first groove 511; as Figure 4E As shown, a patterned second mask layer 820 is formed on the second support layer 520, wherein the second mask layer 820 covers the first region A of the second support layer 520; as Figure 4FAs shown, using the second mask layer 820 as a mask, the second region B of the second support layer 520 is etched and thinned to reduce the film thickness of the second region B of the second support layer 520; as Figure 4G As shown, the second mask layer 820 is removed by processes such as oxidation.

[0067] S606 forms a second sacrificial layer 620 on the second support layer 520, wherein the second region B of the second sacrificial layer 620 protrudes upward relative to the first region A to form a protruding layer portion 612.

[0068] Specifically, this can be obtained through the following steps: Figure 4H The second sacrificial layer 620 shown is deposited on the second support layer 520, and a patterned third mask layer is deposited on the second sacrificial layer 620, covering the second region B of the second sacrificial layer 620; using the third mask layer as a mask, the first region A of the second sacrificial layer 620 is etched and thinned, and the third mask layer is removed, thereby obtaining the following... Figure 4H The second sacrificial layer 620 shown has a raised portion 612 in which the second region B protrudes upward relative to the first region A, and the remaining portion of the second sacrificial layer 620 is a flat portion 611.

[0069] S608 forms a third support layer 720 covering the second sacrificial layer 620, and performs a chemical mechanical polishing planarization process on the third support layer 720 to obtain a stacked structure 10.

[0070] A third support layer 720 is deposited on the second sacrificial layer 620, and its surface is planarized by chemical mechanical polishing to achieve the desired surface shape. Figure 4I The third support layer 720 and the stacked structure 10 shown are provided, wherein the second region B of the third support layer 720 is recessed relative to the first region A to form a second groove 711, and the protruding layer portion 612 fills the second groove 711.

[0071] Figures 5A-5E This is a schematic diagram of the device structure for each step of etching to form a through-hole 920 in the fabrication process of the semiconductor device provided in this embodiment of the invention. Figure 7 This is a schematic flowchart of the fabrication process of a semiconductor device according to an embodiment of the present invention.

[0072] This invention also provides a semiconductor device fabrication process for fabricating the aforementioned semiconductor device, such as... Figure 7 As shown, the preparation process includes:

[0073] S702 provides substrate 100.

[0074] The substrate 100 may be a substrate or other structural layers formed on the substrate, or may include both a substrate and other structural layers formed on the substrate, wherein the substrate may provide a supporting foundation for other structural layers on the substrate.

[0075] S704 A stacked structure 10 is formed on the substrate 100. The stacked structure 10 includes support layers and sacrificial layers stacked alternately from bottom to top. Among the support layers, one at the bottom is the bottom support layer 210, and the rest are upper support layers. The stacked structure 10 includes a first region A and a second region B. The total thickness of the upper support layers in the first region A is greater than the total thickness of the upper support layers in the second region B.

[0076] In the stacked structure 10, the upper support layer affects the etching rate of the via 920 before the bottom support layer 210. Relative to the total thickness of all upper support layers in the first region A, by thinning the total thickness of all upper support layers in the second region B and simultaneously thickening the total thickness of all sacrificial layers in the second region B, while ensuring that the overall thickness of the first region A and the second region B in the stacked structure 10 is uniform, the total thickness of all upper support layers in the second region B is less than the total thickness of all upper support layers in the first region A, thereby reducing the overall etching difficulty of the second region B and effectively improving the overall etching rate of the via 920 in the second region B.

[0077] S706 patterning process is performed on the stacked structure 10 to form a plurality of through holes 920 penetrating the stacked structure 10, wherein the pattern density of the through holes 920 in the first region A is less than the pattern density of the through holes 920 in the second region B.

[0078] In the stacked structure 10, a via 920 array is formed simultaneously by etching in the first region A and the second region B. The pattern density of the via 920 in the first region A is less than that in the second region B. During the etching process of forming the via 920, the etching rate of the via 920 is simultaneously affected by the depth micro-loading effect caused by the difference in pattern density and the etching difficulty caused by the difference in the total thickness of the upper support layer. The depth micro-loading effect makes the overall etching rate of the via 920 in the first region A greater than that in the second region B, while the difference in the total thickness of the upper support layer makes the overall etching rate of the via 920 in the first region A less than that in the second region B. The latter has a greater impact on the etching difficulty of the first region A. The etching rate of vias 920 in regions A and B has the opposite effect to that in the former, thereby improving the consistency of the etching rate of vias 920 formed in regions A and B. This balances the depth loading effect caused by the formation of a via 920 array with a lower pattern density in region A of the stacked structure 10 in the semiconductor device than in region B. This allows the vias 920 in regions A and B to reach the surface of the substrate 100 approximately simultaneously. While reducing etching damage to the substrate 100 and ensuring the performance of the substrate 100, this ensures the continuity of the vias 920 in regions A and B, thereby ensuring the pathway performance of subsequent structures such as capacitors formed in the vias 920, reducing the scrap rate of semiconductor devices, and improving their yield.

[0079] Specifically for Figure 4I The steps for etching the stacked structure 10 to form the through hole 920 are as follows: Figure 5A As shown, the third support layer 720 is first etched. The pattern density of the first region A (array region 11) is less than that of the second region B (boundary region 12 and peripheral region 13). When the trench 910 formed in the first region A reaches the surface of the second sacrificial layer 620, since the thickness of the second region B of the third support layer 720 is smaller, and the effect of the thinning of the third support layer 720 in the second region B on the etching rate is greater than the effect of the difference in pattern density on the etching rate, at this time, the trench 910 formed in the second region B has extended into the second sacrificial layer 620, and the extension depth is greater than the extension depth of the trench 910 in the first region A.

[0080] like Figure 5B As shown, etching continues on the second sacrificial layer 620. When the trench 910 formed in the first region A reaches the surface of the second sacrificial layer 620, the trench 910 formed in the second region B has penetrated the second support layer 520 and extended into the filling sacrificial layer 400; continuing, as... Figure 5CAs shown, the second support layer 520 is etched. When the trench 910 formed in the first region A reaches the surface of the first sacrificial layer 300, the trench 910 formed in the second region B has penetrated and filled the sacrificial layer 400 and extended into the first sacrificial layer 300; as shown Figure 5D As shown, etching continues on the first sacrificial layer 300. When the trench 910 formed in the first region A reaches the surface of the first support layer 220, the trench 910 formed in the second region B has extended into the first support layer 220; continuing, as... Figure 5E As shown, the first support layer 220 is etched further. The thickness of the first support layer 220 to be etched in the first region A is greater than that in the second region B. The pattern density of the trenches 910 in the first region A is less than that in the second region B. Correspondingly, the etching rate of the trenches 910 in the first region A is greater than that in the second region B. Under the dual influence of the etching layer thickness and the etching rate, the trenches 910 in the first region A and the second region B can reach the surface of the substrate 100 at the same time, forming a through hole 920 with a bottom through-hole, and the etching damage to the substrate 100 is small.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A stacked structure, characterized by, The stack structure (10) comprises support layers and sacrificial layers which are alternately stacked from bottom to top, and the etching rate of the support layers is less than that of the sacrificial layers under the same etching process condition; one of the support layers at the bottom is a bottom support layer (210), and the rest are upper support layers, and the bottom support layer (210) is a film layer with uniform thickness and without patterning. The area where the stack structure (10) is located comprises a first area (A) and a second area (B) with uniform thickness, the total layer thickness of the upper support layers in the first area (A) is greater than that in the second area (B), and when the first area (A) and the second area (B) are applied to a semiconductor device, the pattern density of the through holes (920) in the first area (A) is less than that in the second area (B).

2. The laminate structure of claim 1, wherein The layer thickness of the second area (B) of each of the upper support layers is less than that of the first area (A).

3. The laminate structure of claim 2, wherein, The layer thickness of the second area (B) of the upper support layers is 20%-30% less than that of the first area (A).

4. The laminate structure of claim 1, wherein One of the upper support layers at the top is a top support layer (710), and the rest are middle support layers (510), the second area (B) of at least one of the middle support layers (510) is recessed relative to the first area (A) to form a first recess (511), and the first recess (511) is filled with a filling sacrificial layer (400), and the filling sacrificial layer (400) is an ion-un-doped oxide layer.

5. The stacked structure of claim 1, wherein One of the upper support layers at the top is a top support layer (710), and the bottom surface of the second area (B) of the top support layer (710) is recessed upward relative to the first area (A) to form a second recess (711). The sacrificial layer adjacent to the bottom of the top support layer (710) is a top sacrificial layer (610), and the top sacrificial layer (610) comprises a flat layer part (611) and a locally upwardly protruding protruding layer part (612), and the protruding layer part (612) is filled in the second recess (711).

6. The stacked structure of claim 1, wherein The stack structure (10) comprises a first support layer (220), a first sacrificial layer (300), a second support layer (520), a second sacrificial layer (620) and a third support layer (720) which are sequentially stacked from bottom to top, wherein the second area (B) of the second support layer (520) is recessed relative to the first area (A) to form a first recess (511), the first recess (511) is filled with a filling sacrificial layer (400), and the filling sacrificial layer (400) is an ion-un-doped oxide layer; The bottom surface of the second area (B) of the third support layer (720) is recessed upward relative to the first area (A) to form a second recess (711), and the second sacrificial layer (620) comprises a flat layer part (611) and a locally upwardly protruding protruding layer part (612), and the protruding layer part (612) is filled in the second recess (711).

7. The laminate structure according to any one of claims 1 to 6, characterized in that The stack structure (10) comprises an array region (11), a peripheral region (13), and an interface region (12) between the two, wherein the array region (11) is the first region (A); The interface region (12) is the second region (B); or, the interface region (12) and the local region of the peripheral region (13) adjacent to the interface region (12) are the second region (B); or, the interface region (12) and the peripheral region (13) are the second region (B).

8. A semiconductor device, characterized by A substrate (100) and the stack structure (10) of any one of claims 1-7, the stack structure (10) is formed on the substrate (100), and the stack structure (10) is formed with a plurality of through holes (920) extending downward to the surface of the substrate (100), wherein the pattern density of the through holes (920) in the first region (A) is less than the pattern density of the through holes (920) in the second region (B).

9. A process for producing a laminated structure, characterized by A preparation process for preparing the stack structure (10) of claim 6, the preparation process comprising: sequentially forming a first support layer (220), a first sacrificial layer (300), and a patterned filling sacrificial layer (400) on a substrate (100), wherein the filling sacrificial layer (400) covers the second region (B) of the first sacrificial layer (300); forming a second support layer (520) covering the first sacrificial layer (300) and the filling sacrificial layer (400), and thinning the layer thickness of the second region (B) where the second support layer (520) is located; forming a second sacrificial layer (620) on the second support layer (520), wherein the second region (B) of the second sacrificial layer (620) protrudes upward relative to the first region (A) to form a protruding layer portion (612); forming a third support layer (720) covering the second sacrificial layer (620), and performing a chemical mechanical polishing planarization process on the third support layer (720) to obtain the stack structure (10).

10. A process for producing a semiconductor device, characterized by, A preparation process for preparing the semiconductor device of claim 8, the preparation process comprising: providing a substrate (100); forming a stack structure (10) on the substrate (100), the stack structure (10) comprising support layers and sacrificial layers stacked alternately from bottom to top, among the support layers, one at the bottom is a bottom support layer (210), and the rest are upper support layers; the stack structure (10) comprises a first region (A) and a second region (B), and the total layer thickness of the upper support layers in the first region (A) is greater than the total layer thickness of the upper support layers in the second region (B); performing a patterning process on the stack structure (10) to form a plurality of through holes (920) penetrating through the stack structure (10), wherein the pattern density of the through holes (920) in the first region (A) is less than the pattern density of the through holes (920) in the second region (B).

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