Semiconductor structure for three-dimensional memory and manufacturing method thereof
By removing the nitride layer in the peripheral area of the three-dimensional memory and adopting an oxide layer and a dummy pillar structure, the problem of threshold voltage shift after thermal treatment is solved, and the performance and reliability of the memory are improved.
Patent Information
- Application Number
- CN202410458009.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-27
- Filing Date
- 2024-04-16
- Publication Date
- 2025-09-30
AI Technical Summary
After thermal treatment of conventional three-dimensional flash memory devices, hydrogen in the nitride layer can cause threshold voltage shift of P-type metal oxide semiconductor transistors, affecting memory performance.
The nitride layer is removed from the peripheral area of the three-dimensional memory, and the presence of the nitride layer is avoided by forming an oxide layer and a dummy pillar structure, thereby reducing the impact on the circuit structure layer after heat treatment.
The problem of threshold voltage shift of the P-type metal oxide semiconductor transistor caused by the nitride layer is effectively avoided, thereby improving the performance and reliability of the memory.
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Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure for a three-dimensional memory and a manufacturing method thereof. Background Art
[0002] Non-volatile memory (such as flash memory) is widely used in personal computers and other electronic devices because it preserves stored data even after a power outage. Advances in process technology, circuit design, and programming algorithms have significantly reduced the size of memory components, enabling higher levels of integration.
[0003] However, due to process limitations, the size of traditional planar memory devices is no longer able to meet the demand for scaling. Therefore, current research and development of three-dimensional flash memory devices (3D memory devices) has evolved the memory device type from a two-dimensional memory device with a planar gate structure to a three-dimensional memory device with a vertical channel (VC) structure.
[0004] In current 3D flash memory device manufacturing processes, hydrogen contained in the nitride layer in the peripheral region after thermal treatment can cause threshold voltage shifting in P-type metal-oxide-semiconductor (MOS) transistors.
[0005] Therefore, as the size of electronic devices continues to shrink and users' requirements for the performance of electronic devices continue to increase, those skilled in the art continue to improve the size and performance of memory devices used in electronic devices. Summary of the Invention
[0006] The present disclosure provides a semiconductor structure for a three-dimensional memory and a manufacturing method thereof, wherein a nitride layer in a peripheral region surrounding a memory element region is removed to solve the problem of threshold voltage shifting caused by the nitride layer on a P-type metal oxide semiconductor transistor after thermal treatment.
[0007] The semiconductor structure for a three-dimensional memory disclosed herein includes a substrate, a circuit structure layer, a first conductive layer, a stacked structure, an oxide layer, a first insulating wall, and a plurality of first dummy pillars. The substrate has a storage element region and a peripheral region surrounding the storage element region, and the storage element region includes a storage array region and a stepped region. The circuit structure layer is disposed on the substrate. The first conductive layer is disposed on the circuit structure layer. The stacked structure is disposed on the first conductive layer in the storage element region and includes a plurality of second conductive layers and a plurality of insulating layers stacked alternately, and the stacked structure in the stepped region has a stepped profile. The oxide layer is disposed on the first conductive layer and surrounds the stacked structure. The first insulating wall is disposed in the oxide layer and penetrates the first conductive layer and surrounds the stacked structure. The plurality of first dummy pillars are disposed in the peripheral region and the stepped region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the stepped region penetrates the stacked structure and the first conductive layer.
[0008] In an embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, the structure further includes a plurality of support pillars disposed in the stepped region and penetrating the stacked structure and the first conductive layer.
[0009] In one embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, the structure further includes a plurality of second insulating walls parallel to each other and disposed in the stack structure to divide the stack structure into a plurality of blocks arranged parallel to each other.
[0010] In one embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, in each of the blocks, the first dummy pillar is located on a first side of the memory array region, and the plurality of support pillars are located on a second side of the memory array region opposite to the first side.
[0011] In one embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, the first dummy pillars in each of the blocks are adjacent to the support pillars in the adjacent blocks, and the support pillars in each of the blocks are adjacent to the first dummy pillars in the adjacent blocks.
[0012] In an embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, the structure further includes a plurality of vertical channel structures disposed in the memory array region and penetrating the stacked structure and the first conductive layer.
[0013] In one embodiment of the semiconductor structure for a three-dimensional memory disclosed herein, the first insulating wall is located in the storage element region and adjacent to the boundary between the storage element region and the peripheral region, and is spaced a distance from the second conductive layer at the bottom of the stacked structure.
[0014] The manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein includes the following steps. A substrate is provided, wherein the substrate has a storage element region and a peripheral region surrounding the storage element region, and the storage element region includes a storage array region and a step region. A circuit structure layer is formed on the substrate. A first conductive layer is formed on the circuit structure layer. A stacked structure is formed on the first conductive layer in the storage element region, wherein the stacked structure includes a plurality of second conductive layers and a plurality of insulating layers stacked alternately, and the stacked structure in the step region has a stepped profile. An oxide layer is formed on the first conductive layer, wherein the oxide layer surrounds the stacked structure. A first insulating wall is formed in the oxide layer, wherein the first insulating wall penetrates the first conductive layer and surrounds the stacked structure. A plurality of first dummy pillars are formed in the peripheral region and the step region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the step region penetrates the oxide layer, the stacked structure, and the first conductive layer.
[0015] In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory disclosed herein, the method for forming the stacked structure and the oxide layer includes the following steps: forming a first initial stacked structure on the first conductive layer, wherein the first initial stacked structure includes the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing portions of the insulating layers and the sacrificial layers to expose the first conductive layer in the peripheral region; and forming a second initial stacked structure in the memory element region, wherein the second initial stacked structure in the stepped region has the stepped profile; forming the oxide layer on the first conductive layer; and replacing the plurality of sacrificial layers with the plurality of second conductive layers.
[0016] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, after forming the oxide layer and before replacing the multiple sacrificial layers with the multiple second conductive layers, it also includes forming multiple vertical channel structures in the storage array area, wherein each of the vertical channel structures passes through the second initial stacking structure and the first conductive layer.
[0017] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, after forming the multiple vertical channel structures and before replacing the multiple sacrificial layers with the multiple second conductive layers, it also includes forming the multiple first virtual pillars in the peripheral area and the stepped area, wherein each of the first virtual pillars in the peripheral area penetrates the oxide layer and the first conductive layer, and each of the first virtual pillars in the stepped area penetrates the second initial stacking structure and the first conductive layer.
[0018] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, when forming the multiple vertical channel structures, it also includes forming multiple support pillars in the stepped area, wherein each of the support pillars penetrates the second initial stacking structure and the first conductive layer.
[0019] In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory device disclosed herein, after forming the plurality of first dummy pillars, the method further includes the following steps: forming a first slit in the oxide layer, wherein the first slit penetrates the oxide layer and the first conductive layer and surrounds the second initial stacked structure; forming a plurality of second slits parallel to each other in the second initial stacked structure to divide the second initial stacked structure into a plurality of blocks arranged parallel to each other; replacing the plurality of sacrificial layers with the plurality of second conductive layers; and filling the first slit and the plurality of second slits with an insulating material to form a first insulating wall in the first slit and a plurality of second insulating walls in the second slit.
[0020] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, after forming the oxide layer and before replacing the multiple sacrificial layers with the multiple second conductive layers, it also includes forming the multiple first virtual pillars in the peripheral area and the stepped area, wherein each of the first virtual pillars in the stepped area penetrates the second initial stacking structure and the first conductive layer.
[0021] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, after forming the multiple first virtual pillars and before replacing the multiple sacrificial layers with the multiple second conductive layers, it also includes forming multiple vertical channel structures in the storage array area, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.
[0022] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, when forming the multiple vertical channel structures, it also includes forming multiple support pillars in the stepped area, wherein each of the support pillars penetrates the second initial stacking structure and the first conductive layer.
[0023] In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory device disclosed herein, after forming the multiple vertical channel structures, the method further includes the following steps: forming a first slit in the oxide layer, wherein the first slit penetrates the first conductive layer and surrounds the second initial stacked structure; forming multiple second slits parallel to each other in the second initial stacked structure to divide the second initial stacked structure into multiple blocks arranged parallel to each other; replacing the multiple sacrificial layers with the multiple second conductive layers; and filling the first slit and the multiple second slits with an insulating material to form a first insulating wall in the first slit and multiple second insulating walls in the second slit.
[0024] In one embodiment of the disclosed method for fabricating a semiconductor structure for a three-dimensional memory device, the method for forming the stacked structure, the oxide layer, and the plurality of first dummy pillars includes the following steps: forming a first initial stacked structure on the circuit structure layer, wherein the initial stacked structure comprises the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing portions of the insulating layers and portions of the sacrificial layers to form a second initial stacked structure in the memory element region, wherein the second initial stacked structure in the step region has the stepped profile; forming a first oxide material layer to cover the second initial stacked structure; forming the plurality of first dummy pillars in the peripheral region and the step region, wherein each first dummy pillar in the peripheral region penetrates the first initial stacked structure and the first conductive layer, and each first dummy pillar in the step region penetrates the first oxide material layer, the second initial stacked structure, and the first conductive layer; forming a plurality of holes in the peripheral region that penetrate the first initial stacked structure and the first conductive layer; replacing the plurality of sacrificial layers in the peripheral region with a second oxide material layer through the holes to form the oxide layer; and forming a plurality of second dummy pillars in the plurality of openings. The plurality of sacrificial layers in the memory element region are replaced with a plurality of second conductive layers.
[0025] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, before forming the multiple first virtual pillars, it also includes forming multiple vertical channel structures in the storage array area, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.
[0026] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, when forming the multiple vertical channel structures, it also includes forming multiple support pillars in the stepped area, wherein each of the support pillars penetrates the second initial stacking structure and the first conductive layer.
[0027] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, after forming the multiple first virtual pillars and before forming the multiple holes, it also includes forming multiple vertical channel structures in the storage array area, wherein each of the vertical channel structures penetrates the second initial stacking structure and the first conductive layer.
[0028] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, when forming the multiple vertical channel structures, it also includes forming multiple support pillars in the stepped area, wherein each of the support pillars penetrates the second initial stacking structure and the first conductive layer.
[0029] In one embodiment of the method for manufacturing a semiconductor structure for a three-dimensional memory device disclosed herein, after forming the plurality of second dummy pillars, the method further includes the following steps: forming a first slit in the oxide layer, wherein the first slit penetrates the first conductive layer and surrounds the second initial stacked structure; forming a plurality of second slits parallel to each other in the second initial stacked structure to divide the second initial stacked structure into a plurality of blocks arranged parallel to each other; replacing the plurality of sacrificial layers with the plurality of second conductive layers; and filling the first slit and the plurality of second slits with an insulating material to form a first insulating wall in the first slit and a plurality of second insulating walls in the second slit.
[0030] In one embodiment of the manufacturing method of a semiconductor structure for a three-dimensional memory disclosed herein, the first insulating wall is located in the storage element area and adjacent to the boundary between the storage element area and the peripheral area, and is separated from the second conductive layer at the bottom of the stacked structure by a distance.
[0031] Based on the foregoing, in the disclosed semiconductor structure for a three-dimensional memory device and its manufacturing method, the stacked nitride layer in the peripheral region surrounding the memory device region is removed, eliminating the stacked structure of oxide and nitride layers in the peripheral region. This effectively prevents the nitride layer in the peripheral region from causing threshold voltage shift problems on semiconductor devices (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer after thermal treatment. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figures 1A to 1E FIG1 is a cross-sectional diagram of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the first embodiment of the present disclosure.
[0033] Figures 2A to 2E This is a top view schematic diagram of the manufacturing process of the semiconductor structure for three-dimensional memory according to the first embodiment of the present disclosure, wherein Figures 1A to 1E is based on Figures 2A to 2EAs shown by the AA section line in FIG.
[0034] Figure 3A and Figure 3B They are respectively variations of the first virtual column in the first embodiment of the present disclosure.
[0035] Figure 4A and Figure 4B This is a variation of the first insulating wall and the second insulating wall in the first embodiment of the present disclosure.
[0036] Figures 5A to 5E FIG2 is a cross-sectional diagram illustrating the manufacturing process of a semiconductor structure for a three-dimensional memory according to the second embodiment of the present disclosure.
[0037] Figure 6A 、 Figure 6B and Figure 6C They are respectively variations of the second virtual column in the second embodiment of the present disclosure.
[0038] Figure 7 FIG. 4 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of this embodiment.
[0039] Description of Reference Numerals
[0040] 100: Base
[0041] 100a: Storage element area
[0042] 100b: surrounding area
[0043] 102: Circuit structure layer
[0044] 104: First conductive layer
[0045] 106a: Insulation layer
[0046] 106b: Sacrificial layer
[0047] 108, 504: oxide layer
[0048] 110: Vertical channel structure
[0049] 112, 114: Dielectric layer
[0050] 116: Support column
[0051] 118: First virtual column
[0052] 120: Second conductive layer
[0053] 122, 510: spacer layer
[0054] 124a: First insulating wall
[0055] 124b: Second insulating wall
[0056] 126, 508: Polysilicon layer
[0057] 500: first oxide material layer
[0058] 502: Second oxide material layer
[0059] 506: Second virtual column
[0060] AR: Storage Array Area
[0061] AG1, AG2, AG3: air gap
[0062] BL: bit line
[0063] BLOCK: Block
[0064] CH: Channel layer
[0065] D: Drain column
[0066] H: Hole
[0067] MC: Storage Unit
[0068] MSC, MSC1, MSC2: memory array
[0069] S, SP: source column
[0070] SC: Step Zone
[0071] SL: Source line
[0072] SLT1: First Slit
[0073] SLT2: Second Slit
[0074] ST1: First initial stacking structure
[0075] ST2: Second initial stacking structure
[0076] ST3: Stacked structure
[0077] WL: word line DETAILED DESCRIPTION
[0078] The following examples are listed and illustrated in detail, but the examples provided are not intended to limit the scope of this disclosure. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, identical components will be designated by the same reference numerals throughout the following description.
[0079] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".
[0080] When terms such as "first" and "second" are used to describe elements, they are used only to distinguish these elements from each other and do not limit the order or importance of these elements. Therefore, in some cases, a first element can also be referred to as a second element, and a second element can also be referred to as a first element, without departing from the scope of the present disclosure.
[0081] Furthermore, directional terms such as "upper" and "lower" are used herein solely to refer to the directions of the accompanying drawings and are not intended to limit the present disclosure. Therefore, it should be understood that "upper" and "lower" are used interchangeably, and that when an element, such as a layer or film, is placed "on" another element, the element may be placed directly on the other element or intervening elements may be present. On the other hand, when an element is referred to as being "directly" placed "on" another element, there are no intervening elements between the two elements.
[0082] The terms used herein are used to describe exemplary embodiments only and are not intended to limit the present disclosure. In this case, unless the context otherwise indicates, the singular form includes the plural form.
[0083] Figures 1A to 1E FIG1 is a cross-sectional diagram of the manufacturing process of a semiconductor structure for a three-dimensional memory according to the first embodiment of the present disclosure. Figures 2A to 2E This is a top view schematic diagram of the manufacturing process of the semiconductor structure for three-dimensional memory according to the first embodiment of the present disclosure, wherein Figures 1A to 1E is based on Figures 2A to 2E As shown by the AA section line in FIG.
[0084] First, please refer to Figure 1A and Figure 2A , providing a substrate 100. In this embodiment, the substrate 100 has a storage element region 100a and a peripheral region 100b surrounding the storage element region 100a. In addition, in this embodiment, the storage element region 100a includes a storage array region AR and a step region SC. In this embodiment, the substrate 100 may be a silicon substrate. Figure 2A As shown, from a top view direction above the substrate 100 , the peripheral region 100 b surrounds the memory device region 100 a , and in the memory device region 100 a , the step region SC surrounds the memory array region AR.
[0085] Next, a circuit structure layer 102 is formed on the substrate 100. The circuit structure layer 102 may include various commonly known semiconductor devices. For example, the circuit structure layer 102 may include transistors formed on the surface of the substrate 100, interconnect structures electrically connected to the transistors, and an interlayer dielectric layer (ILD layer) covering the transistors and the interconnect structures, but the present disclosure is not limited thereto. Furthermore, for clarity of the drawings and to ensure that the detailed structure of the circuit structure layer 102 is well known to those skilled in the art, the detailed structure of the circuit structure layer 102 is not illustrated in the drawings.
[0086] Next, a first conductive layer 104 is formed on the circuit structure layer 102. In this embodiment, the first conductive layer 104 may be a ground layer and may be electrically connected to the circuit structure layer 102 via conductive vias, but the present disclosure is not limited thereto. The first conductive layer 104 may be a polysilicon layer, but the present disclosure is not limited thereto. In addition, a dielectric layer (not shown) may be formed between the first conductive layer 104 and the circuit structure layer 102. In other embodiments, the first conductive layer 104 may be omitted, depending on practical circumstances.
[0087] Afterwards, a first initial stacking structure ST1 is formed on the first conductive layer 104. The first initial stacking structure ST1 includes a plurality of insulating layers 106a and a plurality of sacrificial layers 106b that are alternately stacked. In this embodiment, in the first initial stacking structure ST1, both the bottom layer and the top layer are insulating layers 106a, but the present disclosure is not limited thereto. Figure 1A In the embodiment, the number and thickness of the insulating layer 106a and the sacrificial layer 106b are only exemplary and are not limited in the present disclosure. In the present embodiment, the insulating layer 106a is a silicon oxide layer and the sacrificial layer 106b is a silicon nitride layer, but the present disclosure is not limited thereto.
[0088] Next, please refer to Figure 1B and Figure 2B , portions of the insulating layer 106a and the sacrificial layer 106b are removed to expose the first conductive layer 104 in the peripheral region 100b and in the memory element region 100a near the boundary between the peripheral region 100b and the memory element region 100a, thereby forming a second preliminary stacked structure ST2 in the memory element region 100a. Furthermore, after removing portions of the insulating layer 106a and the sacrificial layer 106b, the resulting second preliminary stacked structure ST2 has a staircase profile, i.e., the second preliminary stacked structure ST2 has a plurality of steps in the step region SC. The method for forming the second preliminary stacked structure ST2 to have a staircase profile is well known to those skilled in the art and is not further described herein.
[0089] Afterwards, an oxide layer 108 is formed on the substrate 100 to cover the exposed first conductive layer 104 and the second initial stacked structure ST2 in the storage element region 100a. Figure 2B In the figure, the first conductive layer 104, the sacrificial layer 106b, and the oxide layer 108 are omitted for clarity and ease of understanding. In this embodiment, the oxide layer 108 is a silicon oxide layer. The oxide layer 108 is formed by, for example, forming an oxide material layer on the substrate 100 and then performing a planarization process to ensure that the formed oxide layer 108 has a flat top surface. The planarization process is, for example, a chemical mechanical polishing (CMP) process.
[0090] As a result, in the peripheral region 100 b , there is an oxide layer 108 but no nitride layer.
[0091] In the semiconductor structure of the present disclosure formed in this step, an oxide layer but no nitride layer exists in the peripheral region 100 b. Therefore, subsequent heat treatment of the semiconductor structure of the present disclosure will not cause threshold voltage shift issues for the semiconductor elements (particularly the P-type metal oxide semiconductor transistors) in the circuit structure layer 102.
[0092] Then, please also refer to Figure 1C and Figure 2C After forming the oxide layer 108, a plurality of vertical channel structures 110 are formed in the memory array region AR. The vertical channel structures 110 penetrate the oxide layer 108, the second initial stacked structure ST2 and the first conductive layer 104. Figure 2C In order to make the drawings clear and easy to understand, the first conductive layer 104, the sacrificial layer 106b and the oxide layer 108 are omitted.
[0093] Specifically, in the present embodiment, in the memory array region AR, a vertical channel structure 110 extends downward from the top surface of the oxide layer 108 through the oxide layer 108, the second initial stacked structure ST2, and the first conductive layer 104. The vertical channel structure 110 may include a channel layer CH, a source column S, a drain column D, and a dielectric column separating the source column S and the drain column from each other. In the present embodiment, the channel layer CH may be a polysilicon layer, and the material of the source column S and the drain column D may be metal or doped polysilicon. Furthermore, in the present embodiment, the dielectric column may include a dielectric layer 112 and a dielectric layer 114 located above the dielectric layer 112. The dielectric layer 112 may be an oxide layer, and the dielectric layer 114 may be a nitride layer. The method for forming the channel layer CH, the source column S, the drain column D, and the dielectric column is well known to those skilled in the art and will not be described further herein.
[0094] Furthermore, in this embodiment, when forming the vertical channel structure 110 , a plurality of support pillars 116 may be formed in the stepped region SC at the same time. The support pillars 116 penetrate the oxide layer 108 , the second initial stacked structure ST2 , and the first conductive layer 104 .
[0095] Specifically, in this embodiment, in the stepped region SC, support pillars 116 extend downward from the top surface of the oxide layer 108, penetrating the oxide layer 108, the corresponding stepped portion of the second initial stacked structure ST2, and the first conductive layer 104. The support pillars 116 may include a dielectric layer 112 and a dielectric layer 114 located within the dielectric layer 112. The support pillars 116 may provide support for the second initial stacked structure ST2 in the stepped region SC. The method for forming the support pillars 116 is well known to those skilled in the art and will not be further described herein.
[0096] exist Figure 2C In the embodiment, the number and layout of the vertical channel structures 110 and the support pillars 116 are merely exemplary and are not limited in the present disclosure.
[0097] Next, please refer to Figure 1D and Figure 2D After forming the vertical channel structure 110 and the support pillars 116, a plurality of first dummy pillars 118 are formed in the peripheral region 100b and the stepped region SC. The first dummy pillars 118 in the peripheral region 100b penetrate the oxide layer 108 and the first conductive layer 104, while the first dummy pillars 118 in the stepped region 100b penetrate the oxide layer 108, the second initial stacked structure ST2, and the first conductive layer 104. Figure 2D In order to make the drawings clear and easy to understand, the first conductive layer 104, the sacrificial layer 106b and the oxide layer 108 are omitted.
[0098] Specifically, in this embodiment, in the peripheral region 100b, the first dummy pillars 118 extend downward from the top surface of the oxide layer 108, penetrating the oxide layer 108 and the first conductive layer 104. Furthermore, in the stepped region SC, the first dummy pillars 118 extend downward from the top surface of the oxide layer 108, penetrating the oxide layer 108, the corresponding stepped portion of the second initial stacked structure ST2, and the first conductive layer 104. In this embodiment, the material of the first dummy pillars 118 may be an oxide. The first dummy pillars 118 located in the stepped region SC may be used to provide support for the second initial stacked structure ST2 in the stepped region SC. The method for forming the first dummy pillars 118 is well known to those skilled in the art and will not be further described herein.
[0099] In this embodiment, the first dummy pillar 118 is a pillar made of oxide, but the present disclosure is not limited thereto. In other embodiments, the first dummy pillar 118 may have other structures depending on actual circumstances.
[0100] For example, if Figure 3A As shown, the spacer layer 122 can be formed in the first virtual pillar 118 composed of oxide. The material of the spacer layer 122 can be polysilicon or nitride. In this embodiment, when the material of the spacer layer 122 is nitride, since the first virtual pillar 118 only includes a small amount of nitride, the semiconductor elements (especially P-type metal oxide semiconductor transistors) in the circuit structure layer 102 will not have the problem of threshold voltage shift after subsequent heat treatment. In addition, in another embodiment, as Figure 3B As shown, the air gap AG1 may be formed in the first dummy pillar 118 .
[0101] Furthermore, in other embodiments, after forming the first dummy pillar 118 , a via hole may be formed in the first dummy pillar 118 according to actual needs. This is well known to those skilled in the art and will not be further described herein.
[0102] Afterwards, please also refer to Figure 1E and Figure 2E After forming the first dummy pillar 118, a first slit SLT1 and a plurality of second slits SLT2 parallel to each other are formed in the oxide layer 108. In this embodiment, the first slit SLT1 penetrates the oxide layer 108 and the first conductive layer 104 and surrounds the second initial stack structure ST2. In addition, the second slit SLT2 penetrates the oxide layer 108, the second initial stack structure ST2 and the first conductive layer 104 to divide the second initial stack structure ST2 into a plurality of blocks arranged parallel to each other. The first slit SLT1 is not connected to the second slit SLT2. Figure 2E The number of blocks and layout design are only exemplary and are not limited in this disclosure. Figure 2E In order to make the drawings clear and easy to understand, the first conductive layer 104, the sacrificial layer 106b and the oxide layer 108 are omitted.
[0103] Specifically, in this embodiment, the first slit SLT1 extends downward from the top surface of the oxide layer 108, through the oxide layer 108 and the first conductive layer 104, and is located in the storage element region 100a and adjacent to the boundary between the storage element region 100a and the peripheral region 100b. The slit is spaced a distance from the lowermost sacrificial layer 106b in the second initial stacked structure ST2, but the present disclosure is not limited thereto. In other embodiments, the first slit SLT1 may be located in the peripheral region 100b and adjacent to the boundary between the storage element region 100a and the peripheral region 100b. Alternatively, the first slit SLT1 may be located at the boundary between the storage element region 100a and the peripheral region 100b.
[0104] In this embodiment, the second slit SLT2 extends downward from the top surface of the oxide layer 108 through the oxide layer 108, the second initial stacked structure ST2, and the first conductive layer 104, so as to divide the second initial stacked structure ST2 into a plurality of blocks arranged parallel to each other. In each block, the first dummy pillar 118 is located on a first side of the memory array region AR, and the support pillar 116 is located on a second side of the memory array region AR opposite to the first side. For example, Figure 2E As shown, in the blocks of the first and third columns, the first dummy column 118 is located on the right side of the storage array area AR, and the support column 116 is located on the left side of the storage array area AR, while in the blocks of the second column, the first dummy column 118 is located on the left side of the storage array area AR, and the support column 116 is located on the right side of the storage array area AR, but the present disclosure is not limited to this. In addition, the first dummy column 118 in each block is adjacent to the support column 116 in the adjacent block, and the support column 116 in each block is adjacent to the first dummy column 118 in the adjacent block. In other embodiments, depending on actual needs, the support column 116 and the first dummy column 118 may have other layout designs. Alternatively, the second slit SLT2 may not be formed.
[0105] Next, after forming the first slits SLT1 and the second slits SLT2, a replacement process and a charge storage structure formation step are performed through the first slits SLT1 and the second slits SLT2 to replace the sacrificial layer 106b in the second initial stacked structure ST2 with the second conductive layer 120, and to form a charge storage structure between the second conductive layer 120 and the channel layer CH. The above-mentioned replacement process and charge storage structure formation steps are well known to those skilled in the art and are not further described here.
[0106] As a result, a stacked structure ST3 consisting of a plurality of alternately stacked insulating layers 106a and a plurality of second conductive layers 120 is formed on the first conductive layer 104 in the storage element region 100a. The stacked structure ST3 has the same stepped profile as the second initial stacked structure ST2. Furthermore, the formed stacked structure ST3 is surrounded by the oxide layer 108.
[0107] exist Figure 1E For clarity, the charge storage structure is not shown. The charge storage structure can be a composite structure composed of an oxide layer, a nitride layer, and an oxide layer. When the semiconductor structure of this embodiment is applied to a three-dimensional memory, the second conductive layer 120 in the memory array region AR can serve as the gate of the three-dimensional memory, while in the stepped region SC, the second conductive layer 120 can serve as the word line of the three-dimensional memory.
[0108] After performing the replacement process and forming the charge storage structure described above, insulating material is filled into the first slit SLT1 and the second slit SLT2 to form a first insulating wall 124a in the first slit SLT1 and a second insulating wall 124b in the second slit SLT2. In other words, in this embodiment, a first insulating wall 124a is formed in the oxide layer 108, penetrating the oxide layer 108 and the first conductive layer 104 and surrounding the stacked structure ST3. The first insulating wall 124a is located in the memory device region 100a and adjacent to the boundary between the memory device region 100a and the peripheral region 100b, and is spaced a distance from the bottommost second conductive layer 120 in the stacked structure ST3. In this manner, a three-dimensional memory device including the semiconductor structure of the present disclosure is formed.
[0109] In this embodiment, the material of the first insulating wall 124a and the second insulating wall 124b may be oxide or nitride, but the present disclosure is not limited thereto. In other embodiments, the first insulating wall 124a and the second insulating wall 124b may have other structures depending on actual conditions.
[0110] For example, if Figure 4A As shown, the polysilicon layer 126 can be formed in the first insulating wall 124a and the second insulating wall 124b composed of oxide or nitride. In the case where the material of the first insulating wall 124a and the second insulating wall 124b is nitride, since the first insulating wall 124a and the second insulating wall 124b are not large-sized components, that is, there will not be a large amount of nitride, the semiconductor components (especially P-type metal oxide semiconductor transistors) in the circuit structure layer 102 will not have the problem of threshold voltage shift after subsequent heat treatment. In addition, in another embodiment, as Figure 4B As shown, the air gap AG2 may be formed in the first insulating wall 124 a and the second insulating wall 124 b .
[0111] In this embodiment, the first dummy column 118 is formed after the vertical channel structure 110 and the support column 116 are formed, but the present disclosure is not limited thereto. In other embodiments, the first dummy column 118 can be formed before the vertical channel structure 110 and the support column 116 are formed. Figure 1B After the oxide layer 108 is formed in the peripheral region 100b and the stepped region SC, a first dummy pillar 118 is formed. After the first dummy pillar 118 is formed, a vertical channel structure 110 is formed in the memory array region AR and a support pillar 116 is formed in the stepped region SC. Figure 1E and Figure 2E The steps described.
[0112] Figures 5A to 5EFIG2 is a cross-sectional view of a manufacturing process of a semiconductor structure for a three-dimensional memory according to a second embodiment of the present disclosure. In this embodiment, the same elements as those in the first embodiment are denoted by the same reference numerals and will not be further described.
[0113] First, please refer to Figure 5A , in the formation Figure 1A After the first initial stacked structure ST1 in the peripheral region 100b is formed, a portion of the insulating layer 106a and a portion of the sacrificial layer 106b are removed to form a second initial stacked structure ST2 in the storage device region 100a, while retaining the first initial stacked structure ST1 in the peripheral region 100b. In addition, in this embodiment, the first conductive layer 104 in the storage device region 100a adjacent to the boundary between the peripheral region 100b and the storage device region 100a is exposed.
[0114] Then, a first oxide material layer 500 is formed on the substrate 100 to cover the second initial stacked structure ST2 in the storage element region 100a, the first initial stacked structure ST1 in the peripheral region 100b, and the exposed first conductive layer 104. In this embodiment, the first oxide material layer 500 is a silicon oxide layer. The first oxide material layer 500 can be formed by, for example, forming an oxide material layer on the substrate 100 and then performing a planarization process so that the formed first oxide material layer 500 has a flat top surface. The planarization process can be, for example, a chemical mechanical polishing process.
[0115] Next, please refer to Figure 5B ,as Figure 1C As described above, after forming the first oxide material layer 500 , a plurality of vertical channel structures 110 are formed in the memory array region AR, and simultaneously a plurality of support pillars 116 are formed in the stepped region SC.
[0116] Then, after forming the vertical channel structure 110 and the support pillars 116, a plurality of first dummy pillars 118 are formed in the peripheral region 100b and the stepped region SC. In this embodiment, in the peripheral region 100b, the first dummy pillars 118 penetrate the first oxide material layer 500, the first initial stacked structure ST1, and the first conductive layer 104, while in the stepped region 100b, the first dummy pillars 118 penetrate the first oxide material layer 500, the second initial stacked structure ST2, and the first conductive layer 104.
[0117] Specifically, in the present embodiment, in the peripheral region 100 b, the first dummy pillars 118 extend downward from the top surface of the first oxide material layer 500, penetrating the first oxide material layer 500, the first preliminary stacked structure ST1, and the first conductive layer 104. Furthermore, in the step region SC, the first dummy pillars 118 extend downward from the top surface of the first oxide material layer 500, penetrating the first oxide material layer 500, the corresponding stepped portion of the second preliminary stacked structure ST2, and the first conductive layer 104. The first dummy pillars 118 located in the peripheral region 100 b can be used to provide support for the first preliminary stacked structure ST1 in the peripheral region 100 b, and the first dummy pillars 118 located in the step region SC can be used to provide support for the second preliminary stacked structure ST2 in the step region SC.
[0118] Then, please refer to Figure 5C A plurality of holes H are formed in the peripheral region 100b, penetrating the first oxide material layer 500, the first preliminary stacked structure ST1, and the first conductive layer 104. Specifically, in this embodiment, the holes H extend downward from the top surface of the first oxide material layer 500, penetrating the first oxide material layer 500, the first preliminary stacked structure ST1, and the first conductive layer 104, to expose the sacrificial layer 106b in the first preliminary stacked structure ST1.
[0119] Next, please refer to Figure 5D After forming the hole H, a replacement process is performed through the hole H to replace the sacrificial layer 106b in the peripheral region 100b with the second oxide material layer 502. Thus, the first oxide material layer 500, the second oxide material layer 502, and the insulating layer 106a form an oxide layer 504 covering the first conductive layer 104 in the peripheral region 100b. Subsequently, the hole H is filled with an oxide material to form a second dummy pillar 506.
[0120] As a result, the peripheral region 100b contains the oxide layer 504 and the first and second dummy pillars 118 and 506 formed of oxide material, but does not contain a nitride layer (sacrificial layer 106b). In other words, the stacked structure in the peripheral region 100b is composed of the stacked insulating layer 106a and the second oxide material layer 502.
[0121] In the semiconductor structure of the present disclosure formed in this step, an oxide layer but no nitride layer exists in the peripheral region 100 b. Therefore, subsequent heat treatment of the semiconductor structure of the present disclosure will not cause threshold voltage shift issues for the semiconductor elements (particularly the P-type metal oxide semiconductor transistors) in the circuit structure layer 102.
[0122] In this embodiment, the second dummy pillar 506 is a pillar made of oxide, but the present disclosure is not limited thereto. In other embodiments, the second dummy pillar 506 may have other structures depending on actual circumstances.
[0123] For example, if Figure 6A As shown, the polysilicon layer 508 may be formed in the second dummy pillar 506 composed of oxide. Figure 6B As shown, the spacer layer 510 may be formed in the second virtual pillar 506 composed of oxide. The material of the spacer layer 510 may be polysilicon or nitride. In addition, in another embodiment, as shown in FIG. Figure 6C As shown, the air gap AG3 may be formed in the second dummy pillar 206 .
[0124] Afterwards, please refer to Figure 5E After forming the second virtual column 206, a first slit SLT1 and a plurality of second slits SLT2 parallel to each other are formed in the first oxide material layer 500, and a replacement process and a charge storage structure formation step are performed through the first slit SLT1 and the second slit SLT2 to replace the sacrificial layer 106b in the second initial stacking structure ST2 with the second conductive layer 120 and form a charge storage structure between the second conductive layer 120 and the channel layer CH.
[0125] As a result, a stacked structure ST3 consisting of a plurality of alternately stacked insulating layers 106a and a plurality of second conductive layers 120 is formed on the first conductive layer 104 in the storage element region 100a. The stacked structure ST3 has the same stepped profile as the second initial stacked structure ST2. Furthermore, the formed stacked structure ST3 is surrounded by the oxide layer 504.
[0126] After performing the replacement process and forming the charge storage structure, insulating material is filled into the first slit SLT1 and the second slit SLT2 to form a first insulating wall 124a in the first slit SLT1 and a second insulating wall 124b in the second slit SLT2. In this way, a three-dimensional memory device including the semiconductor structure of the present disclosure is formed.
[0127] In this embodiment, the first dummy column 118 is formed after the vertical channel structure 110 and the support column 116 are formed, but the present disclosure is not limited thereto. In other embodiments, the first dummy column 118 can be formed before the vertical channel structure 110 and the support column 116 are formed. Figure 1E and Figure 2E The steps are used to form a three-dimensional memory including the semiconductor structure disclosed herein.
[0128] In summary, in the disclosed semiconductor structure for a three-dimensional memory device and its fabrication method, the nitride layer is removed from the initial stacked structure in the peripheral region surrounding the memory device region, eliminating the stacked structure of oxide and nitride layers in the peripheral region. Consequently, after subsequent thermal treatment, the nitride layer in the peripheral region can effectively prevent the nitride layer from causing threshold voltage shifts in semiconductor devices (particularly P-type metal oxide semiconductor transistors) in the circuit structure layer.
[0129] In addition, even though nitride material (such as a nitride spacer) may exist in the components in the peripheral area (such as virtual pillars), since the nitride material exists only in a small amount, the subsequent heat treatment will not cause the semiconductor components in the circuit structure layer (especially P-type metal oxide semiconductor transistors) to have a threshold voltage shift problem.
[0130] The circuit structure of the three-dimensional memory array MSC including the semiconductor structure of this embodiment is described below.
[0131] Figure 7 FIG. 4 is a circuit diagram of a 3D AND flash memory array including the semiconductor structure of this embodiment.
[0132] Please refer to Figure 7 , 2 blocks of vertical AND memory array MSC (i) With BLOCK (i+1) Arranged into columns and rows. (i) The memory array MSC1 is included. One column (eg, the m+1th column) of the memory array MSC1 has a common word line (eg, WL (i) m+1 ) of the AND memory cell MC set. The AND memory cell MC of each column (for example, the m+1th column) of the memory array MSC1 corresponds to a common word line (for example, WL (i) m+1 ) and coupled to different source columns (eg SP (i) n With SP (i) n+1 ) and the drain column (eg DP (i) n With DP (i) n+1 ), so that the AND memory cell MC is along a common word line (eg WL (i) m+1 ) are logically arranged into a column.
[0133] A row (eg, the nth row) of the memory array MSC1 has a common source column (eg, SP (i)n ) and a common drain column (eg DP (i) n ) of the AND memory cell MC set. The AND memory cell MC of each row (for example, the nth row) of the memory array MSC1 corresponds to a different word line (for example, WL (i) m+1 With WL (i) m ) and coupled to a common source column (eg SP (i) n ) with a common drain column (e.g. DP (i) n ). Therefore, the AND memory cells MC of the memory array MSC1 are connected along the common source column (eg SP (i) n ) and a common drain column (such as DP (i) n ) are logically arranged in a row. In the physical layout, depending on the fabrication method used, the rows or columns may be twisted, arranged in a honeycomb pattern or otherwise for high density or other reasons.
[0134] exist Figure 7 In the block BLOCK (i) In the memory array MSC1, the AND memory cells MC in the nth row share a common source column (eg, SP (i) n ) with a common drain column (e.g. DP (i) n ). The AND memory cells MC in the n+1th row share a common source column (eg SP (i) n+1 ) with a common drain column (e.g. DP (i) n+1 ).
[0135] Common source column (such as SP (i) n ) is coupled to a common source line (eg, SL n ); a common drain column (eg DP (i) n ) is coupled to a common bit line (eg, BL n ). Common source column (such as SP (i) n+1 ) is coupled to a common source line (eg, SL n+1 ); a common drain column (eg DP (i) n+1 ) is coupled to a common bit line (eg, BL n+1 ).
[0136] Similarly, BLOCK(i+1) The memory array MSC2 is comprised of a plurality of memory cells and a plurality of memory cells. (i) A row (e.g., the m+1th row) of the memory array MSC2 has a common word line (e.g., WL (i+1) m+1 ) of the AND memory cell MC set. The AND memory cell MC of each column (for example, the m+1th column) of the memory array MSC2 corresponds to a common word line (for example, WL (i+1) m+1 ) and coupled to different source columns (eg Sp (i+1) n With SP (i+1) n+1 ) and the drain column (eg DP (i +1) n With DP (i+1) n+1 ). A row (eg, the nth row) of the memory array MSC2 has a common source column (eg, SP (i+1) n ) and a common drain column (such as DP (i+1) n ) of AND memory cells MC, which are connected in parallel and are also called memory strings. The AND memory cells MC of each row (for example, the nth row) of the memory array MSC2 correspond to different word lines (for example, WL (i+1) m+1 With WL (i+1) m ) and coupled to a common source column (eg SP (i+1) n ) with a common drain column (e.g. DP (i +1) n ). Therefore, the AND memory cells MC of the memory array MSC2 are connected along the common source column (eg SP (i+1) n ) and a common drain column (such as DP (i+1) n ) are logically configured into one row.
[0137] BLOCK (i+1) With BLOCK (i) Shared source line (eg SL n With SL n+1 ) and bit lines (such as BL n With BL n+1 ). Therefore, the source line SL n and bit line BL n Coupled to block BLOCK(i) The nth row of AND memory cells MC in the AND memory array MSC1 is coupled to the block BLOCK (i+1) The AND memory cell MC in the nth row of the AND memory array MSC2 is shown in FIG. n+1 and bit line BL n+1 Coupled to block BLOCK (i) The AND memory cell MC in the n+1th row in the AND memory array MSC1 is coupled to the block BLOCK (i+1) The AND memory cell MC in the n+1th row in the AND memory array MSC2.
[0138] Although the present disclosure has been disclosed above with reference to the embodiments, they are not intended to limit the present disclosure. Any person skilled in the art may make slight changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the appended claims.
Claims
1. A semiconductor structure for a three-dimensional memory, comprising: A substrate having a storage element region and a peripheral region surrounding the storage element region, wherein the storage element region includes a storage array region and a step region; A circuit structure layer is provided on the substrate; A first conductive layer is provided on the circuit structure layer; a stacked structure disposed on the first conductive layer in the storage element region, comprising a plurality of second conductive layers and a plurality of insulating layers stacked alternately, wherein the stacked structure in the stepped region has a stepped profile; an oxide layer, disposed on the first conductive layer and surrounding the stacked structure; a first insulating wall, disposed in the oxide layer, penetrating the first conductive layer, and surrounding the stack structure; as well as A plurality of first virtual pillars are arranged in the peripheral area and the stepped area, wherein each of the first virtual pillars in the peripheral area penetrates the oxide layer and the first conductive layer, and each of the first virtual pillars in the stepped area penetrates the stacked structure and the first conductive layer. 2 . The semiconductor structure for a three-dimensional memory according to claim 1 , further comprising a plurality of support pillars disposed in the stepped region and penetrating the stacked structure and the first conductive layer. 3 . The semiconductor structure for a three-dimensional memory according to claim 2 , further comprising a plurality of second insulating walls parallel to each other, disposed in the stack structure to divide the stack structure into a plurality of blocks arranged parallel to each other.
4. The semiconductor structure for a three-dimensional memory according to claim 3, wherein in each of the blocks, the first dummy pillars are located on a first side of the memory array region, and the supporting pillars are located on a second side of the memory array region opposite to the first side.
5. The semiconductor structure for a three-dimensional memory according to claim 4, wherein the first dummy pillars in each of the blocks are adjacent to the supporting pillars in the adjacent blocks, and the supporting pillars in each of the blocks are adjacent to the first dummy pillars in the adjacent blocks. 6 . The semiconductor structure for a three-dimensional memory according to claim 1 , further comprising a plurality of vertical channel structures disposed in the memory array region and penetrating the stacked structure and the first conductive layer.
7. The semiconductor structure for a three-dimensional memory according to claim 1, wherein the first insulating wall is located in the memory element region and adjacent to a boundary between the memory element region and the peripheral region, and is spaced a distance from the second conductive layer at the bottom of the stacked structure.
8. A method for manufacturing a semiconductor structure for a three-dimensional memory, comprising: Providing a substrate, wherein the substrate has a memory element region and a peripheral region surrounding the memory element region, and the memory element region includes a memory array region and a step region; forming a circuit structure layer on the substrate; forming a first conductive layer on the circuit structure layer; forming a stacked structure on the first conductive layer in the storage element region, wherein the stacked structure comprises a plurality of second conductive layers and a plurality of insulating layers stacked alternately, and the stacked structure in the stepped region has a stepped profile; forming an oxide layer on the first conductive layer, wherein the oxide layer surrounds the stack structure; forming a first insulating wall in the oxide layer, wherein the first insulating wall penetrates the first conductive layer and surrounds the stack structure; as well as A plurality of first dummy pillars are formed in the peripheral region and the stepped region, wherein each of the first dummy pillars in the peripheral region penetrates the oxide layer and the first conductive layer, and each of the first dummy pillars in the stepped region penetrates the oxide layer, the stacked structure, and the first conductive layer.
9. The method for manufacturing a semiconductor structure for a three-dimensional memory according to claim 8, wherein a method for forming the stacked structure and the oxide layer comprises: forming a first initial stacking structure on the first conductive layer, wherein the first initial stacking structure comprises the plurality of insulating layers and the plurality of sacrificial layers stacked alternately; removing a portion of the insulating layer and a portion of the sacrificial layer to expose the first conductive layer in the peripheral region, and forming a second initial stacked structure in the memory element region, wherein the second initial stacked structure in the stepped region has the stepped profile; forming the oxide layer on the first conductive layer; as well as The plurality of sacrificial layers are replaced with the plurality of second conductive layers.
10. The method for manufacturing a semiconductor structure for a three-dimensional memory according to claim 9, wherein after forming the oxide layer and before replacing the plurality of sacrificial layers with the plurality of second conductive layers, the method further comprises: A plurality of vertical channel structures are formed in the memory array region, wherein each of the vertical channel structures penetrates the second initial stacked structure and the first conductive layer.