Storage array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention discloses a memory array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of semiconductors. The memory array comprises a laminated structure, the laminated structure is provided with a groove group, the groove group comprises grooves, and the grooves extend along a first direction and penetrate through the laminated structure. The laminated structure comprises a plurality of first dielectric layers and a plurality of first conductive layers which are alternately laminated along a third direction. The memory array also includes a plurality of second conductive layers and a memory medium layer within the trench. The plurality of second conductive layers are arranged at intervals at least along the first direction. The storage medium layers are located between the second conductive layers and the side walls of the grooves. The first direction, the second direction and the third direction are perpendicular to one another. Through the arrangement of the groove, the size of the storage unit can be miniaturized, the storage density of the storage array can be improved, the storage capacitor can be of a planar capacitor structure, the electrical property difference of different storage capacitors in the same storage unit can be reduced, and the remanent polarization intensity of the storage medium layer can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a memory array and a preparation method thereof, a memory, and an electronic device. Background Art

[0002] With the continuous evolution of integrated circuit technology, the number of transistors per unit area on chips in various electronic products (such as computers and mobile phones) continues to increase, enabling continuous optimization of electronic product performance. Taking chip memory as an example, as the number of transistors per unit area increases, the storage density of chip memory also continues to increase, thus meeting the data processing needs of people in the information age.

[0003] However, due to differences in the structure and process of logic units in chip processors and storage units in chip memory, there is a gap in the degree of performance improvement between the two. Specifically, the storage density of chip memory cannot keep up with the computing speed of chip processors, resulting in a "memory wall" phenomenon, which limits the overall performance of the system including chip processors and chip memory. Summary of the Invention

[0004] Embodiments of the present application provide a storage array and a method for manufacturing the same, a memory, and an electronic device for improving storage density.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] In a first aspect, a storage array is provided, comprising: a stacked structure. The stacked structure has at least one groove group, each groove group comprising a plurality of grooves, each groove extending along a first direction and penetrating the stacked structure, and the plurality of grooves being spaced apart along a second direction. The stacked structure comprises a plurality of first dielectric layers and a plurality of first conductive layers alternately stacked along a third direction. The storage array further comprises: a plurality of second conductive layers and a storage dielectric layer located within each groove. Each second conductive layer extends along the third direction, and the plurality of second conductive layers are spaced apart at least along the first direction. The storage dielectric layer extends along the third direction, and the storage dielectric layer is located between each second conductive layer and the sidewalls of the groove. The first direction, the second direction, and the third direction are perpendicular to each other.

[0007] The memory array provided by some embodiments of the present application, by setting multiple grooves in the stacked structure, can use the above-mentioned multiple first conductive layers and the storage medium layer located in each groove, and multiple second conductive layers to form multiple storage capacitor strings spaced along the first direction, thereby forming multiple memory cells spaced along the first direction. Since the grooves have a better aspect ratio, the grooves are easier to etch and form. Therefore, the width of the grooves (that is, the size of the grooves in the second direction) can be reduced to reduce the size and area of ​​the storage capacitors, making it easier to achieve a strict 4F 2 The minimum storage unit size allows for more storage units to be configured, effectively increasing the storage density of the storage array.

[0008] In addition, based on the morphology of the groove and the arrangement of the storage dielectric layer, each storage capacitor formed by the above-mentioned first conductive layer, storage dielectric layer, and second conductive layer is a planar capacitor structure rather than a ring capacitor structure. In this way, on the one hand, the difference in the facing area of ​​the two plates in different storage capacitors can be reduced, the capacitance of different storage capacitors can be reduced, the uniformity of the actual electric field distribution inside different storage capacitors can be improved, and the electrical difference can be reduced, and the anti-interference ability of the storage capacitor and the accuracy of its stored data can be improved. On the other hand, the difference in the direction of the metal lattice felt by the storage dielectric layer at different positions can be reduced, and the difference in stress felt by the internal and external interfaces of the storage dielectric layer can be reduced, thereby reducing the difficulty of forming the orthogonal phase (O phase) in the storage dielectric layer and increasing the proportion of the orthogonal phase (O phase) in the storage dielectric layer, so as to increase the residual polarization strength of the storage dielectric layer.

[0009] In a possible design of the first aspect, the plurality of second conductive layers are spaced apart along the first direction, and the storage dielectric layer surrounds the plurality of second conductive layers. This ensures that each storage capacitor has a planar capacitor structure and has a large capacitance.

[0010] In a possible design of the first aspect, the storage array further includes: a plurality of second dielectric layers, each located within the trench and extending along a third direction. Along the first direction, the second dielectric layers and the second conductive layers are alternately arranged; the storage dielectric layer further surrounds the plurality of second dielectric layers. The provision of the second dielectric layers enables electrical insulation between adjacent second conductive layers.

[0011] In a possible design of the first aspect, the plurality of second conductive layers include a plurality of conductive layer pairs, which are spaced apart along the first direction. Each conductive layer pair includes two second conductive layers spaced apart along the second direction. The storage dielectric layer is located at least between the plurality of conductive layer pairs and the sidewalls of the trench. This allows for the placement of more second conductive layers within the same trench, and thus more memory cells, significantly increasing the storage density of the memory array.

[0012] In a possible design of the first aspect, the storage medium layer surrounds the plurality of conductive layer pairs. Alternatively, the storage medium layer has at least one gap, which penetrates the storage medium layer along the third direction and is located at an end of the groove.

[0013] In a possible design of the first aspect, the orthographic projections of the two second conductive layers in the conductive layer pair on a first reference plane overlap. The first reference plane is parallel to the first direction and the third direction. This helps improve the regularity of the arrangement of multiple second conductive layers within the same trench, reduces the spatial area occupied by each conductive layer pair, facilitates the arrangement of more second conductive layers within the trench, and thus greatly improves the storage density of the memory array.

[0014] In a possible design of the first aspect, the memory array further includes a third dielectric layer located in the trench and between any two adjacent second conductive layers. The third dielectric layer can achieve electrical insulation between any two adjacent second conductive layers.

[0015] In a possible design of the first aspect, there are multiple groove groups, at least two of which are arranged in sequence along the first direction, and at least two of which are arranged in sequence along the second direction. The multiple groove groups are arranged in multiple rows and columns, which is conducive to improving the storage density of the storage array.

[0016] In a possible design of the first aspect, the trench has two first sidewalls extending along a first direction, the two first sidewalls being arranged opposite each other and being planar. Thus, on the one hand, the angle between the portion of the side surface forming the first sidewall in each first conductive layer and the third direction can be made consistent, so that the area of ​​the portion of the side surface forming the first sidewall in each first conductive layer is made consistent, thereby facilitating reduction of capacitance differences between different storage capacitors in the same storage cell, improving the uniformity of the actual electric field distribution within different storage capacitors in the same storage cell, and thus reducing electrical property differences. On the other hand, this further reduces the differences in metal lattice orientation felt by different locations in the storage dielectric layer, further reduces the differences in stress felt by the internal and external interfaces of the storage dielectric layer, effectively reduces the difficulty of forming the orthorhombic phase (O phase) in the storage dielectric layer, and improves the residual polarization strength of the storage dielectric layer 3.

[0017] In a possible design of the first aspect, the two first sidewalls are parallel to each other. This not only helps significantly improve the capacitance consistency of different storage capacitors in the same storage cell, significantly improves the uniformity of the actual electric field distribution within different storage capacitors in the same storage cell, effectively reducing electrical property differences, but also helps significantly reduce the difference in metal lattice orientation felt by different locations in the storage medium layer, significantly reduces the difference in stress felt by the internal and external interfaces of the storage medium layer, effectively reduces the difficulty of forming an orthorhombic phase (O phase) in the storage medium layer, and improves the remanent polarization strength of the storage medium layer.

[0018] In a possible design of the first aspect, the trench further comprises two second sidewalls connecting the two first sidewalls, the two second sidewalls being arranged opposite each other and being planar. This, on the one hand, helps reduce the area occupied by the trench and increase the effective area occupied by the memory cell; on the other hand, when a second conductive layer is provided at the end of the trench, it ensures that the storage capacitor corresponding to the second conductive layer is a planar capacitor.

[0019] In a possible design of the first aspect, the two second side walls are parallel to each other, which helps to further reduce the area occupied by the trench, further increase the effective area occupied by the memory cell, and thus help to improve the storage density of the memory array.

[0020] In a possible design of the first aspect, the storage array further includes: a device layer. Along the third direction, the device layer is located on one side of the stacked structure. The device layer includes: a plurality of transistors, a plurality of word lines, and a plurality of bit lines. At least two of the plurality of transistors are arranged in sequence along the first direction, and at least two transistors are arranged in sequence along the second direction. The first electrode of the transistor is electrically connected to the second conductive layer. A plurality of word lines extend along the first direction and are arranged at intervals along the second direction. The word line is electrically connected to the gates of at least two transistors arranged in sequence along the first direction. A plurality of bit lines extend along the second direction and are arranged at intervals along the first direction. The bit line is electrically connected to the second electrodes of at least two transistors arranged in sequence along the second direction. By setting the device layer, the state of the storage medium layer can be changed to achieve data writing or reading.

[0021] In a possible design of the first aspect, the material of the storage medium layer includes a ferroelectric material. In this case, the storage array is a ferroelectric storage array, which can have advantages such as high speed, high density, low power consumption, and radiation resistance.

[0022] In a second aspect, a method for fabricating a memory array is provided, the method comprising: forming an initial stacked structure comprising a plurality of first dielectric layers and a plurality of first conductive layers alternately stacked along a third direction; forming at least one trench group; the trench group comprising a plurality of trenches, each trench extending along a first direction and penetrating the initial stacked structure, the plurality of trenches being spaced apart along a second direction; sequentially forming a storage dielectric layer and a plurality of second conductive layers within the trenches; the second conductive layer extending along the third direction, the plurality of second conductive layers being spaced apart along at least the first direction; the storage dielectric layer extending along the third direction, the storage dielectric layer being positioned between each second conductive layer and the sidewalls of the trenches; the first direction, the second direction, and the third direction being perpendicular to each other.

[0023] In a possible design of the second aspect, a storage dielectric layer and multiple second conductive layers are sequentially formed within the trench, including: forming the storage dielectric layer within the trench; the storage dielectric layer covering the sidewalls of the trench; filling the trench with a first dielectric material to form a filling portion; the storage dielectric layer surrounding the filling portion; etching the filling portion to form multiple second dielectric layers; the second dielectric layer extending along a third direction, the multiple second dielectric layers spaced apart along the first direction; filling the trench with a conductive material to form multiple second conductive layers; the second dielectric layers and the second conductive layers being alternately arranged along the first direction.

[0024] In a possible design of the second aspect, the preparation method further includes: forming a cutting slit in the trench that at least penetrates the plurality of second conductive layers and the plurality of second dielectric layers; the cutting slit extends along the first direction; and filling the cutting slit with the second dielectric material.

[0025] In a possible design method of the second aspect, the preparation method further includes: forming a device layer, and electrically connecting the device layer to the second conductive layer. The device layer includes: the device layer includes: a plurality of transistors, a plurality of word lines, and a plurality of bit lines. At least two of the plurality of transistors are arranged in sequence along the first direction, and at least two transistors are arranged in sequence along the second direction. The first electrode of the transistor is electrically connected to the second conductive layer. The plurality of word lines extend in the first direction and are arranged at intervals along the second direction. The word line is electrically connected to the gate of the at least two transistors arranged in sequence along the first direction. The plurality of bit lines extend in the second direction and are arranged at intervals along the first direction. The bit line is electrically connected to the second electrode of the at least two transistors arranged in sequence along the second direction.

[0026] In a third aspect, a memory is provided, comprising: a memory array as in any embodiment of the first aspect and a controller, wherein the controller is electrically connected to the memory array and is used to control the reading and writing of the memory array.

[0027] In a fourth aspect, an electronic device is provided, comprising: a memory according to any one embodiment of the third aspect and a circuit board, wherein the circuit board is electrically connected to the memory.

[0028] The technical effects brought about by the method for preparing the storage array in the second aspect, the memory in the third aspect, and the electronic device in the fourth aspect can be referred to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 An architectural diagram of an electronic device provided in an embodiment of the present application;

[0030] Figure 2 An architectural diagram of a memory provided in an embodiment of the present application;

[0031] Figure 3 An architectural diagram of another memory provided in an embodiment of the present application;

[0032] Figure 4 An architectural diagram of another memory provided in an embodiment of the present application;

[0033] Figure 5 A structural diagram and equivalent circuit diagram of a memory cell provided in an embodiment of the present application;

[0034] Figure 6 A structural diagram and an equivalent circuit diagram of another memory cell provided in an embodiment of the present application;

[0035] Figure 7 A structural diagram and an equivalent circuit diagram of another memory cell provided in an embodiment of the present application;

[0036] Figure 8 A structural diagram of a storage array provided in an embodiment of the present application;

[0037] Figure 9 A transmission electron microscope image and a cross-sectional view of a local position of a memory array provided in an embodiment of the present application;

[0038] Figure 10 for Figure 7 A cross-sectional view of the storage unit shown in (a) along the PP direction;

[0039] Figure 11 A structural diagram of a storage array provided in an embodiment of the present application;

[0040] Figure 12 for Figure 11 A cross-sectional view of the memory array shown along the QQ direction;

[0041] Figure 13 for Figure 11 A cross-sectional view of the memory array shown along the RR direction;

[0042] Figure 14 A partial cross-sectional structural diagram of a storage array provided in an embodiment of the present application;

[0043] Figure 15 A partial cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0044] Figure 16 A structural diagram of a storage unit provided in an embodiment of the present application;

[0045] Figure 17 A structural diagram of another storage unit provided in an embodiment of the present application;

[0046] Figure 18 A structural diagram of another storage unit provided in an embodiment of the present application;

[0047] Figure 19 A structural diagram of another storage unit provided in an embodiment of the present application;

[0048] Figure 20 A structural diagram of another storage unit provided in an embodiment of the present application;

[0049] Figure 21 A partial cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0050] Figure 22 A partial cross-sectional structural diagram of another memory array provided in an embodiment of the present application;

[0051] Figure 23 A structural diagram of another storage unit provided in an embodiment of the present application;

[0052] Figure 24 A flowchart of a method for preparing a storage array provided in an embodiment of the present application;

[0053] Figure 25a-25h A structural diagram corresponding to each step in a method for preparing a memory array provided in an embodiment of the present application;

[0054] Figure 26a-26b This is a structural diagram corresponding to each step in another method for preparing a memory array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0056] In the description of this application, unless otherwise specified, "plurality" refers to two or more than two. "At least one" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0057] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0058] In the embodiments of this application, unless otherwise specified or limited, the term "connection" may refer to a direct mechanical or electrical connection, or an indirect mechanical or electrical connection through an intermediate medium. The mechanical connection herein is not limited to whether it is used to transmit electrical signals, and the electrical connection is used to transmit electrical signals.

[0059] In the embodiments of the present application, the descriptions "vertical" and "parallel" respectively indicate approximately vertical and approximately parallel within a certain error range, and the error range may be a range in which the deviation angle relative to absolute vertical and absolute parallel is less than or equal to 5°, 8° or 10°, respectively, and no specific limitation is made here.

[0060] This application describes exemplary embodiments with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown in this application, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0062] An embodiment of the present application provides an electronic device. The electronic device can be applied to various communication systems or communication protocols, such as Bluetooth (BT) communication technology, Global Positioning System (GPS) communication technology, Global System of Mobile Communications (GSM) communication technology, Wireless Fidelity (WiFi) communication technology, Wideband Code Division Multiple Access (WCDMA) communication technology, Long Term Evolution (LTE), 5G communication technology, and other future communication technologies.

[0063] The electronic device in the embodiments of the present application may be a mobile phone, a tablet computer (pad), a laptop computer, a smart home, a smart wearable device (e.g., a smart watch, a smart bracelet, smart glasses, a smart helmet), a virtual reality (VR) electronic device, an augmented reality (AR) electronic device, etc. The electronic device may also be a handheld device with wireless communication capabilities, a computing device or other processing device connected to a wireless modem, an in-vehicle device, an electronic device in a 5G network, or an electronic device in a future evolved public land mobile network (PLMN), etc., and the embodiments of the present application are not limited thereto.

[0064] Figure 1 This is a diagram of the architecture of an electronic device provided in an embodiment of the present application. Figure 1As shown, the electronic device 1000 may include a circuit board 100, a bus 200 and a processor 300. The bus 200 is located on the circuit board 100 and is electrically connected to the circuit board 100. The processor 300 is located on the circuit board 100 and is connected to the bus 200. The circuit board 100 is, for example, a PCB, and the processor 300 is, for example, a system on chip (SoC). The system on chip can be used to process data, such as processing application data, processing image data, and caching temporary data. Optionally, the system on chip may include an application processor (AP) 310 for processing applications, a graphics processing unit (GPU) 320 for processing image data, and a first RAM 330 for caching high-speed data. The first RAM 330 may be a static random access memory (SRAM) or an embedded flash memory (EF lash), etc. The application processor 300 , the image processing unit 320 , and the first RAM 330 may be integrated into one die, or may be separately provided in multiple dies.

[0065] Continue reading Figure 1 The electronic device 1000 may further include a second RAM 400, which may be connected to the processor 300 via the bus 200. The second RAM 400 may be a DRAM. The second RAM 400 may be used to store volatile data, such as temporary data generated by the system-on-chip. The storage capacity of the second RAM 400 may generally be greater than the storage capacity of the first RAM 330, but the read speed of the second RAM 400 is generally slower than the read speed of the first RAM 330.

[0066] In addition, the electronic device 1000 may further include a communication chip 500 and a power management chip 600, both of which are connected to the processor 300 via the bus 200. The communication chip 500 can be used for processing the protocol stack, or for amplifying, filtering, and other processing of analog radio frequency signals, or for simultaneously implementing the above functions. The power management chip 600 can be used to power other chips. Exemplarily, the above-mentioned system on chip and the second RAM 400 can be packaged in the same packaging structure. For example, the system on chip and the second RAM 400 can be packaged using 2.5D (dimension) or 3D (three-dimensional) packaging to obtain a faster data transmission rate between chips.

[0067] The present application also provides a memory device for use in the above electronic device. In some embodiments, the memory device can be used as Figure 1 The first RAM330 can also be used as Figure 1 The second RAM 400 in the present application embodiment does not limit the application scenario of the above memory.

[0068] In some examples, such as Figure 2 and Figure 3 As shown, the memory 700 may include a memory array 710 and a controller 720 for accessing the memory array 710. The controller 720 is electrically connected to the memory array 710 and may be used to control read and write operations of the memory array 710. The number of the memory arrays 710 may be one, two, three, or even more. Figure 2 and Figure 3 Four storage arrays 710 are shown.

[0069] For example, Figure 2 As shown, in the memory 700, the memory array 710 and the controller 720 can be two independent chips. The memory array 710 and the controller 720 can be separately disposed on a carrier board (e.g., a packaged transistor chain or an adapter board), and the memory array 710 and the controller 720 are electrically connected to the carrier board. In this way, the memory array 710 and the controller 720 can achieve signal transmission through the metal traces within the carrier board. Based on this, the memory 700 with the memory array 710 can be called a stand-alone memory.

[0070] Alternatively, for example, in the memory 700, the memory array 710 and the controller 720 can be two independent chips, which are stacked on the carrier board. The memory array 710 and the controller 720 can be electrically connected via through silicon vias (TSVs) or redistribution layers (RDLs), thereby enabling signal transmission between the memory array 710 and the controller 720 and the carrier board. Similarly, the memory 700 with the memory array 710 can be referred to as a stand-alone memory.

[0071] Or, for example, Figure 3 As shown, in the memory 700, the memory array 710 is stacked on the controller 720. The memory array 710 and the controller 720 can be integrated into the same chip, and the integrated chip is electrically connected to the carrier board. Based on this, the memory 700 with the memory array 710 can be called an embedded memory.

[0072] In some examples, such as Figure 4 As shown, each memory array 710 in the memory 700 includes a plurality of memory cells (bit cells) 711 arranged in an array, wherein each memory cell 711 can be used to store 1 bit (bit) or multiple bits of data. The memory array 710 may also include signal lines such as word lines (WL) and bit lines (BL). Each memory cell 711 is electrically connected to the corresponding word lines and bit lines. Different memory cells 711 can be electrically connected through word lines and bit lines. One or more of the above-mentioned word lines and bit lines are used to select the memory cell 711 to be read or written in the memory array 710 by receiving the control level output by the control circuit, thereby realizing the read and write operations of data.

[0073] Continue reading Figure 4 The controller 720 in the memory 700 includes, for example, one or more circuit structures including a decoder 721, a driver 722, a timing controller 723, a buffer 724, and an input / output driver circuit 725. The circuit structures in the controller 720 are electrically connected to the memory cells 711 in the memory array 710 via signal lines. The decoder 721 is used to decode the address of the memory cell 711. The decoder 721 decodes the received address to determine the memory cell 711 to be accessed. The driver 722 controls the levels of the aforementioned signal lines based on the decoding result generated by the decoder 721, thereby enabling access to the specified memory cell 711. The buffer 724 caches read data, for example, using a FIFO (first-in, first-out) structure. The timing controller 723 controls the timing of the buffer 724 and controls the driver 722 to drive the signal lines in the memory array 710. The input / output driving circuit 725 is used to drive transmission signals, such as driving received data signals and driving data signals to be sent, so that the data signals can be transmitted over long distances.

[0074] The memory array 710 , decoder 721 , driver 722 , timing controller 723 , buffer 724 and input / output driver circuit 725 may be integrated into one chip or integrated into multiple chips.

[0075] The memory 700 provided in the embodiment of the present application includes various types. Optionally, the memory 700 includes but is not limited to ferroelectric random access memory (FRAM), resistive random access memory (RRAM), phase change memory (PCM), etc. Based on this, the storage unit 711 of the above-mentioned memory 700 includes a storage capacitor, and the storage medium layer included in the storage capacitor includes but is not limited to a ferroelectric material layer, a resistive material layer or a phase change material layer. In the case where the storage medium layer is a ferroelectric material layer, the memory 700 is FRAM; in the case where the storage medium layer is a resistive material layer, the memory 700 is RRAM; in the case where the storage medium layer is a phase change material layer, the memory 700 is PCM.

[0076] The principles of data storage of the above-mentioned types of memories are basically similar. For example, in the above-mentioned storage unit 711, an electric field can be formed between the two capacitor plates, and the storage medium layer can change its state under the action of the electric field. By utilizing the change in the state of the storage medium layer, data storage can be achieved.

[0077] This embodiment of the present application uses a ferroelectric material layer as the storage medium layer and a FRAM as an example for schematic illustration. The ferroelectric material layer comprises a ferroelectric material, which acts as an insulating dielectric, enabling the storage capacitor in the memory cell 711 to function as a ferroelectric capacitor (FeCAP). Ferroelectric random access memory utilizes the ability of ferroelectric materials to undergo spontaneous polarization, and the ability of this polarization state to reorient itself in response to an external electric field, to store data.

[0078] As a non-volatile memory, FRAM offers advantages such as high speed, high density, low power consumption, and radiation resistance. Specifically, ferroelectric memory can perform write operations at bus speeds, with virtually no write delay during data transmission. There are no restrictions on data transfer volume or write delay, and the system can complete write operations on the entire chip memory in an instant. In other words, ferroelectric memory has fast read and write speeds. Furthermore, because it uses ferroelectric capacitors as the storage medium, write operations only require the operating voltage. Consequently, the operating and quiescent currents of ferroelectric memory are very low, which in turn reduces the power consumption required.

[0079] Figure 5 (a) and Figure 6 (a) in the figure provides a structural diagram of a storage unit 711, Figure 5 (b) provides Figure 5 An equivalent circuit diagram of the storage unit 711 shown in (a) is shown in FIG. Figure 6 (b) provides Figure 6 An equivalent circuit diagram of the storage unit 711 shown in (a) in FIG.

[0080] exist Figure 5 In (a) and (b), the memory cell 711 includes a transistor Tr and a storage capacitor C. The gate of the transistor Tr is electrically connected to the word line (WL), the source (or drain) of the transistor Tr is electrically connected to the bit line (BL), the drain (or source) of the transistor Tr is electrically connected to the first plate of the storage capacitor C, and the second plate of the storage capacitor C is electrically connected to the plate line (PL). The storage capacitor C is a ferroelectric capacitor. Figure 5 The structure shown may also be referred to as a 1T1C structure, which is understood to be, for example, a structure in which capacitors in a conventional 1T1C DRAM are replaced with ferroelectric capacitors.

[0081] exist Figure 6 In (a) and (b), the memory cell 711 includes only one transistor Tr, the gate of the transistor Tr is electrically connected to the word line WL, the source of the transistor Tr is electrically connected to the source line (source line, SL), and the drain of the transistor Tr is electrically connected to the drain line (drain line, DL). Figure 6 The structure shown can also be referred to as an 1TOC structure. This structure is understood, for example, to replace the gate oxide dielectric in a conventional metal oxide semiconductor field effect transistor (MOSFET) with a ferroelectric material layer or a composite dielectric layer containing a ferroelectric material layer. This transistor Tr can be referred to as a ferroelectric field effect transistor (FeFET).

[0082] Since each storage capacitor C can be used to store 1 bit of data, Figure 5 and Figure 6 The storage unit 711 shown can only store 1 bit of data, and the storage density is low. Figure 5 and Figure 6 The memory cell 711 shown is a planar structure, and the transistor Tr is a horizontal channel transistor. Due to the limitation of the manufacturing process, it is difficult to further improve the storage density of the memory.

[0083] Based on this, Figure 7 (a) in the figure further provides a structural diagram of a storage unit 711. Figure 7 (b) provides Figure 7 An equivalent circuit diagram of the storage unit 711 shown in (a) in FIG.

[0084] exist Figure 7 In (a) and (b), the memory cell 711 includes a transistor Tr and n storage capacitors C connected in parallel. The gate of the transistor Tr is electrically connected to the word line WL, the source (or drain) of the transistor Tr is electrically connected to the bit line BL, the drain (or source) of the transistor Tr is electrically connected to the first plate C1 of each storage capacitor C, and the second plate C2 of each storage capacitor C is electrically connected to a different plate line (PL). The storage capacitors C are ferroelectric capacitors. Figure 7 The structure shown can also be called 1TnC structure.

[0085] Figure 7 The storage unit 711 shown in FIG can store n bits of data, which is conducive to achieving high-density storage of the memory.

[0086] Figure 8 Shows the basis Figure 7 The structure diagram of a memory array 710 of the memory unit 711 is shown, and the memory array 710 is a 3D structure. Figure 7 and Figure 8 The multiple memory cells 711 in the memory array 710 are arranged in an array. The storage capacitor C in each memory cell 711 is a vertically structured capacitor, with n storage capacitors C stacked vertically. Specifically, each plate line PL is planar and stacked in sequence along the vertical direction. The first plate C1 of each storage capacitor C in the same memory cell 711 is shared and vertically extends through each plate line PL. The storage dielectric layer C3 of the storage capacitor C surrounds the first plate C1.

[0087] Figure 8 The memory array 710 shown has the advantages of simple process and low manufacturing cost, which is conducive to reducing the area of ​​memory cells and can achieve high-density and high-bandwidth storage.

[0088] It can be understood that in the process of preparing the above-mentioned storage array 710, a stacked multilayer plate line PL is first formed, and then the multilayer plate line PL is etched to form a plurality of deep holes passing through the multilayer plate line PL, and then a storage medium layer and a common first electrode C1 are sequentially formed in each deep hole.

[0089] However, based on the preparation process, the etching of the deep hole is relatively difficult, and it is difficult to etch a deep hole with a smaller aperture. This means that the aperture of the deep hole limits the further miniaturization of the size and area of ​​the storage unit 711, and limits the memory 700 from achieving a strict 4F 2 Minimum storage unit size.

[0090] Moreover, if Figure 9 As shown, the pore diameters at different locations of the deep hole vary greatly, e.g. Figure 9The aperture at position A shown in (b) is larger than Figure 9 The aperture of position B shown in (c) in the figure will result in different facing areas of the first plate C1 and the second plate C2 in different storage capacitors C in the same storage unit 711, resulting in different capacitances of different storage capacitors C and uneven distribution of the actual electric field E inside different storage capacitors C, which in turn leads to electrical differences. For the storage capacitors C at the bottom, their capacitance is small, resulting in a relatively weak anti-interference ability of the storage capacitors C, which is easy to affect the accuracy of the stored data. Figure 9 (b) in Figure 9 The cross-sectional view at position A in (a) is shown in FIG. Figure 9 (c) in Figure 9 Cross-sectional view at position B in (a).

[0091] In addition, the above-mentioned deep holes include but are not limited to circular holes. Figure 10 Take the case where the deep hole is a circular hole as an example. Figure 10 In FIG, the double-headed arrow D indicates the metal lattice direction of the first plate C1 of the storage capacitor C, the double-headed arrow F indicates the metal lattice direction of the first plate C2 (i.e., the plate line PL) of the storage capacitor C, and the double-headed arrow H indicates the direction of the stress felt by the storage dielectric layer C3 of the storage capacitor C. Figure 10 It can be seen that since the storage medium layer C3 surrounds the first electrode plate C1 and the second electrode plate C2 surrounds the storage medium layer C3, the metal lattice directions felt by the storage medium layer C3 at different positions are different, resulting in different stresses felt by the inner and outer interfaces of the storage medium layer C3. This will increase the difficulty of forming the orthorhombic phase (O phase) in the storage medium layer C3, which is not conducive to improving the residual polarization strength (Pr) of the storage medium layer C3.

[0092] Based on this, the embodiment of the present application improves the structure of the above-mentioned storage array. Figure 11 A structural diagram of a storage array is shown. Figure 14 、 Figure 15 、 Figure 21 and Figure 22 A partial cross-sectional structure diagram of a storage array is shown respectively. Figure 12 Indicated Figure 11 A cross-sectional view of the storage array along the QQ direction is shown. Figure 13 Indicated Figure 11 A cross-sectional view of the storage array along the RR direction is shown. Figures 16-20 and Figure 23 In addition, in order to more clearly illustrate the structure of the groove and the arrangement of the film layer in the groove, Figure 14 、 Figure 15 、 Figure 21 and Figure 22Each diagram schematically illustrates a partial cross-sectional structure of a memory array, specifically, a second sidewall of a trench and a portion of a film layer located in the trench.

[0093] like Figure 11 As shown, the memory array 710 includes a stacked structure 1 , a second conductive layer 2 , a storage medium layer 3 and a device layer 4 .

[0094] In some examples, such as Figure 11-Figure 15 As shown, the stacked structure 1 includes a plurality of first dielectric layers 11 and a plurality of first conductive layers 12 alternately stacked along a third direction Z. Among the plurality of first dielectric layers 11 and the plurality of first conductive layers 12, one first conductive layer 12 is disposed between two adjacent first dielectric layers 11, and one first dielectric layer 11 is disposed between two adjacent first conductive layers 12. The first dielectric layers 11 are used to achieve electrical insulation between two adjacent first conductive layers 12.

[0095] The materials of the first dielectric layer 11 include, but are not limited to, insulating materials such as silicon dioxide (SiO2), aluminum oxide (Al2O3), hafnium dioxide (HfO2), zirconium oxide (ZrO2), titanium dioxide (TiO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), or any combination thereof. The structure of the first dielectric layer 11 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials. The materials of the multiple first dielectric layers 11 can be the same or different, and the structures of the multiple first dielectric layers 11 can be the same or different.

[0096] The material of the first conductive layer 12 includes a conductive material, for example, the conductive material includes but is not limited to titanium nitride (TiN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), indium tin oxide (ITO), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), etc., or any combination thereof. The materials of the multiple first conductive layers 12 can be the same or different.

[0097] In the above-mentioned stacked structure 1, the thickness of each first conductive layer 12 can be the same or different, and the thickness of each first dielectric layer 11 can be the same or different, and can be set according to actual needs. In addition, in the production process of the stacked structure 1, different numbers of stacked layers will correspond to different stacking heights. For example, the number of film layers stacked in the stacked structure 1 can be dozens or even hundreds of layers (for example, 32 layers, 64 layers, or 128 layers, etc.). The more film layers the stacked structure 1 includes, the higher the integration of the memory and the greater the storage capacity. The number of stacked layers and the stacking height of the stacked structure 1 can be designed according to actual storage requirements, and the embodiments of the present application do not impose any restrictions on this.

[0098] In addition, each first dielectric layer 11 and each first conductive layer 12 in the stacked structure 1 has a high flatness, and the adhesion between adjacent first dielectric layers 11 and first conductive layers 12 is good, with substantially no gap.

[0099] For example, Figure 11 and Figure 14 As shown, the stacked structure 1 has at least one trench group TG, and the number of trench groups TG is, for example, one, two, three, or even more. When there are multiple trench groups TG, at least two trench groups TG can be arranged in sequence along the first direction X, and / or at least two trench groups TG can be arranged in sequence along the second direction Y. Optionally, the multiple trench groups TG are arranged in multiple rows and columns, with each row of trench groups TG including multiple trench groups TG arranged along the first direction X, and each column of trench groups TG including multiple trench groups TG arranged along the second direction Y. The first direction X, the second direction Y, and the third direction Z are mutually perpendicular.

[0100] The trench group TG includes a plurality of trenches (T). For example, each trench group TG may include two, three, or even more trenches T. The number of trenches T included in different trench groups TG may be the same or different. Figure 11 and Figure 12 As shown, for each trench group TG, each trench T includes the trenches T extending along the first direction X, and the plurality of trenches T are arranged at intervals along the second direction Y. The length of the trench T is greater than the width of the trench T. The length of the trench T refers to the dimension of the trench T in the first direction X, and the width of the trench T refers to the dimension of the trench T in the second direction Y.

[0101] Continue reading Figure 11 and Figure 14 , the trench group TG passes through the stacked structure 1, that is, the trench group TG passes through the stacked structure 1 itself. Specifically, as Figure 12 and Figure 13 As shown, each trench T in the trench group TG may extend along the third direction Z and penetrate the first dielectric layer 11 and the first conductive layer 12 included in the stacked structure 1 .

[0102] In some examples, such as Figure 11 and Figure 14 As shown, there are multiple second conductive layers 2, each of which is strip-shaped and extends along the third direction Z. Multiple second conductive layers 2 are disposed in each trench T, and the multiple second conductive layers 2 are spaced apart at least along the first direction X, with two adjacent second conductive layers 2 insulated from each other.

[0103] The material of the second conductive layer 2 includes a conductive material, for example, including but not limited to titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof. The material of the plurality of second conductive layers 2 can be the same, for example, to simplify the fabrication process of the memory array 710. Optionally, the material of the second conductive layer 2 can be the same as or different from the material of the first conductive layer 12.

[0104] In some examples, such as Figure 11-Figure 15 As shown, the storage medium layer 3 is located in the trench T and extends along the third direction Z. The storage medium layer 3 is located between each second conductive layer 2 and the sidewall of the trench T. Optionally, as Figure 11-Figure 15 As shown, no other structure is provided between the storage medium layer 3 and the sidewall of the trench T, and the two can be in direct contact; alternatively, a passivation layer or other structure can be provided between the storage medium layer 3 and the sidewall of the trench T. Optionally, as Figure 11-Figure 15 As shown, no other structure is provided between the storage medium layer 3 and the second conductive layer 2, and the two may be in direct contact; alternatively, a passivation layer or other structure may be provided between the storage medium layer 3 and the second conductive layer 2. This embodiment of the present application is not limited to this.

[0105] Exemplarily, the material of the storage medium layer 3 includes a ferroelectric material. For example, the ferroelectric material includes, but is not limited to, ZrO2, HfO2, Al-doped HfO2, Si (silicon)-doped HfO2, Zr-doped HfO2, La (lanthanum)-doped HfO2, Y (yttrium)-doped HfO2, or materials doped with other elements based on some of the aforementioned ferroelectric materials (e.g., HfO2), and any combination thereof.

[0106] In some examples, along the third direction Z, the device layer 4 is located on one side of the stacked structure 1. For example, Figure 14 and Figure 15 As shown, along the third direction Z, the device layer 4 is located below the stacked structure 1; or, as shown Figure 19 and Figure 20 As shown, along the third direction Z, the device layer is located above the stacked structure.

[0107] Continue reading Figure 11-13 The device layer 4 includes a plurality of transistors Tr, which are field effect transistors, for example. One transistor Tr is electrically connected to one second conductive layer 2 .

[0108] like Figure 11As shown, the portion of the second conductive layer 2 opposite to each first conductive layer 12 can serve as the first plate C1 of the storage capacitor C. In the stacked structure 1, the portion of each first conductive layer 12 surrounding the trench T can serve as the second plate C2 of the storage capacitor C, and the remaining portion can serve as the plate line PL. Therefore, the portion of the second conductive layer 2 opposite to each first conductive layer 12, the portion of the first conductive layer 12 surrounding the trench T, and the portion of the storage dielectric layer 3 located between the first plate C1 and the second plate C2 can constitute a storage capacitor C, wherein the portion of the storage dielectric layer 3 located between the first plate C1 and the second plate C2 is used to store data.

[0109] Furthermore, each second conductive layer 2 can serve as a common electrode, so that the second conductive layer 2, the portion of the storage dielectric layer 3 located between the second conductive layer 2 and the trench T, and the portions of the multiple first conductive layers 12 of the stacked structure 1 that are directly opposite the second conductive layer 2 can form a storage capacitor string, and the storage capacitor string includes multiple storage capacitors C arranged in parallel. The storage capacitor string and the transistor Tr electrically connected thereto can form a storage unit 711. Each storage capacitor C can be used to store one bit of data, and the storage capacitor string can store multiple bits of data. The storage unit 711 has a 1TnC structure.

[0110] It is understood that in the process of preparing the above-mentioned storage array 710, a trench T can be first etched in the stacked structure 1, and then the storage dielectric layer 3 and the second conductive layer 2 are formed in the trench T. Compared with deep holes, the trench T has a better aspect ratio (AR) and is less difficult to etch. In this way, the size and area of ​​the storage capacitor C can be reduced by reducing the width of the trench T, making it easier to achieve a strict 4F 2 The minimum memory cell size allows for more memory cells 711 to be provided, thereby increasing the storage density of the memory array 710. In this case, the capacitance area of ​​the storage capacitor C can be increased by increasing the thickness of the first conductive layer 12, thereby ensuring the capacitance of the storage capacitor C.

[0111] In addition, if Figure 11 、 Figure 14 and Figure 15 As shown, the trench T extends along the first direction X, rather than being hole-shaped; the storage dielectric layer 3 is located between the sidewalls of the trench T and each second conductive layer 2, rather than surrounding each second conductive layer 2; and along the first direction X, the portion of the first conductive layer 12 that forms the second electrode C2 directly faces each second conductive layer 2, rather than surrounding each second conductive layer 2. Therefore, the storage capacitor C in the embodiment of the present application has a planar capacitor structure, rather than a ring-shaped capacitor structure.

[0112] Thus, on the one hand, Figure 16As shown, along the third direction Z, the difference in the facing area between the first plate C1 and the second plate C2 in different storage capacitors C is small. This can make the capacitance of different storage capacitors C tend to be consistent, improve the uniformity of the actual electric field distribution inside different storage capacitors C, thereby reducing electrical differences and improving the anti-interference ability of the storage capacitor C and the accuracy of its stored data. On the other hand, it can reduce the difference in the direction of the metal lattice felt at different positions of the storage medium layer 3, reduce the difference in stress felt at the internal and external interfaces of the storage medium layer 3, thereby reducing the difficulty of forming the orthorhombic phase (O phase) in the storage medium layer 3 and increasing the proportion of the orthorhombic phase (O phase) in the storage medium layer 3, which is conducive to improving the residual polarization strength of the storage medium layer 3.

[0113] In some embodiments, combined Figure 11 、 Figure 12 and Figure 13 The trench T has two first sidewalls T1 extending along a first direction X, and two second sidewalls T2 connecting the two first sidewalls T1. The first sidewalls T1 and the second sidewalls T2 are alternately connected to form a closed annular shape. The orthographic projection of the trench T on the second reference plane is a closed annular shape.

[0114] In some examples, such as Figure 11 and Figure 12 As shown, the two first side walls T1 are disposed opposite each other. Along the second direction Y, the two first side walls T1 at least partially overlap. For example, each first side wall T1 is planar. Here, the term "planar" is not limited to a strict "plane," as long as the first side wall T1 has a relatively high degree of flatness.

[0115] In this way, on the one hand, the angle between the portion of the side surface forming the first side wall T1 in each first conductive layer 12 and the third direction Z can be made consistent, so that the area of ​​the portion of the side surface forming the first side wall T1 in each first conductive layer 12 is made consistent, thereby facilitating the reduction of capacitance differences between different storage capacitors C in the same storage cell 711, improving the uniformity of the actual electric field distribution within different storage capacitors C in the same storage cell 711, and thus reducing electrical property differences. On the other hand, this further helps to reduce the differences in metal lattice orientation felt at different locations in the storage dielectric layer 3, further reducing the differences in stress felt at the internal and external interfaces of the storage dielectric layer 3, effectively reducing the difficulty of forming the orthorhombic phase (O phase) in the storage dielectric layer 3, and improving the remanent polarization strength of the storage dielectric layer 3.

[0116] Furthermore, if Figure 11 and Figure 12 As shown, the two first side walls T1 are parallel to each other.

[0117] This is not only beneficial to significantly improve the consistency of the capacitance of different storage capacitors C in the same storage unit 711, significantly improve the uniformity of the actual electric field distribution inside different storage capacitors C in the same storage unit 711, and effectively reduce the electrical difference, but also beneficial to significantly reduce the difference in the metal lattice direction felt by the storage medium layer 3 at different positions, significantly reduce the difference in stress felt by the internal and external interfaces of the storage medium layer 3, effectively reduce the difficulty of forming the orthorhombic phase (O phase) in the storage medium layer 3, and improve the residual polarization strength of the storage medium layer 3.

[0118] The second side wall T2 may be planar or curved. Furthermore, along the first direction X, the two second side walls T2 may be arranged opposite to each other or staggered. This embodiment of the present application does not limit this.

[0119] In some examples, such as Figure 11 and Figure 13 As shown, the two second side walls T2 are arranged opposite to each other and are planar.

[0120] In this way, on the one hand, it is beneficial to reduce the area occupied by the trench T and increase the effective occupied area of ​​the storage unit 711; on the other hand, when a second conductive layer 2 is provided at the end of the trench T, it can be ensured that the storage capacitor C corresponding to the second conductive layer 2 is a planar structure capacitor.

[0121] Furthermore, if Figure 11 and Figure 13 As shown, the two second side walls T2 are parallel to each other. Optionally, the first side wall T1 and the second side wall T2 are perpendicular to each other.

[0122] This helps to further reduce the area occupied by the trench T, further increase the effective occupied area of ​​the memory cell 711 , and further help to improve the storage density of the memory array 710 .

[0123] It is understandable that there are multiple configurations between the second conductive layer 2 and the storage medium layer 3, which can be selected according to actual needs. The following schematically illustrates the configuration between multiple second conductive layers 2 and the storage medium layer 3 located in the same trench T with reference to the accompanying drawings.

[0124] In some embodiments, as Figure 11 、 Figure 13 and Figure 14 As shown, the plurality of second conductive layers 2 located in the same trench T are arranged at intervals along the first direction X. That is, the plurality of second conductive layers 2 are arranged at intervals in a row.

[0125] Combine Figure 11 and Figure 13The orthographic projection of the storage dielectric layer 3 on the second reference plane is a closed ring. The storage dielectric layer 3 surrounds the multiple second conductive layers 2 located in the same trench T, rather than surrounding each second conductive layer 2 individually. The second reference plane is parallel to the first direction X and parallel to the second direction Y.

[0126] For example, Figure 12 and Figure 16 As shown, each storage capacitor C includes: a portion of the second conductive layer 2 directly opposite the first conductive layer 12, a portion of the first conductive layer 12 directly opposite the second conductive layer 2, and a portion of the storage dielectric layer 3 located between the two. The "portion of the first conductive layer 12 directly opposite the second conductive layer 2" includes a first sub-portion 121 and a second sub-portion 122, which are located on opposite sides of the second conductive layer 2, and the "portion of the storage dielectric layer 3 located between the two" includes a third sub-portion 31 and a fourth sub-portion 32, which are located on opposite sides of the second conductive layer 2.

[0127] exist Figure 12 and Figure 16 In the embodiment, each storage capacitor C includes two sub-capacitors C01 and C02 connected in parallel. Sub-capacitor C01 is composed of the first sub-portion 121, the third sub-portion 31, and the portion of the second conductive layer 2 directly opposite the first sub-portion 121. Sub-capacitor C02 is composed of the second sub-portion 122, the fourth sub-portion 32, and the portion of the second conductive layer 2 directly opposite the second sub-portion 122. Both sub-capacitors C01 and C02 have a planar capacitor structure.

[0128] In this way, it can be ensured that each storage capacitor C has a planar capacitor structure and that each storage capacitor C has a large capacitance.

[0129] In some examples, such as Figure 11 、 Figure 13 and Figure 15 As shown, the storage array 710 also includes multiple second dielectric layers 5. Each second dielectric layer 5 is strip-shaped and extends along the third direction Z. Multiple second dielectric layers 5 are disposed within each trench T. Along the first direction X, the second dielectric layers 5 and the second conductive layers 2 are alternately arranged. A second conductive layer 2 is disposed between two adjacent second dielectric layers 5, and a second dielectric layer 5 is disposed between two adjacent second conductive layers 2. The storage dielectric layer 3 further surrounds the multiple second dielectric layers 5. The second dielectric layers 5 do not disconnect the storage dielectric layers 3. The second dielectric layers 5 are used to provide electrical insulation between two adjacent second conductive layers 2.

[0130] The material of the second dielectric layer 5 includes, but is not limited to, insulating materials such as silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, titanium dioxide, yttrium oxide, silicon nitride, or any combination thereof. The structure of the second dielectric layer 5 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials. The material of the multiple second dielectric layers 5 can be the same, for example, to simplify the fabrication process of the memory array 710. Optionally, the material of the second dielectric layer 5 can be the same as or different from the material of the first dielectric layer 11.

[0131] For example, Figure 11 and Figure 14 As shown, when the second conductive layer 2 is provided at the end of the trench T and the second dielectric layer 5 is not provided, the storage dielectric layer 3 and the first conductive layer 12 are located on opposite sides of the second conductive layer 2 along the second direction Y and on one side along the first direction X, so that the storage capacitor C located at the end of the trench T has a U-shaped planar capacitor structure.

[0132] In other embodiments, Figure 21 、 Figure 22 and Figure 23 As shown, the plurality of second conductive layers 2 include a plurality of conductive layer pairs 2a, which are arranged at intervals along the first direction X. Each conductive layer pair 2a includes two second conductive layers 2 spaced apart along the second direction Y. Exemplarily, the plurality of second conductive layers 2 are arranged in two rows and multiple columns, with the two rows of second conductive layers including an equal number of second conductive layers 2, and the two second conductive layers 2 in each column of second conductive layers are, for example, at least partially facing each other.

[0133] Continue reading Figure 21 and Figure 22 The storage dielectric layer 3 is at least located between the plurality of conductive layer pairs 2a and the sidewalls of the trench T. For example, the storage dielectric layer 3 is at least located between the plurality of conductive layer pairs 2a and each first sidewall T1 of the trench T. No storage dielectric layer 3 is disposed between the two second conductive layers 2 included in each conductive layer pair 2a.

[0134] For example, Figure 23 As shown, the storage dielectric layer 3 includes a fifth sub-portion 33 located between each second conductive layer 2 and the adjacent first sidewall T1, and the first conductive layer 12 includes a sixth sub-portion 123 directly opposite the fifth sub-portion 33. Each storage capacitor C includes a portion of the second conductive layer 2 directly opposite the first conductive layer 12, the fifth sub-portion 33, and the sixth sub-portion 123. Furthermore, the storage capacitor C has a planar capacitor structure. Two adjacent second conductive layers 2 are independently disposed, and each second conductive layer 2 independently constitutes a storage capacitor string.

[0135] With the above arrangement, more second conductive layers 2 can be disposed in the same trench T, and thus more memory cells 711 can be disposed, which is beneficial for greatly improving the storage density of the memory array 710. In this embodiment, for example, the capacitance area of ​​the storage capacitor C can be increased by increasing the thickness of the first conductive layer 12, thereby ensuring the capacitance of the storage capacitor C.

[0136] In some examples, such as Figure 21 and Figure 22 As shown, the orthographic projections of the two second conductive layers 2 in the same conductive layer pair 2a on the first reference plane coincide. The first reference plane is parallel to the first direction X and the third direction Z. That is, along the second direction Y, the two second conductive layers 2 in the same conductive layer pair 2a face each other.

[0137] This is beneficial to improving the regularity of the arrangement of multiple second conductive layers 2 in the same trench T, reducing the space area occupied by each conductive layer pair 2a, and facilitating the arrangement of more second conductive layers 2 in the trench T, thereby greatly improving the storage density of the storage array 710.

[0138] In some examples, such as Figure 21 and Figure 22 As shown, the memory array 710 further includes a third dielectric layer 6, which extends along a third direction Z. The third dielectric layer 6 is located within the trench T and between any two adjacent second conductive layers 2 to separate the two adjacent second conductive layers 2. The third dielectric layer 6 is used to achieve electrical insulation between any two adjacent second conductive layers 2.

[0139] For example, Figure 21 and Figure 22 As shown, the third dielectric layer 6 includes a connected first dielectric sub-section 61 and multiple second dielectric sub-sections 62, wherein the multiple second dielectric sub-sections 62 are located on opposite sides of the first dielectric sub-section 61. The first dielectric sub-section 61 extends along the first direction X and is located between the two second conductive layers 2 in each conductive layer pair 2a. The second dielectric sub-section 62 is located between two adjacent second conductive layers 2 along the first direction X.

[0140] The materials of either the first dielectric sub-section 61 or the second dielectric sub-section 62 include, but are not limited to, insulating materials such as silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, or any combination thereof. The structure of either the first dielectric sub-section 61 or the second dielectric sub-section 62 may be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials. Optionally, the materials of the first dielectric sub-section 61 and the second dielectric sub-section 62 may be the same or different; and the structures of the first dielectric sub-section 61 and the second dielectric sub-section 62 may be the same or different.

[0141] In this embodiment, the storage medium layer 3 has various structures, which can be selected according to actual needs.

[0142] For example, Figure 21 As shown, the storage medium layer 3 surrounds the plurality of conductive layer pairs 2a. The orthographic projection of the storage medium layer 3 on the second reference plane is a closed ring. The storage medium layer 3 surrounds the plurality of conductive layer pairs 2a located in the same trench T, rather than surrounding each conductive layer pair 2a individually.

[0143] For example, Figure 22 As shown, the storage medium layer 3 has at least one gap G. Along the third direction Z, the gap G penetrates the storage medium layer 3 and is located at the end of the groove T. The orthographic projection of the storage medium layer 3 on the second reference plane is an open ring.

[0144] For example, along the second direction Y, the distance between the two second conductive layers 2 in the same conductive layer pair 2a is equal to the size of the gap G. The first dielectric sub-portion 61 of the third dielectric layer 6 is also located in the gap G, for example.

[0145] It is understood that the structure of the transistor Tr in the device layer 4 includes various structures and can be selected according to actual needs. Optionally, the transistor Tr includes but is not limited to a vertical transistor. In each figure, the transistor Tr is illustrated as a vertical transistor.

[0146] In some examples, such as Figure 12 、 Figure 13 and Figure 14 As shown, the transistor Tr includes a first electrode 71, a second electrode 72, a channel 73, a gate dielectric layer 74, and a gate 75. The first electrode 71, the channel 73, and the second electrode 72 are arranged in sequence along the third direction Z, and the channel 73 is a vertical channel. The gate dielectric layer 74 and the gate 75 are both located between the first electrode 71 and the second electrode 72, and the gate 75 is located on the side of the gate dielectric layer 74 away from the channel 73. Among them, one of the first electrode 71 and the second electrode 72 is a drain, and the other is a source. For example, the transistor Tr can be electrically connected to the second conductive layer 2 via the first electrode 71.

[0147] There are many relative positional relationships between the gate 75 and the channel 73. For example, Figure 18 As shown, the gate 75 is located on one side of the channel 73. In this case, the transistor Tr is a single-gate vertical planar transistor. Figure 17 As shown, the gate 75 is located on opposite sides of the channel 73. In this case, the transistor Tr is a dual-gate vertical planar transistor. Figure 16 and Figure 19As shown, the gate 75 surrounds the channel 73. In this case, the transistor Tr is a gate-all-around (GAA) field effect transistor. Figure 20 As shown, the channel 73 surrounds the gate 75, so that the gate dielectric layer 74 separates the gate 75 and the channel 73. In this case, the transistor Tr is a channel-around (CAA) field effect transistor. Of course, the relative positional relationship between the gate 75 and the channel 73 is not limited to this, and accordingly, the type of the transistor Tr is not limited to this.

[0148] Exemplarily, the material of any of the first electrode 71, the second electrode 72, and the gate 75 includes, but is not limited to, titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, or any combination thereof. The material of the channel 73 includes, but is not limited to, silicon (Si), polycrystalline silicon (poly-Si), amorphous silicon (a-Si), indium gallium zinc oxide (In-Ga-Zn-O, IGZO) multi-compound, zinc oxide (ZnO), indium tin oxide, titanium dioxide, molybdenum disulfide (MoS2), or any combination thereof. The material of the gate dielectric layer 74 includes, but is not limited to, insulating materials such as silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, titanium dioxide, yttrium trioxide, silicon nitride, or any combination thereof. The structure of the gate dielectric layer 74 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0149] In some embodiments, the device layer 4 may also include other structures. Figure 11 、 Figure 12 and Figure 13 As shown, the device layer 4 further includes a plurality of word lines WL and a plurality of bit lines BL. One of the word lines WL and the bit lines BL extends along a first direction X, and the other extends along a second direction Y. Figure 11 、 Figure 12 and Figure 13 The word lines WL extend along the first direction X and the bit lines BL extend along the second direction Y as an example for illustration.

[0150] Continue reading Figure 11 、 Figure 12 and Figure 13 The plurality of word lines WL are spaced apart along the second direction Y, and the plurality of bit lines BL are spaced apart along the first direction X. Each word line WL is electrically connected to the gates 75 of at least two transistors Tr sequentially arranged along the first direction X, and each bit line BL is electrically connected to the second electrodes 72 of at least two transistors Tr sequentially arranged along the second direction Y. The word line WL and the gates 75 of the transistors Tr electrically connected thereto are, for example, integrally structured, and the bit line BL and the second electrodes 72 of the transistors Tr electrically connected thereto are, for example, integrally structured.

[0151] Exemplarily, the material of any one of the word lines WL and the bit lines BL includes but is not limited to titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof.

[0152] Some embodiments of the present application also provide a method for preparing a memory array. The method is used, for example, to prepare the memory array 710 in some of the above embodiments. Figure 24 A flow chart illustrating a method for preparing a memory array is shown; Figure 25a-25h 、 Figure 26a-26b The structures corresponding to each step in a method for preparing a memory array are schematically shown. Figure 25b 、 Figure 25c 、 Figure 25d 、 Figure 25e 、 Figure 25f and Figure 25g , (b) of each figure is a partial cross-sectional structural diagram of (a) in the corresponding figure. Figure 25b-25g (b) and Figure 25h 、 Figure 26a-26b , respectively illustrate the local structure of the groove and the part of the film layer located in the groove, so as to more clearly illustrate the structure of the groove and the formation process of each film layer located in the groove. It should be understood that Figure 24 The steps shown are not exclusive and can also be Figure 24 Other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different order. Figure 24 Executed in the order shown.

[0153] The following is a schematic illustration of the method for preparing the memory array with reference to the accompanying drawings. Figure 24 As shown, the preparation method includes: S100-S300.

[0154] S100, such as Figure 25a As shown, an initial stacked structure 1 a is formed. The initial stacked structure 1 a includes a plurality of first dielectric layers 11 and a plurality of first conductive layers 12 alternately stacked along a third direction Z.

[0155] Exemplarily, the method for forming the above-mentioned initial stacked structure 1a includes: using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process or any combination of thin film deposition processes to deposit and form a first dielectric layer 11, and then using a CVD process, a PVD process, an ALD process or any combination of thin film deposition processes to form a first conductive layer 12 on the first dielectric layer 11, and then repeating the above steps to alternately form multiple first dielectric layers 11 and multiple first conductive layers 12.

[0156] The materials of the first dielectric layer 11 and the first conductive layer 12 can be found in the above description and will not be described in detail here.

[0157] S200, such as Figure 25b As shown in (a) and (b) of FIG. , at least one trench group TG is formed. The trench group TG includes a plurality of trenches T. Each trench T extends along a first direction X and penetrates the initial stacked structure 1a. The plurality of trenches T are spaced apart along a second direction Y. The first direction X, the second direction Y, and the third direction Z are mutually perpendicular.

[0158] Illustratively, in the embodiment of the present application, the initial stacked structure 1a may be etched using a photolithography process and a dry etching process (eg, with a better aspect ratio) to form a plurality of trenches T, thereby obtaining a trench group TG and a stacked structure 1.

[0159] For example, in an embodiment of the present application, a hard mask may be formed on the initial stacked structure 1a using a photolithography process, and then the initial stacked structure 1a may be etched using a dry etching process based on the hard mask to form a trench T that penetrates each first dielectric layer 11 and the first conductive layer 12 in the initial stacked structure 1a. The length of the trench T is greater than the width of the trench T. The length of the trench T refers to the dimension of the trench T in the first direction X, and the width of the trench T refers to the dimension of the trench T in the second direction Y.

[0160] Regarding the number and arrangement of the trench groups TG and the number and arrangement of the trenches T, please refer to the relevant descriptions above and will not be repeated here.

[0161] It is understandable that trenches T are easier to etch than deep holes. Therefore, during the process of etching trenches T, it is easier to reduce the width of trenches T, achieving a better aspect ratio (AR). This helps reduce the size of the storage capacitors C formed subsequently, making the memory arrays fabricated using the fabrication methods provided in the embodiments of the present application have greater scaling potential.

[0162] S300, such as Figure 25g As shown in (a) and (b) of FIG, a storage dielectric layer 3 and multiple second conductive layers 2 are sequentially formed in each trench T. The second conductive layer 2 extends along the third direction Z, and the multiple second conductive layers 2 are arranged at least at intervals along the first direction X. The storage dielectric layer 3 extends along the third direction Z and is located between each second conductive layer 2 and the sidewalls of the trench T.

[0163] For example, in the embodiment of the present application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to form the storage dielectric layer 3 or the second conductive layer 2 in the trench T. The materials of the second conductive layer 2 and the storage dielectric layer 3 can be found in the relevant description above and will not be repeated here.

[0164] It can be understood that since the storage dielectric layer 3 and the plurality of second conductive layers 2 are both located within the trench T, the second conductive layer 2 simultaneously surrounds the storage dielectric layer 3 and the plurality of second conductive layers 2 located within the trench, rather than surrounding each second conductive layer 2 individually. Accordingly, the portion of the first conductive layer 12 surrounding the trench T can constitute a second electrode plate C2 corresponding one-to-one with the second conductive layer 2. Based on the morphology of the trench T, the portion of the first conductive layer 12 used to constitute the second electrode plate C2 is planar, and the portion of the second conductive layer 2 used to constitute the first electrode plate C1 is planar. Therefore, the storage capacitor C in the embodiment of the present application has a planar capacitor structure, rather than a ring-shaped capacitor structure.

[0165] Based on this, some embodiments of the present application provide methods for preparing a memory array. By forming a trench T extending along a first direction X in an initial stacked structure 1a, and then forming a storage dielectric layer 3 and multiple second conductive layers 2 within the trench T, rather than forming a second conductive layer 2 within each trench T, the storage capacitors C corresponding to each second conductive layer 2 can be made to have a planar capacitor structure. In this way, on the one hand, along the third direction Z, the difference in the facing area between the first plate C1 and the second plate C2 in different storage capacitors C is small. This can make the capacitance of different storage capacitors C tend to be consistent, improve the uniformity of the actual electric field distribution within different storage capacitors C, thereby reducing electrical property differences and improving the anti-interference ability of the storage capacitors C and the accuracy of their stored data. On the other hand, it can reduce the difference in metal lattice direction felt at different positions of the storage dielectric layer 3, reduce the difference in stress felt at the internal and external interfaces of the storage dielectric layer 3, thereby reducing the difficulty of forming the orthorhombic phase (O phase) in the storage dielectric layer 3 and increasing the proportion of the orthorhombic phase (O phase) in the storage dielectric layer 3, which is conducive to improving the residual polarization strength of the storage dielectric layer 3.

[0166] In addition, since the etching difficulty of the trench T is smaller, the width of the trench T can be reduced in the process of etching the trench T, thereby reducing the size and area of ​​the storage capacitor C, making it easier to achieve a strict 4F 2 The minimum memory cell size allows more memory cells 711 to be arranged, thereby improving the storage density of the prepared memory array 710.

[0167] In some embodiments, in the above S300 , a storage medium layer 3 and a plurality of second conductive layers 2 are sequentially formed in each trench T, including: S310 - S340 .

[0168] S310, such as Figure 25c (a) and (b) in Figure 25d As shown in (a) and (b) of the drawings, a storage medium layer 3 is formed in the trench T, and the storage medium layer 3 covers the sidewalls of the trench T.

[0169] For example, Figure 25c As shown in (a) and (b) of FIG. 1 , the embodiment of the present application can use a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to deposit a target material in the trench T and on the initial stacked structure 1a to form a storage dielectric thin film. The storage dielectric thin film covers the sidewalls and bottom wall of the trench T and the surface of the stacked structure 1. The portion of the storage dielectric thin film that covers the sidewalls of the trench T is the trench storage dielectric layer 3.

[0170] Optionally, in the embodiment of the present application, a chemical mechanical polishing (CMP) process may be used to polish and remove a portion of the storage medium film located on the surface of the stacked structure 1 before or after filling the first dielectric material. For details about the first dielectric material, please refer to the relevant description below and will not be repeated here.

[0171] S320, such as Figure 25e As shown in (a) and (b) of FIG, a first dielectric material is filled in the trench T to form a filling portion 8. The storage medium layer 3 surrounds the filling portion 8.

[0172] For example, in the embodiment of the present application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the trench T with the first dielectric material. In addition to being located within and filling the trench T, the first dielectric material may also be located on the surface of the stacked structure 1. Optionally, in the embodiment of the present application, a CMP process may be used to polish away a portion of the first dielectric material located on the surface of the stacked structure 1, while retaining a portion of the first dielectric material located within the trench T, thereby obtaining the filling portion 8.

[0173] Exemplarily, the first dielectric material includes but is not limited to insulating materials such as silicon dioxide, aluminum oxide, hafnium dioxide, zirconium oxide, titanium dioxide, yttrium oxide, silicon nitride, or any combination thereof. The structure of the filling portion 8 can be a single-layer structure, a stacked structure, or a stacked structure composed of a combination of materials.

[0174] S330, such as Figure 25f As shown in (a) and (b) of FIG, the filling portion 8 is etched to form a plurality of second dielectric layers 5. The second dielectric layers 5 extend along the third direction Z, and the plurality of second dielectric layers 5 are spaced apart along the first direction X.

[0175] For example, after etching the filling portion 8, a plurality of slits S may be formed, each slit S extending along the third direction Z. Along the first direction X, the plurality of slits S and the plurality of second dielectric layers 5 are alternately arranged, and two adjacent second dielectric layers 5 are separated by the slit S located therebetween. The plurality of second dielectric layers 5 are arranged independently of each other. For example, along the second direction Y, the second dielectric layer 5 is in direct contact with the storage dielectric layer 3.

[0176] Along the first direction X, the size of the slit S can be set according to the capacitance of the storage capacitor C to be formed, which is not limited in the embodiment of the present application.

[0177] S340, such as Figure 25g As shown, a conductive material is filled in the trench T to form a plurality of second conductive layers 2. Along the first direction X, the second dielectric layers 5 and the second conductive layers 2 are alternately arranged.

[0178] For example, in the embodiment of the present application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof may be used to fill the trench T with a conductive material. This conductive material not only fills the plurality of slits S but also exists on the surface of the stacked structure 1. Alternatively, in the embodiment of the present application, a CMP process may be used to polish away a portion of the conductive material located on the surface of the stacked structure 1, while retaining a portion of the conductive material located within the slits S, to obtain a plurality of second conductive layers 2. Each adjacent second conductive layer 2 is separated by a second dielectric layer 5 located therebetween.

[0179] Exemplarily, the conductive materials include but are not limited to titanium nitride, titanium, gold, tungsten, molybdenum, indium tin oxide, aluminum, copper, ruthenium, silver, etc., or any combination thereof.

[0180] In this case, the plurality of second conductive layers 2 located in the trenches T are arranged in a row along the first direction X. The plurality of second conductive layers 2 in each trench T correspondingly form a row of memory cells 711 .

[0181] In this way, it can be ensured that each storage capacitor C has a planar capacitor structure and that each storage capacitor C has a large capacitance.

[0182] In some embodiments, the second conductive layer 2 may be arranged in other ways within the same trench T. Exemplarily, after the above S340 , the above preparation method further includes: S350 - S360 .

[0183] S350, such as Figure 26a As shown, a cutting gap CG is formed in the trench T, which at least penetrates the plurality of second conductive layers 2 and the plurality of second dielectric layers 5. The cutting gap CG extends along the first direction X.

[0184] Exemplarily, the cutting slit CG cuts each second conductive layer 2 into two second conductive layers 2 (ie, conductive layer pairs 2a) facing each other along the second direction Y, and cuts each second dielectric layer 5 into two second dielectric sub-portions 62 facing each other along the second direction Y.

[0185] Furthermore, the cutting gap CG may also cut the storage medium layer 3 to form a notch penetrating the storage medium layer 3 at the end of the trench T.

[0186] S360, such as Figure 26b As shown, the cutting gap CG is filled with a second dielectric material.

[0187] For example, in the embodiments of the present application, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to fill the slit CG with a second dielectric material to form a first dielectric sub-section 61. The first dielectric sub-section 61 separates the two second conductive layers 2 in each conductive layer pair 2a. The first dielectric sub-section 61 is connected to the plurality of second dielectric sub-sections 62, forming a trench in the third dielectric layer 6.

[0188] In this case, the plurality of second conductive layers 2 located in the trenches T are arranged in two rows at intervals along the first direction X. The plurality of second conductive layers 2 in each trench T correspondingly form two rows of memory cells 711 .

[0189] This effectively increases the number of second conductive layers 2 in the same trench T, thereby allowing for the provision of more memory cells 711 , thereby significantly improving the storage density of the memory array 710 .

[0190] In some embodiments, as Figure 25h As shown, the above preparation method further includes: forming a device layer 4 and electrically connecting the device layer 4 to the second conductive layer 2 .

[0191] Exemplarily, the device layer 4 and the initial stacked structure 1a can be prepared and formed independently of each other, and then the device layer 4 and the second conductive layer 2 are electrically connected; in this case, along the third direction Z, the device layer 4 is located below the stacked structure 1; along the third direction Z, the device layer 4 is located above the stacked structure 1. Alternatively, in an embodiment of the present application, the device layer 4 can be prepared first, and then the initial stacked structure 1a can be formed on the device layer 4, and then subsequent preparation steps can be performed. Alternatively, in an embodiment of the present application, the initial stacked structure 1a can be prepared first, and then after the second conductive layer 2 is prepared, the device layer 4 can be prepared and formed on the second conductive layer 2 or the stacked structure 1.

[0192] Here, combined with Figure 25c 、 Figure 25d and Figure 25h When the device layer 4 is located below the stacked structure 1 along the third direction Z, before S330, the preparation method further includes: etching and removing the portion of the storage dielectric layer 3 covering the bottom wall of the trench T to expose the bottom wall of the trench T. This facilitates electrical connection between the portion of the second conductive layer 2 extending into the bottom wall of the trench T and the device layer 4.

[0193] For example, Figure 25h As shown, the device layer 4 includes multiple transistors Tr, multiple word lines WL and multiple bit lines BL. The first electrode 71 of a transistor Tr is electrically connected to a second conductive layer 2, each word line WL is electrically connected to the gates 75 of at least two transistors Tr arranged in sequence along the first direction X, and each bit line BL is electrically connected to the second electrodes 72 of at least two transistors Tr arranged in sequence along the second direction Y.

[0194] Regarding the specific structure and materials of the transistor Tr, the arrangement and materials of the word line WL and the bit line BL, please refer to the relevant descriptions above and will not be repeated here.

[0195] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this disclosure should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A storage array, characterized in that: The storage array comprises: A stacked structure having at least one trench group; the trench group includes a plurality of trenches, the trenches extending along a first direction and penetrating the stacked structure, the plurality of trenches being spaced apart along a second direction; the stacked structure includes a plurality of first dielectric layers and a plurality of first conductive layers alternately stacked along a third direction; the first direction, the second direction, and the third direction being perpendicular to each other; a plurality of second conductive layers located in the groove; the second conductive layers extending along the third direction, and the plurality of second conductive layers being arranged at intervals at least along the first direction; A storage medium layer is located in the trench; the storage medium layer extends along the third direction, and the storage medium layer is located between each second conductive layer and a sidewall of the trench.

2. The storage array according to claim 1, wherein: The plurality of second conductive layers are arranged at intervals along the first direction; The storage medium layer surrounds the plurality of second conductive layers.

3. The storage array according to claim 2, wherein: The memory array further includes: a plurality of second dielectric layers, the second dielectric layers being located in the trenches and extending along the third direction; Along the first direction, the second dielectric layers and the second conductive layers are alternately arranged; and the storage dielectric layer further surrounds the plurality of second dielectric layers.

4. The storage array according to claim 1, wherein: The plurality of second conductive layers include a plurality of conductive layer pairs, the plurality of conductive layer pairs are spaced apart along the first direction; the conductive layer pair includes two second conductive layers spaced apart along the second direction; The storage medium layer is at least located between the plurality of conductive layer pairs and the sidewalls of the trench.

5. The storage array according to claim 4, wherein: The storage medium layer surrounds the plurality of conductive layer pairs; or, The storage medium layer has at least one notch; along the third direction, the notch penetrates the storage medium layer; and the notch is located at an end of the groove.

6. The storage array according to claim 4 or 5, characterized in that: The orthographic projections of the two second conductive layers in the conductive layer pair on the first reference plane coincide with each other; The first reference plane is parallel to the first direction and the third direction.

7. The storage array according to any one of claims 4 to 6, wherein: The storage array further includes: a third dielectric layer; The third dielectric layer is located in the trench and between any two adjacent second conductive layers.

8. The storage array according to any one of claims 1 to 7, wherein: There are multiple groove groups, at least two of which are arranged in sequence along the first direction, and at least two of which are arranged in sequence along the second direction.

9. The storage array according to any one of claims 1 to 8, wherein: The groove has two first side walls extending along the first direction. The two first side walls are oppositely arranged and are planar.

10. The storage array according to claim 9, wherein: The two first side walls are parallel to each other.

11. The storage array according to claim 9 or 10, wherein: The groove further has two second side walls connecting the two first side walls, and the two second side walls are oppositely arranged and are planar.

12. The storage array according to claim 11, wherein: The two second side walls are parallel to each other.

13. The storage array according to any one of claims 1 to 12, wherein: The memory array further comprises: a device layer; along the third direction, the device layer is located on one side of the stacked structure; The device layer includes: a plurality of transistors, at least two of the transistors being arranged in sequence along the first direction, and at least two of the transistors being arranged in sequence along the second direction; a first electrode of the transistor being electrically connected to the second conductive layer; a plurality of word lines extending along the first direction and arranged at intervals along the second direction; the word lines being electrically connected to gates of at least two of the transistors arranged sequentially along the first direction; A plurality of bit lines extend along the second direction and are arranged at intervals along the first direction; the bit lines are electrically connected to the second electrodes of at least two of the transistors arranged in sequence along the second direction.

14. The storage array according to any one of claims 1 to 13, wherein: The material of the storage medium layer includes ferroelectric material.

15. A method for preparing a storage array, characterized in that: The preparation method comprises: forming an initial stacked structure, the initial stacked structure comprising a plurality of first dielectric layers and a plurality of first conductive layers alternately stacked along a third direction; forming at least one groove group; the groove group includes a plurality of grooves, the grooves extending along a first direction and penetrating the initial stacked structure, the plurality of grooves being spaced apart along a second direction; the first direction, the second direction, and the third direction being perpendicular to each other; A storage medium layer and a plurality of second conductive layers are sequentially formed in the groove; the second conductive layer extends along the third direction, and the plurality of second conductive layers are at least spaced apart along the first direction; the storage medium layer extends along the third direction, and the storage medium layer is located between each of the second conductive layers and the sidewall of the groove.

16. The preparation method according to claim 15, characterized in that The step of sequentially forming a storage medium layer and a plurality of second conductive layers in each of the trenches includes: forming the storage medium layer in the trench; the storage medium layer covers the sidewalls of the trench; Filling the groove with a first dielectric material to form a filling portion; the storage dielectric layer surrounds the filling portion; Etching the filling portion to form a plurality of second dielectric layers; the second dielectric layers extend along the third direction, and the plurality of second dielectric layers are spaced apart along the first direction; Conductive material is filled in the trench to form the plurality of second conductive layers; and the second dielectric layers and the second conductive layers are alternately arranged along the first direction.

17. The preparation method according to claim 16, characterized in that The preparation method further comprises: In the trench, a cutting slit is formed which at least penetrates the plurality of second conductive layers and the plurality of second dielectric layers; the cutting slit extends along the first direction; The cutting gap is filled with a second dielectric material.

18. The preparation method according to any one of claims 15 to 17, characterized in that: The preparation method further comprises: forming a device layer, and electrically connecting the device layer to the second conductive layer; Wherein, the device layer includes: a plurality of transistors, at least two of the transistors being arranged in sequence along the first direction, and at least two of the transistors being arranged in sequence along the second direction; a first electrode of the transistor being electrically connected to the second conductive layer; a plurality of word lines extending along the first direction and arranged at intervals along the second direction; the word lines being electrically connected to gates of at least two of the transistors arranged sequentially along the first direction; A plurality of bit lines extend along the second direction and are arranged at intervals along the first direction; the bit lines are electrically connected to the second electrodes of at least two of the transistors arranged in sequence along the second direction.

19. A memory, characterized in that: The memory includes: The storage array according to any one of claims 1 to 14; A controller is electrically connected to the storage array; the controller is used to control the reading and writing of the storage array.

20. An electronic device, characterized in that: The electronic device comprises: The memory as claimed in claim 19; A circuit board is electrically connected to the memory.

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