Semiconductor structure and forming method

Abstract

The invention provides a semiconductor structure and a forming method, and the semiconductor structure comprises a substrate, a barrier layer, a groove structure, a plurality of supporting structures, and a capacitor structure. Wherein the barrier layer covers a partial region of the substrate; the groove structure penetrates through the barrier layer and extends into the substrate; the multiple supporting structures are arranged in the groove structure and extend to the opening end from the bottom of the groove structure; the capacitor structure covers the plurality of supporting structures and covers the groove structure. Therefore, the capacitance density of the capacitor structure can be further improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] The rapid development of the semiconductor industry is driving technological advancements. Limited by the laws of physics, increasing device density and miniaturizing device size per unit area in traditional chip manufacturing faces numerous challenges, and Moore's Law is gradually approaching its physical limits. Against this backdrop, three-dimensional integration technology has emerged as a key path to breaking through existing bottlenecks and continuing the semiconductor industry's momentum, attracting significant research and development resources from researchers and companies worldwide.

[0003] With its unique advantages, three-dimensional integration technology has opened up a new path for chip performance improvement and function expansion. Among them, the 2.5D silicon adapter board process route, as a crucial technical branch in three-dimensional integration technology, plays an irreplaceable role in achieving high-speed interconnection between chips and improving system integration. In the complex system of 2.5D silicon adapter board technology, deep trench capacitors (DTCs) are important components, and their performance directly affects the operating performance of the entire system. Improving the capacitance density per unit area of ​​deep trench capacitors can achieve greater capacitance storage capacity within a limited chip space, and has become the core direction of the industry's long-term unremitting exploration. However, existing methods of increasing capacitance density are often accompanied by a significant increase in process difficulty, which not only increases production costs, but also extends the R&D cycle, restricting the large-scale application and promotion of the technology. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same to further improve the capacitance density of deep trench capacitors.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate, a barrier layer, a groove structure, a plurality of support structures and a capacitor structure; wherein the barrier layer covers a partial area of ​​the substrate; the groove structure penetrates the barrier layer and extends into the interior of the substrate; the plurality of support structures are all arranged in the groove structure and extend from the bottom of the groove structure to the open end; the capacitor structure covers the plurality of support structures and covers the groove structure.

[0007] In the above scheme, the multiple support structures extend along the first direction and are arranged at intervals; the first direction is perpendicular to the bottom surface of the groove structure; the support structure includes a support column and an epitaxial column; wherein the support column extends from the bottom of the groove structure to the first contact interface; the epitaxial column extends from the first contact interface to the open end of the groove structure; the first contact interface is the reference plane where the contact interface between the substrate and the barrier layer is located.

[0008] In the above solution, the length of the epitaxial column in the first direction is greater than the length of the supporting column in the first direction.

[0009] In the above scheme, the capacitor structure includes: a first electrode layer, an insulating dielectric layer and a second electrode layer; wherein, the first electrode layer covers multiple support structures and covers the groove structure; the insulating dielectric layer covers the first electrode layer; and the second electrode layer covers the insulating dielectric layer.

[0010] An embodiment of the present disclosure also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a barrier layer on the substrate; wherein the barrier layer covers a partial area of ​​the substrate; forming a groove structure and a plurality of support structures; wherein the groove structure passes through the barrier layer and extends into the interior of the substrate; the plurality of support structures are all arranged in the groove structure and extend from the bottom of the groove structure to the open end; forming a capacitor structure; wherein the capacitor structure covers the plurality of support structures and covers the groove structure.

[0011] In the above scheme, the support structure includes: support columns and epitaxial columns; forming multiple support structures includes: etching the substrate to form multiple support columns and the groove structure; filling the groove structure to form a first sacrificial layer; etching the first sacrificial layer to form a first hard mask; wherein the grooves of the first hard mask expose the top surfaces of the multiple support columns; epitaxially growing multiple epitaxial columns on the top surfaces of the multiple support columns; wherein the multiple epitaxial columns fill the grooves of the first hard mask; and removing the first hard mask.

[0012] In the above scheme, etching the first sacrificial layer to form the first hard mask includes: forming a photoresist pattern on the surface of the blocking structure and the first sacrificial layer; wherein the photoresist pattern is the same as the pattern of the plurality of support pillars; and etching along the photoresist pattern until the top surface of the support pillar is exposed.

[0013] In the above scheme, the substrate is etched to form the plurality of support pillars and the groove structure, including: etching the substrate to form the plurality of support pillars; filling the gaps between the plurality of support pillars to form a second sacrificial layer; depositing a blocking material layer on the top surfaces of the second sacrificial layer and the plurality of support pillars; etching the blocking material layer to form the blocking layer; wherein the blocking layer exposes the second sacrificial layer and the top surfaces of the plurality of support pillars; and removing the second sacrificial layer.

[0014] In the above solution, forming the capacitor structure includes: depositing a first electrode layer, an insulating dielectric layer and a second electrode layer in sequence on the surfaces of the plurality of support structures, the barrier layer and the groove structure.

[0015] The groove structure in the present disclosure passes through the barrier layer and extends to the inside of the substrate. In other words, the barrier layer and the portion of the substrate covered by it together constitute the sidewalls of the groove structure. Multiple support structures extend from the bottom surface of the groove structure to the open end. In this way, the barrier layer of the embodiment of the present disclosure can increase the length of the sidewalls of the groove structure. The length of the multiple support structures is greater than the depth of the groove structure in the substrate. In other words, the embodiment of the present disclosure extends the multiple support structures, as well as the length of the sidewalls of the groove structure. Thus, when the capacitor structure covers the support structure and covers the groove structure, the multiple support structures and the sidewalls of the groove structure in the embodiment of the present disclosure can increase the area of ​​the capacitor structure, further improving the capacitance density of the capacitor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of the semiconductor structure provided in the embodiment of the present disclosure Figure 1 ;

[0017] Figure 2 Schematic diagram of the semiconductor structure provided in the embodiment of the present disclosure Figure 2 ;

[0018] Figure 3 A schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 4 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 1 ;

[0020] Figure 5 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 2 ;

[0021] Figure 6 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 3 ;

[0022] Figure 7 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 4 ;

[0023] Figure 8 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 5 ;

[0024] Figure 9 A schematic diagram of the structure during the formation of the semiconductor structure provided in the embodiment of the present disclosure Figure 6 . DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0026] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0027] If similar descriptions of "first / second" appear in the application documents, the following explanation is added. In the following description, the terms "first / second / third" are merely used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0029] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, semiconductor structure, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or also includes elements inherent to such process, semiconductor structure, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, semiconductor structure, article, or device comprising the element.

[0030] Figure 1 and Figure 2 is a schematic structural diagram of an optional semiconductor structure 100 provided in an embodiment of the present disclosure. It should be noted that: Figure 1 and Figure 2 The first direction X in the example may be perpendicular to the substrate 10, and the second direction Y may be parallel to the substrate 10. Figure 1 In order to facilitate the illustration of the groove structure 30, the Figure 2 Capacitor structure 50 is shown.

[0031] In the embodiments of the present disclosure, reference Figure 1 , the semiconductor structure 100 includes a substrate 10, a barrier layer 20 and a groove structure 30. The barrier layer 20 covers a portion of the substrate 10; for example, the barrier layer 20 can cover the area on the substrate 10 for forming a capacitor. The material of the barrier layer 20 can be silicon nitride (Si3N4) or the like. The groove structure 30 penetrates the barrier layer 20 and extends into the interior of the substrate 10. In other words, the barrier layer 20 and the portion of the substrate 10 covered by it together constitute the sidewall of the groove structure 30. In this way, the barrier layer 20 of the embodiment of the present disclosure can increase the length of the sidewall of the groove structure 30 in the first direction X.

[0032] In the embodiment of the present disclosure, Figure 1 and Figure 2 , the semiconductor structure 100 also includes a plurality of support structures 40 and a capacitor structure 50. The capacitor structure 50 can be a deep trench capacitor (Deep Trench Capacitor). The material of the support structure 40 can be a material such as silicon (Si). The plurality of support structures 40 are all arranged in the groove structure 30. For example, the plurality of support structures 40 can be distributed inside the groove structure 30 in the form of an array layout. The plurality of support structures 40 extend from the bottom surface 31 of the groove structure to the open end 32. That is, the length of the plurality of support structures 40 in the first direction X is greater than the depth of the groove structure 30 in the substrate 10.

[0033] Further, combined with Figure 1 and Figure 2 The capacitor structure 50 covers the plurality of support structures 40 and covers the groove structure 30. In this way, the plurality of support structures 40 can increase the area of ​​the capacitor structure 50 by extending the length in the first direction X. The groove structure 30 can increase the area of ​​the capacitor structure 50 by extending the thickness of the barrier layer 20 in the first direction X.

[0034] It can be understood that the length of the multiple support structures 40 in the first direction X in the embodiment of the present disclosure is greater than the depth of the groove structure 30 in the substrate 10. The barrier layer 20 can increase the length of the sidewall of the groove structure 30 in the first direction X. In this way, the embodiment of the present disclosure extends the length of the multiple support structures 40 and the sidewall of the groove structure 30 in the first direction X. Therefore, the sidewalls of the multiple support structures 40 and the groove structure 30 in the embodiment of the present disclosure can increase the area of ​​the capacitor structure 50, thereby further improving the capacitance density of the capacitor structure 50.

[0035] In some embodiments of the present disclosure, reference Figure 1 , multiple support structures 40 all extend along the first direction X and are arranged at intervals. The first direction X is perpendicular to the bottom surface 31 of the groove structure 30. The support structure 40 includes a support column 41 and an epitaxial column 42. Among them, the support column 41 extends from the bottom surface 31 of the groove structure 30 to the first contact interface 33. The epitaxial column 42 extends from the first contact interface 33 to the open end 32 of the groove structure 30. The first contact interface 33 is the reference plane where the contact interface between the substrate 10 and the barrier layer 20 is located. In other words, the embodiment of the present disclosure increases the length of the support structure 40 in the first direction X by epitaxially growing the epitaxial column 42 on the support column 41, thereby being able to further improve the capacitance density of the capacitor structure 50.

[0036] In some embodiments of the present disclosure, reference Figure 1 , the length of the epitaxial pillar 42 in the first direction X is greater than the length of the support pillar 41 in the first direction X. In this way, the embodiment of the present disclosure increases the extension of the epitaxial pillar 42 in the first direction X, thereby further increasing the length of the support structure 40 in the first direction X, and can further increase the capacitance density of the capacitor structure 50.

[0037] In some embodiments of the present disclosure, reference Figure 2 The capacitor structure 50 covers the barrier layer 20. Thus, the electrodes in the capacitor structure 50 are exposed on the horizontal plane where the barrier layer 20 is located, thereby facilitating the extraction of the first electrode layer 51 and the third electrode layer 53 of the capacitor structure 50 from the barrier layer 20.

[0038] In some embodiments of the present disclosure, reference Figure 2The capacitor structure 50 includes a first electrode layer 51, an insulating dielectric layer 52, and a second electrode layer 53. The first electrode layer 51 covers the multiple support structures 40 and covers the groove structure 30. The insulating dielectric layer 52 covers the first electrode layer 51. The second electrode layer 53 covers the insulating dielectric layer 52. The material of the first electrode layer 51 and the second electrode layer 53 can be any one of conductive materials such as tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). The material of the insulating dielectric layer 52 can be any one or a combination of any of insulating materials such as silicon oxide (SiO2) and low-k dielectrics.

[0039] It should be noted that Figure 2 The isolation layer 60 is used to isolate multiple sections of the third electrode layer 53 located on different support structures 40. The isolation layer 60 can be made of any one or a combination of insulating materials such as silicon oxide (SiO2) and low-k dielectrics.

[0040] Figure 3 is a schematic flow chart of a method for forming a semiconductor structure provided by an embodiment of the present disclosure. Figure 3 The exemplary forming method can be used to form Figure 2 The semiconductor structure shown will be described in conjunction with each step.

[0041] S101. Provide a substrate.

[0042] S102 , forming a barrier layer on the substrate; wherein the barrier layer covers a partial area of ​​the substrate.

[0043] S103, forming a groove structure and multiple supporting structures; wherein the groove structure penetrates the barrier layer and extends into the interior of the substrate; the multiple supporting structures are all arranged in the groove structure and extend from the bottom of the groove structure to the open end.

[0044] Figure 4 、 Figure 5 and Figure 6 This is a schematic structural diagram of an optional semiconductor structure during the formation process provided by an embodiment of the present disclosure. It should be noted that: Figure 4 Specifically, the substrate 10 and the substrate for forming Figure 2 The barrier material layer 210 of the middle barrier layer 20, Figure 5 The first photoresist layer 81 for forming the blocking layer is specifically illustrated. Figure 6 The groove structure 30 and the barrier layer 20 are specifically illustrated.

[0045] In the embodiments of the present disclosure, reference Figure 4 The substrate 10 may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0046] In the embodiments of the present disclosure, reference Figure 4 , a barrier material layer 210 is deposited on the substrate 10 by a process such as chemical vapor deposition (CVD). Then, a second hard mask is formed on the barrier material layer 210, and the barrier material layer 210 and the substrate 10 are etched along the second hard mask to form Figure 4 The support column 41 is shown.

[0047] Further, combined with Figure 4 and Figure 5 By using chemical vapor deposition (CVD) and other processes, the gaps between the support pillars 41 are filled with materials such as silicon oxide to form a Figure 5 The second sacrificial layer 71 is formed as shown, and then a first photoresist layer 81 is formed on the surface of the second sacrificial layer 71. The pattern of the first photoresist layer 81 is consistent with the pattern of the barrier layer. Therefore, the second sacrificial layer 71 and the barrier material layer 210 are etched along the first photoresist layer 81 to form Figure 6 The barrier layer 20 and the recessed structure 30 are shown.

[0048] Figure 7 、 Figure 8 and Figure 9 This is a schematic structural diagram of an optional semiconductor structure during the formation process provided by an embodiment of the present disclosure. It should be noted that: Figure 7 Specific examples are given for forming Figure 1 The first sacrificial layer 72 and the first hard mask 82 of the epitaxial pillar 42, Figure 8 Specific examples are given for forming Figure 1 The filling structure 73 of the middle epitaxial pillar 42 is shown. Figure 9 Specific examples are given Figure 1 The epitaxial column 42 in the.

[0049] In the embodiment of the present disclosure, Figure 6 and Figure 7 , depositing silicon dioxide and other materials in the groove structure 30 to form Figure 7 The first sacrificial layer 72 is shown. Then, a first hard mask 82 is formed on the surface of the first sacrificial layer 72. The projection of the pattern of the first hard mask 82 can cover the epitaxial pillars 42 and expose the gaps between the epitaxial pillars 42. Then, the first sacrificial layer 72 is etched along the first hard mask 82 until the top surface of the epitaxial pillars 42 is exposed, forming Figure 8 Filling structure 73 is shown.

[0050] Further, combined with Figure 8 and Figure 9 , formed on the top surface of the epitaxial column 42 by an epitaxial process Figure 9 Epitaxial pillars 42 are shown. Filling structures 73 may define the orientation of epitaxial pillars 42.

[0051] S104 , forming a capacitor structure; wherein the capacitor structure covers the plurality of support structures and covers the groove structure.

[0052] In the embodiment of the present disclosure, Figure 9 and Figure 2 , in removing Figure 9 After filling the structure 73 shown in FIG, a dielectric material, a first electrode, an insulating dielectric layer, and a second electrode are sequentially deposited to form Figure 2 The capacitor structure 50 is shown. Then, a dielectric material is deposited to fill the remaining gap of the groove structure to form Figure 2 An isolation layer 60 is shown.

[0053] It can be understood that in the embodiment of the present disclosure, the lengths of the multiple support structures 40 and the sidewalls of the groove structure 30 in the first direction X are extended. Therefore, the multiple support structures 40 and the sidewalls of the groove structure 30 in the embodiment of the present disclosure can increase the area of ​​the capacitor structure 50, thereby further improving the capacitance density of the capacitor structure 50.

[0054] In some embodiments of the present disclosure, it is also possible to implement the following steps S201 to S205: Figure 2 S103 in the embodiment will be described in conjunction with each step.

[0055] S201 , etching the substrate to form a plurality of support pillars and groove structures.

[0056] S202 , filling the groove structure to form a first sacrificial layer.

[0057] S203 , etching the first sacrificial layer to form a first hard mask; wherein the grooves of the first hard mask expose top surfaces of the plurality of support pillars.

[0058] S204 , epitaxially growing a plurality of epitaxial pillars on top surfaces of the plurality of support pillars; wherein the plurality of epitaxial pillars fill the trenches of the first hard mask.

[0059] In the embodiment of the present disclosure, Figure 8 and Figure 9 , formed on the top surface of the epitaxial column 42 by an epitaxial process Figure 9 Epitaxial pillars 42 are shown.

[0060] It is understandable that the support column 41 is usually formed by etching the substrate 10, and the epitaxial column 42 is usually formed on the support column 41 by an epitaxial process or the like. However, the existing epitaxial growth is constrained by factors such as stress accumulation, defect formation and process control, and there are technical limitations on the length. In the embodiment of the present disclosure, the filling structure 73 can define the direction of the epitaxial column 42, thereby increasing the length of the epitaxial column 42, further increasing the length of the support structure 40 in the first direction X, and further increasing the capacitance density of the capacitor structure 50.

[0061] S205 , removing the first hard mask.

[0062] In some embodiments of the present disclosure, S202 may also be implemented through S301 to S302, which will be described in conjunction with each step.

[0063] S301 , forming a photoresist pattern on surfaces of the blocking structure and the first sacrificial layer; wherein the photoresist pattern is the same as a pattern of the plurality of support pillars.

[0064] S302 , etching along the photoresist pattern until the top surface of the support pillar is exposed.

[0065] In the embodiment of the present disclosure, Figure 6 and Figure 7 , the first sacrificial layer 72 is etched along the first hard mask 82 until the top surface of the epitaxial column 42 is exposed, forming Figure 8 Filling structure 73 is shown.

[0066] In some embodiments of the present disclosure, S201 may also be implemented through S401 to S405 , which will be described in conjunction with each step.

[0067] S401 , etching the substrate to form a plurality of support pillars.

[0068] S402 , filling the gaps between the plurality of support pillars to form a second sacrificial layer.

[0069] S403 , depositing a barrier material layer on top surfaces of the second sacrificial layer and the plurality of support pillars.

[0070] S404, etching the barrier material layer to form a barrier layer; wherein the barrier layer exposes the top surfaces of the second sacrificial layer and the plurality of support pillars;

[0071] S405 , removing the second sacrificial layer.

[0072] In the embodiments of the present disclosure, reference Figure 4, a barrier material layer 210 is deposited on the substrate 10 by a process such as chemical vapor deposition (CVD). Then, a second hard mask is formed on the barrier material layer 210, and the barrier material layer 210 and the substrate 10 are etched along the second hard mask to form Figure 4 The support column 41 is shown.

[0073] Further, combined with Figure 4 and Figure 5 By using chemical vapor deposition (CVD) and other processes, the gaps between the support pillars 41 are filled with materials such as silicon oxide to form a Figure 5 The second sacrificial layer 71 is formed as shown, and then a first photoresist layer 81 is formed on the surface of the second sacrificial layer 71. The pattern of the first photoresist layer 81 is consistent with the pattern of the barrier layer. Therefore, the second sacrificial layer 71 and the barrier material layer 210 are etched along the first photoresist layer 81 to form Figure 6 The barrier layer 20 and the recessed structure 30 are shown.

[0074] In some embodiments of the present disclosure, S104 may also be implemented through S501 , which will be described in conjunction with each step.

[0075] S501 , depositing a first electrode layer, an insulating dielectric layer, and a second electrode layer in sequence on surfaces of a plurality of support structures, barrier layers, and groove structures.

[0076] In the embodiment of the present disclosure, Figure 9 and Figure 2 , in removing Figure 9 After filling the structure 73 shown in FIG, a dielectric material, a first electrode, an insulating dielectric layer, and a second electrode are sequentially deposited to form Figure 2 The capacitor structure 50 is shown. Then, a dielectric material is deposited to fill the remaining gap of the groove structure to form Figure 2 An isolation layer 60 is shown.

[0077] The serial numbers of the embodiments of the present disclosure are for descriptive purposes only and do not represent the merits of the embodiments. The semiconductor structures disclosed in the several semiconductor structure embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments. The features disclosed in the several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several semiconductor structure or device embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new semiconductor structure embodiments or device embodiments.

[0078] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: substrate, barrier layer, groove structure, multiple support structures and capacitor structure; wherein, The barrier layer covers a portion of the substrate; The groove structure penetrates the barrier layer and extends into the interior of the substrate; The plurality of support structures are all disposed in the groove structure and extend from the bottom of the groove structure to the open end; The capacitor structure covers the plurality of support structures and covers the groove structure.

2. The semiconductor structure according to claim 1, wherein: The plurality of support structures extend along a first direction and are spaced apart; the first direction is perpendicular to the bottom surface of the groove structure; the support structure includes a support column and an epitaxial column; wherein, The support column extends from the bottom of the groove structure to a first contact interface; the epitaxial column extends from the first contact interface to the open end of the groove structure; the first contact interface is a reference plane where the contact interface between the substrate and the barrier layer is located.

3. The semiconductor structure according to claim 2, wherein: The length of the epitaxial column in the first direction is greater than the length of the supporting column in the first direction.

4. The semiconductor structure according to claim 1, wherein: The capacitor structure covers the barrier layer.

5. The semiconductor structure according to claim 1, wherein: The capacitor structure includes: a first electrode layer, an insulating dielectric layer, and a second electrode layer; wherein, The first electrode layer covers the plurality of support structures and covers the groove structure; The insulating dielectric layer covers the first electrode layer; The second electrode layer covers the insulating dielectric layer.

6. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a barrier layer on the substrate; wherein the barrier layer covers a portion of the substrate; A groove structure and a plurality of support structures are formed; wherein the groove structure penetrates the barrier layer and extends into the interior of the substrate; the plurality of support structures are all disposed in the groove structure and extend from the bottom of the groove structure to the open end; A capacitor structure is formed; wherein the capacitor structure encloses the plurality of support structures and covers the groove structure.

7. The forming method according to claim 6, wherein: The support structure includes: a support column and an epitaxial column; forming a plurality of said support structures, comprising: Etching the substrate to form a plurality of support pillars and the groove structure; filling the groove structure to form a first sacrificial layer; Etching the first sacrificial layer to form a first hard mask; wherein the grooves of the first hard mask expose the top surfaces of the plurality of support pillars; Epitaxially growing a plurality of epitaxial pillars on top surfaces of the plurality of support pillars; wherein the plurality of epitaxial pillars fill the trenches of the first hard mask; The first hard mask is removed.

8. The forming method according to claim 7, wherein: Etching the first sacrificial layer to form the first hard mask includes: forming a photoresist pattern on the surfaces of the blocking structure and the first sacrificial layer; wherein the photoresist pattern is the same as the pattern of the plurality of support pillars; Etching is performed along the photoresist pattern until the top surface of the support pillar is exposed.

9. The forming method according to claim 7, wherein: Etching the substrate to form a plurality of support pillars and the groove structure, comprising: Etching the substrate to form a plurality of support pillars; filling the gaps between the plurality of support pillars to form a second sacrificial layer; Depositing a barrier material layer on top surfaces of the second sacrificial layer and the plurality of support pillars; Etching the barrier material layer to form the barrier layer; wherein the barrier layer exposes the second sacrificial layer and the top surfaces of the plurality of support pillars; The second sacrificial layer is removed.

10. The forming method according to claim 9, wherein: Forming the capacitor structure includes: A first electrode layer, an insulating dielectric layer and a second electrode layer are sequentially deposited on surfaces of the plurality of support structures, the barrier layer and the groove structure.

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