Metal capacitor structure and preparation method thereof

Abstract

According to the metal capacitor structure and the preparation method thereof provided by the invention, the TixOy transition layer is grown in situ at the interface of the first polar plate and the insulating layer through a plasma process, the problem of high interface roughness is successfully solved, the forbidden bandwidth of TixOy is greater than that of titanium nitride, the transition layer can prevent migration of carriers across the interface, and the performance of the metal capacitor structure is improved. A first oxide layer is formed on the surface of the insulating layer through a plasma process, so that interface defects on the surface of the insulating layer are reduced, abnormal charge aggregation is avoided, local strong electric field concentration causing early breakdown is reduced, and breakdown is fundamentally delayed; in addition, active Si atoms in the silicon-rich oxide layer can capture plasma charges, so that the silicon-rich oxide layer is used as a charge neutralization layer, charges generated in the plasma process are prevented from being accumulated on the insulating layer and migrated and accumulated into the insulating layer, and the overall breakdown resistance is further enhanced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a metal capacitor structure and a preparation method thereof. Background Art

[0002] Capacitors are used in semiconductor integrated circuits for charge storage, coupling, and filtering. Metal-insulator-metal (MIM) capacitors are widely used in analog and RF circuits due to their low parasitic resistance, stable frequency characteristics, and ability to be formed directly from the device's interconnect layers. Different applications require different parasitic resistance requirements for metal capacitors. For example, in RF circuits, due to the high frequencies (GHz), the capacitive reactance is low, and the parasitic resistance contributes to the overall impedance of the metal capacitor, making it necessary to minimize the parasitic resistance. However, for low-frequency analog circuits such as panel driver chips, when metal capacitors are used as charge pump storage, the breakdown voltage (BV) becomes a critical parameter limiting device reliability. A high breakdown voltage (typically at least 25V) effectively ensures the stability of the dielectric layer under long-term high-voltage stress, avoiding the risk of failure caused by time-dependent dielectric breakdown (TDDB).

[0003] Figure 1 The figure shows a cross-sectional view of a metal capacitor structure in the prior art. Figure 1 The metal capacitor structure includes a substrate and a capacitor structure formed on the substrate. The capacitor structure includes a barrier layer, a lower plate, a capacitor insulating layer, an upper plate and an anti-reflection layer stacked on the substrate from bottom to top. Part of the upper plate is removed by photolithography and selective etching, and the anti-reflection layer covers the capacitor insulating layer. Then, part of the lower plate is removed by photolithography and selective etching. On the one hand, multiple patterning steps will cause the capacitor insulating layer to be exposed to the plasma environment, which is easy to cause surface defects and increase the interface state density, thereby weakening the dielectric strength of the capacitor insulating layer. On the other hand, Figure 2 The TEM image of the prior art metal capacitor structure shown shows that the roughness of the lower plate surface is high, resulting in uneven coverage of the capacitor insulation layer. This causes the actual electric field strength in the weak spots to be significantly higher than the theoretical value, which can easily induce premature breakdown. When the above metal capacitor structure is further applied to the manufacture of semiconductor devices, the breakdown voltage value of the semiconductor device is tested. The test results show that the breakdown voltage of the metal capacitor structure is only 17.7V, far below the conventional breakdown voltage value of 25V, thereby significantly reducing the reliability of the semiconductor device.

[0004] Therefore, it is necessary to provide a metal capacitor structure and a preparation method thereof to solve the problem of low breakdown voltage of the metal capacitor structure. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a metal capacitor structure and a preparation method thereof, so as to solve the problem of low breakdown voltage of the metal capacitor structure in the prior art and the resulting reduced device reliability.

[0006] To achieve the above-mentioned and other related objectives, the present invention provides a method for preparing a metal capacitor structure, the method comprising:

[0007] Providing a substrate, and sequentially preparing an etching stop layer and a first electrode plate on the substrate;

[0008] performing an oxidation treatment on the surface of the first electrode plate using a first plasma to form a transition layer on the first electrode plate;

[0009] depositing an insulating layer on the transition layer, and performing an oxidation treatment on the surface of the insulating layer using a first plasma to form a first oxide layer on the insulating layer;

[0010] forming a second electrode plate and a first anti-reflection layer on the first oxide layer, partially etching the second electrode plate using the first anti-reflection layer as a mask layer to expose the insulating layer, and removing the first anti-reflection layer;

[0011] performing an oxidation treatment on the surface of the second electrode plate and the insulating layer using a second plasma to form a second oxide layer on the second electrode plate and a third oxide layer on the insulating layer;

[0012] forming a silicon-rich oxide layer and a second anti-reflection layer in sequence on the second oxide layer and the third oxide layer, wherein the silicon-rich oxide layer covers the second oxide layer and the third oxide layer, and the second anti-reflection layer covers the silicon-rich oxide layer;

[0013] The first electrode plate is etched to remove a portion of the first electrode plate.

[0014] Optionally, the first plasma is oxygen gas, and the second plasma is nitrous oxide gas.

[0015] Optionally, the process temperature corresponding to the oxidation treatment of the surface of the first electrode plate using the first plasma is set to 200°C~420°C, and the process temperature corresponding to the oxidation treatment of the surface of the insulating layer using the first plasma is set to 200°C~420°C.

[0016] Optionally, the time for oxidizing the surface of the first electrode plate using the first plasma is 10 to 200 seconds, and the time for oxidizing the surface of the insulating layer using the first plasma is 10 to 200 seconds.

[0017] Optionally, the process temperature corresponding to the oxidation treatment of the surface of the second electrode plate and the insulating layer using the second plasma is set to 300°C to 420°C, and the time for the oxidation treatment of the surface of the second electrode plate and the insulating layer using the second plasma is 10 to 200s.

[0018] Optionally, the width of the second electrode plate after the second electrode plate is partially etched is smaller than the width of the first electrode plate after the first electrode plate is etched.

[0019] Optionally, the thickness of the silicon-rich oxide layer is 100-300Å.

[0020] Optionally, the material of the first electrode plate and the second electrode plate includes titanium nitride.

[0021] Optionally, the insulating layer is made of silicon nitride.

[0022] The present invention also provides a metal capacitor structure, which is manufactured using the above-mentioned method for manufacturing the metal capacitor structure.

[0023] As described above, the present invention provides a metal capacitor structure and a preparation method thereof, which has the following beneficial effects: a TixOy transition layer is in-situ grown at the interface between the first electrode and the insulating layer through a plasma process, and the transition layer successfully solves the problem of high interface roughness in the traditional process, and the band gap width of TixOy is greater than the band gap width of titanium nitride, so that the transition layer becomes an effective charge blocking barrier, significantly hindering the migration of carriers across the interface, thereby effectively suppressing the leakage current at the interface and improving the withstand voltage capability of the insulating layer. The present invention applies the plasma process to the oxidation treatment of the surface of the insulating layer to form a first oxide layer, so that the interface on the surface of the insulating layer is The significant reduction in surface defects, pinholes, or uneven areas prevents abnormal charge accumulation, resulting in a more balanced voltage distribution during device operation. This significantly reduces the localized strong electric field concentration that can lead to early breakdown, fundamentally delaying the onset of breakdown. The excess active Si atoms in the silicon-rich oxide layer can capture plasma charges generated during the plasma process, allowing the silicon-rich oxide layer to act as a charge neutralization layer, actively consuming and blocking the accumulation of charges generated during the plasma process on the insulating layer, as well as their migration and accumulation within the insulating layer. This further enhances the overall breakdown resistance. Breakdown voltage testing of the metal capacitor structure revealed a breakdown voltage of 27 V. This significant improvement in breakdown voltage, one of the most critical indicators of a capacitor's ability to operate stably under high-voltage conditions, significantly enhances the device's ability to withstand abnormal voltage stress without failure under complex operating conditions (such as high temperature, high humidity, and high bias). This not only significantly reduces the risk of accidental failure due to voltage overload during application, but also provides a solid foundation for long-term, stable, and reliable device operation, significantly extending its service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a cross-sectional schematic diagram of a metal capacitor structure in the prior art.

[0025] Figure 2 Shown is a TEM image of a metal capacitor structure in the prior art.

[0026] Figure 3 It is a schematic flow chart of the method for preparing the metal capacitor structure of the present invention.

[0027] Figure 4 It is a schematic diagram of the cross-sectional structure after forming an etching stop layer and a first electrode plate on a substrate according to the present invention.

[0028] Figure 5 It shows a schematic diagram of the cross-sectional structure after the transition layer is formed in the present invention.

[0029] Figure 6 It shows a schematic diagram of the cross-sectional structure after the insulating layer and the first oxide layer are formed according to the present invention.

[0030] Figure 7 It shows a schematic cross-sectional structure diagram after forming the second electrode plate and the first anti-reflection layer according to the present invention.

[0031] Figure 8 It shows a schematic cross-sectional structure diagram of the second electrode plate after partial etching according to the present invention.

[0032] Figure 9 It shows a schematic diagram of the cross-sectional structure after the second oxide layer and the third oxide layer are formed according to the present invention.

[0033] Figure 10 It is a schematic diagram of the cross-sectional structure after forming the silicon-rich oxide layer and the second anti-reflection layer according to the present invention.

[0034] Figure 11 It shows a schematic diagram of the cross-sectional structure after the first electrode plate is partially etched according to the present invention.

[0035] Component number description

[0036] 11. Base; 12. Barrier layer; 13. Lower plate; 14. Capacitor insulating layer; 15. Upper plate; 16. Anti-reflection layer; 101. Substrate; 1011. Dielectric layer; 1012. Metal via; 102. Etching barrier layer; 103. First plate; 104. Transition layer; 105. Insulation layer; 106. First oxide layer; 107. Second plate; 108. First anti-reflection layer; 109. Second oxide layer; 110. Third oxide layer; 111. Silicon-rich oxide layer; 112. Second anti-reflection layer; S1~S7, steps. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0038] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0039] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "over," and the like may be used herein to describe the relationship of one element or feature to other elements or features illustrated in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings, and may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which additional features are formed between the first and second features so that the first and second features may not be in direct contact. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0040] See also Figures 3 to 11 It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0041] Example 1

[0042] This embodiment provides a method for preparing a metal capacitor structure. Figure 3 , which is a process flow chart of the preparation method, comprising the following steps:

[0043] S1: providing a substrate 101, and sequentially preparing an etching stop layer 102 and a first electrode plate 103 on the substrate 101;

[0044] S2: using a first plasma to perform an oxidation treatment on the surface of the first electrode plate 103 to form a transition layer 104 on the first electrode plate 103;

[0045] S3: depositing an insulating layer 105 on the transition layer 104 , and performing an oxidation treatment on the surface of the insulating layer 105 using a first plasma to form a first oxide layer 106 on the insulating layer 105 ;

[0046] S4: forming a second electrode 107 and a first anti-reflection layer 108 on the first oxide layer 106, partially etching the second electrode 107 using the first anti-reflection layer 108 as a mask layer to expose the insulating layer 105, and removing the first anti-reflection layer 108;

[0047] S5: using a second plasma to oxidize the surface of the second electrode plate 107 and the insulating layer 105 to form a second oxide layer 109 on the second electrode plate 107 and a third oxide layer 110 on the insulating layer 105;

[0048] S6: forming a silicon-rich oxide layer 111 and a second anti-reflection layer 112 on the second oxide layer 109 and the third oxide layer 110 in sequence, wherein the silicon-rich oxide layer 111 covers the second oxide layer 109 and the third oxide layer 110, and the second anti-reflection layer 112 covers the silicon-rich oxide layer 111;

[0049] S7: Etching the first electrode plate 103 to remove a portion of the first electrode plate 103 .

[0050] The method for preparing the metal capacitor structure of this embodiment will be described in detail below with reference to the specific drawings.

[0051] like Figure 4 As shown, step S1 is performed to provide a substrate 101, and an etching stop layer 102 and a first electrode 103 are sequentially prepared on the substrate 101. Optionally, the substrate 101 may include a silicon substrate 101, a germanium substrate 101, a silicon-germanium substrate 101, or an insulator substrate 101, such as a silicon-on-insulator (SOI) substrate 101 or a silicon-on-glass (SOG) substrate 101, and before performing subsequent processes, the substrate 101 may be cleaned first, for example, by sequentially using an organic solvent such as acetone and deionized water to remove contaminants on the surface of the substrate 101, and then drying, or first using a dilute acid solution to remove the natural oxide layer on the surface of the substrate 101, and then using deionized water to clean, and finally drying, or using the aforementioned cleaning methods for multiple cleanings. It should be noted that in this embodiment, as Figure 4 FIG. 1 is a schematic cross-sectional view of the substrate 101. In this embodiment, the substrate 101 is a copper-containing structure fabricated using a Damascene process. The substrate 101 includes a dielectric layer 1011 and metal vias 1012. The metal vias 1012 are formed in the dielectric layer 1011. Specifically, the dielectric layer 1011 may be a single layer or a stack of one or more dielectric materials. The dielectric materials may include silicon oxide, or materials with a relatively high dielectric constant, such as silicon nitride (SiN), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum oxide (Al2O3), titanium oxide (TiO2), or ferroelectric materials. For example, dielectric materials that can be used to form the dielectric layer 1011 include any one of silicon nitride (SiN), silicon oxide, or silicon oxynitride. Preferably, the material of the metal vias 1012 includes one or more of titanium, copper, or aluminum.

[0052] Furthermore, an etch stop layer 102 and a first electrode 103 are sequentially formed on the substrate 101. The etch stop layer 102 covers the surface of the substrate 101 and can prevent damage to the substrate 101 during subsequent etching of the first electrode 103. The etch stop layer 102 can be formed by a chemical vapor deposition process or a thermal oxidation process. The material forming the etch stop layer 102 includes nitrogen-doped silicon carbide or silicon nitride. The first electrode 103 (for example, including a tantalum nitride or titanium nitride layer) can also be formed on the etch stop layer 102 by a sputtering process. Preferably, in this embodiment, the material of the first electrode 103 is titanium nitride. Figure 5 As shown, step S2 is performed to oxidize the surface of the first electrode plate 103 using a first plasma to form a transition layer 104 on the first electrode plate 103 .

[0053] As an example, the first plasma is oxygen, and the process temperature corresponding to the oxidation treatment of the surface of the first electrode plate 103 using the first plasma is set to 200°C~420°C, and the time for oxidizing the surface of the first electrode plate 103 using the first plasma is 10~200s.

[0054] Specifically, the substrate 101 is placed in a reaction chamber of a plasma process equipment and a gas mixture of a first plasma is introduced. The flow rate of the first plasma can be 1000 sccm to 20000 sccm. The first plasma can be oxygen (O2). The surface of the first electrode 103 is oxidized using the first plasma for 10 to 200 seconds to oxidize the titanium nitride layer on the surface of the first electrode 103 into TixOy, thereby forming a transition layer 104 on the first electrode 103. In one embodiment, the titanium nitride layer on the surface of the first electrode 103 can be oxidized using the first plasma, and the corresponding process temperature can be set to 200°C to 420°C. Figure 5 As shown, TixOy serves as the transition layer 104, and its surface is smoother, which solves the problem of high surface roughness of the first electrode 103. In addition, the band gap of TixOy is greater than the band gap of titanium nitride, making the transition layer 104 an effective charge blocking barrier, thereby effectively suppressing the leakage current at the interface and improving the voltage resistance of the subsequently formed insulating layer 105.

[0055] like Figure 6 As shown, step S3 is performed to deposit an insulating layer 105 on the transition layer 104 , and oxidize the surface of the insulating layer 105 using a first plasma to form a first oxide layer 106 on the insulating layer 105 .

[0056] As an example, the first plasma is oxygen, and the process temperature corresponding to the oxidation treatment of the surface of the insulating layer 105 using the first plasma is set to 200°C~420°C, and the time for oxidizing the surface of the insulating layer 105 using the first plasma is 10~200s.

[0057] Specifically, the insulating layer 105 can be formed by a chemical vapor deposition process. The material of the insulating layer 105 includes any one of silicon nitride and silicon oxide. In this embodiment, silicon nitride with a higher dielectric constant is preferably used. After the insulating layer 105 is formed, the substrate 101 is placed in the reaction chamber of the plasma process equipment again and a gas mixture of the first plasma is introduced. The flow rate of the first plasma can be 1000sccm~20000sccm. The first plasma can be oxygen (O2). The time for oxidizing the surface of the first electrode 103 using the first plasma is 10~200s, so as to oxidize the silicon nitride layer on the surface of the insulating layer 105 into SixOyNz, thereby forming a first oxide layer 106 on the insulating layer 105. In one embodiment, the silicon nitride layer on the surface of the insulating layer 105 can be oxidized using the first plasma, and the corresponding process temperature can be 200℃~420℃. Figure 6 As shown, SixOyNz as the first oxide layer 106 has better uniformity than pure silicon nitride, which greatly reduces the interface defects or uneven areas on the surface of the insulating layer 105, thereby avoiding abnormal accumulation of charges and reducing local electric field concentration, making the voltage distribution more balanced when the device is working, fundamentally delaying the occurrence of breakdown.

[0058] like Figure 7 and Figure 8 As shown, step S4 is performed to form a second electrode 107 and a first anti-reflection layer 108 on the first oxide layer 106, and the second electrode 107 is partially etched based on the first anti-reflection layer 108 as a mask layer to expose the insulating layer 105, and the first anti-reflection layer 108 is removed.

[0059] Specifically, the second electrode plate 107 can be formed by a physical vapor deposition process, and the material forming the second electrode plate 107 includes a tantalum nitride or titanium nitride layer. Preferably, in this embodiment, the material of the second electrode plate 107 is the same as that of the first electrode plate 103, both of which are titanium nitride.

[0060] Specifically, such as Figure 7As shown, after the second electrode plate 107 is formed, a first anti-reflection layer 108 needs to be formed on the surface of the second electrode plate 107. For example, an epitaxial process or a deposition process is performed on the surface of the second electrode plate 107 to form the first anti-reflection layer 108. The first anti-reflection layer 108 can effectively reduce light reflection and reduce or even eliminate the standing wave effect.

[0061] Specifically, such as Figure 8 As shown, a photoresist is coated on top of the first anti-reflection layer 108, and a patterning process is performed on the second electrode 107 using the first anti-reflection layer 108 as a mask layer. The patterning process includes, but is not limited to, process steps such as exposure, development, and etching. After the patterning process, the second electrode 107 is partially etched away to expose the insulating layer 105. Since the first anti-reflection layer 108 is formed on the surface of the second electrode 107, the standing wave effect during exposure can be effectively prevented during the patterning process, making the sidewall morphology of the etched portion of the second electrode 107 more uniform. In addition, after the second electrode 107 is partially etched, the photoresist coated on the top of the first anti-reflection layer 108 needs to be removed through ashing, pickling and drying processes. In this process, the first anti-reflection layer 108 is easily damaged, causing its physical or optical properties to deteriorate. Therefore, after the photoresist is removed, the first anti-reflection layer 108 needs to be removed through processes such as plasma dry etching. In other embodiments, the first anti-reflection layer 108 can also be removed by a wet etching process based on the different etching ratios of the first anti-reflection layer 108 and the second electrode 107 in the chemical solution.

[0062] like Figure 9 As shown, step S5 is performed to oxidize the surface of the second electrode plate 107 and the insulating layer 105 using a second plasma to form a second oxide layer 109 on the second electrode plate 107 and a third oxide layer 110 on the insulating layer 105 .

[0063] As an example, the second plasma is nitrous oxide gas, and the second plasma is used to oxidize the surface of the second electrode 107 and the insulating layer 105. The corresponding process temperature is set to 300°C to 420°C, and the time for oxidizing the surface of the second electrode 107 and the insulating layer 105 using the second plasma is 10 to 200s.

[0064] Specifically, the substrate 101 is placed again in the reaction chamber of the plasma enhanced chemical vapor deposition process equipment and a second plasma gas mixture is introduced. The flow rate of the second plasma can be 1000sccm~20000sccm, and the second plasma can be nitrous oxide (N2O). The second plasma is used to oxidize the surface of the second electrode 107 and the insulating layer 105 for 10~200s, so that the titanium nitride layer on the surface of the second electrode 107 can be oxidized to TixOy, thereby forming a second oxide layer 109 on the second electrode 107, and the silicon nitride layer on the surface of the insulating layer 105 is oxidized to SixOyNz, thereby forming a third oxide layer 110 on the insulating layer 105. Among them, the surface of the second oxide layer 109 is smoother, which can solve the problem of high surface roughness of the second electrode 107, and the band gap width of TixOy is greater than the band gap width of titanium nitride, making the second oxide layer 109 an effective charge blocking barrier, thereby effectively suppressing the leakage current at the interface and improving the voltage resistance of the metal capacitor structure. SixOyNz, as the third oxide layer 110, has better surface uniformity than the insulating layer 105 formed by pure silicon nitride, greatly reducing the interface defects or unevenness on the surface of the insulating layer 105, thereby avoiding abnormal charge accumulation and reducing local electric field concentration, which can fundamentally delay the possibility of breakdown of the metal capacitor.

[0065] like Figure 10 As shown, step S6 is performed to sequentially form a silicon-rich oxide layer 111 and a second anti-reflection layer 112 on the second oxide layer 109 and the third oxide layer 110, wherein the silicon-rich oxide layer 111 covers the second oxide layer 109 and the third oxide layer 110, and the second anti-reflection layer 112 covers the silicon-rich oxide layer 111.

[0066] Specifically, the process of depositing the silicon-rich oxide layer 111 on the second oxide layer 109 and the third oxide layer 110 may include using an atomic layer deposition (ALD) process, a molecular beam epitaxy (MBE) process, or a chemical vapor deposition (CVD) process. In some embodiments, the thickness of the silicon-rich oxide layer 111 is 100~300Å. As a type of oxide layer, the silicon-rich silicon oxide layer (SRO) has good adhesion, so that the second oxide layer 109 and the third oxide layer 110 and the subsequently formed second anti-reflection layer 112 are stably adhered together to improve the stability between the material layers. In addition, the material in the silicon-rich oxide layer 111 refers to a non-stoichiometric silicon oxide (SiOx) material, and its silicon-oxygen ratio is greater than the stoichiometric silicon-oxygen ratio of about 1:2. The excess active Si atoms can capture the plasma charge in the plasma process, so that the silicon-rich oxide layer 111 can act as a charge neutralization layer, actively consuming and blocking the charge generated in the plasma process from accumulating on the insulating layer 105 and migrating and accumulating into the insulating layer 105, further enhancing the overall anti-breakdown capability of the metal capacitor structure.

[0067] Specifically, the second anti-reflection layer 112 is deposited on the silicon-rich oxide layer 111 using the same material and growth method as used to form the first anti-reflection layer 108, so that the second anti-reflection layer 112 has the same properties as the first anti-reflection layer 108 before photolithography.

[0068] like Figure 11 As shown, step S7 is performed to etch the first electrode plate 103 to remove a portion of the first electrode plate 103 .

[0069] Specifically, such as Figure 11 As shown, an etching process is performed on the first electrode 103 based on the second anti-reflection layer 112 as a mask layer, wherein the etching barrier layer 102 serves as the end point of etching, and the material layers above the etching barrier layer 102 are etched away. Since the second anti-reflection layer 112 is formed on the surface of the second electrode 107, the standing wave effect can be effectively prevented during the etching process, and the side wall morphology of the first electrode 103 and the etched parts of the material layers can be made more uniform. In addition, the width of the first electrode 103 after etching is greater than the width of the second electrode 107 after partially etching the second electrode 107, thereby finally forming a metal capacitor structure.

[0070] In other embodiments, the present invention also provides a metal capacitor structure, wherein the metal capacitor structure can be directly prepared using the above-mentioned preparation method of the metal capacitor structure, so that the specific materials and parameters of the metal capacitor structure can refer to the above content and will not be repeated here. Of course, according to needs, the metal capacitor structure can also be prepared using other preparation processes.

[0071] In summary, the present invention provides a metal capacitor structure and a preparation method thereof, wherein a TixOy transition layer is in-situ grown at the interface between the first electrode and the insulating layer through a plasma process, and the transition layer successfully solves the problem of high interface roughness in the traditional process, and the band gap width of TixOy is greater than the band gap width of titanium nitride, making the transition layer an effective charge blocking barrier, significantly hindering the migration of carriers across the interface, thereby effectively suppressing the leakage current at the interface and improving the withstand voltage capability of the insulating layer. The present invention applies a plasma process to the oxidation treatment of the surface of the insulating layer to form a first oxide layer, so that the interface defects on the surface of the insulating layer, The significant reduction in pinholes or uneven areas prevents abnormal charge accumulation, resulting in a more balanced voltage distribution during device operation. This significantly reduces the localized strong electric field concentration that can lead to early breakdown, fundamentally delaying the onset of breakdown. The excess active Si atoms in the silicon-rich oxide layer can capture plasma charges generated during the plasma process, allowing the silicon-rich oxide layer to act as a charge neutralization layer, actively consuming and blocking the accumulation of charges generated during the plasma process on the insulating layer, as well as their migration and accumulation within the insulating layer. This further enhances the overall breakdown resistance. Breakdown voltage testing of the metal capacitor structure revealed a breakdown voltage of 27 V. This significant improvement in breakdown voltage, one of the most critical indicators for measuring the stable operation of capacitor devices under high-voltage environments, significantly enhances the device's ability to withstand abnormal voltage stress without failure under complex operating conditions (such as high temperature, high humidity, and high bias). This not only significantly reduces the risk of accidental failure due to voltage overload during application, but also provides a solid foundation for long-term, stable, and reliable device operation, significantly extending its service life. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a metal capacitor structure, characterized in that: The preparation method comprises: Providing a substrate, and sequentially preparing an etching stop layer and a first electrode plate on the substrate; performing an oxidation treatment on the surface of the first electrode plate using a first plasma to form a transition layer on the first electrode plate; depositing an insulating layer on the transition layer, and performing an oxidation treatment on the surface of the insulating layer using a first plasma to form a first oxide layer on the insulating layer; forming a second electrode plate and a first anti-reflection layer on the first oxide layer, partially etching the second electrode plate using the first anti-reflection layer as a mask layer to expose the insulating layer, and removing the first anti-reflection layer; performing an oxidation treatment on the surface of the second electrode plate and the insulating layer using a second plasma to form a second oxide layer on the second electrode plate and a third oxide layer on the insulating layer; forming a silicon-rich oxide layer and a second anti-reflection layer in sequence on the second oxide layer and the third oxide layer, wherein the silicon-rich oxide layer covers the second oxide layer and the third oxide layer, and the second anti-reflection layer covers the silicon-rich oxide layer; The first electrode plate is etched to remove a portion of the first electrode plate.

2. The method for preparing a metal capacitor structure according to claim 1, wherein: The first plasma is oxygen gas, and the second plasma is nitrous oxide gas.

3. The method for preparing a metal capacitor structure according to claim 1, wherein: The process temperature corresponding to the oxidation treatment of the surface of the first electrode plate using the first plasma is set to 200°C~420°C, and the process temperature corresponding to the oxidation treatment of the surface of the insulating layer using the first plasma is set to 200°C~420°C.

4. The method for preparing a metal capacitor structure according to claim 1, wherein: The time for oxidizing the surface of the first electrode plate using the first plasma is 10 to 200 seconds, and the time for oxidizing the surface of the insulating layer using the first plasma is 10 to 200 seconds.

5. The method for preparing a metal capacitor structure according to claim 1, wherein: The process temperature corresponding to the oxidation treatment of the surface of the second electrode plate and the insulating layer using the second plasma is set to 300° C. to 420° C., and the time for the oxidation treatment of the surface of the second electrode plate and the insulating layer using the second plasma is 10 to 200 seconds.

6. The method for preparing a metal capacitor structure according to claim 1, wherein: The width of the second electrode plate after the second electrode plate is partially etched is smaller than the width of the first electrode plate after the first electrode plate is etched.

7. The method for preparing a metal capacitor structure according to claim 1, wherein: The thickness of the silicon-rich oxide layer is 100-300 Å.

8. The method for preparing a metal capacitor structure according to any one of claims 1 to 7, characterized in that: The material of the first electrode plate and the second electrode plate includes titanium nitride.

9. The method for preparing a metal capacitor structure according to any one of claims 1 to 7, characterized in that: The insulating layer is made of silicon nitride.

10. A metal capacitor structure, characterized in that: The metal capacitor structure is manufactured by the method for manufacturing a metal capacitor structure according to any one of claims 1 to 9.

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