Semiconductor device based on BCD process and manufacturing method thereof

Abstract

The invention discloses a semiconductor device based on a BCD process and a manufacturing method thereof. In the device, an N-type buried layer, a deep N well region and a first N well region are all located in the middle of a P-type substrate and are sequentially arranged from bottom to top; the first N well region comprises a P buried layer well region; the P buried layer well region comprises a second N well region; the middle of the second N well region surrounds the first P well region; a shallow trench isolation structure is formed on the P-type substrate; forming N + injection regions in the two N-type isolator regions; the third N well is located in the middle of the first P well, and an N + injection region is formed in the third N well; two P + injection regions are formed in the first P trap and are isolated through a shallow trench. According to the invention, the P buried layer well region is introduced into the first N well region, and the P buried layer well region not only can be in short circuit with the first N well region, but also can float. When negative voltage is applied to the cathode of the device, the P buried layer well region can block an electric leakage path from the substrate to the N-type isolator region, and the negative-voltage-resistant working state of the device is realized when the device is applied to the active clamp of a high-side power switch.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology and relates to a semiconductor device based on a BCD process and a manufacturing method thereof. Background Art

[0002] The BCD process is primarily used to fabricate easily integrated lateral double-diffused metal oxide semiconductors (LDMOS). With the development of intelligent power switches, the BCD process can also be used to create PN junction diodes by fabricating the LDMOS P-type and N-type well regions. Diodes are widely used as reference voltage sources in regulated power supplies and as protection diodes in overcurrent protection circuits. They are also used for surge protection, overvoltage protection, arc suppression, and series voltage regulation.

[0003] When traditional BCD process diodes are used in active clamping of high-side power switches, the cathode forward withstand voltage is usually achieved by the PN junction. However, when a negative voltage is applied to the diode cathode, the isolation potential of the diode will be clamped to a negative potential. At this time, the PN junction at the substrate to the isolation potential is turned on, and a leakage path exists, resulting in increased leakage current and affecting the reliability performance of the device. Specifically, Figure 1 The structure of the traditional BCD process diode is shown in the figure. When a negative voltage is applied to the diode contact electrode 15, the potential of the N-type isolator region 8 of the diode is clamped to a negative potential. At this time, the substrate is at zero potential, and the PN junction from the substrate to the N-type isolator region 8 is turned on. There is a leakage path, which leads to an increase in leakage current. It can be seen that the traditional BCD process diode does not have reverse voltage resistance. Summary of the Invention

[0004] The purpose of the present invention is to propose a semiconductor device based on the BCD process. While fully utilizing the preparation process of the BCD process, by adding an injection of the P buried layer well region, the current from the substrate to the N-type isolator region is blocked, thereby facilitating the application of multiple diodes in series in the active clamping of the high-side power switch to achieve a negative voltage-resistant working state of the device.

[0005] In order to achieve the above-mentioned purpose, the present invention adopts the following technical solutions:

[0006] A semiconductor device based on a BCD process includes a P-type substrate, an N-type buried layer, a deep N-well region, and a first N-well region; the N-type buried layer, the deep N-well region, and the first N-well region are all located in the middle of the P-type substrate and are arranged in order from bottom to top;

[0007] A P buried well region is provided in the middle of the first N well region, and the junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region; a second N well region is provided in the middle of the P buried well region, and the depth and width of the second N well region are respectively smaller than the depth and width of the P buried well region;

[0008] A first P-well region is provided in the middle of the second N-well region; a shallow trench is formed on the P-type substrate for isolating the active region and the N-type isolation region, wherein the depth of the shallow trench is less than the depth of the second N-well region;

[0009] Two N-type isolator regions are provided in the second N-well region, and the two N-type isolator regions are respectively located on the left and right sides of the first P-well region; and heavily doped N+ implantation regions are formed in the two N-type isolator regions respectively.

[0010] A third N-well region is provided in the middle of the first P-well region, and the third N-well region is connected to the second N-well region;

[0011] A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the first P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, respectively, and are isolated by shallow trenches;

[0012] The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the second N-well region form a second PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode;

[0013] A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

[0014] In addition, based on the above structure, the present invention also proposes a method for manufacturing a semiconductor device based on the BCD process, which is used to manufacture the semiconductor device based on the BCD process. The technical solution is as follows:

[0015] A method for manufacturing a semiconductor device based on a BCD process comprises the following steps:

[0016] Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate;

[0017] Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate;

[0018] Step 3. A P buried well region is defined by a photolithography process, and a P-type ion implantation process is performed to form a P buried well region in the first N well region. The junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region.

[0019] Step 4. A second N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a second N-well region in the P-buried layer well region. The depth and width of the second N-well region are respectively smaller than the junction depth and junction width of the P-buried layer well region.

[0020] Step 5. Use a photolithography process to define a first P-well region, and perform a P-type ion implantation process to form the first P-well region in the second N-well region;

[0021] Step 6. Form a shallow trench on the P-type substrate to isolate the active area from the N-type isolator region; define a third N-well region using a photolithography process, and perform an N-type ion implantation process to form a third N-well region in the first P-well region. The third N-well region is connected to the second N-well region; and form two N-type isolator regions in the second N-well region using an N-type ion implantation process.

[0022] Step 7. Use an ion implantation process to implant heavily doped N+ regions into the third N-well region and the two N-type isolation regions; implant heavily doped P+ regions onto the surface of the second P-well region; deposit a process dielectric layer on the surface of the P-type substrate, etch contact holes in the dielectric layer through an etching process, and fill the holes with metal to form contact hole metal, i.e., contact electrodes.

[0023] Based on the above-mentioned semiconductor device based on the BCD process, the present invention further proposes an improved semiconductor device based on the BCD process, in which the second N-well region is omitted, and the following technical solution is adopted:

[0024] A semiconductor device based on a BCD process includes a P-type substrate, an N-type buried layer, a deep N-well region, and a first N-well region; the N-type buried layer, the deep N-well region, and the first N-well region are all located in the middle of the P-type substrate and are arranged in order from bottom to top;

[0025] Two P buried layer well regions are provided in the first N well region and are respectively located at the left and right sides of the first N well region; the junction depth and junction width of the P buried layer well regions are respectively smaller than the junction depth and junction width of the first N well region;

[0026] A first P-well region is provided in the middle of the first N-well region; a shallow trench is formed on the P-type substrate to isolate the active region and the N-type isolator region; an N-type isolator region is provided in each P-buried well region; and heavily doped N+ implant regions are formed in the two N-type isolator regions.

[0027] A third N-well region is provided in the middle of the first P-well region, and the third N-well region is connected to the first N-well region;

[0028] A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the first P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, respectively, and are isolated by shallow trenches;

[0029] The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode

[0030] A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

[0031] In addition, based on the above structure, the present invention also proposes a method for manufacturing a semiconductor device based on the BCD process, which is used to manufacture the semiconductor device based on the BCD process. The technical solution is as follows:

[0032] A method for manufacturing a semiconductor device based on a BCD process comprises the following steps:

[0033] Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate;

[0034] Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate;

[0035] Step 3. Define a P buried well region using a photolithography process, and perform a P-type ion implantation process to form two P buried well regions in the first N well region, located on the left and right sides of the first N well region, respectively. The junction depth and junction width of the P buried well regions are respectively smaller than the junction depth and junction width of the first N well region.

[0036] Step 4. Define a first P-well region using a photolithography process, and perform a P-type ion implantation process to form a first P-well region in the first N-well region;

[0037] Step 5. Form a shallow trench on the P-type substrate to isolate the active area from the N-type isolator region; define a third N-well region using a photolithography process, and perform an N-type ion implantation process to form a third N-well region in the first P-well region, wherein the third N-well region is connected to the first N-well region; and form an N-type isolator region in each P-buried layer well region using an N-type ion implantation process;

[0038] Step 6. Use an ion implantation process to implant heavily doped N+ regions into the third N-well region and the two N-type isolation regions; implant heavily doped P+ regions onto the surface of the first P-well region; deposit a process dielectric layer on the surface of the P-type substrate, etch contact holes in the dielectric layer through an etching process, and fill the holes with metal to form contact hole metal, i.e., contact electrodes.

[0039] In addition, based on the above-mentioned semiconductor device based on the BCD process, the present invention also proposes an improved semiconductor device based on the BCD process, in which an N-type polysilicon region is added, and the following technical solutions are adopted:

[0040] A semiconductor device based on a BCD process includes a P-type substrate, an N-type buried layer, a deep N-well region, and a first N-well region; the N-type buried layer, the deep N-well region, and the first N-well region are all located in the middle of the P-type substrate and are arranged in order from bottom to top;

[0041] A P buried well region is provided in the middle of the first N well region, and the junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region; a second N well region is provided in the middle of the P buried well region, and the depth and width of the second N well region are respectively smaller than the depth and width of the P buried well region;

[0042] A first P-well region is provided in the middle of the second N-well region; a shallow trench is formed on the P-type substrate for isolating the active region and the N-type isolation region, wherein the depth of the shallow trench is less than the depth of the second N-well region;

[0043] Two N-type isolator regions are provided in the second N-well region, and the two N-type isolator regions are respectively located on the left and right sides of the first P-well region; and heavily doped N+ implantation regions are formed in the two N-type isolator regions respectively.

[0044] A third N-well region is provided in the middle of the second P-well region, and the third N-well region is connected to the second N-well region;

[0045] A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the second P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, and are isolated by shallow trenches;

[0046] An N-type polysilicon region is provided on the surface of each N-type isolator region;

[0047] The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the second N-well region form a second PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode;

[0048] A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

[0049] In addition, based on the above structure, the present invention also proposes a method for manufacturing a semiconductor device based on the BCD process, which is used to manufacture the semiconductor device based on the BCD process. The technical solution is as follows:

[0050] A method for manufacturing a semiconductor device based on a BCD process comprises the following steps:

[0051] Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate;

[0052] Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate;

[0053] Step 3. A P buried well region is defined by a photolithography process, and a P-type ion implantation process is performed to form a P buried well region in the first N well region. The junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region.

[0054] Step 4. A second N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a second N-well region in the P-buried layer well region. The depth and width of the second N-well region are respectively smaller than the junction depth and junction width of the P-buried layer well region.

[0055] Step 5. Use a photolithography process to define a first P-well region, and perform a P-type ion implantation process to form the first P-well region in the second N-well region;

[0056] Step 6. Forming a shallow trench on the P-type substrate to isolate the active region from the N-type isolator region; defining a third N-well region using a photolithography process; performing an N-type ion implantation process to form a third N-well region in the first P-well region, the third N-well region being connected to the second N-type well region; and forming two N-type isolator regions in the second N-well region using an N-type ion implantation process;

[0057] Step 7. Implant a heavily doped N+ region into the third N-well region and the two N-type isolator regions through an ion implantation process; and implant a heavily doped P+ region on the surface of the second P-well region;

[0058] Step 8. Deposit N-type polysilicon at the position corresponding to each N-type isolation region on the surface of the P-type substrate, and use photolithography and etching processes to form N-type polysilicon regions on the P-type substrate; deposit a process dielectric layer on the surface of the P-type substrate, etch contact holes in the dielectric layer through an etching process, and fill metal to form contact hole metal, i.e., contact electrodes.

[0059] The present invention has the following advantages:

[0060] As described above, the present invention relates to a semiconductor device based on a BCD process and its manufacturing method. Compared to conventional BCD process diodes, the semiconductor device of the present invention utilizes the BCD process method for fabricating N-wells and P-wells. When the cathode voltage is negative, the diode's isolation potential is clamped to a negative potential. At this time, by adding an injection of a P buried well region, the conduction current from the P-type substrate to the N-type isolator region is blocked, enabling the diode to withstand high negative voltages when actively clamped in a high-side power switch, thereby improving the device's performance and reliability. Furthermore, by depositing N-type polysilicon on the surface of the N-type isolator region, the polysilicon and silicon heterojunction contact raises the potential of the N-type isolator region, further preventing the fourth PN junction diode from conducting. This allows the diode to withstand high negative voltages when actively clamped in a high-side power switch, facilitating efficient current control and switch management, particularly in applications requiring high voltage and current control. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] Figure 1 This is a schematic diagram of the structure of a traditional BCD process diode;

[0062] Figure 2 4 is a structural diagram of a semiconductor device based on a BCD process in Example 1 of the present invention;

[0063] Figure 3 1 is a schematic diagram of step 1 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0064] Figure 4 2 is a schematic diagram of step 2 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0065] Figure 5 3 is a schematic diagram of step 3 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0066] Figure 6 4 is a schematic diagram of step 4 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0067] Figure 7 4 is a schematic diagram of step 5 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0068] Figure 8 is a schematic diagram of step 6 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0069] Figure 9 is a schematic diagram of step 7 of the method for manufacturing a semiconductor device based on the BCD process in Example 1 of the present invention;

[0070] Figure 10 is a structural diagram of a semiconductor device based on a BCD process in Example 2 of the present invention;

[0071] Figure 11 It is a structural diagram of a semiconductor device based on the BCD process in Example 3 of the present invention. DETAILED DESCRIPTION

[0072] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0073] In the present invention, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediary. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0074] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0075] BCD process diodes are core components of reference power supplies and high- and low-side power switches. Traditional BCD process diodes can only achieve cathode forward voltage resistance. When the cathode is at a negative voltage, the isolation electrode will be clamped to a negative potential, so the leakage current from the substrate to the isolation potential increases, affecting device performance. In response to the problem that traditional BCD process diodes do not have directional voltage resistance, the present invention introduces a P buried layer well region in the first N well region. The P buried layer well region can not only be short-circuited with the first N well region, but also float. When a negative voltage is applied to the cathode, the P buried layer well region can block the leakage path from the substrate to the N-type isolation region, thereby achieving the diode's high negative voltage resistance characteristic. Therefore, the BCD process semiconductor device of the present invention has forward and reverse voltage resistance characteristics.

[0076] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0077] Example 1

[0078] like Figure 2 As shown, this embodiment describes a semiconductor device based on the BCD process, which includes a P-type substrate 1, an N-type buried layer 2, a deep N-well region 3 and a first N-well region 4a.

[0079] The N-type buried layer 2, deep N-well region 3 and first N-well region 4a are all located in the P-type substrate 1, and the N-type buried layer 2, deep N-well region 3 and first N-well region 4a are all located in the middle position of the P-type substrate 1 and are arranged in sequence from bottom to top.

[0080] The junction depth of the first N-well region 4a is smaller than that of the deep N-well region 3. A P-buried well region 5 is provided in the middle of the first N-well region 4a. The junction depth and junction width of the P-buried well region 5 are respectively smaller than those of the first N-well region 4a.

[0081] A second N-well region 4b is provided in the middle of the P-buried well region 5. The depth and width of the second N-well 4b are respectively smaller than the depth and width of the P-buried well region 5. The first N-well region 4a and the second N-well region 4b have the same doping concentration.

[0082] A first P-well region 6 is provided in the middle of the second N-well 4b; a shallow trench 7 isolation structure is formed on the P-type substrate 1 for isolating the active area and the N-type isolation region 8, wherein the depth of the shallow trench 7 is less than the depth of the second N-well region 4b.

[0083] Two N-type isolation regions 8 are provided in the second N-well 4 b , and the two N-type isolation regions 8 are respectively located on the left and right sides of the first P-well region 6 ; heavily doped N+ implantation regions 10 are formed correspondingly in the two N-type isolation regions 8 .

[0084] The well depth of the N-type isolation region 8 is greater than the depth of the shallow trench 7 .

[0085] A third N-well region 9 is provided in the middle of the second P-well region 6 , and the third N-well region 9 is connected to the second N-well region 4 b .

[0086] A heavily doped N+ implant region 10 is formed in the third N-well region 9 . Two heavily doped P+ implant regions 11 are formed in the second P-well region 6 . The two heavily doped P+ implant regions 11 are located on the left and right sides of the third N-well region 9 , respectively, and are isolated by shallow trenches 7 .

[0087] The first P-well region 6 and the third N-well region 9 constitute a first PN junction diode; the P-buried well region 5 and the second N-well region 4b constitute a second PN junction diode; the P-buried well region 5 and the first N-well region 4a constitute a third PN junction diode; the P-type substrate 1 and the first N-well region 4a constitute a fourth PN junction diode.

[0088] A dielectric layer 12 is provided on the surface of the P-type substrate 1 .

[0089] The heavily doped N+ implantation region 10 and the heavily doped P+ implantation region 11 are connected to external metal via contact hole metals, namely contact electrodes 13, 14, and 15, respectively. Figure 1 As shown, each contact electrode passes through the dielectric layer 12 .

[0090] In this embodiment, the P buried layer well region 5 is added to prevent a leakage channel from being formed when the fourth PN junction diode is turned on.

[0091] Traditional BCD process diodes such as Figure 1 As shown. When a positive voltage is applied to contact electrode 15, the reverse-bias withstand voltage of the PN junction formed by the first P-well region 6 and the third N-well region 9, the reverse-bias withstand voltage of the PN junction formed by the first P-well region 6 and the first N-well region 4a, the reverse-bias withstand voltage of the PN junction formed by the substrate 1 and the first N-well region 4a, the reverse-bias withstand voltage of the PN junction formed by the substrate 1 and the deep N-well region 3, and the reverse-bias withstand voltage of the PN junction formed by the substrate 1 and the N-type buried layer 2. At this time, the diode can achieve forward withstand voltage at contact electrode 15. However, when a negative voltage is applied to contact electrode 15, the potentials of contact electrodes 13 and 14 are clamped to a negative potential, but substrate 1 is at zero potential. At this time, the PN junction formed by substrate 1, the first N-well region 4a, and the N-type isolator region 8 conducts, forming a leakage path. The leakage path flows from the substrate to the isolation electrode 13. It can be seen that conventional BCD process diodes cannot form a withstand voltage region, and the substrate leakage current increases. Therefore, conventional BCD process diodes do not have reverse withstand voltage.

[0092] In this embodiment, a P-buried well region 5 is introduced into the first N-well region 4a. The P-buried well region 5 can not only be short-circuited with the first N-well region 4a but also floated. When a positive voltage is applied to the contact electrode 15, the PN junction formed by the first P-well region 6 and the third N-well region 9 withstands reverse bias, and the PN junction formed by the P-buried well region 5 and the third N-well region 9 withstands reverse bias. At this point, the diode can achieve forward voltage withstand capability at the contact electrode 15. When a negative voltage is applied to the contact electrode 15, the contact electrodes 13 and 14 are also clamped to a negative potential, leaving the substrate at zero potential. At this point, the PN junction formed between the substrate 1 and the first N-well region 4a is conductive. Due to the presence of the P-buried well region 5, leakage current generated by the conductive PN junction between the substrate 1 and the first N-well region 4a is blocked, thereby achieving high negative voltage withstand capability. In this embodiment, the concentration of the introduced P-buried well region 5 is higher than that of the first N-well region 4a, but lower than that of the P-type substrate 1, thereby ensuring that the device has a high forward and reverse voltage withstand capability.

[0093] In addition, based on the semiconductor device based on the BCD process disclosed above, this embodiment 1 further proposes a method for manufacturing a semiconductor device based on the BCD process, which includes the following steps:

[0094] Step 1: Use photolithography to define the N-type buried layer area, and perform ion implantation to form an N-type buried layer 2 on the P-type substrate 1. Figure 3 shown.

[0095] Step 2: Use a photolithography process to define a deep N-type well region, and perform an N-type ion implantation process to form a deep N-well region 3 on the P-type substrate 1; use a photolithography process to define a first N-well region, and perform an N-type ion implantation process to form a first N-well region 4a on the P-type substrate 1, as shown in FIG. Figure 4 shown.

[0096] Step 3. Use a photolithography process to define a P buried well region, and perform a P-type ion implantation process to form a P buried well region 5 in the first N well region 4a. The junction depth and junction width of the P buried well region 5 are respectively smaller than the junction depth and junction width of the first N well region 4a. Figure 5 shown.

[0097] Step 4. Use a photolithography process to define a second N-well region, and perform an N-type ion implantation process to form a second N-well region 4b in the P-buried well region 5. The depth and width of the second N-well 4b are respectively smaller than the junction depth and junction width of the P-buried well region 5. Figure 6 shown.

[0098] Step 5. Use photolithography to define the first P-well region, and perform P-type ion implantation to form the first P-well region 6 in the second N-well region 4b. Figure 7 shown.

[0099] Step 6. Form a shallow trench 7 on the P-type substrate 1 to isolate the active area and the N-type isolation region. Figure 8 As shown; a photolithography process is used to define a third N-well region, and an N-type ion implantation process is performed to form a third N-well region 9 in the first P-well region 6; the third N-well region 9 is connected to the second N-well region 4b. An N-type ion implantation process is performed to form two N-type isolation regions 8 in the second N-well region 4b, as shown. Figure 8 shown.

[0100] Step 7. Use ion implantation to implant heavily doped N+ regions 10 into the third N-well region 9 and the two N-type isolation regions 8; implant heavily doped P+ regions 11 on the surface of the first P-well region 6; deposit a process dielectric layer 12 on the surface of the P-type substrate 1, etch contact holes through an etching process, and fill them with metal to form contact hole metal, i.e., contact electrodes 13, 14, and 15. Figure 9 shown.

[0101] This embodiment 1 adopts the method of manufacturing N-well and P-well in the BCD process. By adding an injection of a P-buried layer well region 5, the conduction current from the P-type substrate 1 to the N-type isolation region 8 is blocked, thereby achieving a negative voltage-resistant working state when the diode is used in the active clamping of the high-side power switch, thereby improving the performance and reliability of the device.

[0102] Example 2

[0103] like Figure 10 As shown, this embodiment 2 also describes a semiconductor device based on the BCD process. Different from the semiconductor device based on the BCD process in the above-mentioned embodiment 1, there are two P buried well regions 5 in this embodiment, which are respectively located on the left and right sides of the first N well region 4a and surround the N-type isolation region 8 on the corresponding side.

[0104] Specifically, a semiconductor device based on the BCD process includes a P-type substrate 1, an N-type buried layer 2, a deep N-well region 3, and a first N-well region 4a. The N-type buried layer 2, the deep N-well region 3, and the first N-well region 4a are all located in the P-type substrate 1. The N-type buried layer 2, the deep N-well region 3, and the first N-well region 4a are all located in the middle of the P-type substrate 1 and are arranged in sequence from bottom to top.

[0105] Two P buried well regions 5 are provided in the first N well region 4a and are located at the left and right sides of the first N well region 4a respectively; the junction depth and junction width of the P buried well region 5 are respectively smaller than the junction depth and junction width of the first N well region 4a.

[0106] A first P-well region 6 is provided in the middle of the first N-well region 4a; a shallow trench 7 isolation structure is formed on the P-type substrate 1 to isolate the active area and the N-type isolation region; an N-type isolation region 8 is provided in each P-buried layer well region 5; and heavily doped N+ injection regions 10 are formed in the two N-type isolation regions 8 respectively.

[0107] A third N-well region 9 is provided in the middle of the first P-well region 6, and the third N-well region 9 is connected to the first N-well region 4a.

[0108] A heavily doped N+ injection region 10 is formed in the third N-well region 9 ; two heavily doped P+ injection regions 11 are formed in the first P-well region 6 . The two heavily doped P+ injection regions 11 are respectively located on the left and right sides of the third N-well region 9 and are isolated by a shallow trench 7 .

[0109] The first P-well region 6 and the third N-well region 9 form a first PN junction diode; the P-buried well region 5 and the first N-well region 4a form a third PN junction diode; and the P-type substrate 1 and the first N-well region 4a form a fourth PN junction diode.

[0110] A dielectric layer 12 is provided on the surface of the P-type substrate 1, and the heavily doped N+ injection region 10 and the heavily doped P+ injection region 11 are connected to external metals through contact hole metals 13, 14, and 15, respectively. Figure 9 As shown, the contact hole metal passes through the dielectric layer 12.

[0111] In addition, based on the above-mentioned semiconductor device based on the BCD process, this embodiment further proposes a method for manufacturing a semiconductor device based on the BCD process, which includes the following steps:

[0112] Step 1: Use a photolithography process to define an N-type buried layer region, and perform an ion implantation process to form an N-type buried layer 2 on a P-type substrate 1.

[0113] Step 2: Use photolithography to define a deep N-type well region, and perform N-type ion implantation to form a deep N-well region 3 on the P-type substrate 1; use photolithography to define a first N-well region, and perform N-type ion implantation to form a first N-well region 4a on the P-type substrate 1.

[0114] Step 3. Define a P buried well region using a photolithography process, and perform a P-type ion implantation process to form two P buried well regions 5 in the first N well region 4 a, located on the left and right sides of the first N well region 4 a, respectively. The junction depth and junction width of the P buried well region 5 are respectively smaller than the junction depth and junction width of the first N well region 4 a.

[0115] Step 4: Use a photolithography process to define the first P-well region, and perform a P-type ion implantation process to form a first P-well region 6 in the first N-well region 4a.

[0116] Step 5. Form a shallow trench 7 on the P-type substrate 1 to isolate the active area and the N-type isolator area; use a photolithography process to define a third N-well area, and perform an N-type ion implantation process to form a third N-well area 9 in the first P-well area 6. The third N-well area 9 is connected to the first N-well area 4a, and use an N-type ion implantation process to form an N-type isolator area 8 in each P-buried layer well area 5.

[0117] Step 6. Use an ion implantation process to implant heavily doped N+ regions 10 into the third N-well region 9 and the two N-type isolation regions 8; implant heavily doped P+ regions 11 on the surface of the first P-well region 6; deposit a process dielectric layer 12 on the surface of the P-type substrate 1, etch contact holes through an etching process, and fill them with metal to form contact hole metal, i.e., contact electrodes 13, 14, and 15.

[0118] Compared with Example 1, this embodiment saves one second N-well region 4b injection process, saves costs, and realizes the device's high negative voltage resistance working state when the diode is used in the active clamping of the high-side power switch, thereby improving the performance and reliability of the device.

[0119] Example 3

[0120] like Figure 11 As shown, this embodiment 3 also describes a semiconductor device based on the BCD process. Different from the semiconductor device based on the BCD process in the above-mentioned embodiment 1, this embodiment 3 deposits N-type polysilicon on the surface of the N-type isolation region.

[0121] Specifically, the semiconductor device based on the BCD process includes a P-type substrate 1, an N-type buried layer 2, a deep N-well region 3, and a first N-well region 4a. The N-type buried layer 2, the deep N-well region 3, and the first N-well region 4a are all located in the P-type substrate 1. The N-type buried layer 2, the deep N-well region 3, and the first N-well region 4a are all located in the middle of the P-type substrate 1 and are arranged in order from bottom to top.

[0122] The junction depth of the first N-well region 4a is smaller than that of the deep N-well region 3. A P-buried well region 5 is provided in the middle of the first N-well region 4a. The junction depth and junction width of the P-buried well region 5 are respectively smaller than those of the first N-well region 4a.

[0123] A second N-well region 4b is provided in the middle of the P-buried well region 5. The depth and width of the second N-well 4b are respectively smaller than the depth and width of the P-buried well region 5. The first N-well region 4a and the second N-well region 4b have the same doping concentration.

[0124] A first P-well region 6 is provided in the middle of the second N-well 4b; a shallow trench 7 is formed on the P-type substrate 1 to isolate the active area and the N-type isolation region, wherein the depth of the shallow trench 7 is less than the depth of the second N-well region 4b.

[0125] Two N-type isolation regions 8 are provided in the second N-well 4 b , and the two N-type isolation regions 8 are respectively located on the left and right sides of the first P-well region 6 ; heavily doped N+ implantation regions 10 are formed correspondingly in the two N-type isolation regions 8 .

[0126] The well depth of the N-type isolation region 8 is greater than the depth of the shallow trench 7 .

[0127] A third N-well region 9 is provided in the middle of the first P-well region 6, and the third N-well region 9 is connected to the second N-well region 4b.

[0128] A heavily doped N+ implant region 10 is formed in the third N-well region 9 . Two heavily doped P+ implant regions 11 are formed in the first P-well region 6 . The two heavily doped P+ implant regions 11 are located on the left and right sides of the third N-well region 9 , respectively, and are isolated by shallow trenches 7 .

[0129] N-type polysilicon regions 16 are provided on the surfaces of the two N-type isolation regions 8 .

[0130] The first P-well region 6 and the third N-well region 9 constitute a first PN junction diode; the P-buried well region 5 and the second N-well region 4b constitute a second PN junction diode; the P-buried well region 5 and the first N-well region 4a constitute a third PN junction diode; the P-type substrate 1 and the first N-well region 4a constitute a fourth PN junction diode.

[0131] A dielectric layer 12 is provided on the surface of the P-type substrate 1, and the heavily doped N+ injection region 10 and the heavily doped P+ injection region 11 are connected to external metals through contact hole metals 13, 14, and 15, respectively. Figure 10 As shown, the contact hole metal passes through the dielectric layer 12.

[0132] In addition, based on the structure of the semiconductor device based on the BCD process, this embodiment further proposes a method for manufacturing a semiconductor device based on the BCD process, which includes the following steps:

[0133] Step 1: Use a photolithography process to define an N-type buried layer region, and perform an ion implantation process to form an N-type buried layer 2 on a P-type substrate 1.

[0134] Step 2: Use photolithography to define a deep N-type well region, and perform N-type ion implantation to form a deep N-well region 3 on the P-type substrate 1; use photolithography to define a first N-well region, and perform N-type ion implantation to form a first N-well region 4a on the P-type substrate 1.

[0135] Step 3. Use a photolithography process to define the first P-well region, and perform a P-type ion implantation process to form a P-buried well region 5 in the first N-well region 4a. The junction depth and junction width of the P-buried well region 5 are respectively smaller than the junction depth and junction width of the first N-well region 4a.

[0136] Step 4. Use photolithography to define the second N-well region, and perform N-type ion implantation to form a second N-well region 4b in the P-buried well region 5. The depth and width of the second N-well 4b are respectively smaller than the junction depth and junction width of the P-buried well region 5.

[0137] Step 5: Use a photolithography process to define the first P-well region, and perform a P-type ion implantation process to form the first P-well region 6 in the second N-well region 4b.

[0138] Step 6. A shallow trench 7 is formed in the P-type substrate 1 to separate the active area from the N-type isolator region. A third N-well region is defined using photolithography. N-type ion implantation is performed to form a third N-well region 9 in the first P-well region 6. The third N-well region 9 is connected to the second N-well region 4b. Two N-type isolator regions 8 are formed in the second N-well region 4b using N-type ion implantation.

[0139] Step 7. Implant a heavily doped N+ region 10 into the third N-well region 9 and the two N-type isolation regions 8 through an ion implantation process; and implant a heavily doped P+ region 11 on the surface of the first P-well region 6 .

[0140] Step 8. N-type polysilicon is deposited on the surface of P-type substrate 1 at locations corresponding to each N-type isolator region 8. Photolithography and etching processes are used to form N-type polysilicon regions 16 on P-type substrate 1. A dielectric layer 12 is deposited on the surface of P-type substrate 1. Contact holes are etched and filled with metal to form contact hole metal, i.e., contact electrodes 13, 14, and 15.

[0141] In this embodiment 3, N-type polysilicon is deposited on the surface of the N-type isolator region 8. Due to the contact between the polysilicon and the silicon heterojunction, the potential of the N-type isolator region 8 is raised, further preventing the fourth PN junction diode from being turned on, and further realizing the device's high negative voltage resistance working state when the diode is used in the active clamping of the high-side power switch, thereby improving the performance and reliability of the device.

[0142] Of course, the above description is only a preferred embodiment of the present invention, and the present invention is not limited to the above-mentioned embodiments. It should be noted that all equivalent substitutions and obvious deformation forms made by any technician familiar with this field under the guidance of this specification fall within the substantive scope of this specification and should be protected by the present invention.

Claims

1. A semiconductor device based on BCD process, characterized in that: It includes a P-type substrate, an N-type buried layer, a deep N-well region and a first N-well region; the N-type buried layer, the deep N-well region and the first N-well region are all located in the middle of the P-type substrate and are arranged in sequence from bottom to top; A P buried well region is provided in the middle of the first N well region, and the junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region; a second N well region is provided in the middle of the P buried well region, and the depth and width of the second N well are respectively smaller than the depth and width of the P buried well region; A first P-well region is provided in the middle of the second N-well region; a shallow trench is formed on the P-type substrate for isolating the active region and the N-type isolation region, wherein the depth of the shallow trench is less than the depth of the second N-well region; Two N-type isolator regions are provided in the second N-well region, and the two N-type isolator regions are respectively located on the left and right sides of the first P-well region; A heavily doped N+ implantation region is formed in each of the two N-type isolation regions; A third N-well region is provided in the middle of the first P-well region, and the third N-well region is connected to the second N-well region; A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the first P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, respectively, and are isolated by shallow trenches; The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the second N-well region form a second PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode; A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

2. A method for manufacturing a semiconductor device based on a BCD process, for manufacturing the semiconductor device based on a BCD process according to claim 1, characterized in that: The manufacturing method comprises the following steps: Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate; Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate; Step 3. A P buried well region is defined by a photolithography process, and a P-type ion implantation process is performed to form a P buried well region in the first N well region. The junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region. Step 4. A second N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a second N-well region in the P-buried layer well region. The depth and width of the second N-well region are respectively smaller than the junction depth and junction width of the P-buried layer well region. Step 5. Use a photolithography process to define a first P-well region, and perform a P-type ion implantation process to form the first P-well region in the second N-well region; Step 6. forming a shallow trench on the P-type substrate to isolate the active region and the N-type isolation region; A third N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form the third N-well region in the first P-well region, wherein the third N-well region is connected to the second N-well region; forming two N-type isolation regions in the second N-well region by adopting an N-type ion implantation process; Step 7. Implanting heavily doped N+ regions into the third N-well region and the two N-type isolation regions through an ion implantation process; Implanting a heavily doped P+ region on the surface of the first P-well region; A process dielectric layer is deposited on the surface of the P-type substrate, a contact hole is etched in the dielectric layer through an etching process, and metal is filled to form a contact hole metal, that is, a contact electrode.

3. A semiconductor device based on BCD process, characterized in that: It includes a P-type substrate, an N-type buried layer, a deep N-well region and a first N-well region; the N-type buried layer, the deep N-well region and the first N-well region are all located in the middle of the P-type substrate and are arranged in sequence from bottom to top; Two P buried layer well regions are provided in the first N well region and are respectively located at the left and right sides of the first N well region; the junction depth and junction width of the P buried layer well regions are respectively smaller than the junction depth and junction width of the first N well region; A first P-well region is provided in the middle of the first N-well region; a shallow trench is formed on the P-type substrate for isolating the active region and the N-type isolator region; an N-type isolator region is provided in each P-buried well region; A heavily doped N+ implantation region is formed in each of the two N-type isolation regions; A third N-well region is provided in the middle of the first P-well region, and the third N-well region is connected to the first N-well region; A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the first P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, respectively, and are isolated by shallow trenches; The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode; A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

4. A method for manufacturing a semiconductor device based on a BCD process, for manufacturing the semiconductor device based on a BCD process as claimed in claim 3, characterized in that: The manufacturing method comprises the following steps: Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate; Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate; Step 3. Define a P buried well region using a photolithography process, and perform a P-type ion implantation process to form two P buried well regions in the first N well region, located on the left and right sides of the first N well region, respectively. The junction depth and junction width of the P buried well regions are respectively smaller than the junction depth and junction width of the first N well region. Step 4. Define a first P-well region using a photolithography process, and perform a P-type ion implantation process to form a first P-well region in the first N-well region; Step 5. forming a shallow trench on the P-type substrate to isolate the active region and the N-type isolation region; A third N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form the third N-well region in the first P-well region, wherein the third N-well region is connected to the first N-well region; An N-type isolator region is formed in each P-buried layer well region by adopting an N-type ion implantation process; Step 6. Implanting heavily doped N+ regions into the third N-well region and the two N-type isolation regions through an ion implantation process; Implanting a heavily doped P+ region on the surface of the first P-well region; A process dielectric layer is deposited on the surface of the P-type substrate, a contact hole is etched in the dielectric layer through an etching process, and metal is filled to form a contact hole metal, that is, a contact electrode.

5. A semiconductor device based on BCD process, characterized in that: It includes a P-type substrate, an N-type buried layer, a deep N-well region and a first N-well region; the N-type buried layer, the deep N-well region and the first N-well region are all located in the middle of the P-type substrate and are arranged in sequence from bottom to top; A P buried well region is provided in the middle of the first N well region, and the junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region; a second N well region is provided in the middle of the P buried well region, and the depth and width of the second N well region are respectively smaller than the depth and width of the P buried well region; A first P-well region is provided in the middle of the second N-well region; a shallow trench is formed on the P-type substrate for isolating the active region and the N-type isolation region, wherein the depth of the shallow trench is less than the depth of the second N-well region; Two N-type isolator regions are provided in the second N-well region, and the two N-type isolator regions are respectively located on the left and right sides of the first P-well region; A heavily doped N+ implantation region is formed in each of the two N-type isolation regions; A third N-well region is provided in the middle of the first P-well region, and the third N-well region is connected to the second N-well region; A heavily doped N+ implant region is formed in the third N-well region; two heavily doped P+ implant regions are formed in the first P-well region, the two heavily doped P+ implant regions are located on the left and right sides of the third N-well region, respectively, and are isolated by shallow trenches; An N-type polysilicon region is provided on the surface of each N-type isolator region; The first P-well region and the third N-well region form a first PN junction diode; the P-buried well region and the second N-well region form a second PN junction diode; the P-buried well region and the first N-well region form a third PN junction diode; the P-type substrate and the first N-well region form a fourth PN junction diode; A dielectric layer is provided on the surface of the P-type substrate, and the heavily doped N+ injection region and the heavily doped P+ injection region are respectively connected to external metal through contact hole metals; the contact hole metals pass through the dielectric layer.

6. A method for manufacturing a semiconductor device based on a BCD process, for manufacturing the semiconductor device based on a BCD process according to claim 5, characterized in that: The manufacturing method comprises the following steps: Step 1. Use a photolithography process to define the N-type buried layer area, and perform an ion implantation process to form an N-type buried layer on the P-type substrate; Step 2: A deep N-type well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a deep N-type well region on the P-type substrate; a first N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a first N-well region on the P-type substrate; Step 3. A P buried well region is defined by a photolithography process, and a P-type ion implantation process is performed to form a P buried well region in the first N well region. The junction depth and junction width of the P buried well region are respectively smaller than the junction depth and junction width of the first N well region. Step 4. A second N-well region is defined by a photolithography process, and an N-type ion implantation process is performed to form a second N-well region in the first P-well region. The depth and width of the second N-well region are respectively smaller than the junction depth and junction width of the P-buried layer well region. Step 5. Use a photolithography process to define a first P-well region, and perform a P-type ion implantation process to form the first P-well region in the second N-well region; Step 6. forming a shallow trench on the P-type substrate to isolate the active region and the N-type isolation region; Defining a third N-well region by using a photolithography process, and performing an N-type ion implantation process to form a third N-well region in the first P-well region, wherein the third N-well region is connected to the second N-well region; forming two N-type isolation regions in the second N-well region by adopting an N-type ion implantation process; Step 7. Implanting heavily doped N+ regions into the third N-well region and the two N-type isolation regions through an ion implantation process; Implanting a heavily doped P+ region on the surface of the first P-well region; Step 8. Depositing N-type polysilicon on the surface of the P-type substrate at a position corresponding to each N-type isolator region, and using photolithography and etching processes to form N-type polysilicon regions on the P-type substrate; A process dielectric layer is deposited on the surface of the P-type substrate, a contact hole is etched in the dielectric layer through an etching process, and metal is filled to form a contact hole metal, that is, a contact electrode.

7. The semiconductor device based on the BCD process according to claim 1 or 5, characterized in that: The doping concentrations of the first N-well region and the second N-well region are the same.

8. The semiconductor device based on the BCD process according to claim 1, 3 or 5, characterized in that: The well depth of the N-type isolation region is greater than the depth of the shallow trench.

9. The semiconductor device based on the BCD process according to claim 1, 3 or 5, characterized in that: The P buried layer well region is short-circuited with the first N well region or is floating.

10. The semiconductor device based on the BCD process according to claim 1, 3 or 5, characterized in that: The concentration of the P buried layer well region is higher than the concentration of the first N well region, and the concentration of the P buried layer well region is lower than the concentration of the P-type substrate.

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