Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The preparation method comprises the steps of providing a semiconductor substrate of a first conduction type; forming a drift region above the semiconductor substrate; first grooves and second grooves are synchronously formed in the drift region, the second grooves are located on the two sides of the second grooves in the first direction, the opening width of the first grooves is larger than that of the second grooves, and the depth of the first grooves is smaller than that of the second grooves; based on the second groove, forming a shielding layer of a second conduction type on the outer sides of the side wall and the bottom of the second groove; forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure; and forming a first metal layer filling the second groove and covering the interlayer dielectric layer. According to the semiconductor structure and the preparation method thereof, the process complexity and the cost are remarkably reduced, the manufacturing efficiency and the yield are improved, the electric field concentration effect at the corner of the trench gate structure is effectively reduced, and the voltage resistance and the reliability of a device are remarkably improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Silicon carbide (SiC) metal oxide semiconductor field effect transistors (MOSFETs), as third-generation wide-bandgap semiconductor power devices, offer significant advantages such as high voltage resistance, high frequency, high temperature, and low loss. They are widely used in high-voltage, high-power applications such as new energy vehicles, power grids, and motor drives. Compared to traditional planar MOSFETs, SiC MOSFETs with a trench structure significantly improve device performance and have become a key area of ​​research and industrial development.

[0003] Existing trench SiC MOSFETs generally adopt either a single trench or dual trench design. The dual trench structure, by introducing auxiliary trenches (also known as dummy trenches or source trenches) on both sides of the gate, effectively improves the device's electric field distribution and reduces the local electric field strength on the gate oxide layer, thereby enhancing the device's breakdown resistance and reliability.

[0004] However, existing dual-trench structures generally have the following shortcomings: the typical dummy trench structure is filled with metal materials (such as aluminum, tungsten, etc.), which requires multiple deposition and patterning steps. In particular, when achieving both a heavily doped shielding layer and metal contact, additional high-energy ion implantation is required to improve the electric field distribution, which not only increases manufacturing costs but also reduces process yield and repeatability. In some structures, there is an interface stress concentration problem between the dummy trench filling material and the surrounding layer structure, which can easily lead to an excessively high electric field in the gate oxide layer, limiting the breakdown voltage of the device. At the same time, the design of the heavily doped shielding layer is limited by the trench structure size, making it difficult to further reduce the on-resistance of the device. In some dual-trench structures, the source contact metal is too deeply embedded in the substrate, which can easily form parasitic capacitance with the gate structure, resulting in a decrease in the switching speed and efficiency of the device in high-frequency application scenarios.

[0005] Therefore, how to simplify the trench process, reduce manufacturing costs, and further optimize the electric field distribution and conduction characteristics while ensuring the device's high voltage resistance, high frequency, and high reliability has become a key technical issue in the current design and manufacturing of dual-trench SiC MOSFET structures. Summary of the Invention

[0006] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof to address the problems in the prior art of trench gate devices, such as complex structure processes, high manufacturing costs, and difficulty in balancing pressure resistance and conduction performance.

[0007] To achieve the above objectives, the present application provides a semiconductor structure, including:

[0008] providing a semiconductor substrate of a first conductivity type;

[0009] forming a drift region above the semiconductor substrate;

[0010] Simultaneously forming a first trench and a second trench in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, an opening width of the first trench is greater than an opening width of the second trench, and a depth of the first trench is less than a depth of the second trench;

[0011] Based on the second trench, forming a shielding layer of a second conductivity type on the outer side of the sidewall and bottom of the second trench;

[0012] forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure;

[0013] A first metal layer is formed to fill the second trench and cover the interlayer dielectric layer.

[0014] In one embodiment, the synchronously forming the first trench and the second trench in the drift region includes:

[0015] forming a patterned photoresist layer on the drift region, wherein the photoresist layer includes a first opening having a first opening width and a second opening having a second opening width, wherein the first opening width is greater than the second opening width and corresponds to the opening widths of the first trench and the second trench, respectively;

[0016] The drift region is etched based on the patterned photoresist layer to simultaneously form the first trench and the second trench, wherein the depth of the first trench is smaller than the depth of the second trench.

[0017] In one embodiment, the ratio of the depth of the second groove to the depth of the first groove is 1.1-2.0.

[0018] In one embodiment, forming a shielding layer of the second conductivity type on the outer sidewalls and bottom of the second trench based on the second trench includes:

[0019] forming a mask layer above the drift region, wherein a third opening is formed in the mask layer, the third opening and the second trench are arranged correspondingly in a second direction, the opening width of the third opening is greater than the opening width of the second trench, and the second direction intersects the first direction;

[0020] Ion implantation is performed in the outer regions of the sidewalls and the bottom of the second trench based on the third opening to form the shielding layer.

[0021] In one embodiment, forming a drift region above the semiconductor substrate includes:

[0022] epitaxially growing an epitaxial layer of a first conductivity type on the semiconductor substrate;

[0023] Ion implantation is performed on the upper surface of the epitaxial layer to form a stacked transition layer of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type, wherein the doping concentration of the shielding layer is greater than the doping concentration of the well region.

[0024] In one embodiment, before forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes:

[0025] A first dielectric layer is formed on the sidewall of the second trench, and the first dielectric layer covers the shielding layer located outside the sidewall of the second trench.

[0026] In one embodiment, the forming of a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure includes:

[0027] forming a second dielectric material layer covering the inner wall of the first trench, the inner wall of the second trench and above the drift region;

[0028] filling a gate material layer in the first trench and the second trench;

[0029] forming an interlayer dielectric material layer above the gate material layer and the second dielectric material layer;

[0030] Etching the interlayer dielectric material layer to form the interlayer dielectric layer;

[0031] Based on the interlayer dielectric layer, the gate material layer and the second dielectric material layer in the second trench are removed, and the second dielectric material layer and the gate material layer located in the first trench are used as the second dielectric layer and the gate layer respectively to form the trench gate structure, and the interlayer dielectric layer covers the trench gate structure.

[0032] In one embodiment, before forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes:

[0033] A first contact layer is formed above the drift region and at the bottom of the second trench.

[0034] In one embodiment, after forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes:

[0035] A second contact layer and a second metal layer are formed on the back surface of the semiconductor substrate.

[0036] On the other hand, the present application also provides a semiconductor structure, comprising:

[0037] a semiconductor substrate of a first conductivity type;

[0038] a drift region located above the semiconductor substrate;

[0039] A first trench and a second trench are formed simultaneously in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, an opening width of the first trench is larger than an opening width of the second trench, and a depth of the first trench is smaller than a depth of the second trench;

[0040] A shielding layer of the second conductive type is located on the sidewalls and outside the bottom of the second trench;

[0041] a trench gate structure filling the first trench;

[0042] an interlayer dielectric layer covering the trench gate structure;

[0043] A first metal layer fills the second trench and covers the interlayer dielectric layer.

[0044] The semiconductor structure and its preparation method are described above. A first trench and a second trench are simultaneously formed in the drift region. The second trench is located on either side of the first trench in a first direction. The first trench has an opening width greater than that of the second trench, and a depth less than that of the second trench. This allows the first and second trenches to be etched simultaneously. Depth control is achieved through design differences in the opening widths, thereby avoiding multiple photolithography, complex etching, and repeated filling processes in conventional double-trench processes. This significantly reduces process complexity and cost, and improves manufacturing efficiency and yield. Furthermore, a shielding layer of the second conductivity type is formed on the sidewalls and outside the bottom of the second trench. The bottom implantation region of the shielding layer is staggered with respect to the corners on either side of the first trench. This effectively reduces the electric field concentration effect at the corners of the trench gate structure, thereby reducing the maximum electric field strength borne by the gate oxide and significantly improving the device's withstand voltage and reliability. Furthermore, the shielding layer located on the sidewalls of the second trench can significantly reduce the lateral extension width of the shielding layer, thereby reducing the device's cell pitch, increasing the effective device cell density, and improving the on-state current per unit area while reducing the on-state resistance and optimizing device performance. In some embodiments, by forming a first dielectric layer on the sidewall of the second trench, and the first dielectric layer covering the shielding layer located on the outside of the sidewall of the second trench, the high-energy ion injection damage to the sidewall of the second trench is reduced. At the same time, the depth of the second trench can be adjusted by designing the first dielectric layer to control the injection depth of the shielding layer, thereby precisely controlling the electric field distribution and the performance of the terminal protection structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a flow chart of a method for preparing a semiconductor structure provided in one embodiment;

[0047] Figure 2 It is a schematic diagram of a cross-sectional structure after a well region is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0048] Figure 3 A schematic diagram of a cross-sectional structure after a source region is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0049] Figure 4 Schematic diagram of a cross-sectional structure after forming a first trench and a second trench in a method for manufacturing a semiconductor structure provided in one embodiment;

[0050] Figure 5A schematic diagram of a cross-sectional structure after a shielding layer is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0051] Figure 6 is a schematic diagram of a cross-sectional structure after forming a second dielectric material layer in a method for preparing a semiconductor structure provided in one embodiment;

[0052] Figure 7 A schematic diagram of a cross-sectional structure after a gate material layer is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0053] Figure 8 Schematic diagram of a cross-sectional structure after removing the gate material layer above the drift region in a method for preparing a semiconductor structure provided in one embodiment;

[0054] Figure 9 A schematic diagram of a cross-sectional structure after an interlayer dielectric layer is formed in a method for preparing a semiconductor structure provided in one embodiment;

[0055] Figure 10 Schematic diagram of a cross-sectional structure after removing the gate material layer and the second dielectric material layer in the second trench in a method for preparing a semiconductor structure provided in one embodiment;

[0056] Figure 11 Schematic diagram of a cross-sectional structure after forming a first dielectric layer and a first contact layer in a method for preparing a semiconductor structure provided in one embodiment;

[0057] Figure 12 is a schematic diagram of a cross-sectional structure after forming a first metal layer in a method for preparing a semiconductor structure provided in one embodiment;

[0058] Figure 13 FIG. 1 is a schematic diagram of a cross-sectional structure after forming a second contact layer and a second metal layer in a method for preparing a semiconductor structure provided in one embodiment.

[0059] Description of reference numerals:

[0060] 1-semiconductor substrate, 2-drift region, 21-epitaxial layer, 22-transition layer, 23-well region, 24-source region, 3-first trench, 4-second trench, 41-first dielectric layer, 5-shielding layer, 6-trench gate structure, 61-second dielectric layer, 611-second dielectric material layer, 62-gate layer, 621-gate material layer, 7-interlayer dielectric layer, 8-first metal layer, 81-first contact layer, 9-second metal layer, 91-second contact layer. DETAILED DESCRIPTION

[0061] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0062] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0063] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0064] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0065] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0066] See also Figure 1 , the present application provides a method for preparing a semiconductor structure, comprising the following steps:

[0067] Step S1: providing a semiconductor substrate 1 of a first conductivity type;

[0068] Step S2: forming a drift region 2 above the semiconductor substrate 1;

[0069] Step S3: Simultaneously forming a first trench 3 and a second trench 4 in the drift region 2, wherein the second trench 4 is located on both sides of the first trench 4 in the first direction, and the opening width of the first trench 3 is larger than the opening width of the second trench 4, and the depth of the first trench 3 is smaller than the depth of the second trench 4;

[0070] Step S4: Based on the second trench 4 , forming a shielding layer 5 of the second conductivity type on the outer sidewalls and bottom of the second trench 4 ;

[0071] Step S5: forming a trench gate structure 6 filling the first trench 3 and an interlayer dielectric layer 7 covering the trench gate structure 6;

[0072] Step S6 : forming a first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7 .

[0073] In the above example, the first trench 3 and the second trench 4 are formed simultaneously in the drift region 2, wherein the second trench 4 is located on both sides of the first trench 3 in the first direction, and the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4, that is, the first trench 3 and the second trench 4 can be etched simultaneously, and then the depth control is achieved by the design difference of the opening width, thereby avoiding multiple photolithography, complex etching and repeated filling processes in the traditional double-trench process, significantly reducing the process complexity and cost, and improving the manufacturing efficiency and yield; A shielding layer 5 is formed on the outer side of the sidewalls and bottom of the second trench 4. The bottom injection region of the shielding layer 5 is staggered with the corners on both sides of the first trench 3, which can effectively reduce the electric field concentration effect at the corners of the trench gate structure 6, thereby reducing the maximum electric field strength borne by the second dielectric layer 61, significantly improving the device's withstand voltage performance and reliability. In addition, the shielding layer 5 located on the sidewalls of the second trench 4 can significantly reduce the lateral expansion width of the shielding layer 5, thereby reducing the unit spacing of the device, increasing the effective device unit density, and improving the on-state current per unit area, while reducing the on-state resistance and optimizing the device performance.

[0074] Specifically, see Figures 2 to 3 , performing step S1 to step S2 to provide a semiconductor substrate 1 of a first conductivity type; and forming a drift region 2 above the semiconductor substrate 1 .

[0075] It should be noted that the first conductivity type and the second conductivity type are opposite conductivity types, that is, when the first conductivity type is N-type, the second conductivity type is P-type; when the first conductivity type is P-type, the second conductivity type is N-type. In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0076] Semiconductor substrate 1 is made of silicon carbide, such as a 4H-SiC (tetragonal silicon carbide) single crystal substrate. Compared to traditional silicon, silicon carbide has a higher breakdown electric field strength, higher thermal conductivity, a wider bandgap, and stronger radiation resistance, making it particularly suitable for manufacturing high-voltage, high-frequency, and high-power-density power devices.

[0077] In one embodiment, Figures 2 to 3 As shown, a drift region 2 is formed above a semiconductor substrate 1, comprising:

[0078] An epitaxial layer 21 of a first conductive type is epitaxially grown on the semiconductor substrate 1; illustratively, the method for forming the epitaxial layer 21 includes chemical vapor deposition, physical vapor deposition, or other technical means suitable for epitaxial growth of silicon carbide materials, such as molecular beam epitaxy or thermal plasma enhanced epitaxy. The epitaxial layer 21 is epitaxially grown on the semiconductor substrate 1. The material of the epitaxial layer 21 is the same as that of the semiconductor substrate 1 to ensure lattice structure matching, reduce interface defects, and improve device reliability. The epitaxial layer 21 has the same conductive type as the semiconductor substrate 1, but the doping concentration of the drift region 2 is less than the doping concentration of the semiconductor substrate 1 to form a high-resistance drift region in the longitudinal direction, i.e., the second direction, thereby improving the breakdown voltage of the device; the thickness and doping of the epitaxial layer 21 can be adjusted according to the target breakdown voltage to ensure that the device has sufficient voltage resistance. In this embodiment, the thickness of the epitaxial layer 21 is greater than 4μm;

[0079] Ion implantation is performed on the upper surface of the epitaxial layer 21 to form a stacked transition layer 22 of the first conductivity type, a well region 23 of the second conductivity type, and a source region 24 of the first conductivity type. The source region 24 provides an ohmic contact region for achieving low contact resistance for the device's source electrode; the well region 23 forms the channel region, creating a conduction path under gate bias. The transition layer 22 (also known as the junction field-effect transistor layer, or JFET layer), as part of the epitaxial layer 21 between the source and drain electrodes, regulates the carrier flow path, controls the electric field distribution, and influences the on-resistance and breakdown voltage.

[0080] The implantation depth of the transition layer 22 is greater than that of the well region 23, and the implantation depth of the well region 23 is greater than that of the source region 24, to meet the overall device structure requirements for trench depth, electric field control, and on-resistance. In this embodiment, the implantation depth of the transition layer 22 is 0.8-1.5 μm, the implantation depth of the well region 23 is 0.5-0.8 μm, and the implantation depth of the source region 24 is 0.1-0.4 μm. The implantation depth here refers to the vertical distance between the bottom of each doped region and the upper surface of the epitaxial layer 21. The actual optimization can be tailored to the device design parameters, breakdown voltage level, and the depth of the subsequent trench structure (such as the first trench 3 and the second trench 4). For example, to ensure that the shielding layer 5 completely covers the bottom area of ​​the first trench 3, the trench structure should be designed so that the extension depth of the shielding layer 5 is greater than the implantation depth of the transition layer 22, thereby achieving a superjunction-like electric field extension effect.

[0081] Specifically, see Figure 4, execute step S3 to simultaneously form a first trench 3 and a second trench 4 in the drift region 2, wherein the second trench 4 is located on both sides of the first trench 3 in the first direction, and the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4.

[0082] In one embodiment, Figure 4 As shown, the first trench 3 and the second trench 4 are formed simultaneously in the drift region 2, including:

[0083] A patterned photoresist layer (not shown) is formed on the drift region 2, the photoresist layer including a first opening having a first opening width and a second opening having a second opening width, the first opening width being greater than the second opening width, and the first opening width and the second opening width corresponding to the opening widths of the first trench 3 and the second trench 4, respectively;

[0084] Based on the patterned photoresist layer, the drift region 2 is etched to simultaneously form a first trench 3 and a second trench 4. The depth of the first trench 3 is smaller than that of the second trench 4. The first trench 3 has a slower etching rate due to its larger opening, resulting in its depth being smaller than that of the second trench 4.

[0085] The method for etching the drift region 2 includes a plasma dry etching process, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), or other suitable methods. Since the etching rate is affected to some extent by the opening size, that is, there is a so-called etch loading effect, which results in a greater etching depth in the area with a smaller opening (i.e., the second trench 4), while the etching depth in the area with a larger opening (i.e., the first trench 3) is relatively shallow within the same etching time.

[0086] Therefore, two types of groove structures with different depths can be achieved in one etching process, effectively avoiding the complicated process of multiple photolithography and multiple groove etching in the traditional process, thereby realizing the one-time synchronous formation of the first groove 3 and the second groove 4 with different depths and widths, greatly simplifying the process steps, reducing manufacturing costs, and improving production efficiency and consistency.

[0087] In this embodiment, the opening width of the first trench 3 can be about 0.4μm~0.8μm, and the depth can be about 0.8μm~1.0μm; the opening width of the second trench 4 is relatively small (such as about 0.2μm~0.4μm), but the depth is larger, which can be 1.2μm~1.5μm.

[0088] It should be noted that the specific depth values ​​of the first trench 3 and the second trench 4 can be flexibly set according to the design objectives of the device. For example, they can be optimized and adjusted based on multiple parameters such as on-resistance, electric field distribution, channel length, and target breakdown voltage.

[0089] In this embodiment, the etching depths of the first trench 3 and the second trench 4 are both less than the depth of the bottom of the transition layer 22 in the drift region 2 to ensure that the etching does not penetrate the transition layer 22, thereby avoiding shortening the current path between the source and drain, thereby reducing the device's withstand voltage capability and reliability. This design helps prevent the formation of a breakdown channel shortening effect.

[0090] Furthermore, to achieve electric field passivation at the corners on both sides of the first trench 3, the depth of the second trench 4 is 1.1 to 2 times the depth of the first trench. This design facilitates the subsequent formation of a shielding layer 5 in the second trench 4, providing protection where the lateral electric field is strongest, effectively reducing the electric field concentration effect at the edges of the trench gate structure and improving the overall compressive strength and reliability of the device.

[0091] Furthermore, the second trenches 4 are arranged on opposite sides of the first trench 3 in the planar layout, i.e., the second trenches 4 are symmetrically formed on the left and right sides of the first trench 3. This layout structure not only helps to increase the overall cell density, but also forms symmetrical second trenches 4 and shielding layers 5 on both sides of the first trench 3, increasing the device's current output capacity per unit area while also improving current uniformity and thermal distribution.

[0092] Specifically, see Figure 5 , executing step S4 , based on the second trench 4 , forming a shielding layer 5 of the second conductive type on the outer side of the sidewall and bottom of the second trench 4 .

[0093] In one embodiment, Figure 5 As shown, a shielding layer 5 is formed on the sidewall and bottom of the second trench 4, including:

[0094] A mask layer (not shown) is formed above the drift region 2. The mask layer has a third opening. The third opening has a width greater than that of the second trench 4 and corresponds to a position of the second trench 4 in the second direction, thereby ensuring that the implantation region covers the sidewalls and the outer area of ​​the bottom of the second trench 4.

[0095] Ion implantation is performed based on the third opening to form a shielding layer 5 in the outer area of ​​the sidewalls and bottom of the second trench 4. The shielding layer 5 is used to passivate the electric field in the high electric field areas on both sides of the subsequent trench gate structure 6, suppress the electric field concentration in the trench corners, and enhance the voltage resistance of the device. The shielding layer 5 forms a PN junction structure with the drift region 2. Under the reverse bias state, the junction region will form an extended depletion layer. The electric field of the depletion layer will superimpose the electric field in the trench gate structure 6 to weaken the field, that is, to ease the steep gradient of the electric field at the corner, reduce the width of the potential mutation zone near the trench gate structure 6 formed subsequently, and suppress the over-concentrated electric field. The high electric field originally concentrated at the corner of the first trench 3 diffuses into the shielding layer 5, acting like an electric field buffer.

[0096] Among them, the maximum injection depth of the shielding layer 5 can reach about 2μm. If the depth of the second groove 4 itself is superimposed, the actual effective depth of the shielding layer 5 in the second direction can reach about 4μm, thereby forming an electric field control effect similar to that of a superjunction structure. It can achieve uniform electric field distribution without increasing the groove spacing, improve the breakdown voltage, and do not significantly increase the on-resistance. If cost and process simplification are considered, a shallower shielding layer 5 injection can be selected according to actual design requirements. It is only necessary to ensure that its injection depth is greater than the injection depth of the transition layer 22, so that it can still effectively block the breakdown channel and prevent electric field spikes.

[0097] In the first direction, the horizontal width of the shielding layer can be optimized based on the device cell design. For example, when the cell density is high, that is, the spacing between the first trench 3 and the second trench 4 is small, the horizontal width of the shielding layer 5 can be minimized while ensuring the electric field protection performance of the trench gate structure 6, thereby increasing the cell density and reducing the on-resistance.

[0098] In this embodiment, the shielding layer 5 is respectively located on the sidewalls and outside of the bottom of the second trench 4, and plays a synergistic role in optimizing device performance. The shielding layer 5 located on the sidewalls of the second trench 4 is mainly used to passivate the high electric field areas on both sides of the trench gate structure 6, alleviate the electric field concentration, and improve the anti-breakdown capability; at the same time, the shielding layer 5 vertically penetrates the source region 24 and the well region 23, which can adjust the channel length, suppress the short channel effect, and facilitate the formation of ohmic contact with the source metal to achieve body-source shorting, thereby improving the reliability and reverse bias continuous current capability of the device. The shielding layer 5 located at the bottom of the second trench 4 forms a deep injection region and forms a deep PN junction structure with the drift region 2, effectively extending the depletion layer width and improving the vertical withstand voltage capability of the device; at the same time, it can simulate the superjunction-like electric field distribution characteristics, while increasing the breakdown voltage and reducing the conduction loss. In addition, the presence of the shielding layer 5 at the bottom can reduce the dependence on the thickness of the well region 23 to a certain extent, thereby further compressing the size of the device and improving the unit density and conduction current capability. Therefore, the shielding layer 5 located on the sidewall and the outside of the bottom of the second trench 4 effectively optimizes the electric field distribution, conduction performance and structural integration of the device.

[0099] In addition, the doping concentration of the shielding layer 5 is higher than that of the well region 23 , which helps to form a stronger barrier region at the edge of the trench gate, thereby enhancing the overall breakdown voltage capability of the device, improving shock resistance and long-term reliability.

[0100] Specifically, after forming the first trench 3 and the second trench 4, the method further includes:

[0101] Defect repair treatment is performed on the inner walls of the first trench 3 and the second trench 4 to improve the device interface quality and enhance reliability.

[0102] Defect repair treatment is performed on the inner walls of the first and second trenches 3 and 4, including sequential high-temperature annealing and sacrificial oxidation treatments. The annealing temperature range is 1200-1300°C. This heat treatment effectively eliminates dislocations, defects, and lattice damage formed on the surface of the drift region 2 during ion implantation in the shielding layer 5, transition layer 22, source region 24, and well region 23. Simultaneously, the sacrificial oxidation process forms a high-quality oxide film on the inner walls of the first and second trenches 3 and 4. This oxide film, which will be removed in subsequent processes, serves to absorb and eliminate residual surface defects and impurities, further improving the electrical performance of the subsequent gate oxide interface. This treatment significantly improves the interface quality of the trench sidewalls and bottom, suppresses leakage current and premature breakdown, and enhances the overall device withstand voltage and long-term reliability. This further repairs surface defects in the drift region caused by ion implantation during the formation of the shielding layer 5, transition layer 22, source region 24, and well region 23.

[0103] Specifically, see Figures 6 to 10, performing step S5 to form a trench gate structure 6 filling the first trench 3 and an interlayer dielectric layer 7 covering the trench gate structure 6 .

[0104] In one embodiment, Figures 6 to 10 As shown, a trench gate structure 6 is formed in the first trench 3, and an interlayer dielectric layer 7 is formed above the trench gate structure 6, including:

[0105] A second dielectric material layer 611 is formed covering the inner wall of the first trench 3, the inner wall of the second trench 4, and the upper portion of the drift region 2. The second dielectric material layer 611 may be formed by thermal oxidation, chemical vapor deposition, or other suitable methods. The second dielectric material layer 611 may be made of silicon dioxide (SiO2), silicon oxynitride (SiON), or the like, which are commonly used for gate oxide layers. The thickness of the second dielectric material layer 611 is controlled according to the channel design and is typically in the range of tens to hundreds of nanometers.

[0106] A gate material layer 621 is filled in the first trench 3 and the second trench 4. The gate material layer 621 may be made of polysilicon, or may be made of doped polysilicon or a metal gate material such as titanium nitride (TiN) or tungsten (W) to meet high-performance device requirements. The gate material layer 621 may be formed by low-pressure chemical vapor deposition (LPCVD) or other suitable methods to ensure good coverage and filling.

[0107] Filling the first trench 3 and the second trench 4 with a gate material layer 621 includes:

[0108] forming a gate material layer 621 covering the second dielectric material layer 611 and filling the first trench 3 and the second trench 4;

[0109] Removing the gate material layer 621 above the drift region 2. The method for removing the gate material layer 621 above the drift region 2 includes dry etching, wet etching, chemical mechanical polishing, or other suitable methods, so that the gate material layer 621 is flush with the surface of the drift region 2 to facilitate subsequent processes.

[0110] An interlayer dielectric material layer (not shown) is formed on the gate material layer 621 and the second dielectric material layer 611. The interlayer dielectric material layer may be made of materials such as tetraethoxysilane (TEOS) silicon oxide, boro-phospho-silicate glass (BPSG), SiO2, or silicon nitride (SiN). The interlayer dielectric material layer serves as a support layer for electrical isolation and subsequent metal interconnect structures. The interlayer dielectric material layer may be formed by plasma-enhanced chemical vapor deposition or spin coating.

[0111] Etching the interlayer dielectric material layer to form an interlayer dielectric layer 7, that is, removing the interlayer dielectric material layer located above the second trench 4. The method of etching the interlayer dielectric material layer includes dry etching, wet etching or other suitable methods;

[0112] Based on the interlayer dielectric layer 7, the gate material layer 621 and the second dielectric material layer 611 in the second trench 4 are removed, and the second dielectric material layer 611 and the gate material layer 621 in the first trench 3 serve as the second dielectric layer 61 and the gate layer 62, respectively, to form the trench gate structure 6. The interlayer dielectric layer 7 covers the trench gate structure 6. The method for removing the gate material layer 621 and the second dielectric material layer 611 in the second trench 4 includes dry etching, wet etching, or other suitable methods.

[0113] The trench gate structure 6 is composed of a second dielectric layer 61 and a gate layer 62 filled in the first trench 3, forming a vertical channel structure to implement the switching control function of the device. The trench gate structure 6 also helps to reduce gate length, lower on-resistance, and increase current density per unit area.

[0114] The interlayer dielectric layer 7 is located above the trench gate structure 6 and serves to electrically isolate the trench gate structure 6 from contact with the first metal layer 8 and provide good flatness and insulation support for the first metal layer 8 to avoid short circuit risks and improve device reliability and processing compatibility.

[0115] Specifically, see Figures 11 to 13 , performing step S6 to form a first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7.

[0116] In one embodiment, Figure 11 As shown, before forming the first metal layer 8 that fills the second trench 4 and covers the interlayer dielectric layer 7, it also includes: forming a first dielectric layer 41 on the sidewall of the second trench 4, the first dielectric layer 41 covers the shielding layer 5 located on the outside of the sidewall of the second trench 4, and the first dielectric layer 41 is used to achieve insulation isolation of the first metal layer 8, thereby preventing the metal layer from being electrically connected to the source region 24 or the transition layer 22 at the sidewall of the second trench 4, thereby ensuring the electrical integrity and stability of the device structure.

[0117] Furthermore, because the first dielectric layer 41 acts as a dielectric barrier between the sidewalls of the second trench 4 and the source region 24 and transition layer 22, it effectively reduces damage to the sidewalls of the second trench 4 and impurity diffusion during high-energy ion implantation (IMP), lowering the probability of localized defects and improving device consistency and yield. Furthermore, because the depth of the second trench 4 is adjustable, the first dielectric layer 41 can indirectly control the location and depth of the implantation region, optimizing the electric field distribution at the trench bottom and thereby improving the device's breakdown voltage and reliability.

[0118] In addition, the first dielectric layer 41 can also extend upward to cover the sidewalls of the interlayer dielectric layer 7, further enhancing the electrical isolation capability of the first metal layer 8 and the surrounding structures, avoiding the risk of short circuits caused by edge overflow or sidewall climbing of the metal during the deposition process, and at the same time enhancing the mechanical stability and thermal reliability between the multi-layer structures, which is beneficial to the compatibility and processing window of the subsequent patterning and interconnection processes of the metal layer.

[0119] Therefore, the design of the above-mentioned first dielectric layer 41 not only plays the role of electrical isolation and structural protection, but also provides the flexibility to regulate the device electric field distribution, improve injection accuracy and suppress edge damage in the structural design dimension. It is one of the key technologies for improving device performance and simplifying the process.

[0120] In one embodiment, before forming the first metal layer 8 that fills the second trench 4 and covers the interlayer dielectric layer 7, it also includes: forming a first contact layer 81 above the drift region 2 and at the bottom of the second trench 4 to further reduce the contact resistance between the first metal layer 8 and the semiconductor, thereby optimizing the conduction performance of the device.

[0121] A first contact layer 81 is formed above the drift region 2 and at the bottom of the second trench 4, comprising:

[0122] A metal layer is deposited on the source region 24 above the drift region 2 and at the bottom of the second trench 4. The metal layer may be made of nickel, cobalt, titanium, or other metal materials suitable for contacting silicon carbide. The thickness of the metal layer may be adjusted according to process requirements and is not limited here.

[0123] Performing a first annealing treatment on the metal layer, for example, annealing at a temperature range of 950°C to 1050°C for tens of seconds to several minutes, to promote a solid-phase reaction between the metal layer and the epitaxial layer 21 substrate made of silicon carbide to form a metal silicide (such as nickel silicide Ni2Si, NiSi, etc.). The metal silicide can significantly reduce the Schottky barrier at the metal / semiconductor interface and improve the ohmic contact characteristics;

[0124] Remove the metal layer that does not participate in the reaction by wet etching or dry etching to avoid affecting subsequent process steps;

[0125] The first contact layer 81 is subjected to a second annealing treatment, such as rapid thermal annealing in the range of 400° C. to 600° C., to further stabilize the crystal structure of the metal silicide layer and improve its thermal stability and reliability.

[0126] Through the above process steps, a stable and low-resistance first contact layer 81 is formed at the source region 24 and the shield layer 5. This structure effectively reduces the energy barrier at the ohmic contact interface, improves electron injection efficiency, and significantly reduces the device's source resistance and on-state resistance, thereby improving the device's overall conduction performance and efficiency. Furthermore, the formation of the first contact layer 81 exhibits excellent thermal stability and process compatibility, not only meeting the high-temperature operation requirements of high-power silicon carbide devices but also avoiding the lattice damage and interface defects caused by traditional highly doped ion implantation methods, further enhancing device reliability and manufacturing yield.

[0127] In one embodiment, Figure 13 As shown, after forming the first metal layer 8 filling the second trench 4 and covering the interlayer dielectric layer 7, the method further includes:

[0128] A second contact layer 91 and a second metal layer 9 are formed on the back surface of the semiconductor substrate 1 .

[0129] Exemplarily, forming the second contact layer 91 and the second metal layer 9 includes:

[0130] Thinning the back side of the semiconductor substrate 1; the method for thinning the back side of the semiconductor substrate 1 includes mechanical grinding, chemical mechanical polishing, dry etching or other suitable methods to reduce the on-resistance and improve the heat dissipation performance and power density of the device;

[0131] A metal layer (e.g., nickel) is deposited on the back side of the thinned semiconductor substrate 1 and annealed to allow the metal layer to react with the semiconductor substrate 1 to form a second contact layer 91, thereby significantly reducing the contact resistance of the second metal layer 9 and achieving good ohmic contact.

[0132] A second metal layer 9 is formed on the surface of the second contact layer 91. The structure of the second metal layer 9 includes a stacked structure such as titanium / nickel / silver (Ti / Ni / Ag) or titanium / nickel / gold (Ti / Ni / Au). The Ti layer can be used as an adhesion layer to improve the bonding strength between the metal and the silicide; the Ni layer provides conductivity and blocks the diffusion of silver / gold; and the Ag or Au layer has excellent conductivity and weldability, making it suitable for package welding.

[0133] Through the above-mentioned back-side process steps, a low-resistance, high-thermal-stability drain ohmic contact structure is finally formed on the back of the device, which together with the front-side source structure completes the entire vertical conduction path, significantly improving the device's overall conduction capability, breakdown voltage performance, power density and heat dissipation efficiency.

[0134] In one embodiment, the present application also provides a semiconductor structure, which is prepared by the above-mentioned semiconductor structure preparation method, including: a semiconductor substrate 1 of a first conductive type, a drift region 2, a first trench 3, a second trench 4, a shielding layer 5 of a second conductive type, a trench gate structure 6, an interlayer dielectric layer 7 and a first metal layer 8, wherein the drift region 2 is located above the semiconductor substrate 1; the first trench 3 and the second trench 4 are formed simultaneously in the drift region 2, the second trench 4 is located on both sides of the first trench 3 in the first direction, the opening width of the first trench 3 is greater than the opening width of the second trench 4, and the depth of the first trench 3 is less than the depth of the second trench 4; the shielding layer 5 of the second conductive type is located outside the sidewall and bottom of the second trench 4; the trench gate structure 6 fills the first trench 3; the interlayer dielectric layer 7 covers the top of the trench gate structure 6; the first metal layer 8 fills the second trench 4 and covers the interlayer dielectric layer 7.

[0135] In one embodiment, the ratio of the depth of the second trench 4 to the depth of the first trench 3 is 1.1-2.0.

[0136] In one embodiment, a first dielectric layer 41 is further formed on the sidewall of the second trench 4 , and the first dielectric layer 41 covers the shielding layer 5 located outside the sidewall of the second trench 4 .

[0137] In one embodiment, a first contact layer 81 is further formed between the first metal layer 8 and the upper portion of the drift region 2 and the bottom portion of the second trench 4 .

[0138] In one embodiment, a second contact layer 91 and a second metal layer 9 are further formed on the back surface of the semiconductor substrate 1 .

[0139] It should be noted that, regarding other structures of the semiconductor structure and their specific contents, reference may be made to the specific contents of the above-mentioned method for preparing the semiconductor structure, which will not be repeated here.

[0140] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0141] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0142] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0143] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a semiconductor substrate of a first conductivity type; forming a drift region above the semiconductor substrate; Simultaneously forming a first trench and a second trench in the drift region, wherein the second trench is located on both sides of the first trench in a first direction, an opening width of the first trench is greater than an opening width of the second trench, and a depth of the first trench is less than a depth of the second trench; Based on the second trench, forming a shielding layer of a second conductivity type on the outer side of the sidewall and bottom of the second trench; forming a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure; A first metal layer is formed to fill the second trench and cover the interlayer dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The step of simultaneously forming a first trench and a second trench in the drift region includes: forming a patterned photoresist layer on the drift region, wherein the photoresist layer includes a first opening having a first opening width and a second opening having a second opening width, wherein the first opening width is greater than the second opening width and corresponds to the opening widths of the first trench and the second trench, respectively; The drift region is etched based on the patterned photoresist layer to simultaneously form the first trench and the second trench, wherein the depth of the first trench is smaller than the depth of the second trench.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The ratio of the depth of the second groove to the depth of the first groove is 1.1-2.

0.

4. The method for preparing a semiconductor structure according to claim 1, wherein: The step of forming a shielding layer of a second conductive type on the outer sidewalls and bottom of the second trench based on the second trench includes: forming a mask layer above the drift region, wherein a third opening is formed in the mask layer, the third opening and the second trench are arranged correspondingly in a second direction, the opening width of the third opening is greater than the opening width of the second trench, and the second direction intersects the first direction; Ion implantation is performed in the outer regions of the sidewalls and the bottom of the second trench based on the third opening to form the shielding layer.

5. The method for preparing a semiconductor structure according to claim 1, wherein: The step of forming a drift region above the semiconductor substrate comprises: epitaxially growing an epitaxial layer of a first conductivity type on the semiconductor substrate; Ion implantation is performed on the upper surface of the epitaxial layer to form a stacked transition layer of the first conductivity type, a well region of the second conductivity type, and a source region of the first conductivity type, wherein the doping concentration of the shielding layer is greater than the doping concentration of the well region.

6. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes: A first dielectric layer is formed on the sidewall of the second trench, and the first dielectric layer covers the shielding layer located outside the sidewall of the second trench.

7. The method for preparing a semiconductor structure according to claim 1, wherein: The forming of a trench gate structure filling the first trench and an interlayer dielectric layer covering the trench gate structure includes: forming a second dielectric material layer covering the inner wall of the first trench, the inner wall of the second trench and above the drift region; filling a gate material layer in the first trench and the second trench; forming an interlayer dielectric material layer above the gate material layer and the second dielectric material layer; Etching the interlayer dielectric material layer to form the interlayer dielectric layer; Based on the interlayer dielectric layer, the gate material layer and the second dielectric material layer in the second trench are removed, and the second dielectric material layer and the gate material layer located in the first trench are used as the second dielectric layer and the gate layer respectively to form the trench gate structure, and the interlayer dielectric layer covers the trench gate structure.

8. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes: A first contact layer is formed above the drift region and at the bottom of the second trench.

9. The method for preparing a semiconductor structure according to claim 1, wherein: After forming the first metal layer filling the second trench and covering the interlayer dielectric layer, the method further includes: A second contact layer and a second metal layer are formed on the back surface of the semiconductor substrate.

10. A semiconductor structure, characterized in that include: a semiconductor substrate of a first conductivity type; a drift region located above the semiconductor substrate; A first trench and a second trench are formed simultaneously in the drift region, wherein the second trench is located on both sides of the second trench in a first direction, an opening width of the first trench is larger than an opening width of the second trench, and a depth of the first trench is smaller than a depth of the second trench; A shielding layer of the second conductive type is located on the sidewalls and outside the bottom of the second trench; a trench gate structure filling the first trench; an interlayer dielectric layer covering the trench gate structure; A first metal layer fills the second trench and covers the interlayer dielectric layer.

Images