Semiconductor device preparation method and semiconductor device

Abstract

The invention discloses a semiconductor device preparation method and a semiconductor device, and the method comprises the following steps: providing a substrate which comprises a first region and a second region, the first region is used for forming a grid electrode on the first region, and the second region is used for forming a source-drain region; forming a sacrificial layer on the substrate; etching the sacrificial layer to form a groove, wherein the bottom of the groove is exposed out of the first region of the substrate; a grid side wall and a grid are sequentially formed, the grid side wall covers the side wall of the groove, and the grid fills the groove; ashing to remove the sacrificial layer so as to expose the second region of the substrate; and executing an ion implantation process to form a source-drain region in the second region. The sacrificial layer is formed on the substrate, and the sacrificial layer always covers the substrate region for forming the source and drain regions in the process of forming the gate side wall and the gate, so that the substrate is prevented from being damaged by an etching process, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] Since its invention, semiconductors have profoundly transformed human production and life. Beyond their applications in computers, semiconductors are also widely used in communications, networking, consumer electronics, and automated control. The development of semiconductor integrated circuits is closely intertwined with electronics, mathematics, physics, chemistry, machining, and other scientific fields. The advancement of semiconductor manufacturing integrated circuits has significantly boosted the development of these fields.

[0003] The semiconductor manufacturing process involves numerous processes, including oxidation, diffusion, ion implantation, photolithography, etching, epitaxy, and metallization. For example, spacers are formed in semiconductor devices. Spacers are located on the sidewalls of the gate and serve to electrically isolate the gate from impurity regions (such as source / drain or lightly doped regions) in transistors. Forming spacers requires depositing spacer material on the substrate surface and then performing an etching process to form the spacers. Dry etching of the substrate surface can damage the substrate, thereby affecting the performance of the semiconductor device. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device preparation method and a semiconductor device to address the problems in the above background technology, so as to avoid substrate damage during the process of dry etching to form sidewalls and improve the performance of semiconductor devices.

[0005] To achieve the above-mentioned and other related objectives, one aspect of the present application provides a method for manufacturing a semiconductor device, characterized in that it includes the following steps:

[0006] Providing a substrate, the substrate comprising a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form a source and drain region;

[0007] forming a sacrificial layer on the substrate;

[0008] etching the sacrificial layer to form a groove, wherein a bottom of the groove exposes the first area of ​​the substrate;

[0009] forming a gate spacer and a gate in sequence, wherein the gate spacer covers the sidewall of the groove and the gate fills the groove;

[0010] removing the sacrificial layer by ashing to expose the second region of the substrate;

[0011] An ion implantation process is performed to form source and drain regions in the second region.

[0012] In some embodiments, the sacrificial layer includes at least one of amorphous carbon, an anti-reflective layer, and a polymer.

[0013] In some embodiments, the gate spacer is inclined, and a bottom area of ​​the gate spacer is larger than an upper opening area of ​​the gate spacer.

[0014] In some embodiments, the ions in the source and drain regions are distributed in different concentration gradients.

[0015] In some embodiments, the substrate directly below the gate sidewall includes a graded junction with gradually changing doping concentration; the source and drain regions are adjacent to the graded junction; and the graded junction and the gate are isolated by an air gate isolation structure.

[0016] In some embodiments, etching the sacrificial layer to form a groove includes:

[0017] Performing vertical dry etching to form a first groove in the sacrificial layer, wherein the bottom of the first groove exposes the first region of the substrate, and the sidewall of the first groove is vertical;

[0018] Lateral dry etching is performed to tilt the sidewalls of the first groove, thereby forming the groove with a bottom area larger than an upper opening area.

[0019] In some embodiments, performing lateral dry etching includes:

[0020] Isotropic etching is performed at the bottom of the first groove, and a concentration of plasma for the isotropic etching in a bottom region of the first groove is greater than a concentration of plasma for the isotropic etching in an upper region of the first groove.

[0021] In some embodiments, the bias power of the plasma etching is reduced and the pressure of the plasma etching is increased so that the plasma used for isotropic etching is concentrated at the bottom of the first groove.

[0022] In some embodiments, sequentially forming the gate spacer and the gate includes:

[0023] forming a gate sidewall, the gate sidewall covering at least the sidewall of the groove; the gate sidewall comprising a liner layer located on the inner sidewall of the groove, and a sidewall material layer located on the side surface of the liner layer; forming a work function layer, the work function layer covering the bottom and sidewall of the groove;

[0024] forming a dielectric layer, wherein the dielectric layer covers the sidewalls of the groove;

[0025] A gate is formed, the gate filling the groove.

[0026] In some embodiments, forming the gate spacer includes:

[0027] forming an inner lining layer, wherein the inner lining layer covers the bottom and sidewalls of the groove;

[0028] forming a sidewall material layer covering the liner layer;

[0029] Performing dry etching to remove a portion of the sidewall material layer at the bottom of the groove;

[0030] Wet etching is performed to completely remove the sidewall material layer at the bottom of the groove to expose the liner layer.

[0031] In some embodiments, after forming the gate, the method further includes:

[0032] removing a portion of the work function layer outside the groove to expose a top surface of the work function layer covering a sidewall of the groove;

[0033] Etching the top surface of the work function layer until the surface of the substrate is exposed to form an air gate isolation region;

[0034] The top of the air grid isolation area is sealed to form an air grid isolation structure.

[0035] Another aspect of the present application is a semiconductor device manufactured using any of the above methods for manufacturing a semiconductor device.

[0036] The semiconductor device manufacturing method and semiconductor device provided by the embodiments of the present application include the following unexpected technical effects:

[0037] By forming a sacrificial layer on the substrate, during the process of forming the gate sidewalls and the gate, the sacrificial layer always covers the substrate area used to form the source and drain regions. After the gate sidewalls and the gate are formed, the sacrificial layer is removed by ashing to expose the substrate to form the source and drain regions, thereby avoiding damage to the substrate by the etching process and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0039] Figure 1 1 is a schematic flow chart of a method for preparing a semiconductor device provided in one embodiment;

[0040] Figure 2Schematic diagram of a cross-sectional structure of a structure obtained after forming a sacrificial layer in step S102 of a method for manufacturing a semiconductor device provided in one embodiment;

[0041] Figure 3 Schematic diagram of a cross-sectional structure of a structure obtained after forming a groove in step S103 of a method for manufacturing a semiconductor device provided in one embodiment;

[0042] Figure 4 Schematic diagram of the cross-sectional structure of the structure obtained after forming the spacer material layer in step S104 of the method for manufacturing a semiconductor device provided in one embodiment;

[0043] Figure 5 1 is a schematic cross-sectional view of a structure obtained after forming a gate in step S104 of a method for manufacturing a semiconductor device provided in one embodiment;

[0044] Figure 6 1 is a schematic cross-sectional view of a structure obtained after forming an air gate isolation structure in step S104 of a method for manufacturing a semiconductor device provided in one embodiment;

[0045] Figure 7 Schematic diagram of the cross-sectional structure of the structure obtained after the sacrificial layer is removed in step S105 of the method for manufacturing a semiconductor device provided in one embodiment;

[0046] Figure 8 1 is a schematic cross-sectional view of a structure obtained after forming source and drain regions in step S106 of a method for manufacturing a semiconductor device provided in one embodiment.

[0047] Description of reference numerals:

[0048] 200, substrate; 201, sacrificial layer; 202, hard mask layer; 203, photoresist layer; 204, groove; 205, liner layer; 206, sidewall material layer; 207, work function layer; 208, dielectric layer; 209, gate; 210, air gate isolation structure; 211, source and drain region; 212, graded junction; 20, gate sidewall. DETAILED DESCRIPTION

[0049] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0051] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present application, a first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0053] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present invention. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, embodiments of the present invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. The regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the present invention.

[0055] It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present application in a schematic manner. Although the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation, the type, quantity and proportion of each component in actual implementation can be changed at will, and the component layout type may also be more complicated.

[0056] The traditional gate sidewall preparation process includes: step 1, using chemical vapor deposition to prepare a gate dielectric layer and a polysilicon layer on the surface of a silicon substrate, then using a gate mask to form a photoresist pattern, and then dry etching the polysilicon layer and the gate dielectric layer until the surface of the source and drain regions of the silicon substrate are exposed, forming a polysilicon gate; step 2, using chemical vapor deposition to prepare a sidewall material layer covering the surface of the silicon substrate, the surface of the polysilicon gate and the sidewall, and then dry etching the sidewall material layer until the surface of the source and drain regions of the silicon substrate are exposed, forming a gate sidewall; step 3, using plasma implantation to form the source and drain regions in the silicon substrate.

[0057] In the above-mentioned traditional gate sidewall preparation process, before performing ion implantation on the source and drain regions of the silicon substrate, steps 1 and 2 have already performed two dry etchings on the surface of the source and drain regions, causing damage to the substrate and thus affecting the performance of the semiconductor device.

[0058] To address the substrate damage issue, the present invention provides a method for preparing a semiconductor device. Figure 1 As shown, the following steps are included:

[0059] Step S101: providing a substrate, the substrate comprising a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form a source and drain region;

[0060] Step S102: forming a sacrificial layer on the substrate;

[0061] Step S103: etching the sacrificial layer to form a groove, wherein the bottom of the groove exposes the first area of ​​the substrate;

[0062] Step S104: forming a gate spacer and a gate in sequence, wherein the gate spacer covers the sidewall of the groove and the gate fills the groove;

[0063] Step S105: removing the sacrificial layer by ashing to expose the second region of the substrate;

[0064] Step S106: performing an ion implantation process to form source and drain regions in the second region.

[0065] First, refer to Figure 2 As shown, step S101 is performed to provide a substrate 200, wherein the substrate 200 includes a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form a source and drain region.

[0066] In some embodiments, the substrate 200 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Preferably, the substrate 200 is a single crystal silicon substrate.

[0067] In some embodiments, the substrate 200 includes a first region for forming a gate thereon and a second region for forming a source and drain region thereon, the second region further including a sub-region for forming a source region and a sub-region for forming a drain region, the sub-region for forming the source region and the sub-region for forming the drain region being separated by the first region, that is, the first region is located between the sub-region for forming the source region and the sub-region for forming the drain region.

[0068] Next, refer to Figure 2 As shown, step S102 is performed to form a sacrificial layer 201 on the substrate 200 .

[0069] In some embodiments, the material of sacrificial layer 201 is selected to be removable without damaging substrate 200. That is, during the step of removing sacrificial layer 201, substrate-damaging processes such as dry etching are not required. Furthermore, the material of sacrificial layer 201 can be selected from a material that can be removed by ashing, such as at least one of amorphous carbon, an anti-reflective coating (ARC), and a polymer.

[0070] In some embodiments, when amorphous carbon is used as the sacrificial layer 201, the sacrificial layer 201 can be formed by chemical vapor deposition (CVD) or other methods using one or more of C3H6, C2H4, and C2H2 as source gases. For example, the sacrificial layer 201 can be formed by one of low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), ultra-high vacuum chemical vapor deposition (UHVCVD), rapid thermal chemical vapor deposition (RTCVD), and molecular beam epitaxy (MBE).

[0071] Next, refer to Figure 3 As shown, step S103 is performed to etch the sacrificial layer 201 to form a groove 204, the bottom of which exposes the first area of ​​the substrate 200. Furthermore, the sidewalls of the groove 204 are inclined, and the bottom area of ​​the groove 204 is larger than the upper opening area of ​​the groove.

[0072] Exemplarily, etching the sacrificial layer to form the groove includes: performing vertical dry etching to form a first groove (not shown) in the sacrificial layer, wherein the bottom of the first groove exposes the first region of the substrate and the sidewalls of the first groove are vertical; and performing lateral dry etching to tilt the sidewalls of the first groove, thereby forming the groove 204 having a bottom area larger than an upper opening area. The lateral dry etching includes performing isotropic etching at the bottom of the first groove, wherein the concentration of the plasma used for isotropic etching in the bottom region of the first groove is greater than the concentration of the plasma used for isotropic etching in the upper region of the first groove, resulting in a groove 204 having an opening area that gradually increases as it approaches the substrate 200.

[0073] In some embodiments, first refer to Figure 2As shown, a hard mask layer 202 and a patterned photoresist layer 203 are formed on top of the sacrificial layer 201, and then a photolithography process is performed to transfer the pattern of the photoresist layer 203 to the hard mask layer 202, thereby forming a patterned hard mask layer 202. Next, using the patterned hard mask layer 202 as a mask, anisotropic dry etching is performed on the sacrificial layer 201 using plasma etching to achieve vertical etching of the sacrificial layer 201 until the surface of the substrate 200 is exposed, thereby forming a first groove (not shown) in the sacrificial layer 201. The sidewalls of the first groove are vertical, that is, the sidewalls of the first groove are perpendicular or substantially perpendicular to the surface of the substrate 200. Next, the bias power of the plasma etching is reduced to weaken the directionality of the etching radicals, and the pressure of the plasma etching is increased at the same time, so that the plasma used for isotropic etching is concentrated at the bottom of the first groove. At this time, the concentration of the plasma used for isotropic etching in the bottom area of ​​the first groove is greater than the concentration of the plasma used for isotropic etching in the upper area of ​​the first groove, thereby achieving isotropic etching of the bottom of the first groove, and making the etching degree of the sidewall of the first groove decrease from the bottom to the top, forming an overall inclined or lower inclined groove sidewall, that is, forming a groove 204 with a bottom area larger than the upper opening area.

[0074] like Figure 3 As shown. Specifically, using SO2 and O2 plasma as an example, when performing anisotropic etching to form the first groove, the bias power is approximately 150V and the gas pressure is approximately 10mT. When performing isotropic etching to form the inclined groove sidewalls, the bias power is approximately 100V and the gas pressure is approximately 20mT. As the bias power decreases and the gas pressure increases, the plasma concentrates at the bottom of the first groove, causing the plasma concentration in the first groove to gradually increase from the top to the bottom. The plasma concentration is proportional to the degree of etching, thereby forming inclined groove sidewalls and obtaining a groove 204 whose opening area gradually increases as it approaches the substrate 200.

[0075] Next, refer to Figures 4 to 6 As shown, step S104 is performed to sequentially form a gate spacer and a gate, wherein the gate spacer covers the sidewall of the groove, and the gate fills the groove 204 .

[0076] For example, referring to Figure 4 As shown, forming the gate sidewall includes: forming an inner liner layer 205, wherein the inner liner layer 205 covers the bottom and sidewalls of the groove 204; forming a sidewall material layer 206 covering the inner liner layer 205; performing dry etching to remove part of the sidewall material layer 206 at the bottom of the groove 204; performing wet etching to completely remove the sidewall material layer 206 at the bottom of the groove 204 to expose the inner liner layer 205.

[0077] In some embodiments, a liner layer 205 can be formed using a process technique familiar to those skilled in the art, such as atomic vapor deposition (ALD). The liner layer 205 covers the entire substrate 200. Specifically, the liner layer 205 covers the top surface of the hard mask layer 202, the sidewalls of the recess 204, and the bottom of the recess 204. The bottom of the recess 204 is the top surface of the first region of the substrate 200. The liner layer 205 can be made of an oxide, such as silicon oxide (SiO2). Next, a spacer material layer 206 can be formed completely covering the liner layer 205 using a process technique familiar to those skilled in the art, such as chemical vapor deposition (CVD). The spacer material layer 206 covers the sidewalls and bottom of the recess 204, and further, covers the entire liner layer 205. The spacer material layer 206 can be made of a nitride, such as silicon nitride (SiN).

[0078] Furthermore, the formed sidewall material layer 206 has a sufficient thickness to fill the space below the inclined sidewall of the groove 204, so that the bottom area of ​​the groove 204 is the same as or similar to the upper opening area. Next, the sidewall material layer 206 is etched back by dry etching to thin the sidewall material layer covering the bottom of the groove 204. However, in order to avoid damage caused by dry etching, a portion of the sidewall material layer covering the bottom of the groove 204 is retained, and then wet etching is used to remove the remaining sidewall material layer until the liner layer 205 covering the bottom of the groove 204 is exposed. In addition, through the above-mentioned dry etching, or the combination of dry etching and wet etching, the sidewall material layer covering the surface of the hard mask layer 202 is completely removed to form Figure 4 The structure shown.

[0079] Further, refer to Figure 5 As shown, the sequential formation of the gate sidewall and the gate includes: forming the gate sidewall, the gate sidewall at least covering the sidewall of the groove; forming the work function layer 207, the work function layer 207 covering the bottom and sidewall of the groove; forming the dielectric layer 208, the dielectric layer 208 covering the sidewall of the groove; forming the gate 209, the gate 209 filling the groove.

[0080] In some embodiments, after forming the gate spacers, a work function layer 207 and a dielectric layer 208 are sequentially formed. Specifically, before forming the work function layer 207, a gate dielectric layer (not shown) is also formed. The gate dielectric layer is typically made of a high-K dielectric material, including but not limited to one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. The work function layer 207 includes but is not limited to one or more of TiN, TaN, TiC, TiAl, TiAlC, or TaAlC, preferably titanium nitride (TiN). The dielectric layer 208 is made of an oxide material, such as silicon oxide (SiO2). The gate dielectric layer, work function layer 207, and dielectric layer 208 can be formed using chemical vapor deposition (CVD) or other process techniques familiar to those skilled in the art, and will not be further described here. The above-mentioned work function layer 207 and dielectric layer 208 both cover the bottom and sidewalls of the groove 204 and cover the hard mask layer 202. Dry etching is then performed to remove the gate dielectric layer, the work function layer 207, and the portions of the dielectric layer 208 outside the groove that cover the hard mask layer 202, and to remove the portion of the dielectric layer 208 covering the bottom of the groove, leaving only the portion of the dielectric layer 208 covering the sidewalls of the groove.

[0081] In some embodiments, after forming the work function layer 207 and the dielectric layer 208, a gate 209 is formed in the recess 204. Specifically, the gate 209 can be made of polysilicon or metal. For example, the method for forming the polysilicon gate can use silane (SiH4) as a reaction gas and helium or nitrogen as a buffer gas. By controlling the flow rate of the reaction gas and the buffer gas, as well as the temperature and pressure of the reaction chamber, a low-pressure chemical vapor deposition (LPCVD) process or other methods can be used to form a gate material layer. Then, chemical mechanical polishing (CMP) is performed to remove excess gate material to form the gate 209 in the recess 204. It should be noted that the gate 209 formed by the method of the present invention can be directly used as the gate of the semiconductor device without the need to pre-form a dummy gate, thereby optimizing the gate formation process in the semiconductor manufacturing process.

[0082] For example, referring to Figure 6 As shown, after the gate 209 is formed, it also includes: removing the work function layer 207 covering the hard mask layer 202 to expose the top surface of the work function layer 207 covering the side wall of the groove; etching the top surface of the work function layer 207 until the surface of the substrate 200 is exposed to form an air gate isolation region; sealing the top of the air gate isolation region to form an air gate isolation structure 210.

[0083] Please continue to refer to Figure 6As shown, in some embodiments, a dry etching process is used to remove the portions of the gate dielectric layer, work function layer 207, dielectric layer 208, and liner layer 205 outside the recess, i.e., the portions covering the hard mask layer 202, until the top surface of the hard mask layer 202 is exposed. The portions of the gate dielectric layer, work function layer 207, dielectric layer 208, and liner layer 205 within the recess remain. The dielectric layer 208 covers the sidewalls of the recess, the gate dielectric layer and work function layer 207 cover the bottom and sidewalls of the recess, and the liner layer 205 covers the bottom and sidewalls of the recess. Next, an etching process is performed to etch the gate dielectric layer and work function layer 207, completely removing the portions of the gate dielectric layer and work function layer 207 covering the sidewalls of the recess, leaving only the portion covering the bottom of the recess, until the liner layer 205 is exposed. The etching process is continued to etch the liner layer 205 until the substrate 200 is exposed. Thus, an air gate isolation region is formed between the gate 209 and the spacer. Next, a sealing material is deposited using a chemical vapor deposition (CVD) process or other method. Since the air gate isolation region has a high aspect ratio, the sealing material only fills a portion of the top of the air gate isolation region to form a top seal. An air gap remains between the top seal and the substrate 200. A CMP process is performed to remove excess sealing material until the top surface of the hard mask layer 202 is processed. Figure 6 At this point, an air gate isolation structure 210 is formed between the gate 209 and the sidewall spacer.

[0084] Next, refer to Figure 7 As shown, in step S105 , the sacrificial layer is removed by ashing to expose the second region of the substrate. The remaining spacer material layer 206 and the liner layer 205 located on the outer sidewall of the spacer material layer 206 are used to form the gate spacer 20 together.

[0085] In some embodiments, dry etching is first performed to remove the hard mask layer 202, and then the sacrificial layer 201 is removed by ashing. Taking amorphous carbon as an example, the ashing method is to use a plasma gas containing oxygen radicals or oxygen ions to remove amorphous carbon. The ashing process is generally carried out at a high temperature, and the ashing temperature can be 300°C to 800°C, for example, 300°C, 600°C, and 800°C. The sacrificial layer 201 is removed by ashing without dry etching. Ashing will not cause damage to the second area of ​​the substrate 200 covered by the sacrificial layer 201, thereby avoiding damage to the substrate by dry etching. After removing the sacrificial layer 201, the exposed gate structure is as shown in FIG. Figure 7 As shown, the area of ​​the bottom of the gate spacer is larger than the opening area of ​​the upper portion, that is, the gate spacer is inclined.

[0086] Next, refer to Figure 8 As shown, step S106 is performed to perform an ion implantation process to form source and drain regions 211 in the second region.

[0087] Please refer to Figure 8 In some embodiments, ion implantation is performed on both sides of the gate structure using the inclined gate sidewall as a mask. The implanted ions can be N-type ions or P-type ions, so that ion-doped source and drain regions 211 are formed in the second region of the substrate. Due to the inclined gate sidewall, the ions in the formed source and drain regions 211 have different concentration gradients. Furthermore, a graded junction 212 is formed at the junction of the source and drain regions 211 (i.e., the second region of the substrate 200) and the substrate below the gate structure (i.e., the first region of the substrate 200), as shown in FIG. Figure 8 As shown, by forming source and drain regions with different concentration gradients and forming a graded junction 212 with gradually changing doping concentrations between the source and drain regions and the gate structure, the graded junction 212 is located directly below the gate sidewall 20, the source and drain regions are adjacent to the graded junction 212, and the graded junction 212 is isolated from the dielectric layer 208 by an air gate isolation structure 210. This can make the longitudinal electric field distribution near the source and drain terminals smoother, avoid the peak electric field problem caused by sudden changes in doping concentration, suppress the hot carrier injection effect, and improve the electrical performance of the semiconductor device.

[0088] This concludes the introduction to the steps of the method for fabricating a semiconductor device according to an embodiment of the present invention. It is understood that the method for fabricating a semiconductor device according to this embodiment includes not only the aforementioned steps but may also include other necessary steps before, during, or after the aforementioned steps, all of which are included within the scope of this manufacturing method.

[0089] The method for manufacturing a semiconductor device according to the embodiments of the present application has the following unexpected technical effects:

[0090] By forming a sacrificial layer on the substrate, during the process of forming the gate sidewalls and the gate, the sacrificial layer always covers the substrate area used to form the source and drain regions. After the gate sidewalls and the gate are formed, the sacrificial layer is removed by ashing to expose the substrate to form the source and drain regions, thereby avoiding damage to the substrate by the etching process and improving the performance of the semiconductor device.

[0091] Reference Figure 8 , which shows a schematic cross-sectional view of a semiconductor device provided according to the present invention. The semiconductor device is manufactured by the above method.

[0092] like Figure 8 As shown, the semiconductor device includes: a substrate 200, wherein the substrate 200 includes spaced source and drain regions 211; the top surface of the substrate includes a gate structure located between the source and drain regions, and the gate structure includes an inclined gate sidewall.

[0093] like Figure 8As shown, in some embodiments, the substrate 200 may be at least one of the following materials: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). Preferably, the substrate 200 is a single crystal silicon substrate.

[0094] like Figure 8 As shown, in some embodiments, the substrate 200 includes a first region for forming a gate thereon and a second region for forming a source and drain region 211, the second region further includes a source region and a drain region, the source region and the drain region are arranged at intervals, and the first region is located between the source region and the drain region.

[0095] like Figure 8 As shown, in some embodiments, the gate structure includes a gate 209, a dielectric layer 208, an air gate isolation structure 210, a spacer material layer 206, and a liner layer 205 arranged in sequence along a first direction, and the gate structure includes a gate 209, a work function layer 207, a gate dielectric layer, and a liner layer 205 arranged in sequence along a second direction. The first direction is a direction perpendicular to the sidewalls of the gate 209, and the second direction is a direction perpendicular to the bottom surface of the gate 209. The gate spacer includes the spacer material layer 206 and the liner layer 205.

[0096] like Figure 8As shown, in some embodiments, gate 209 can be made of polysilicon or metal. Dielectric layer 208 covers the sidewalls of gate 209 but not the bottom. Dielectric layer 208 is made of an oxide material, such as silicon oxide (SiO2). Work function layer 207 and gate dielectric layer cover the bottom of gate 209 but not the sidewalls. Work function layer 207 includes, but is not limited to, one or more of TiN, TaN, TiC, TiAl, TiAlC, or TaAlC, preferably titanium nitride (TiN). The gate dielectric layer is typically made of a high-K dielectric material, including, but not limited to, one or more of hafnium oxide, zirconium oxide, hafnium silicon oxynitride, hafnium silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, or aluminum oxide. The air gate isolation structure 210 includes an air gap between the dielectric layer 208 and the spacer layer 206. The bottom of the air gate isolation structure 210 is connected to the substrate 200, and the top of the air gate isolation structure 210 includes a top seal. In other words, the air gate isolation structure 210 is formed by the dielectric layer 208, the spacer layer 206, the substrate 200, and the top seal, surrounding the air gap on all sides. The spacer layer 206 covers the sidewalls of the gate 209 but not the bottom of the gate 209. The material of the spacer layer 206 can be a nitride, such as silicon nitride (SiN). The liner layer covers the bottom and sidewalls of the gate, and the liner layer 205 is penetrated by the air gate isolation structure 210. The material of the liner layer 205 can be an oxide, such as silicon oxide (SiO2).

[0097] like Figure 8 As shown, in some embodiments, the gate sidewall spacer is tilted. Specifically, the area at the bottom of the gate sidewall spacer is larger than the opening area at the top. Ions in the source and drain regions 211 are distributed with different concentration gradients. Furthermore, a graded junction 212 is formed between the source and drain regions 211 (i.e., the second region of the substrate 200) and the substrate below the gate structure (i.e., the first region of the substrate 200). The graded junction 212 is located directly below the gate sidewall spacer 20 and is isolated from the dielectric layer 208 by an air gate isolation structure 210. By forming source and drain regions with different concentration gradients and forming a graded junction 212 with a gradually changing doping concentration between the source and drain regions and the gate structure, the longitudinal electric field distribution near the source and drain terminals can be made smoother, avoiding peak electric field problems caused by sudden changes in doping concentration, suppressing hot carrier injection effects, and improving the electrical performance of the semiconductor device.

[0098] The specific structure of the semiconductor device can refer to the description of the corresponding part above, and will not be repeated here for the sake of brevity.

[0099] Please note that the above embodiments are for illustrative purposes only and are not intended to limit the present application.

[0100] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a semiconductor device, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a first region and a second region, wherein the first region is used to form a gate thereon, and the second region is used to form a source and drain region; forming a sacrificial layer on the substrate; etching the sacrificial layer to form a groove, wherein a bottom of the groove exposes the first area of ​​the substrate; forming a gate spacer and a gate in sequence, wherein the gate spacer covers the sidewall of the groove and the gate fills the groove; removing the sacrificial layer by ashing to expose the second region of the substrate; An ion implantation process is performed to form source and drain regions in the second region.

2. The method for preparing a semiconductor device according to claim 1, wherein: The sacrificial layer includes at least one of amorphous carbon, an anti-reflection layer, and a polymer.

3. The method for preparing a semiconductor device according to claim 1, wherein: The gate sidewall spacer is inclined, and the bottom area of ​​the gate sidewall spacer is larger than the upper opening area of ​​the gate sidewall spacer.

4. The method for preparing a semiconductor device according to claim 3, wherein: The ions in the source and drain regions are distributed in different concentration gradients; and / or The substrate directly below the gate sidewall includes a graded junction with a gradually changing doping concentration; The source and drain regions are adjacent to the graded junction; The graded junction is isolated from the gate via an air gate isolation structure.

5. The method for preparing a semiconductor device according to claim 1, wherein: The etching the sacrificial layer to form a groove comprises: Performing vertical dry etching to form a first groove in the sacrificial layer, wherein the bottom of the first groove exposes the first region of the substrate, and the sidewall of the first groove is vertical; Lateral dry etching is performed to tilt the sidewalls of the first groove, thereby forming the groove with a bottom area larger than an upper opening area.

6. The method for preparing a semiconductor device according to claim 5, wherein: The performing of lateral dry etching comprises: Isotropic etching is performed at the bottom of the first groove, and a concentration of plasma for the isotropic etching in a bottom region of the first groove is greater than a concentration of plasma for the isotropic etching in an upper region of the first groove.

7. The method for preparing a semiconductor device according to claim 6, wherein: The bias power of plasma etching is reduced and the pressure of plasma etching is increased so that the plasma used for isotropic etching is gathered at the bottom of the first groove.

8. The method for preparing a semiconductor device according to claim 1, wherein: The sequentially forming of the gate sidewall spacer and the gate comprises: forming a gate sidewall, the gate sidewall at least covering the sidewall of the groove; the gate sidewall comprising a liner layer located on the inner sidewall of the groove, and a sidewall material layer located on the side surface of the liner layer; forming a work function layer, wherein the work function layer covers the bottom and sidewalls of the groove; forming a dielectric layer, wherein the dielectric layer covers the sidewalls of the groove; A gate is formed, the gate filling the groove.

9. The method for preparing a semiconductor device according to claim 8, wherein: Forming the gate sidewall includes: forming an inner lining layer, wherein the inner lining layer covers the bottom and sidewalls of the groove; forming a sidewall material layer covering the liner layer; Performing dry etching to remove a portion of the sidewall material layer at the bottom of the groove; Wet etching is performed to completely remove the sidewall material layer at the bottom of the groove to expose the liner layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: After forming the gate, the method further includes: removing a portion of the work function layer outside the groove to expose a top surface of the work function layer covering a sidewall of the groove; Etching the top surface of the work function layer until the surface of the substrate is exposed to form an air gate isolation region; The top of the air grid isolation area is sealed to form an air grid isolation structure.

11. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 10.

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